A high-speed generalized cascade decoder based on FPGA

Abstract

The present invention provides a high-speed generalized cascade decoder based on FPGA, comprising L cascaded decoding modules of different layers and 1 H The total input of the generalized cascade decoder is V 0 means, pass through L After the cascaded decoding modules of different layers, the i The output of the cascaded decoding module of the layer is expressed as We ;No. L The output of the generalized cascade decoding layer #imgabs0# passes through H After the matrix multiplier, the total output of the generalized cascade decoder is obtained C The generalized cascade decoder of the present invention achieves performance equivalent to that of long codes with lower complexity by cascade iterative decoding of short codes; compared with RS codes of the same code rate, the bit error rate performance is significantly improved.

Description

Technical Field

[0001] The invention belongs to the technical field of channel coding, relates to a decoder, and in particular to a high-speed generalized cascade decoder based on FPGA. Background Art

[0002] In 1965, GD. Forney proposed concatenated codes, which achieve a compromise between decoding performance and complexity by combining short codes into long codes. Initially, concatenated codes generally use a two-stage code serial concatenation method, where the code close to the channel is called the inner code and the code far from the channel is the outer code. Generalized concatenated codes (GCC codes for short) extend the concatenation of two codes to the concatenation of multiple codes, and were first proposed by E. Blokh and Y. Zyablov in 1973. Turbo codes are serial concatenated convolutional codes, LDPC codes (Low Density Parity Check Codes) are a type of low-density parity check code, and are a type of linear block code. The generator matrix of LDPC codes can also be seen as a multi-stage concatenation of multiple component codes, and the polar code encoder is composed of multiple subcode codes. Therefore, these three modern codes can all be seen as generalized concatenated codes. At present, scholars have conducted a lot of research on GCC codes, and most of them call the multi-layer concatenation code of the outer code RS code (Reed-Solomon codes) and the inner code BCH (abbreviation of Bose, Ray-Chaudhuri and Hocquenghem) code GCC code. However, the decoding complexity of this GCC code is high, and there is still a gap in the research on the efficient FPGA (Field Programmable Gate Array) implementation of the GCC decoder. Summary of the invention

[0003] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a high-speed generalized cascade decoder based on FPGA to solve the technical problem that the decoder in the prior art is difficult to achieve both structural simplicity and low bit error rate.

[0004] In order to solve the above technical problems, the present invention adopts the following technical solutions to achieve the above problems:

[0005] A high-speed generalized cascade decoder based on FPGA, L cascaded decoding modules of different layers and 1 H Matrix multiplier.

[0006] The total input of the generalized cascade decoder is V 0 means, pass through L After the cascaded decoding modules of different layers, the iThe output of the cascaded decoding module of the layer is expressed as V i ;No. L The output of the layer generalized concatenated decoding go through H After the matrix multiplier, the total output of the generalized cascade decoder is obtained C .

[0007] in:

[0008] L Indicates the number of outer code layers of generalized concatenated decoding;

[0009] H is the inner code check matrix, the size of the inner code check matrix is n × n ;

[0010] n represents The number of rows in the inner code check matrix, n = m × L ;

[0011] m Indicates the number of bits contained in each symbol of the outer code RS encoding. Each codeword input lasts N clock cycles;

[0012] N Indicates the encoding symbol length of RS encoding.

[0013] The present invention also has the following technical features:

[0014] Specifically, the cascade decoding module includes H Matrix multiplier, GCC codeword memory, RS codeword memory, RS decoder, G Matrix multiplier and BCH decoder.

[0015] in:

[0016] G Represents the generator matrix, which is the inverse matrix of the inner code check matrix. The size of the generator matrix is n × n .

[0017] Specifically, the i The input of the cascaded decoding module of the layer It is divided into two branches. The first branch enters the GCC codeword memory and i The input of the cascaded decoding module of the layer The second branch enters the cascade decoding module. H Matrix multiplier, recover the outer code vector after operation S .

[0018] The outer code vector S The specific operation is S = H × , the outer code vector S is a L × m bit vector, the outer code vector S By m The bits are grouped into sets S= { s 1, s 2,…, s L}.

[0019] gather S middle, i = 1 , 2 ,…, L , s i Corresponding to i The codeword sequence of the layer RS ​​encoding is from the set S Remove s i The resulting set is recorded as the set ,gather Enter the RS codeword memory for caching, s i Enter the RS decoder i The RS coded codeword of the layer is decoded, and the decoding result is recorded as , then decode the result Replacement Collection S The original s i After, gather And the decoding result Composed new outer code vector .

[0020] Next, the outer code vector Enter G Matrix multiplier to generate updated GCC codeword U i , updated GCC codeword U i The first i The input of the cascaded decoding module of the layer Perform modulo 2 addition to restore the inner code array D i .

[0021] The inner code array Di The specific calculation is D i = + U i ,in U i = G × .

[0022] The inner code array D i Each column is a BCH code word, and the inner code array is decoded by the BCH decoder. D i Each column of the BCH decoding operation is performed to generate a new inner code array .

[0023] The inner code array and GCC codewords U i After performing modulo 2 addition, we get i The modified GCC codeword after the update is obtained. i The output of the cascaded decoding module of the layer V i .

[0024] The said i The output of the cascaded decoding module of the layer V i The specific calculation is V i = + U i .

[0025] Specifically, the i The output of the cascaded decoding module of the layer V i is a L × m A vector of bits.

[0026] Specifically, the total output of the generalized cascade decoder is C = H × .

[0027] Compared with the prior art, the present invention has the following technical effects:

[0028] (I) The generalized cascade decoder of the present invention achieves performance equivalent to that of long codes with lower complexity by cascaded iterative decoding of short codes; compared with RS codes of the same code rate, the bit error rate performance is significantly improved.

[0029] (II) The generalized cascade decoder of the present invention realizes iterative decoding by serially cascading multiple decoding modules with the same structure, which effectively simplifies the implementation structure of the decoder. By adjusting the implementation parameters of the RS decoder and the BCH decoder at each layer, the code length and code rate can be flexibly adjusted, thereby achieving a compromise between coding overhead and bit error rate performance.

[0030] (III) The structure of the generalized cascade decoder of the present invention can realize high-parallel GCC decoding calculation, which is suitable for communication applications requiring high speed and high error correction capability such as laser communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the overall structure of the high-speed generalized cascade decoder based on FPGA of the present invention.

[0032] Figure 2 It is a schematic diagram of the composition of the cascade decoding module.

[0033] Figure 3 This is the decoding performance comparison result of GCC code and RS(255,223) code.

[0034] The specific contents of the present invention are further explained in detail below in conjunction with embodiments. DETAILED DESCRIPTION

[0035] It should be noted that, unless otherwise specified, all devices and operations in the present invention adopt devices and operations known in the prior art.

[0036] The present invention proposes an FPGA implementation architecture of a generalized cascade decoder suitable for high-speed applications. It implements iterative decoding by cascading multiple decoding modules with the same structure in series, effectively simplifies the implementation structure of the decoder, and can flexibly adjust the code length and code rate by adjusting the implementation parameters of each layer of RS decoder and BCH decoder. The implementation results show that the decoder proposed in the present invention achieves performance equivalent to that of long codes with lower complexity through cascade iterative decoding of short codes, and significantly improves the bit error rate performance compared with RS codes of the same code rate.

[0037] Specific embodiments of the present invention are given below. It should be noted that the present invention is not limited to the following specific embodiments, and all equivalent changes made on the basis of the technical solution of this application fall within the protection scope of the present invention.

[0038] Example:

[0039] This embodiment provides a high-speed generalized cascade decoder based on FPGA, such as Figure 1 As shown by L cascaded decoding modules of different layers and 1 H Matrix multiplier.

[0040] The total input of the generalized cascade decoder is V 0 means, pass through L After the cascaded decoding modules of different layers, the i The output of the cascaded decoding module of the layer is expressed as V i ;No. L The output of the layer generalized concatenated decoding go through H After the matrix multiplier, the total output of the generalized cascade decoder is obtained C .

[0041] in:

[0042] L Indicates the number of outer code layers of generalized concatenated decoding (abbreviated as GCC code);

[0043] H is the inner code check matrix, the size of the inner code check matrix is n × n ;

[0044] n represents The number of rows in the inner code check matrix, n = m × L ;

[0045] m Indicates the number of bits contained in each symbol of the outer code RS encoding. Each codeword input lasts N clock cycles;

[0046] N Indicates the encoding symbol length of RS encoding.

[0047] As a preferred solution of this embodiment, the cascade decoding module includes H Matrix multiplier, GCC codeword memory, RS codeword memory, RS decoder, G Matrix multiplier and BCH decoder.

[0048] in:

[0049] G Represents the generator matrix, which is the inverse matrix of the inner code check matrix. The size of the generator matrix is n × n .

[0050] Further, i The input of the cascaded decoding module of the layer It is divided into two branches. The first branch enters the GCC codeword memory and i The input of the cascaded decoding module of the layer The second branch enters the cascade decoding module H Matrix multiplier, recover the outer code vector after operation S ; External code vector S The specific operation is S = H × , the outer code vector S is a L × m bit vector, the outer code vector S By m The bits are grouped into sets S= { s 1, s 2,…, s L}.

[0051] gather S middle, i = 1 , 2 ,…, L , s i Corresponding to i The codeword sequence of the layer RS ​​encoding is from the set S Remove s i The resulting set is recorded as the set ,gather Enter the RS codeword memory for cache, s i Enter the RS decoder i The RS coded codeword of the layer is decoded, and the decoding result is recorded as , then decode the result Replacement Collection S The original s i After, gather And the decoding result Composed new outer code vector .

[0052] Next, the outer code vector Enter G Matrix multiplier to generate updated GCC codeword U i , updated GCC codeword U i The first i The input of the cascaded decoding module of the layer Perform modulo 2 addition to restore the inner code array D i .

[0053] Internal code array D i The specific calculation is D i = + U i ,in U i = G × .

[0054] Internal code array D i Each column is a BCH code word, and the inner code array is decoded by the BCH decoder. D i Each column of the BCH decoding operation is performed to generate a new inner code array .

[0055] Internal code array and GCC codewords U i After performing modulo 2 addition, we get i The modified GCC codeword after the update is i The output of the cascaded decoding module of the layer V i .

[0056] No. i The output of the cascaded decoding module of the layer V i The specific calculation is V i = + U i .

[0057] In this embodiment, the difference between the cascade decoding modules of different layers is that the RS decoders and BCH decoders used are different, and the decoder type used corresponds to the RS code type and BCH code type used for encoding in the layer.

[0058] As a preferred solution of this embodiment, i The output of the cascaded decoding module of the layer V i is a L × m A vector of bits.

[0059] As a preferred solution of this embodiment, the total output of the generalized cascade decoder is C = H × .

[0060] Application examples:

[0061] This application example provides a high-speed generalized cascade decoder based on FPGA based on the above embodiment. Specifically:

[0062] For a GCC code (RS code with an outer code length of 200 + BCH code with an inner code length of 32), the number of coding layers is L =4, code length N =200, the number of bits in a single symbol m =8, the first layer uses the shortened RS code of (200,148), the second layer uses the shortened RS code of (200,186), the third layer uses the shortened RS code of (200,194), and the fourth layer uses the shortened RS code of (200,196). The first layer uses the BCH code with a code length of 32 and an error correction capability of 1, the second layer uses the BCH code with a code length of 32 and an error correction capability of 2, the third layer uses the BCH code with a code length of 32 and an error correction capability of 3, and the fourth layer uses the BCH code with a code length of 32 and an error correction capability of 4.

[0063] According to the above embodiment, a cascade decoder is implemented for the GCC code (RS code with an outer code length of 200 + BCH code with an inner code length of 32). 4 cascaded decoding modules of different layers and 1 H Matrix multiplier.

[0064] The total input of the generalized cascade decoder is V 0 means that after passing through 4 different layers of cascaded decoding modules, the output of the decoding from the 1st to the 4th layer is expressed as , the output of the 4th level cascade decoding V4 go through H After the matrix multiplier, the total output of the generalized cascade decoder is obtained C .

[0065] Each is a 4×8 bit vector. The outer code RS encoding contains 8 bits per symbol. Each codeword input lasts for 200 clock cycles. H Output of the matrix multiplier C = H × , H is the inner code check matrix of the concatenated coding, and its size is 32×32.

[0066] Each cascade decoding module is mainly composed of H Matrix multiplier, GCC codeword memory, RS codeword memory, RS decoder, G The structure is composed of matrix multiplier and BCH decoder. Figure 2 shown.

[0067] No.i The input of the cascaded decoding module of the layer It is divided into two branches. The first branch enters the GCC codeword memory and Cache; the second branch enters H Matrix multiplier, recover the outer code vector after operation S , the specific operation is S = H × , S is a 32-bit vector. S Divide into groups of 8 bits each , si Corresponding to i The codeword sequence of layer RS ​​encoding, i=1,2,…,4 , will be S Remove si The resulting set is recorded as ,gather Enter the RS codeword memory for caching, si Enter the RS decoder i The RS coded codeword of the layer is decoded, and the decoding result is recorded as , then decode the result Replace the original si and collection Composed new outer code vector .

[0068] Next, the new outer code vector Enter G Matrix multiplier to generate updated GCC codeword Ui , G The size of the matrix is 32×32 , then Ui The GCC codeword memory Perform modulo 2 addition to restore the inner code array Di , Di The specific calculation is Di = + Ui ,in Ui = G × .

[0069] at this time Di Each column of is a BCH codeword, Di Through the BCH decoder Di Each column of the BCH decoding operation is performed to generate a new inner code array . Internal code array and Ui After performing modulo 2 addition, we get iCorrected GCC codewords after update Vi , specifically calculated as Vi = + Ui ,at this time Vi It is the input vector of the next layer of cascade decoding.

[0070] The difference between the cascade decoding modules of the 1st to 4th layers mainly lies in the RS decoders and BCH decoders used. The cascade decoding module of the 1st layer uses the RS (200, 148) decoder and the BCH decoder with a code length of 32 and an error correction capability of 1. The cascade decoding module of the 2nd layer uses the RS (200, 186) decoder and the BCH decoder with a code length of 32 and an error correction capability of 2. The cascade decoding module of the 3rd layer uses the RS (200, 194) decoder and the BCH decoder with a code length of 32 and an error correction capability of 3. The cascade decoding module of the 4th layer uses the RS (200, 196) decoder and the BCH decoder with a code length of 32 and an error correction capability of 4.

[0071] The code rate of the GCC code (RS code with an outer code length of 200 + BCH code with an inner code length of 32) is equivalent to that of the RS (255, 223) code. Under 64APSK modulation, the decoding performance comparison results are as follows: Figure 3 As shown, in Figure 3 In the equation, Eb represents the energy required to transmit 1 bit of information, N0 represents the power spectrum density of the channel noise, and Eb / N0 represents the ratio of the energy required to transmit 1 bit of information to the power spectrum density of the channel noise; APSK represents amplitude phase keying modulation; BER represents the bit error probability. When the BER is 0.8dB, the performance is improved. There is a 1.5dB performance improvement.

Claims

1. A high-speed generalized cascade decoder based on FPGA, characterized in that: Depend on L cascaded decoding modules of different layers and 1 H Matrix multiplier composition; The total input of the generalized cascade decoder is V 0 means, pass through L After the cascaded decoding modules of different layers, the i The output of the cascaded decoding module of the layer is expressed as V i ;No. L The output of the layer generalized concatenated decoding go through H After the matrix multiplier, the total output of the generalized cascade decoder is obtained C ; in: L Indicates the number of outer code layers of generalized concatenated decoding; H is the inner code check matrix, the size of the inner code check matrix is n × n ; n represents The number of rows in the inner code check matrix, n = m × L ; m Indicates the number of bits contained in each symbol of the outer code RS encoding. Each codeword input lasts N clock cycles; N Indicates the encoding symbol length of RS encoding; The cascade decoding module includes H Matrix multiplier, GCC codeword memory, RS codeword memory, RS decoder, G Matrix multiplier and BCH decoder; in: G Represents the generator matrix, which is the inverse matrix of the inner code check matrix. The size of the generator matrix is n × n ; The said i The input of the cascaded decoding module of the layer It is divided into two branches. The first branch enters the GCC codeword memory and i The input of the cascaded decoding module of the layer The second branch enters the cascade decoding module. H Matrix multiplier, recover the outer code vector after operation S ; The outer code vector S The specific operation is S = H × , the outer code vector S is a L × m bit vector, the outer code vector S By m The bits are grouped into sets S= { s 1, s 2,…, s L }; gather S middle, i = 1 , 2 ,…, L , s i Corresponding to i The codeword sequence of the layer RS ​​encoding is from the set S Remove s i The resulting set is recorded as the set ,gather Enter the RS codeword memory for cache, s i Enter the RS decoder i The RS coded codeword of the layer is decoded, and the decoding result is recorded as , then decode the result Replacement Collection S The original s i After, gather And the decoding result Composed new outer code vector ; Next, the outer code vector Enter G Matrix multiplier to generate updated GCC codeword U i , updated GCC codeword U i The first i The input of the cascaded decoding module of the layer Perform modulo 2 addition to restore the inner code array D i ; The inner code array D i The specific calculation is D i = + U i ,in U i = G × ; The inner code array D i Each column is a BCH code word, and the inner code array is decoded by the BCH decoder. D i Each column of the BCH decoding operation is performed to generate a new inner code array ; The inner code array and GCC codewords U i After performing modulo 2 addition, we get i The modified GCC codeword after the update is obtained. i The output of the cascaded decoding module of the layer V i ; The said i The output of the cascaded decoding module of the layer V i The specific calculation is V i = + U i .

2. The high-speed generalized cascade decoder based on FPGA as claimed in claim 1, characterized in that: The said i The output of the cascaded decoding module of the layer V i is a L × m A vector of bits.

3. The high-speed generalized cascade decoder based on FPGA as claimed in claim 1, characterized in that: The total output of the generalized cascade decoder is C = H × .

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