A circuit and detection method of a high-precision encoder speed and frequency detection device

Abstract

A circuit for detecting speed and frequency of an encoder with high precision and a detection method thereof. The method comprises an encoder, an XOR device and a CPU. The encoder generates A and B phase signals. The XOR device performs XOR conversion on the received encoder signals to generate 4X edge signals. The CPU is used to process the 4X edge signal capture time generated by the XOR device and the 4-fold frequency counting of the A and B phase pulses generated on the encoder. The CPU outputs parameters through an internal timer and counter, converts the parameters for speed measurement, calculates the speed frequency, and repeats monitoring and calculation until a stable speed reading is obtained. The method combines the characteristics of CPU chip peripheral resources, uses the system main clock such as 1GHz as the measurement timer, and has an error accuracy of only 1ns. For frequency measurement and period measurement with a 1ms period, the accuracy can reach one millionth.

Description

Technical Field

[0001] The invention discloses a high-precision speed and frequency detection device circuit for an encoder and a detection method thereof, belonging to the technical field of motor control. Background Art

[0002] In the field of modern industrial automation and precision machinery control, accurate speed measurement and control of mechanical equipment is crucial. Encoders, as a common position and speed detection device, are widely used in various automation control systems, such as CNC machine tools, robots, conveying systems, etc. However, the traditional encoder M / T speed measurement method has errors caused by inaccurate pulse counting and unstable time measurement. These errors are particularly obvious in high-speed or low-speed measurements, limiting the overall performance and reliability of the system. Summary of the invention

[0003] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a high-precision encoder speed and frequency detection device circuit and a detection method thereof, so as to solve the problem of errors caused by inaccurate pulse counting and unstable time measurement in the existing traditional encoder M / T speed measurement method.

[0004] In order to achieve the above object, the present invention is implemented through the following technical scheme: a circuit of an encoder high-precision speed and frequency detection device, comprising the following components:

[0005] Encoder: The encoder is used to generate A and B phase signals;

[0006] XOR device: the signal at the encoder output end received at the input end of the XOR device is XOR-converted to generate a 4X edge signal;

[0007] CPU, the input end of the CPU receives the 4X edge signal generated by the output end of the XOR device and the A and B phase pulses generated on the output end of the encoder;

[0008] A timer and a counter are arranged inside the CPU, and the CPU converts and measures the speed through the parameters output by the timer and the counter.

[0009] Furthermore, the output end of the encoder is connected to the A port and the B port on the input side of the XOR device, and the signal that completes the XOR operation is directly connected to the timer in the CPU via the Y port on the output side of the XOR device.

[0010] Furthermore, the circuit is provided with two groups of encoders, and the XOR device and the CPU are both provided with pins capable of receiving signals from the two groups of encoders.

[0011] Furthermore, the CPU is provided with at least two encoder pins for receiving orthogonal signals, the CPU is provided with at least one timer for capturing edge time intervals, and the CPU is provided with a counter for capturing count values.

[0012] Furthermore, the device type of the XOR device is specifically selected from one of the 74LS series, CD74HC series, and 74AVC series.

[0013] Furthermore, the measurement error of the counter does not depend on the number of external pulses.

[0014] Furthermore, a method for detecting speed and frequency of an encoder with high precision is characterized by comprising the following steps:

[0015] S1, receiving the encoder A-phase and B-phase signals through the circuit interfaces XA and XB, performing XOR operation on the signals through the XOR device to generate 4X edge signals;

[0016] S2, pulses XA and XB are used as orthogonal encoding signals and connected to the CPU counter pins TCKLA and TCKLKB. The counter counts up when the A and B edges change, achieving 4 times counting, which is synchronized with the 4X edge change after the XOR device XORs.

[0017] S3, the timer automatically captures the CPU's main frequency TICK value when the 4X edge changes, and the count value of the counter changes at the same time, while monitoring and processing the timer's cycle overflow times n;

[0018] S4. In each millisecond cycle, monitor whether the new timer capture value Tc1 and the counter value P1 are changed from the previous timer capture value Tc0 and the counter value P0. If there is a change, calculate the speed frequency.

[0019] Furthermore, in step S3, monitoring the overflow period needs to ensure that the initial capture time Tc0 and the count value jump P0 are aligned at the same time.

[0020] Furthermore, in the millisecond period of step S4, if no new values ​​of Tc0 and P0 are detected, the next millisecond period is continued to be waited for until a new change is detected and the frequency calculation is then performed.

[0021] Furthermore, the step S4 includes the following steps:

[0022] S41, in each millisecond cycle, the CPU continuously monitors and captures the new value of the timer Tc1 and the new value of the counter P1;

[0023] S42, judging the change, if the values ​​of Tc0 and P0 have changed, that is, Tc0 is not equal to Tc1 or P0 is not equal to P1, then the data is considered valid, if the values ​​of Tc0 and P0 have not changed, the CPU waits for the next millisecond cycle to continuously monitor the change of the new value, and judges if there is a timer cycle overflow flag to perform n counting and self-increment, and clears the timer overflow flag;

[0024] S43, using the formula: (P1-P0) / (Tc1+n*T-Tc0) to calculate the speed frequency, where n is the number of cycle overflows of the timer, and T is the counting period of the timer;

[0025] S44, update the counter count value P1 and the timer capture value Tc1 to P0 and Tc0 variables, clear the timer cycle overflow times n, and perform first-order filtering on the newly calculated speed frequency and filter frequency to generate a smoother new frequency calculation value.

[0026] Furthermore, the measurement error of the speed frequency depends on the main frequency accuracy of the CPU.

[0027] The beneficial effects of the present invention are as follows: when using an encoder to monitor speed with high precision, the user needs to connect the A-phase and B-phase signals of the encoder to the circuit interfaces XA and XB respectively, process the XA and XB signals through an XOR device to generate a 4X edge signal, and also directly connect the A-phase and B-phase signals of the encoder to the orthogonal encoder counting pins TCKLA and TCKLB of the CPU, and initialize the configuration of the orthogonal encoder and timer inside the CPU, set the main frequency of the CPU and the timing period T of the timer, and after all software configurations are completed, start the counter to count the A-phase and B-phase signals generated by the encoder, perform an XOR operation on the signals, and generate an output signal of a 4X edge change. When the timer detects 4 When the X edge changes, the TICK value of the CPU main frequency is automatically captured, the initial capture time Tc0 and the count value P0 are recorded, Tc0 and P0 are monitored in each ms period, the new values ​​Tc1 and P1 are recorded, and the judgment and processing T period timer overflow n times are made. When a new change is detected, the speed frequency is calculated using the formula (P1-P0) / (Tc1+n*T-Tc0), and the monitoring and calculation process is repeated until a stable speed reading is obtained. Combined with the above instructions for use, this application uses the characteristics of the CPU chip peripheral resources and the system main clock (such as a main frequency of 1GHz) as a measurement timer, with an error accuracy of only 1ns. For 1ms period processing frequency and week measurement, the accuracy can reach one millionth. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0029] Figure 1 This is a schematic diagram of the structure of a circuit of a device for detecting speed and frequency of an encoder with high precision according to the present invention;

[0030] Figure 2 A schematic diagram of a flow chart of a method for high-precision speed and frequency detection of an encoder according to the present invention;

[0031] Figure 3 This is a schematic diagram of a further detailed flow chart of step S4 of a method for high-precision speed and frequency detection of an encoder according to the present invention. DETAILED DESCRIPTION

[0032] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further explained below in conjunction with specific implementation methods.

[0033] Figure 1 The present invention is a schematic diagram of the structure of a circuit of a device for detecting speed and frequency of an encoder with high precision.

[0034] like Figure 1 As shown, the present invention provides a technical solution of a high-precision speed and frequency detection device circuit of an encoder and a detection method thereof: a high-precision speed and frequency detection device circuit of an encoder, characterized in that it includes the following components:

[0035] Encoder 1: Encoder 1 is used to generate A and B phase signals;

[0036] XOR device 2, the signal at the output end of encoder 1 received at the input end of XOR device 2 is XOR-converted to generate a 4X edge signal;

[0037] CPU3, the input end of CPU3 receives the 4X edge signal generated by the output end of XOR device 2 and the A and B phase pulses generated by the output end of encoder 1;

[0038] A timer 5 and a counter 4 are provided inside the CPU 3 , and the CPU 3 converts and measures the speed through the parameters output by the timer 5 and the counter 4 .

[0039] In order to realize edge detection and frequency multiplication of the orthogonal encoder signal, the output end of the encoder 1 is connected to the A port and the B port on the input side of the XOR device 2. The signal that completes the XOR operation is directly connected to the timer 5 in the CPU 3 via the Y port on the output side of the XOR device 2.

[0040] In order to realize orthogonal encoding, the circuit is provided with two groups of encoders 1, and the XOR device 2 and the CPU 3 are both provided with pins capable of receiving signals from the two groups of encoders 1.

[0041] In order to effectively receive and process signals and achieve precise control, the CPU 3 is provided with at least two encoder 1 pins to receive orthogonal signals, the CPU 3 is provided with at least one timer 5 to capture edge time intervals, and the CPU 3 is provided with a counter 4 to capture count values.

[0042] In order to increase the usage scenarios, the device selection of the XOR device 2 is specifically one of the 74LS series, CD74HC series, and 74AVC series.

[0043] In order to reduce the error, the measurement error of the counter 4 is not dependent on the number of external pulses.

[0044] Figure 2 This is a flow chart of a method for high-precision speed and frequency detection of an encoder according to the present invention, referring to Figure 2 As shown, in order to improve the accuracy of measurement, the present invention also provides a process of a method for high-precision speed and frequency detection of an encoder, wherein the method for high-precision speed and frequency detection of an encoder is characterized in that it includes the following steps:

[0045] S1, receiving the encoder A phase and B phase signals through the circuit interface XA and XB, the signals are XORed through the XOR device 2 to generate a 4X edge signal;

[0046] S2, pulses XA and XB are used as orthogonal coding signals and connected to the counter 4 pins TCKLA and TCKLKB of CPU3. The counter 4 counts up when the A and B edges change, achieving 4 times counting, which is synchronized with the 4X edge change after XOR device 2;

[0047] S3, timer 5 automatically captures the CPU3 main frequency TICK value when the 4X edge changes, and the count value of counter 4 changes at the same time, and the number of cycle overflows n of timer 5 is monitored and processed;

[0048] S4. In each millisecond cycle, monitor whether the new value timer 5 capture value Tc1 and counter 4 value P1 have changed with the previous timer capture value Tc0 and counter value P0. If there is a change, calculate the speed frequency.

[0049] In order to achieve precise control and monitoring, in step S3, monitoring the overflow period needs to ensure that the initial capture time Tc0 and the count value jump P0 are aligned at the same time.

[0050] In order to realize dynamic monitoring, if no new values ​​of Tc0 and P0 are detected within the millisecond period of step S4, the next millisecond period is waited for until a new change is detected and the frequency calculation is performed again.

[0051] Figure 3This is a further detailed flow chart of step S4 of a method for high-precision speed and frequency detection of an encoder according to the present invention, referring to Figure 3 As shown, in order to improve the accuracy of the collected measurement data, the present invention also provides a process of step S4 in a method for high-precision speed and frequency detection of an encoder, wherein step S4 comprises the following steps:

[0052] S41, in each millisecond cycle, CPU3 continuously monitors and captures the new value Tc1 of timer 5 and the new value P1 of counter 4;

[0053] S42, judging the change, if the values ​​of Tc0 and P0 have changed, that is, Tc0 is not equal to Tc1 or P0 is not equal to P1, then the data is considered valid, if the values ​​of Tc0 and P0 have not changed, CPU3 waits for the next millisecond cycle to continuously monitor the change of the new value, and judges if there is a timer cycle overflow flag to perform n counting and self-increment, and clears the timer overflow flag;

[0054] S43, using the formula: P1-P0 / Tc1+n*T-Tc0 to calculate the speed frequency, where n is the number of cycle overflows of timer 5, and T is the counting period of timer 5;

[0055] S44, update the counter count value P1 and the timer capture value Tc1 to P0 and Tc0 variables, clear the timer cycle overflow times n, and perform first-order filtering on the newly calculated speed frequency and filter frequency to generate a smoother new frequency calculation value.

[0056] In order to improve the accuracy of measurement, the measurement error of the speed frequency depends on the main frequency accuracy of CPU3.

[0057] When using the encoder to monitor the speed with high precision, the user needs to connect the encoder's A-phase and B-phase signals to the circuit interfaces XA and XB respectively, process the XA and XB signals through the XOR device 2 to generate a 4X edge signal, and also directly connect the encoder's A-phase and B-phase signals to the orthogonal encoder counting pins TCKLA and TCKLB of the CPU3, and initialize the configuration of the orthogonal encoder and timer 5 inside the CPU3, set the CPU3's main frequency and the timing period T of the timer 5, and after all the software configurations are completed, start the counter 4 to count the A-phase and The B-phase signal is counted and the signal is XOR-operated to generate an output signal with 4X edge changes. When the timer 5 detects the 4X edge change, it automatically captures the TICK value of the CPU3 main frequency, records the initial capture time Tc0 and the count value P0, monitors Tc0 and P0 in each ms cycle, records the new values ​​Tc1 and P1, and determines whether the T-cycle timer overflows n times. When a new change is detected, the speed frequency is calculated using the formula (P1-P0) / (Tc1+n*T-Tc0), and the monitoring and calculation process is repeated until a stable speed reading is obtained.

[0058] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention. Therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the attached claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims are included in the present invention. Any figure mark in the claims should not be regarded as limiting the claims involved.

[0059] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A high-precision encoder speed and frequency detection device circuit, characterized in that: It includes the following components: The encoder (1) is used to generate A and B phase signals; An XOR device (2) performs XOR conversion on the signal at the output end of the encoder (1) received at the input end of the XOR device (2) to generate a 4X edge signal; CPU (3), the input end of CPU (3) receives the 4X edge signal generated by the output end of the XOR device (2) and the A and B phase pulses generated by the output end of the encoder (1); The CPU (3) is provided with a timer (5) and a counter (4), and the CPU (3) converts and measures the speed using the parameters output by the timer (5) and the counter (4). The measurement error of the counter (4) does not depend on the number of external pulses. Wherein, the timer (5) automatically captures the TICK value of the CPU (3) main frequency when detecting the 4X edge signal change, records the initial capture time Tc0 and the count value P0, monitors Tc0 and P0 in each ms cycle, records the new values ​​Tc1 and P1, and determines and processes the T cycle timer overflow n times, and uses the formula (P1-P0) / (Tc1+n*T-Tc0) to calculate the speed frequency when a new change is detected.

2. The high-precision speed and frequency detection device circuit of an encoder according to claim 1, characterized in that: The output end of the encoder (1) is connected to the A port and the B port on the input side of the XOR device (2), and the signal that completes the XOR operation is directly connected to the timer (5) in the CPU (3) via the Y port on the output side of the XOR device (2).

3. The high-precision speed and frequency detection device circuit of an encoder according to claim 2 is characterized in that: The circuit is provided with two groups of encoders (1), and the XOR device (2) and the CPU (3) are both provided with pins capable of receiving signals from the two groups of encoders (1).

4. The circuit of the encoder high-precision speed and frequency detection device according to claim 1 is characterized in that: The CPU (3) is provided with at least two encoder (1) pins for receiving orthogonal signals, the CPU (3) is provided with at least one timer (5) for capturing edge time intervals, and the CPU (3) is provided with a counter (4) for capturing count values.

5. The circuit of the encoder high-precision speed and frequency detection device according to claim 1 is characterized in that: The device type of the XOR device (2) is specifically selected from the group consisting of 74LS series, CD74HC series, and 74AVC series.

6. A method for detecting speed and frequency of an encoder with high precision, characterized in that: The steps include: S1, receiving encoder A phase and B phase signals through circuit interfaces XA and XB, performing XOR operation on the signals through XOR device (2) to generate 4X edge signals; S2, pulses XA and XB are used as orthogonal coding signals and are connected to the counter (4) pins TCKLA and TCKLKB of the CPU (3). The counter (4) counts up when the A and B edges change, achieving 4 times counting, which is synchronized with the change of the 4X edge signal after the XOR of the XOR device (2); S3, the timer (5) automatically captures the main frequency TICK value of the CPU (3) when the 4X edge signal changes, records the initial capture time Tc0 and the count value P0, and at the same time the count value of the counter (4) changes, and monitors and processes the number of cycle overflows n of the timer (5); Step S4 includes the following steps: S41, in each millisecond cycle, the CPU (3) continuously monitors the new value Tc1 of the capture timer (5) and the new value P1 of the counter (4); S42, judging the change. If the values ​​of Tc0 and P0 have changed, that is, Tc0 is not equal to Tc1 or P0 is not equal to P1, then the data is considered valid. If the values ​​of Tc0 and P0 have not changed, the CPU (3) waits for the next millisecond cycle to continuously monitor the change of the new value, and judges if there is a timer cycle overflow flag to perform n count self-increment, and clears the timer overflow flag; S43, using the formula: (P1-P0) / (Tc1+n*T-Tc0) to calculate the speed frequency, where n is the number of cycle overflows of the timer (5), and T is the counting cycle of the timer (5); S44, respectively update the counter count value P1 and the timer capture value Tc1 to P0 and Tc0 variables, clear the timer cycle overflow times n, and perform first-order filtering on the newly calculated speed frequency and filter frequency to generate a smoother new frequency calculation value.

7. A method for detecting speed and frequency of an encoder with high precision according to claim 6, characterized in that: In step S3, monitoring the overflow period needs to ensure that the initial capture time Tc0 and the count value jump P0 are aligned at the same time.

8. The method for detecting speed and frequency of an encoder with high precision according to claim 6, characterized in that: If no new values ​​of Tc0 and P0 are detected during the millisecond period of step S4, the next millisecond period is continued to be waited for until a new change is detected and the frequency calculation is then performed.

9. The method for detecting speed and frequency of an encoder with high precision according to claim 6, characterized in that: The measurement error of the speed frequency depends on the main frequency accuracy of the CPU (3).

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