A BOOT mode determination method, system and storage medium

Abstract

The present invention discloses a BOOT mode judgment method, system and storage medium, belonging to the technical field of integrated circuits. The method includes: S1: after the power-on reset is released, the gpio0 pin is latched; S2: after the power-on reset or hard reset is released, the gpio1 pin is latched; S3: when the power-on reset release signal is high, the hard reset low level duration is counted; S4: the hard reset low level duration is judged, and when it exceeds the preset clock cycle, it is switched to DFT_MODE mode or TEST_MODE mode according to the gpio0 pin or the gpio1 pin; if the hard reset low level duration does not exceed the preset clock cycle, S5 is executed to make a FUNC mode judgment; S5: the boot mode is selected according to the OB information and the OTP information. Through the time-sharing multiplexing of the gpio pin, the dedicated BOOT pin is replaced to realize the BOOT mode judgment, the number of chip pins is reduced, the package size is reduced, and the package cost is reduced; the design and layout of the PCB board are simplified, the complexity is reduced, and the possibility of errors and failures is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a BOOT mode determination method, system and storage medium. Background Art

[0002] Currently, most of the boot mode decisions of MCU chips on the market rely on dedicated BOOT pins. That is, after the MCU is powered on, the boot mode is determined based on the level (high or low) of the BOOT pin, and the initialization code is loaded from different memories and executed. In the early days when there were fewer boot modes, it was more convenient to use the BOOT pin to start or guide the loading mode of the chip. However, with the enrichment of MCU chip BOOT modes, the number of dedicated BOOT pins has also increased, which has become a major problem for chip costs.

[0003] The prior art has the following technical problems:

[0004] 1. Dedicated BOOT pins will affect the chip package size, PCB design and wiring complexity, and are not conducive to chip cost control.

[0005] 2. The MCU chips on the market have relatively fixed handling of the security features of the BOOT mode and cannot flexibly adapt to customer needs, which reduces the versatility of the chip. Summary of the invention

[0006] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a BOOT mode determination method, system and storage medium.

[0007] The objective of the present invention is achieved through the following technical solutions: The first aspect of the present invention provides: a BOOT mode determination method, comprising the following steps:

[0008] S1: After the power-on reset is released, the gpio0 pin is latched;

[0009] S2: After power-on reset or hard reset is released, the gpio1 pin is latched;

[0010] S3: When the power-on reset release signal is high, the low level duration of the hard reset is counted;

[0011] S4: Determine the low level duration of the hard reset. When it exceeds the preset clock cycle, switch to DFT_MODE mode or TEST_MODE mode according to the gpio0 pin or gpio1 pin. If the low level duration of the hard reset does not exceed the preset clock cycle, execute S5 to make a FUNC mode judgment.

[0012] S5: Select to execute NormalBoot mode, BootStrap mode, SecureBoot mode, SramBoot mode or FlashDirectBoot mode according to OB information and OTP information;

[0013] The gpio0 pin and the gpio1 pin are time-division multiplexed. When a power-on reset or a hard reset is performed, the gpio0 pin and the gpio1 pin are used to determine the startup mode. When the startup mode selection is completed, the por domain locks the pin status of the gpio0 pin and the gpio1 pin.

[0014] Preferably, the preset clock cycle is 512 clock cycles.

[0015] Preferably, when the BootStrap mode is executed, the boot program is started, and the loader is written through the UART or CAN interface. When SecureLevel is equal to 2, only the factory reset and authentication instructions are responded to.

[0016] Preferably, when the SecureBoot mode is executed and the SecureLevel is equal to 2, authentication is performed before performing the mode switching operation.

[0017] Preferably, when the SramBoot mode is executed, the emulator downloads the program to the memory for startup, and if the SecureLevel is not equal to 0, it jumps to the NormalBoot mode.

[0018] Preferably, when the FlashDirectBoot mode is executed, Flash is directly started.

[0019] The second aspect of the present invention provides: a BOOT mode determination system, which is used to implement any of the above-mentioned BOOT mode determination methods, comprising:

[0020] The latch module is used to latch the gpio0 pin after the power-on reset is released; and to latch the gpio1 pin after the power-on reset or hard reset is released;

[0021] A counting module, used for counting the low level duration of hard reset when the power-on reset release signal is high;

[0022] The mode judgment module is used to judge the low-level duration of the hard reset. When it exceeds the preset clock cycle, it switches to the DFT_MODE mode or the TEST_MODE mode according to the gpio0 pin or the gpio1 pin; if the low-level duration of the hard reset does not exceed the preset clock cycle, S5 is executed to make a FUNC mode judgment;

[0023] The mode selection module is used to select the NormalBoot mode, the BootStrap mode, the SecureBoot mode, the SramBoot mode or the FlashDirectBoot mode according to the OB information and the OTP information.

[0024] The third aspect of the present invention provides: a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by a processor, any of the above-mentioned BOOT mode determination methods is implemented.

[0025] The beneficial effects of the present invention are:

[0026] 1) By time-sharing multiplexing of GPIO pins, dedicated BOOT pins are replaced to implement BOOT mode judgment, reducing the number of chip pins, which helps to reduce the package size and packaging cost; simplifying the design and layout of the PCB board, reducing complexity, and reducing the possibility of errors and failures.

[0027] 2) BOOT mode judgment based on security level classification can be flexibly used in working environments with different security requirements of customers. The BOOT mode will determine whether to execute based on the chip security characteristics and level to prevent malicious startup and tampering. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a flow chart of the BOOT mode judgment method;

[0029] Figure 2 This is the decision diagram for switching between DFT_MODE mode, TEST_MODE mode, and FUNC mode. DETAILED DESCRIPTION

[0030] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0031] The existing BOOT mode startup judgment depends on the latch state of the dedicated pin. The present invention replaces the dedicated BOOT pin by using the gpio pin time-sharing multiplexing method. At the same time, it realizes the flexible judgment of the BOOT mode by combining OB (option word) and OTP (one-time programming) information. The startup flow chart is as follows: Figure 1 shown.

[0032] See also Figure 1-Figure 2 The first aspect of the present invention provides: a BOOT mode determination method, comprising the following steps:

[0033] S1: After the power-on reset is released, the gpio0 pin is latched;

[0034] S2: After power-on reset or hard reset is released, the gpio1 pin is latched;

[0035] S3: When the power-on reset release signal is high, the low level duration of the hard reset is counted;

[0036] S4: Determine the low level duration of the hard reset. When it exceeds the preset clock cycle, switch to DFT_MODE mode or TEST_MODE mode according to the gpio0 pin or gpio1 pin. If the low level duration of the hard reset does not exceed the preset clock cycle, execute S5 to make a FUNC mode judgment.

[0037] S5: Select to execute NormalBoot mode, BootStrap mode, SecureBoot mode, SramBoot mode or FlashDirectBoot mode according to OB information and OTP information;

[0038] The gpio0 pin and the gpio1 pin are time-division multiplexed. When a power-on reset or a hard reset is performed, the gpio0 pin and the gpio1 pin are used to determine the startup mode. When the startup mode selection is completed, the por domain locks the pin status of the gpio0 pin and the gpio1 pin.

[0039] In this embodiment, after the power-on reset (rst_por_n) is released, gpio0 is latched; after the power-on reset / hard reset (hard_rst_n), gpio1 is latched; after the power-on reset is released, the low level duration of the hard reset is counted; the low level duration of the hard reset is determined as follows: Figure 2 As shown, if it exceeds 512 clock cycles (hard_rst_ind signal is pulled high to indicate), it switches to DFT_MODE mode or TEST_MODE mode according to gpio0 / 1 (see Table 1 for decision logic), otherwise, it enters the function mode (FUNC) decision;

[0040] Table 1

[0041]

[0042] The decision logic of FUNC mode needs to be implemented based on gpio1 (used as BOOT0) and OB information (n_BOOT1, n_SWBOOT1) (see Table 2 for decision logic). n_SWBOOT1 is the enable control signal of n_BOOT1, which is used to determine whether to enable n_BOOT1 information. OB information works in the system reset (sys_rst_n) domain. Each system reset will re-determine the boot mode. Except for FlashDirectBoot mode, other modes need to be started through BOOTROM.

[0043] Table 2

[0044]

[0045] The OTP information TESTCODE is used for sample debugging. Before the CP / FT stage, TESTCODE is not equal to 0, SecureLevel is ignored, and the above-mentioned full-mode startup is supported; after the sample debugging is completed, TESTCODE is equal to 0, SecureLevel information is enabled, FlashDirectBoot will be disabled, and other BOOT modes will be executed according to the security level division (see Table 3 for the execution of BOOT modes at different security levels).

[0046] Table 3

[0047]

[0048] DFT_MODE and TEST_MODE can be switched by following hard_rst_n reset; FUNC can be switched by following sys_rst_n reset; but these two situations can only be switched by por reset.

[0049] The time-sharing multiplexing of the two gpio pins (gpio0 / 1) is used as the BOOT pin function in mode judgment and as an output function in function mode. When por and hard reset, the gpio0 / 1 pin replaces the dedicated BOOT pin to judge the boot mode. After the mode selection is completed, the por domain will lock the gpio pin state, so that when the system is reset, the mode switching between FUNC will not care about the gpio pin state, and will not limit the output function of the gpio pin.

[0050] In some embodiments, the preset clock cycle is 512 clock cycles.

[0051] In some embodiments, when the BootStrap mode is executed, the boot program is started and the loader is written through the UART or CAN interface. When the SecureLevel is equal to 2, only the factory reset and authentication instructions are responded to.

[0052] In some embodiments, when the SecureBoot mode is executed and SecureLevel is equal to 2, authentication is performed before performing the switch mode operation.

[0053] In some embodiments, when the SramBoot mode is executed, the emulator downloads the program to the memory for startup, and if the SecureLevel is not equal to 0, it jumps to the NormalBoot mode.

[0054] In some embodiments, when FlashDirectBoot mode is executed, Flash boots directly.

[0055] NormalBoot: The default boot mode of the chip;

[0056] BootStrap: boot program starts, writes loader program through UART or CAN interface, when SecureLevel is 2, only responds to factory reset and authentication commands to prevent tampering;

[0057] SecureBoot: secure boot mode. When SecureLevel is 2, authentication is required to switch to other modes.

[0058] SramBoot: Sram boot mode, the emulator downloads the program to Sram boot, it is valid when SecureLevel is equal to 0, otherwise it jumps to NormalBoot mode;

[0059] FlashDirectBoot: escape mode, Flash direct boot, only supported in the CP / FT stage.

[0060] The second aspect of the present invention provides: a BOOT mode determination system, which is used to implement any of the above-mentioned BOOT mode determination methods, comprising:

[0061] The latch module is used to latch the gpio0 pin after the power-on reset is released; and to latch the gpio1 pin after the power-on reset or hard reset is released;

[0062] A counting module, used for counting the low level duration of hard reset when the power-on reset release signal is high;

[0063] The mode judgment module is used to judge the low-level duration of the hard reset. When it exceeds the preset clock cycle, it switches to the DFT_MODE mode or the TEST_MODE mode according to the gpio0 pin or the gpio1 pin; if the low-level duration of the hard reset does not exceed the preset clock cycle, S5 is executed to make a FUNC mode judgment;

[0064] The mode selection module is used to select the NormalBoot mode, the BootStrap mode, the SecureBoot mode, the SramBoot mode or the FlashDirectBoot mode according to the OB information and the OTP information.

[0065] The third aspect of the present invention provides: a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by a processor, any of the above-mentioned BOOT mode determination methods is implemented.

[0066] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.

Claims

1. A BOOT mode determination method, characterized in that: The following steps are involved: S1: After the power-on reset is released, the gpio0 pin is latched; S2: After power-on reset or hard reset is released, the gpio1 pin is latched; S3: When the power-on reset release signal is high, the low level duration of the hard reset is counted; S4: Determine the low level duration of the hard reset. When it exceeds the preset clock cycle, switch to DFT_MODE mode or TEST_MODE mode according to the gpio0 pin or gpio1 pin. If the low level duration of the hard reset does not exceed the preset clock cycle, execute S5 to make a FUNC mode judgment. S5: Select to execute NormalBoot mode, BootStrap mode, SecureBoot mode, SramBoot mode or FlashDirectBoot mode according to OB information and OTP information; The gpio0 pin and the gpio1 pin are time-division multiplexed. When a power-on reset or a hard reset is performed, the gpio0 pin and the gpio1 pin are used to determine the startup mode. When the startup mode selection is completed, the por domain locks the pin status of the gpio0 pin and the gpio1 pin.

2. The BOOT mode determination method according to claim 1, characterized in that: The preset clock cycle is 512 clock cycles.

3. The BOOT mode determination method according to claim 1, characterized in that: When the BootStrap mode is executed, the bootloader is started and the loader is written through the UART or CAN interface. When SecureLevel is equal to 2, it only responds to factory reset and authentication commands.

4. The BOOT mode determination method according to claim 1, characterized in that: When the SecureBoot mode is executed and the SecureLevel is equal to 2, authentication is performed before performing the mode switching operation.

5. The BOOT mode determination method according to claim 1, characterized in that: When executing SramBoot mode, the emulator downloads the program to the memory to start. If SecureLevel is not equal to 0, it jumps to NormalBoot mode.

6. The BOOT mode determination method according to claim 1, characterized in that: When the FlashDirectBoot mode is executed, the Flash is directly started.

7. A BOOT mode determination system, characterized in that: The method for implementing the BOOT mode determination method according to any one of claims 1 to 6 comprises: The latch module is used to latch the gpio0 pin after the power-on reset is released; and to latch the gpio1 pin after the power-on reset or hard reset is released; A counting module, used for counting the low level duration of hard reset when the power-on reset release signal is high; The mode judgment module is used to judge the low-level duration of the hard reset. When it exceeds the preset clock cycle, it switches to the DFT_MODE mode or the TEST_MODE mode according to the gpio0 pin or the gpio1 pin; if the low-level duration of the hard reset does not exceed the preset clock cycle, S5 is executed to make a FUNC mode judgment; The mode selection module is used to select the NormalBoot mode, the BootStrap mode, the SecureBoot mode, the SramBoot mode or the FlashDirectBoot mode according to the OB information and the OTP information.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by the processor, the BOOT mode determination method according to any one of claims 1 to 6 is implemented.

Images