Reset circuit

Abstract

The invention relates to a reset circuit, the reset circuit comprises a clock module, a processor and a reset control module, the reset control module is used for sending a power-on reset signal to the processor in the power-on starting process of a system to which the reset circuit belongs, the power-on reset signal comprises a low level of a first preset duration and a high level of a second preset duration, when the power-on reset signal is at a low level, the power-on reset mark is reset; the processor is used for executing power-on reset after receiving the power-on reset signal, and setting a power-on reset mark as 1 after the power-on reset is executed; and the reset control module is also used for detecting the power-on reset mark when the power-on reset signal is at the high level, and determining that the power-on reset of the processor is completed when the power-on reset mark is detected to be 1. According to the embodiment of the invention, the reliability of the reset circuit can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a reset circuit. Background Art

[0002] The reset circuit is a circuit used to control and ensure the correct startup of digital circuits. It can initialize all related circuits to a known state when the system is powered on and force the system to restart when necessary. The normal operation of the processor is inseparable from the reset circuit.

[0003] In the related art, a reset IC (Integrated Circuit Chip) chip or a RC (Resistor-Capacitance) charging and discharging circuit is used to power on and reset the processor. However, the above reset circuits are not flexible and have poor reliability. In a complex circuit use environment, there is a risk that the processor cannot operate normally due to reset failure. Therefore, a reset circuit with high reliability is urgently needed. Summary of the invention

[0004] In view of this, a reset circuit is proposed.

[0005] In the first aspect, an embodiment of the present application provides a reset circuit, which includes a clock module, a processor and a reset control module; the clock module is connected to the processor and the reset control module, and the processor is connected to the reset control module; the reset control module is implemented by a programmable logic device; the clock module is used to: provide a first clock signal to the processor and the reset control module; the reset control module is used to: during the power-on startup process of the system to which the reset circuit belongs, according to the first clock signal, send a power-on reset signal to the processor, the power-on reset signal including a low level of a first preset duration and a high level of a second preset duration; during the period when the power-on reset signal is at a low level, clear a power-on reset mark; the processor is used to: after receiving the power-on reset signal, perform a power-on reset; after the power-on reset is completed, set the power-on reset mark to 1; the reset control module is also used to: during the period when the power-on reset signal is at a high level, detect the power-on reset mark; when the power-on reset mark is detected to be 1, determine that the power-on reset of the processor is completed.

[0006] In some possible implementations, the reset control module also includes a reset state machine, and while the power-on reset signal is at a low level, the reset state machine is in an idle state; after the power-on reset signal becomes a high level, the reset state machine jumps to a power-on reset handshake state.

[0007] In some possible implementations, the reset control module is used to: when detecting that the power-on reset mark is 1, send first information to the reset state machine, the first information being used to indicate that the power-on reset mark is 1; the reset state machine is used to: when receiving the first information, jump to the watchdog waiting state.

[0008] In some possible implementations, the reset control module is used to: when it is detected that the power-on reset flag is always 0 during the period when the power-on reset signal is at a high level, resend the power-on reset signal to the processor.

[0009] In some possible implementations, the reset state machine is used to: in the watchdog waiting state, after waiting for a third preset time period according to the first clock signal, jump to the watchdog detection state.

[0010] In some possible implementations, the processor is used to: continuously send a periodic square wave signal to the reset control module according to the first clock signal during the running of the application; the reset control module is used to: when the reset state machine is in a watchdog detection state, detect the signal value of the square wave signal and calculate the retention time of the signal value; when the retention time of the signal value is greater than or equal to a preset time threshold, send second information to the reset state machine to make the reset state machine jump to the watchdog reset state; when the reset state machine is in the watchdog reset state, send a watchdog reset signal to the processor to make the processor perform a watchdog reset.

[0011] In some possible implementations, the reset control module is used to: clear the holding time when the signal value of the square wave signal changes.

[0012] In some possible implementations, the reset state machine is used to: jump to the watchdog waiting state after the watchdog reset signal ends.

[0013] In some possible implementations, the reset control module further includes a first register and a second register, the first register is used to store the power-on reset flag, and the second register is used to store the square wave signal.

[0014] In some possible implementations, the clock module includes a crystal oscillator and a clock buffer, the crystal oscillator is connected to the clock buffer, and the clock buffer is connected to the processor and the reset control module; the crystal oscillator is used to: generate a second clock signal; the clock buffer is used to: receive the second clock signal, and fan out the first clock signal according to the second clock signal.

[0015] The reset circuit of the embodiment of the present application includes a clock module, a processor and a reset control module implemented by a programmable logic device, which is used to reset the processor. During the power-on startup process of the system to which the reset circuit belongs, the reset control module sends a power-on reset signal (including a low level of a first preset duration and a high level of a second preset duration) to the processor and clears the power-on reset mark during the low level of the power-on reset signal; after receiving the power-on reset signal, the processor performs a power-on reset, and after the power-on reset is completed, the power-on reset mark is set to 1; at the same time, the reset control module detects the power-on reset mark during the high level of the power-on reset signal, and when the power-on reset mark is detected to be 1, it is determined that the processor power-on reset is completed. The reset circuit of the embodiment of the present application, when the processor is powered on, the reset control module sends a power-on reset signal to the processor, and the processor sets the power-on reset mark to 1 and the reset control module detects the power-on reset mark to confirm the power-on reset of the processor, and the reset control module is implemented by a programmable logic device, which is flexible in configuration and easy to use, thereby improving the reliability of the reset circuit and the robustness of the system.

[0016] These and other aspects of the present application will become more apparent from the following description of the embodiment(s). BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A schematic diagram showing a reset circuit according to an embodiment of the present application;

[0019] Figure 2 A schematic diagram showing a reset circuit according to an embodiment of the present application;

[0020] Figure 3 A state transition diagram of a reset state machine according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0022] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0023] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0024] In order to solve the above technical problems, the present application provides a reset circuit. The reset circuit of the embodiment of the present application includes a clock module, a processor and a reset control module; the clock module is connected to the processor and the reset control module, and the processor is connected to the reset control module; the reset control module is implemented by a programmable logic device. The clock module is used to provide a first clock signal to the processor and the reset control module. The reset control module is used to send a power-on reset signal to the processor according to the first clock signal during the power-on startup process of the system to which the reset circuit belongs, and the power-on reset signal includes a low level of a first preset duration and a high level of a second preset duration; during the period when the power-on reset signal is at a low level, the power-on reset mark is cleared; the processor is used to perform a power-on reset after receiving the power-on reset signal; after the power-on reset is completed, the power-on reset mark is set to 1; the reset control module is also used to detect the power-on reset mark during the period when the power-on reset signal is at a high level; when the power-on reset mark is detected to be 1, it is determined that the power-on reset of the processor is completed.

[0025] The reset circuit of the embodiment of the present application includes a clock module, a processor and a reset control module implemented by a programmable logic device, which is used to reset the processor. During the power-on startup process of the system to which the reset circuit belongs, the reset control module sends a power-on reset signal (including a low level of a first preset duration and a high level of a second preset duration) to the processor and clears the power-on reset mark during the period when the power-on reset signal is at a low level; after receiving the power-on reset signal, the processor performs a power-on reset, and after the power-on reset is completed, the power-on reset mark is set to 1; at the same time, the reset control module detects the power-on reset mark during the period when the power-on reset signal is at a high level, and when the power-on reset mark is detected to be 1, it is determined that the processor power-on reset is completed.

[0026] The reset circuit of the embodiment of the present application, when the processor is powered on and reset, the reset control module sends a power-on reset signal to the processor, and the processor sets the power-on reset mark to 1 and the reset control module detects the power-on reset mark to perform a handshake confirmation on the power-on reset of the processor. Moreover, the reset control module is implemented by a programmable logic device, and has flexible configuration and is easy to use, thereby being able to improve the reliability of the reset circuit and the robustness of the system.

[0027] Figure 1 FIG. 1 is a schematic diagram of a reset circuit according to an embodiment of the present application. Figure 1 As shown, the reset circuit 10 includes a clock module 110, a processor 120 and a reset control module 130. The clock module 110 is connected to the processor 120 and the reset control module 130. The processor 120 is connected to the reset control module 130. The reset circuit 10 is used to reset the processor 120.

[0028] The clock module 110 is used as a clock source of the reset circuit 10 to provide the processor 120 and the reset control module 130 with a first clock signal required for their operation. The processor 120 and the reset control module 130 can perform timing, counting and other processing according to the first clock signal.

[0029] The processor 120 is used to run the application program. The processor 120 may be a central processing unit (CPU), a digital signal processor (DSP), a system on chip (SoC), etc. The present application does not limit the specific type of the processor 120.

[0030] The reset control module 130 can be used to perform reset processing such as power-on reset, power-on startup abnormal reset (i.e., continuing to perform power-on reset after the first power-on reset of the processor fails during the startup process), and watchdog reset (reset during the operation of the processor) on the processor 120. The reset control module 130 is implemented by a programmable logic device. For example, the reset control module 130 can be implemented by a field programmable gate array (FPGA), a complex programmable logic device (CPLD), etc. This application does not limit the specific type of the programmable logic device.

[0031] Figure 2 FIG. 1 is a schematic diagram of a reset circuit according to an embodiment of the present application. Figure 2 As shown, the reset circuit 10 includes a clock module 110, a processor 120 and a reset control module 130. The reset circuit 10 is used to reset the processor 120.

[0032] The clock module 110 includes a crystal oscillator (i.e., a crystal oscillator) and a clock buffer. The crystal oscillator is connected to the clock buffer, and the clock buffer is connected to the processor 120 and the reset control module 130. The crystal oscillator is used as a clock source to generate a second clock signal and send the second clock signal to the clock buffer. The clock buffer receives the second clock signal from the crystal oscillator, and fans out the first clock signal required for the operation of the processor 120 and the reset control module 130 according to the second clock signal, so that the clock signal matches the operation requirements of the processor and the reset control module.

[0033] The reset control module 130 includes a first register, a second register and a reset state machine. The first register is used to store a power-on reset flag, so the first register can also be called a power-on reset flag register. The second register is used to store a periodic square wave signal sent by the processor to the reset control module during the running of the application. The periodic square wave signal can also be called a dog feeding signal, so the second register can also be called a dog feeding signal register.

[0034] The reset state machine is used to set various states required for the operation of the reset circuit, and completes state migration when specific conditions are met. The reset state machine includes five states: idle state (idle, also known as initial state), power-on reset handshake state (por-hd), watchdog wait state (wdg-wait), watchdog detection state (wdg-chk) and watchdog reset state (wdg-rst). The reset state machine can be implemented by programming using very-high-speed integrated circuit hardware description language (Very-High-Speed ​​Integrated Circuit Hardware Description Language, VHDL), hardware description language (such as Verilog Hardware Description Language, Verilog HDL), etc., and can also be implemented by graphical input. Counting personnel in this field can determine the specific implementation of the reset state machine according to actual conditions, and this application does not limit this.

[0035] The following is an exemplary description of the process of powering on and resetting the processor.

[0036] During the power-on startup process of the system to which the reset circuit belongs, after the reset control module is loaded, counting or timing is performed according to the first clock signal, and a power-on reset signal is sent to the processor. The power-on reset signal includes a low level (value is 0) of a first preset duration (for example, 20ms) and a high level (value is 1) of a second preset duration (for example, 80ms), and the power-on reset signal is sent to the reset pin of the processor. After the processor receives the power-on reset signal, it immediately performs a power-on reset, and after the power-on reset is completed, the processor sets the power-on reset mark to 1, and at the same time, the processor enters the application, that is, the processor starts to execute the application. In the case of storing the power-on reset mark through the first register, the processor can write 1 to the first register through the local bus, that is, the power-on reset mark in the first register is set to 1.

[0037] In the above example, the power-on reset signal is valid at a low level (value is 0), that is, during the low level of the first preset duration, the processor performs a power-on reset, and during the high level of the second preset duration, the processor and the reset control module perform a power-on reset handshake. In some embodiments, the power-on reset signal can also be valid at a high level (value is 1), so that the power-on reset signal may include a high level of the first preset duration and a low level of the second preset duration. In the embodiment of the present application, the low level of the power-on reset signal is used as an example for explanation.

[0038] During the period when the power-on reset signal is at a low level, the reset control module clears the power-on reset flag, that is, sets the power-on reset flag to 0. In the case where the power-on reset flag is stored in the first register, during the period when the power-on reset signal is at a low level, the reset control module sets the power-on reset flag in the first register to 0. Wherein, the power-on reset flag of 0 indicates that the processor has not executed the power-on reset or the power-on reset execution has failed, and the power-on reset flag of 1 indicates that the processor has completed the power-on reset execution.

[0039] During the period when the power-on reset signal is at a low level, the reset state machine is in an idle state. The idle state can be regarded as the initial state of the reset state machine.

[0040] During the period when the power-on reset signal is at a high level, the reset control module can detect the power-on reset mark in the first register, and when the power-on reset mark is detected to be 1, it is determined that the processor power-on reset is completed. When the reset control module detects that the power-on reset mark is 1, it sends first information to the reset state machine, and the first information is used to indicate that the power-on reset mark is 1. When the reset state machine receives the first information, it jumps to the watchdog waiting state.

[0041] In some possible implementations, when the reset control module detects that the power-on reset mark is always 0 during the period when the power-on reset signal is at a high level, it can be considered that the processor power-on reset execution has failed, and the reset control module re-sends the power-on reset signal to the processor to make the processor re-execute the power-on reset process until the power-on reset mark is detected to be 1, so that the power-on reset process can be re-performed after the processor fails to reset due to interference when powered on, until the power-on reset is successful, realizing automatic reset after power-on reset failure, and improving the reliability of the reset circuit. During the process of the processor re-executing the power-on reset, the reset state machine is still in the power-on reset handshake state.

[0042] After the processor is powered on and reset in the above manner, the processor enters the application program, that is, starts to execute the application program.

[0043] The following is an exemplary description of the process of watchdog reset (reset after an application program in the processor runs away).

[0044] In the process of running the application, the processor can count or time according to the first clock signal, and continuously send a periodic square wave signal to the reset control module. The square wave signal here can be regarded as the heartbeat signal of the processor, and its period can be, for example, 10ms. The present application does not limit the specific period of the square wave signal. In the case where the reset control module includes a second register, the processor can continuously write the periodic square wave signal to the second register.

[0045] In some possible implementations, when the reset state machine is in the watchdog waiting state, it can count or time according to the first clock signal, wait for a third preset time (e.g., 300ms), and then jump to the watchdog detection state. The third waiting time is to ensure that the processor starts to run the application program normally and starts to continuously write the periodic square wave signal to the second register.

[0046] In some possible implementations, when the reset state machine is in the watchdog detection state, the reset control module can detect the signal value of the square wave signal in the second register and calculate the retention time of the signal value. When the signal value of the square wave signal changes (i.e., the signal edge of the square wave signal), the retention time is cleared.

[0047] For example, assuming that the period of the square wave signal is 10ms, and the signal values ​​of the square wave signal are 0, 1, 0, 1, etc., then when the reset control module detects that the signal value of the square wave signal is 0, it starts to calculate the retention time of the signal value; when it detects that the signal value changes from 0 to 1, it clears the retention time and restarts the calculation of the retention time; when it detects that the signal value changes from 1 to 0, it clears the retention time and restarts the calculation of the retention time, and so on, to calculate the retention time of the signal value. Since the period of the square wave signal is 10ms, under normal circumstances, the retention time of each signal value is 5ms.

[0048] After the reset control module calculates the retention time of the signal value of the square wave signal, it can determine whether the retention time is greater than or equal to a preset time threshold (for example, 300ms); if the retention time is less than the time threshold, it can be considered that the application in the processor is running normally, and the signal value of the square wave signal can continue to be detected. In this process, the reset state machine is always in the watchdog detection state.

[0049] In some possible implementations, when the signal value is maintained for a time greater than or equal to a preset time threshold (e.g., 300ms), the reset control module believes that the processor has not sent a square wave signal (i.e., a heartbeat signal) for a long time, and the application in the processor has run away. In this case, the reset control module sends a second message to the reset state machine, and the second message is used to indicate that the signal value of the square wave signal has timed out. When the reset state machine receives the second message, it jumps to the watchdog reset state.

[0050] In the watchdog reset state, the reset control module sends a watchdog reset signal to the processor, and the watchdog reset signal includes a low level of a fourth preset duration (e.g., 20ms). After receiving the watchdog reset signal, the processor performs a watchdog reset. The watchdog reset is a reset performed after the application in the processor runs away, and its purpose is to restore the processor to its initial state.

[0051] After the watchdog reset signal ends, the reset state machine jumps to the watchdog waiting state. In the watchdog waiting state, after waiting for the third preset time, the reset state machine jumps to the watchdog detection state. In the watchdog detection state, the reset control module continues to detect the signal value of the square wave signal and its holding time in the above manner.

[0052] Through the above method, the reset control module can dynamically detect the periodic square wave signal sent by the processor. When the signal value of the square wave signal is maintained for a period greater than or equal to the duration threshold, it is considered that the application in the processor has run away, and then a watchdog reset signal is sent to the processor to cause the processor to perform a watchdog reset, thereby achieving automatic reset of the processor when the application runs away, thereby reducing the risk of the processor being unable to reset after the application runs away, and improving the reliability of the reset circuit.

[0053] It should be noted that the specific values ​​of the first preset time length, the second preset time length, the third preset time length, the fourth preset time length, and the time length threshold in the above embodiments can be set by those skilled in the art according to actual conditions, and this application does not impose any restrictions on this.

[0054] Figure 3 FIG. 2 shows a state transition diagram of a reset state machine according to an embodiment of the present application. Figure 3 As shown, the reset state machine includes five states: an initial state 31, a power-on reset handshake state 32, a watchdog waiting state 33, a watchdog detection state 34 and a watchdog reset state 35.

[0055] During the power-on startup process of the system to which the reset circuit belongs, while the power-on reset signal is at a low level, the reset state machine is in an idle state 31. After the power-on reset signal becomes a high level, the reset state machine jumps from the idle state 31 to the power-on reset handshake state 32.

[0056] In the power-on reset handshake state 32, the reset control module sends first information to the reset state machine when detecting that the power-on reset mark is 1, and the first information is used to indicate that the power-on reset mark is 1; when the reset state machine receives the first information, it jumps from the power-on reset handshake state 32 to the watchdog waiting state 33. When the reset control module detects that the power-on reset mark is 0, it re-sends the power-on reset signal to the processor so that the processor re-executes the power-on reset. During this process, the reset state machine remains in the power-on reset handshake state 32.

[0057] In the watchdog waiting state 33 , according to the first clock signal, the reset state machine waits for a third preset time period and then jumps to the watchdog detection state 34 .

[0058] In the watchdog detection state 34, the processor continuously sends a periodic square wave signal to the reset control module according to the first clock signal while running the application; the reset control module detects the signal value of the square wave signal sent by the processor and calculates the retention time of the signal value; when the retention time of the signal value is greater than or equal to the preset time threshold, the reset state machine sends second information, which is used to indicate that the retention time of the signal value of the square wave signal is greater than or equal to the time threshold; when the reset state machine receives the second information, it jumps from the watchdog detection state 34 to the watchdog reset state 35.

[0059] In the watchdog reset state 35, the reset control module sends a watchdog reset signal of a fourth preset duration to the processor to cause the processor to perform a watchdog reset. After the watchdog reset signal ends, the reset state machine jumps from the watchdog reset state 35 to the watchdog waiting state 33, thereby continuing to perform the above-mentioned related processing, which will not be repeated here.

[0060] The reset circuit of the embodiment of the present application supports power-on reset of the processor, power-on startup abnormal reset (i.e., continuing to power-on reset the processor after the first power-on reset fails during the startup process) and watchdog reset, so that it can automatically reset the processor when it encounters interference reset failure or the application program runs away when it is powered on, thereby improving the reliability of the reset circuit and the robustness of the system.

[0061] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the device, system, method and computer program product according to multiple embodiments of the present application. In this regard, each square frame in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the functions marked in the square frame can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square frames can actually be executed substantially in parallel, and they can also be executed in reverse order sometimes, depending on the functions involved.

[0062] It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented by hardware that performs the corresponding function or action (such as a circuit or ASIC (Application Specific Integrated Circuit)), or can be implemented by a combination of hardware and software, such as firmware.

[0063] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0064] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those of ordinary skill in the art without departing from the scope of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A reset circuit, characterized in that: The reset circuit includes a clock module, a processor and a reset control module; the clock module is connected to the processor and the reset control module, and the processor is connected to the reset control module; the reset control module is implemented by a programmable logic device; The clock module is used to: provide a first clock signal to the processor and the reset control module; The reset control module is used for: During the power-on startup process of the system to which the reset circuit belongs, a power-on reset signal is sent to the processor according to the first clock signal, wherein the power-on reset signal includes a low level of a first preset duration and a high level of a second preset duration; while the power-on reset signal is at a low level, a power-on reset flag is cleared; The processor is used to: After receiving the power-on reset signal, performing a power-on reset; after the power-on reset is completed, setting the power-on reset flag to 1; The reset control module is also used for: During the period when the power-on reset signal is at a high level, the power-on reset mark is detected; when it is detected that the power-on reset mark is 1, it is determined that the power-on reset of the processor is completed.

2. The reset circuit according to claim 1, characterized in that: The reset control module also includes a reset state machine, which is in an idle state while the power-on reset signal is at a low level; after the power-on reset signal becomes at a high level, the reset state machine jumps to a power-on reset handshake state.

3. The reset circuit according to claim 2, characterized in that: The reset control module is used to: when detecting that the power-on reset mark is 1, send first information to the reset state machine, wherein the first information is used to indicate that the power-on reset mark is 1; The reset state machine is used to jump to the watchdog waiting state when receiving the first information.

4. The reset circuit according to claim 1, characterized in that: The reset control module is used for: when it is detected that the power-on reset flag is always 0 during the period when the power-on reset signal is at a high level, resending the power-on reset signal to the processor.

5. The reset circuit according to claim 3, characterized in that: The reset state machine is used to: in the watchdog waiting state, after waiting for a third preset time period according to the first clock signal, jump to the watchdog detection state.

6. The reset circuit according to claim 5, characterized in that: The processor is used to: during the running of the application, continuously send a periodic square wave signal to the reset control module according to the first clock signal; The reset control module is used to: when the reset state machine is in the watchdog detection state, detect the signal value of the square wave signal and calculate the holding time of the signal value; When the retention time of the signal value is greater than or equal to a preset time threshold, sending second information to the reset state machine to make the reset state machine jump to the watchdog reset state; When the reset state machine is in the watchdog reset state, a watchdog reset signal is sent to the processor to enable the processor to perform a watchdog reset.

7. The reset circuit according to claim 6, characterized in that: The reset control module is used to reset the holding time when the signal value of the square wave signal changes.

8. The reset circuit according to claim 6, characterized in that: The reset state machine is used to jump to the watchdog waiting state after the watchdog reset signal ends.

9. The reset circuit according to claim 6, characterized in that: The reset control module further includes a first register and a second register, wherein the first register is used to store the power-on reset mark, and the second register is used to store the square wave signal.

10. The reset circuit according to claim 1, characterized in that: The clock module includes a crystal oscillator and a clock buffer, the crystal oscillator is connected to the clock buffer, and the clock buffer is connected to the processor and the reset control module; The crystal oscillator is used to: generate a second clock signal; The clock buffer is used to receive the second clock signal and fan out the first clock signal according to the second clock signal.

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