A fault location method and device, storage medium and computer program product

Abstract

The present application discloses a fault location method and device, a storage medium and a computer program product, and relates to the field of computer technology. The method includes: obtaining the address information of a server; wherein the address information includes the address information of input and output ports, the system address topology, and the address information of each peripheral device; when a peripheral device fault is detected, determining the fault address corresponding to the peripheral device fault; determining the corresponding fault address type according to the fault address, and performing fault location based on the fault address type and the address information of the server. The fault location method provided by the present application realizes automatic location of peripheral device faults by a baseboard management controller, and the baseboard management controller collects the address information of the server in advance. When a peripheral device fault is detected, the fault location is automatically realized according to the fault address and the pre-collected address information, realizing full automation of fault data collection and fault location, and improving the efficiency of fault location.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and more specifically, to a fault location method and device, a storage medium, and a computer program product. Background Art

[0002] With the explosive growth of data volume and the popularity of cloud computing, the increase in workload, hardware density and high-performance requirements has led to an exponential growth in the scale of data centers. This trend has directly led to downtime caused by equipment failure becoming one of the biggest challenges in maintaining stable operations.

[0003] ADDC (Autonomous Debug Data Collection) technology can collect debug data with minimal human intervention. However, ADDC is only responsible for automating the collection of fault registers during the fault register collection phase. Register parsing needs to be done manually using parsing tools, and fault location is manually implemented, which results in low fault location efficiency.

[0004] Therefore, how to improve the fault location efficiency is a technical problem that those skilled in the art need to solve. Summary of the invention

[0005] The purpose of the present application is to provide a fault location method and device, a storage medium and a computer program product, which improve the efficiency of fault location.

[0006] To achieve the above object, the present application provides a fault location method, which is applied to a baseboard management controller in a server, and the method includes:

[0007] Acquire address information of the server; wherein the address information includes address information of input and output ports, system address topology, and address information of each peripheral device;

[0008] When a peripheral device fault is detected, determining a fault address corresponding to the peripheral device fault;

[0009] A corresponding fault address type is determined according to the fault address, and fault location is performed based on the fault address type and address information of the server.

[0010] Before determining the fault address corresponding to the peripheral fault, the method further includes:

[0011] Acquire register information corresponding to the fault from a hardware error storage area, and determine whether the fault is a timer timeout error according to the register information;

[0012] If so, the fault is determined to be a peripheral fault, and the step of determining a fault address corresponding to the peripheral fault is performed.

[0013] The fault address type includes any one or a combination of any one of a memory address space address, a memory mapped input / output address, a configuration space address of a preset bus protocol, an input / output address of a preset bus protocol, and a system function address.

[0014] Wherein, if the fault address belongs to the memory address space address or the memory mapped input / output address, the fault location is performed based on the fault address type and the address information of the server, including:

[0015] Determining whether the fault address belongs to the memory address space address according to the system address topology;

[0016] If the fault address belongs to the memory address space address, it is determined that the peripheral fault belongs to a memory fault, and the fault address is translated into a memory address;

[0017] If the fault address belongs to the memory-mapped input / output address, the faulty peripheral device corresponding to the fault address is matched according to the address information of each peripheral device.

[0018] Among them, the address information of each peripheral includes bus device function information and memory mapping input and output information;

[0019] Accordingly, matching the faulty peripheral device corresponding to the faulty address according to the address information of each peripheral device includes:

[0020] The fault address is matched with the memory mapping input and output information of each peripheral device, the successfully matched peripheral device is determined to be the faulty peripheral device, and the bus device function information of the faulty peripheral device is determined.

[0021] Wherein, if the fault address belongs to the configuration space address of the preset bus protocol, the fault location is performed based on the fault address type and the address information of the server, including:

[0022] The bus device function information of the faulty peripheral device is determined in the fault address according to the addressing rule of the preset bus protocol.

[0023] Wherein, if the fault address belongs to the input / output address of the preset bus protocol, the fault location is performed based on the fault address type and the address information of the server, including:

[0024] The faulty peripheral device corresponding to the faulty address is matched according to the address information of the input and output ports.

[0025] Wherein, if the fault address belongs to the system function address, the fault location is performed based on the fault address type and the address information of the server, including:

[0026] It is determined that the peripheral device fault is a processor fault.

[0027] After locating the fault based on the fault address type and the address information of the server, the method further includes:

[0028] Generate a fault alarm based on the fault location result.

[0029] The fault alarm is generated based on the fault location result, including:

[0030] If the peripheral device fault is a memory fault, a fault alarm of a memory uncorrectable error is generated; wherein the fault alarm includes a memory address of the memory fault.

[0031] The fault alarm is generated based on the fault location result, including:

[0032] If the peripheral device fault is a related fault of the preset bus protocol, a fault alarm information of an unrecoverable error of the faulty peripheral device is generated; wherein the fault alarm includes bus device function information of the faulty peripheral device.

[0033] The fault alarm is generated based on the fault location result, including:

[0034] If the peripheral fault is a processor fault, a processor machine check exception fault alarm is generated.

[0035] To achieve the above object, the present application provides a fault location device, which is applied to a baseboard management controller in a server, and the device includes:

[0036] An acquisition module, used to acquire address information of the server; wherein the address information includes address information of input and output ports, system address topology, and address information of each peripheral device;

[0037] A determination module, used for determining a fault address corresponding to the peripheral fault when a peripheral fault is detected;

[0038] A positioning module is used to determine a corresponding fault address type according to the fault address, and perform fault positioning based on the fault address type and address information of the server.

[0039] To achieve the above objectives, the present application provides an electronic device, including:

[0040] Memory for storing computer programs;

[0041] A processor is used to implement the steps of the above-mentioned fault location method when executing the computer program.

[0042] To achieve the above objectives, the present application provides a non-volatile storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above fault location method are implemented.

[0043] To achieve the above objectives, the present application provides a computer program product, including a computer program, which implements the steps of the above fault location method when executed by a processor.

[0044] It can be seen from the above scheme that a fault locating method provided by the present application is applied to a baseboard management controller in a server, and the method includes: obtaining address information of the server; wherein the address information includes address information of input and output ports, system address topology, and address information of each peripheral device; when a peripheral device fault is detected, determining a fault address corresponding to the peripheral device fault; determining a corresponding fault address type according to the fault address, and locating the fault based on the fault address type and the address information of the server.

[0045] The fault location method provided by the present application realizes automatic location of peripheral faults by a baseboard management controller, and the baseboard management controller collects the address information of the server in advance. When a peripheral fault is detected, the fault location is automatically realized according to the fault address and the pre-collected address information, so that the collection of fault data and fault location are fully automated, the efficiency of fault location is improved, the downtime for troubleshooting is minimized, and the availability of server products is improved. The present application also discloses a fault location device, an electronic device, a non-volatile storage medium, and a computer program product, which can also achieve the above technical effects.

[0046] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. The drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific implementation methods, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:

[0048] Figure 1 It is an architecture diagram of a server in the related technology;

[0049] Figure 2is a flow chart of a fault location method according to an exemplary embodiment;

[0050] Figure 3 is a schematic diagram of a system address topology according to an exemplary embodiment;

[0051] Figure 4 is a flow chart of another fault location method according to an exemplary embodiment;

[0052] Figure 5 An architectural diagram of a server in an application embodiment provided by this application;

[0053] Figure 6 is a structural diagram of a fault location device according to an exemplary embodiment;

[0054] Figure 7 The figure is a structural diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. In addition, in the embodiments of the present application, "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0056] The ADDC (Autonomous Debug Data Collection) technology provided by AMD can collect debug data with minimal human intervention. In related technologies, the analyzer analysis tool provided by AMD can be used to analyze fault data and locate faults.

[0057] In related technologies, such as Figure 1As shown in the figure, hardware errors include peripheral failures, such as PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) device, memory, CXL (Compute Express Link, a high-speed interconnect technology) device errors, etc., as well as processor failures. The processor detection and recording mechanism includes error detection and processor error recording mechanisms, which are implemented by the AMD platform processor machine check mechanism (MACHINE-CHECK ARCHITECTURE, MCA). The processor contains logic and registers for detecting, recording and correcting errors in data or control paths. The machine check mechanism defines a device that records processor and system hardware errors and reports them to system software. This enables system software to play a strategic role in the recovery and diagnosis of hardware errors. The baseboard controller (Baseboard Management Controller, BMC) obtains fault data through APML (Advanced Platform Management Link) and packages the acquired fault registers into a two-level Crashdump file. Remote Analysis System: When a fault occurs, the automatically packaged Crashdump file can be transmitted to the remote analysis system via the network. The remote analysis system can manually analyze the fault using the analyzer analysis tool provided by AMD to determine the source of the fault. For example, the MEDT (AMD Machine Error Decode Tool) tool is a command-line utility that can decode MCA errors into error messages. It also provides the function of decoding the physical address to the fault row and column address of the memory particle.

[0058] It can be seen that in the relevant technology, ADDC is only responsible for realizing automated collection work in the fault register collection stage. The register parsing rules are not automatically implemented and need to be manually parsed using the AMD parsing tool. For example, when a WDT (Watchdog Timer) timeout error occurs, the fault address parsing is completely manually implemented. It is necessary to first determine the space where the fault address falls: In the Linux system, the cat / proc / iomem command can be used to determine whether the fault address belongs to the memory or the PCIE device. When the fault address falls into the PCIE space, use the lspci command to determine which peripheral the fault address belongs to. When the fault address falls into the memory space, the AMD MEDT tool needs to be used to parse which memory the address belongs to.

[0059] Therefore, the baseboard management controller realizes automatic location of peripheral faults. The baseboard management controller collects the address information of the server in advance. When a peripheral fault is detected, the fault is automatically located according to the fault address and the pre-collected address information, thereby realizing complete automation of fault data collection and fault location, improving the efficiency of fault location, minimizing the downtime for troubleshooting, and improving the availability of server products.

[0060] The embodiment of the present application discloses a fault location method, which improves the efficiency of fault location.

[0061] See also Figure 2 , a flowchart of a fault location method according to an exemplary embodiment is shown, such as Figure 2 As shown, including:

[0062] S101: Acquire address information of a server; wherein the address information includes address information of input and output ports, system address topology, and address information of each peripheral device;

[0063] The executor of this embodiment is the baseboard management controller in the server. In the specific implementation, the baseboard management controller pre-acquires the address information of the server, including the address information of the input and output ports, the system address topology, and the address information of each peripheral. The address information of each peripheral includes bus device function information and memory mapping input and output information.

[0064] The address information of the input and output ports can be collected by the operating system and passed to the baseboard management controller. In a specific implementation, each time the server is started, the Linux operating system is entered, and the self-starting IO report daemon is used to obtain the address information of the system input and output ports through the command "cat / proc / ioports" and pass it to the BMC.

[0065] For example, the address information of the input and output ports is as follows:

[0066] 0000-02e7: PCI Bus 0000:00; / / Indicates that the devices on PCI bus 0 (usually the primary PCI bus) occupy the I / O port address range from 0000 to 02E7.

[0067] 0000-001f: dma1; / / Indicates that the first DMA (Direct Memory Access) controller occupies the address range from 0000 to 001F.

[0068] 0020-0021: pic1; / / Indicates that the first programmable interrupt controller (PIC) occupies the address range from 0020 to 0021.

[0069] 0040-0043: timer0; / / indicates that the first timer (Timer 0) occupies the address range from 0040 to 0043.

[0070] 0050-0053: timer1; / / indicates that the second timer (Timer 1) occupies the address range from 0050 to 0053.

[0071] 0060-0060: keyboard; / / Indicates that the keyboard controller occupies address 0060.

[0072] 0061-0061: PNP0800:00; / / Indicates that a Plug and Play device occupies address 0061.

[0073] 0064-0064: keyboard; / / Indicates that another keyboard controller occupies address 0064.

[0074] 0070-0071: rtc0; / / Indicates that the real-time clock (Real-Time Clock) 0 occupies the address 0070 to 0071.

[0075] 0080-008f: dma page reg; / / Indicates that the DMA page register occupies the address range from 0080 to 008F.

[0076] 00a0-00a1: pic2; / / Indicates that the second programmable interrupt controller occupies the address range of 00A0 to 00A1.

[0077] 00c0-00df: dma2; / / Indicates that the second DMA controller occupies the address range from 00C0 to 00DF.

[0078] 00f0-00ff: fpu; / / Indicates that the floating point unit (FPU) occupies the address range from 00F0 to 00FF.

[0079] 02f8-02ff: serial; / / Indicates that a serial port occupies the address range of 02F8 to 02FF.

[0080] 0300-03af: PCI Bus 0000:00; / / Respectively indicates that PCI bus 0 and a certain device occupy the address range from 0300 to 03AF.

[0081] 03b0-03df: PCI Bus 0000:c0; / / Respectively indicate that PCI bus 0 and a certain device occupy the address range from 03B0 to 03DF.

[0082] 03f8-03ff: serial; / / indicates that another serial port occupies the address range of 03F8 to 03FF.

[0083] 0400-0cf7: PCI Bus 0000:00; / / Indicates that the devices on PCI bus 0 occupy the address range from 0400 to 0CF7.

[0084] 040b-040b: pnp 00:02; / / Indicates that the plug-and-play device occupies the corresponding address.

[0085] 04d0-04d1: pnp 00:02; / / Indicates that the plug-and-play device occupies the corresponding address.

[0086] 04d6-04d6: pnp 00:02; / / Indicates that the plug-and-play device occupies the corresponding address.

[0087] 0800-089f: pnp 00:02; / / Indicates that the plug-and-play device occupies the corresponding address.

[0088] 0800-0803: ACPI PM1a_EVT_BLK; / / indicates the ACPI-related I / O port address range.

[0089] 0804-0805: ACPI PM1a_CNT_BLK; / / Indicates the I / O port address range related to ACPI (Advanced Configuration and Power Interface).

[0090] 0808-080b: ACPI PM _TMR; / / Indicates the ACPI-related I / O port address range.

[0091] 0820-0827: ACPI GPE0_BLK; / / Indicates the ACPI-related I / O port address range.

[0092] 0900-090f: pnp 00:02; / / Indicates that the plug-and-play device occupies the corresponding address.

[0093] 0910-091f: pnp 00:02; / / Indicates that the plug-and-play device occupies the corresponding address.

[0094] 0b00-0b0f: pnp 00:02; / / Indicates that the plug-and-play device occupies the corresponding address.

[0095] 0b00-0b08: piix4_smbus; / / Indicates that the PIIX4 SMBus (System Management Bus) controller occupies the address range from 0B00 to 0B08.

[0096] 0b20-0b3f: pnp 00:02; / / Indicates that the plug-and-play device occupies the corresponding address.

[0097] 0b20-0b28: piix4_smbus; / / Indicates that the PIIX4 SMBus controller occupies the address range of 0B20 to 0B28.

[0098] 0c00-0c01: pnp 00:02; / / Indicates that the plug-and-play device occupies the corresponding address.

[0099] 0c14-0c14: pnp 00:02; / / Indicates that the plug-and-play device occupies the corresponding address.

[0100] The system address topology can be sent from the BIOS (Basic Input Output System) to the BMC. During the machine startup phase, the BIOS sends the system address topology to the BMC for BMC diagnosis. For example, Figure 3 As shown in the figure, in the system address topology, the addresses below 4G space include BIOS FW and Reserved (BIOS firmware and reserved area), MMIO Above Pcie Cfg (memory mapped I / O above PCIe configuration space), Pcie ConfigurationSpace (PCIe configuration space), MMIO Below Pcie Cfg (memory mapped I / O below PCIe configuration space), L-DRAM: low memory DRAM (Dynamic Random Access Memory), and the addresses above 4G space include MMIO for RootBridge x (0~7): memory mapped I / O of root bridge x (0~7) and H-DRAM: high memory DRAM.

[0101] The address information of each peripheral can also be collected by BIOS during the machine startup phase and sent to BMC. For example, the address information of a device is as follows:

[0102] PCIE 0 INFO: Device BDF=0x10.0x0.0x0, RootPort BDF=0xf. 0x0.0x0;

[0103] PCIE_0_MMIO_0: Type: 0x4 (MMIO32), Start:0x9B000000, End: 0x9BFFFFFF;

[0104] PCIE_0_MMIO_1: Type: 0x7 (MMIO64-Prefetchable), Start: 0x5C000000000, End: 0x5DFFFFFFFFF;

[0105] PCIE 0 MMIO 2: Type: 0x7 (MMIO64-Prefetchable), Start: 0x5F428000000, End: 0x5F429FFFFFF.

[0106] In general, the device's BDF (bus-device-function) information is collected, as well as MMIO32 (32-bit non-prefetched memory-mapped I / O resources), MMIO64 (64-bit non-prefetched memory-mapped I / O resources), MMIO32-prefetchable (32-bit prefetched memory-mapped I / O resources), and MMIO64-prefetchable (64-bit prefetched memory-mapped I / O resources) resource information.

[0107] S102: When a peripheral device fault is detected, determining a fault address corresponding to the peripheral device fault;

[0108] In the specific implementation, when a hardware fatal error occurs, after the processor detects a fatal fault, the system will generate a syncflood to stop the error propagation and prevent pollution. At the moment the error occurs, the processor will lock the error state, including the program counter, register state, cache content, etc., to facilitate subsequent error analysis and debugging. By stopping the operation of the processor and related buses, erroneous data is prevented from being written to the memory or external memory to avoid data pollution. The machine check mechanism (MCA) of the processor detects the fault content information and records it in the MACHINE-CHECK Bank, waiting for BMC to obtain it.

[0109] As a feasible implementation method, before determining the fault address corresponding to the peripheral fault, it also includes: obtaining register information corresponding to the fault from the hardware error storage area, and judging whether the fault is a timer timeout error according to the register information; if so, judging that the fault is a peripheral fault, and executing the step of determining the fault address corresponding to the peripheral fault.

[0110] In a specific implementation, after the BMC collects the fault register information, it parses the MACHINE-CHECK Bank information. When the parsed error type is a WDT timeout error, the fault address is recorded in the registers DF::OrigWdtAddrLogLo and DF::OrigWdtAddrLogHi.

[0111] S103: Determine a corresponding fault address type according to the fault address, and locate the fault based on the fault address type and address information of the server.

[0112] In the specific implementation, the address type to which the fault address belongs is determined by analyzing and identifying the features of the fault address, including memory address space address, memory mapping input and output address, configuration space address of the preset bus protocol, input and output address of the preset bus protocol, system function address, etc. Then, combined with the detailed address mapping information of the server, the fault address is matched with the corresponding hardware resource or memory area in the system to accurately locate the fault, including memory fault, fault related to the preset bus protocol, and processor fault.

[0113] If the fault address belongs to the memory address space address, the peripheral fault is a memory fault. If the fault address belongs to the memory mapped input / output address, the configuration space address of the preset bus protocol, or the input / output address of the preset bus protocol, the peripheral fault is a fault related to the preset bus protocol, where the preset bus protocol can be the PCIe protocol. If the peripheral fault belongs to the system function address, the peripheral fault is a processor fault.

[0114] As a preferred implementation, after fault location is performed based on the fault address type and the address information of the server, it also includes: generating a fault alarm based on the fault location result. In a specific implementation, if the peripheral fault is a memory fault, a fault alarm of an uncorrectable CPU Error (UCE) is generated; wherein the fault alarm includes the memory address of the memory fault. If the peripheral fault is a related fault of a preset bus protocol, a fault alarm information of an uncorrectable error (fatal) of the faulty peripheral is generated; wherein the fault alarm includes the bus device function information of the faulty peripheral. If the peripheral fault is a processor fault, a fault alarm of a processor machine check exception is generated.

[0115] The fault location method provided in the embodiment of the present application realizes automatic location of peripheral faults by a baseboard management controller. The baseboard management controller collects address information of the server in advance. When a peripheral fault is detected, the fault location is automatically realized according to the fault address and the pre-collected address information, thereby realizing full automation of fault data collection and fault location, improving the efficiency of fault location, minimizing the downtime for troubleshooting, and improving the availability of server products.

[0116] The embodiment of the present application discloses a fault location method. Compared with the previous embodiment, this embodiment further explains and optimizes the technical solution. Specifically:

[0117] See also Figure 4 , a flowchart of another fault location method according to an exemplary embodiment is shown, such as Figure 4 As shown, including:

[0118] S201: Acquire address information of a server; wherein the address information includes address information of input and output ports, system address topology, and address information of each peripheral device;

[0119] S202: When a peripheral device fault is detected, determining a fault address corresponding to the peripheral device fault;

[0120] S203: Determine a corresponding fault address type according to the fault address;

[0121] S204: If the fault address belongs to the memory address space address or the memory mapped input / output address, when the fault address belongs to the memory address space address, it is determined that the peripheral fault belongs to a memory fault, and the fault address is translated into a memory address; when the fault address belongs to the memory mapped input / output address, the faulty peripheral corresponding to the fault address is matched according to the address information of each peripheral;

[0122] In a specific implementation, when the fault address belongs to a memory address space address or a memory mapped input / output address, the system address topology matching determines whether the fault address belongs to a memory address space address or a memory mapped input / output address. If the fault address belongs to a memory address space address, the BIOS performs DRAM address resolution while waiting for the system to restart, and the fault address can be translated into a memory address (memory channel-dimm-rank-bank-row-column). If the fault address belongs to a memory mapped input / output address, the BDF (bus-device-function) of the faulty peripheral is matched according to the address information of each peripheral. That is, the fault address is matched with the memory mapped input / output information of each peripheral, and the successfully matched peripheral is determined to be a faulty peripheral, and the bus device function information of the faulty peripheral is determined.

[0123] S205: If the fault address belongs to the configuration space address of the preset bus protocol, determine the bus device function information of the faulty peripheral in the fault address according to the addressing rule of the preset bus protocol;

[0124] In a specific implementation, if the fault address belongs to the configuration space address of the preset bus protocol, the bus is determined according to bits 20-27 of the fault address, the device is determined according to bits 15-19, and the function is determined according to bits 12-13, thereby parsing the BDF of the faulty peripheral.

[0125] S206: if the fault address belongs to the input / output address of the preset bus protocol, matching the faulty peripheral device corresponding to the fault address according to the address information of the input / output port;

[0126] In a specific implementation, if the fault address belongs to the input / output address of the preset bus protocol, the BMC matches bits 0-15 of the fault address with the address information of the input / output port, thereby determining the faulty peripheral.

[0127] S207: If the fault address belongs to the system function address, it is determined that the peripheral fault belongs to a processor fault.

[0128] In a specific implementation, if the fault address belongs to a system function address, it is an internal error of AMD, that is, a processor failure, and it is prompted to consult AMD to troubleshoot the fault.

[0129] It should be noted that in a server system, if a processor failure is detected and there is a redundant design, the system will automatically perform a series of carefully designed failover steps to ensure service continuity and data integrity. First, the system will confirm the fault state and activate the backup processor, while seamlessly migrating services and operations to this hot backup or cold backup redundant unit. After the backup processor takes over, the system will gradually restore services, isolate the faulty processor, and notify the system administrator. Subsequently, the administrator will perform necessary maintenance and repair work, and conduct thorough testing after the problem is resolved to ensure the stability of the system. Throughout the process, the system's goal is to minimize downtime and maintain the reliability of mission-critical operations. This redundancy and automatic switching mechanism significantly improves the availability of the system and effectively protects the system from interruptions even in the face of serious failures at the processor level.

[0130] The fault location method provided in the embodiment of the present application realizes automatic location of peripheral faults by a baseboard management controller. The baseboard management controller collects address information of the server in advance. When a peripheral fault is detected, the fault location is automatically realized according to the fault address and the pre-collected address information, thereby realizing full automation of fault data collection and fault location, and improving the efficiency of fault location.

[0131] The following describes an application embodiment provided by the present application. The structural diagram of a server provided by this embodiment is as follows: Figure 5 As shown, it includes faulty peripherals, processors, basic input and output systems, baseboard management controllers, and operating systems.

[0132] Operating system: When the computer is turned on for the first time, it boots into the Linux operating system, obtains IO resources, and sends the IO resources to the baseboard management controller through the IOreport daemon process developed in the background.

[0133] Basic Input and Output System: responsible for the collection and transmission of system address space, the integration and transmission of peripheral resources, and the translation of memory addresses.

[0134] Hardware fatal fault occurrence and detection: When a hardware fatal error occurs, the processor detects the fatal fault and the system generates a syncflood to stop the error propagation and prevent contamination. The processor's machine check mechanism (MCA) detects the fault content information and records it in the MACHINE-CHECK Bank, waiting for the baseboard management controller to obtain it.

[0135] Baseboard management controller: responsible for obtaining fault register information through the APML interface, fault analysis, fault classification, fault location, and fault alarm.

[0136] A fault locating device provided in an embodiment of the present application is introduced below. The fault locating device described below and the fault locating method described above can be referenced to each other.

[0137] See also Figure 6 , a structural diagram of a fault location device according to an exemplary embodiment is shown, such as Figure 6 As shown, including:

[0138] The acquisition module 601 is used to acquire the address information of the server; wherein the address information includes the address information of the input and output ports, the system address topology, and the address information of each peripheral device;

[0139] A determination module 602 is used to determine a fault address corresponding to the peripheral device fault when a peripheral device fault is detected;

[0140] The positioning module 603 is used to determine the corresponding fault address type according to the fault address, and perform fault positioning based on the fault address type and the address information of the server.

[0141] The fault locating device provided in the embodiment of the present application realizes automatic locating of peripheral faults by a baseboard management controller. The baseboard management controller collects address information of the server in advance. When a peripheral fault is detected, the fault is automatically located according to the fault address and the pre-collected address information, thereby realizing full automation of fault data collection and fault locating, improving the efficiency of fault locating, minimizing the downtime for troubleshooting, and improving the availability of server products.

[0142] Based on the above embodiment, as a preferred implementation, it also includes:

[0143] The judgment module is used to obtain the register information corresponding to the fault from the hardware error storage area, and judge whether the fault is a timer timeout error according to the register information; if so, the fault is determined to be a peripheral fault, and the working process of the determination module 602 is started.

[0144] Based on the above embodiments, as a preferred implementation mode, the fault address type includes any one or a combination of any one of the memory address space address, memory mapped input and output address, configuration space address of a preset bus protocol, input and output address of a preset bus protocol, and system function address.

[0145] On the basis of the above embodiments, as a preferred implementation mode, if the fault address belongs to the memory address space address or the memory mapped input and output address, the positioning module 603 is specifically used to: determine whether the fault address belongs to the memory address space address according to the system address topology; if the fault address belongs to the memory address space address, determine that the peripheral fault belongs to a memory fault, and translate the fault address into a memory address; if the fault address belongs to the memory mapped input and output address, match the faulty peripheral corresponding to the fault address according to the address information of each peripheral.

[0146] Based on the above embodiment, as a preferred implementation mode, the address information of each peripheral device includes bus device function information and memory mapping input and output information;

[0147] Accordingly, the positioning module 603 is specifically used to: match the fault address with the memory mapping input and output information of each peripheral, determine that the successfully matched peripheral is a faulty peripheral, and determine the bus device function information of the faulty peripheral.

[0148] Based on the above embodiments, as a preferred implementation, if the fault address belongs to the configuration space address of the preset bus protocol, the positioning module 603 is specifically used to: determine the bus device function information of the faulty peripheral in the fault address according to the addressing rules of the preset bus protocol.

[0149] Based on the above embodiment, as a preferred implementation, if the fault address belongs to the input / output address of the preset bus protocol, the positioning module 603 is specifically used to match the faulty peripheral corresponding to the fault address according to the address information of the input / output port.

[0150] Based on the above embodiment, as a preferred implementation, if the fault address belongs to the system function address, the positioning module 603 is specifically used to determine that the peripheral fault belongs to a processor fault.

[0151] Based on the above embodiment, as a preferred implementation, it also includes:

[0152] The generation module is used to generate a fault alarm based on the fault location result.

[0153] Based on the above embodiment, as a preferred implementation mode, the generation module is specifically used for: if the peripheral fault is a memory fault, generating a fault alarm of a memory uncorrectable error; wherein the fault alarm includes a memory address of the memory fault.

[0154] On the basis of the above embodiments, as a preferred implementation mode, the generation module is specifically used for: if the peripheral fault belongs to a related fault of the preset bus protocol, then generating fault alarm information of an unrepairable error of the faulty peripheral; wherein the fault alarm includes bus device function information of the faulty peripheral.

[0155] Based on the above embodiment, as a preferred implementation mode, the generating module is specifically used for: if the peripheral fault is a processor fault, generating a fault alarm of a processor machine check exception.

[0156] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0157] Based on the hardware implementation of the above program modules, and in order to implement the method of the embodiment of the present application, the embodiment of the present application further provides an electronic device, Figure 7 FIG. 1 is a structural diagram of an electronic device according to an exemplary embodiment. Figure 7 As shown, the electronic equipment includes:

[0158] Communication interface 1, capable of exchanging information with other devices such as network devices;

[0159] The processor 2 is connected to the communication interface 1 to implement information exchange with other devices and is used to execute the fault location method provided by one or more technical solutions when running a computer program. The computer program is stored in the memory 3.

[0160] Of course, in actual application, the various components in the electronic device are coupled together through the bus system 4. It can be understood that the bus system 4 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 4 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 7 Various buses are labeled as bus system 4.

[0161] The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program used to operate on the electronic device.

[0162] It can be understood that the memory 3 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAMbus random access memory (DRRAM, Direct Rambus Random Access Memory).The memory 3 described in the embodiments of the present application is intended to include but is not limited to these and any other suitable types of memories.

[0163] The method disclosed in the above embodiment of the present application can be applied to the processor 2, or implemented by the processor 2. The processor 2 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 2 or the instruction in the form of software. The above processor 2 may be a general-purpose processor, a DSP, or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 2 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. In combination with the steps of the method disclosed in the embodiment of the present application, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in the memory 3, and the processor 2 reads the program in the memory 3 and completes the steps of the above method in combination with its hardware.

[0164] When the processor 2 executes the program, the corresponding processes in the various methods of the embodiments of the present application are implemented, which will not be repeated here for the sake of brevity.

[0165] In an exemplary embodiment, the embodiment of the present application further provides a non-volatile storage medium storing a computer program, which can be executed by the processor 2 to complete the steps of the aforementioned method.

[0166] In an exemplary embodiment, the present application also provides a computer program product, including a computer program, which is executed by the processor 2 to complete the steps of the aforementioned method.

[0167] A person of ordinary skill in the art can understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to computer program instructions, and the aforementioned computer program can be stored in a non-volatile storage medium. When the computer program is executed, it executes the steps of the above-mentioned method embodiment. Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a non-volatile storage medium. Based on this understanding, the technical solution of the embodiment of the present application can be essentially or partly embodied in the form of a software product, which is stored in a non-volatile storage medium and includes a number of instructions for an electronic device (which can be a personal computer, a server, a network device, etc.) to execute all or part of the methods described in each embodiment of the present application.

[0168] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A fault location method, characterized in that: A baseboard management controller applied to a server, the method comprising: Acquire address information of the server; wherein the address information includes address information of input and output ports, system address topology, and address information of each peripheral device; Acquire register information corresponding to the fault from a hardware error storage area, and determine whether the fault is a timer timeout error according to the register information; If yes, determine that the fault is a peripheral fault, and determine the fault address corresponding to the peripheral fault; Determine a corresponding fault address type according to the fault address; the fault address type includes any one or a combination of any one of a memory address space address, a memory mapped input / output address, a configuration space address of a preset bus protocol, an input / output address of a preset bus protocol, and a system function address; Performing fault location based on the fault address type and the address information of the server, including any one or a combination of a memory fault, a preset bus protocol related fault, and a processor fault; The performing of fault location based on the fault address type and the address information of the server includes: If the fault address belongs to the memory address space address, the peripheral fault belongs to the memory fault; if the fault address belongs to the memory mapped input and output address, the configuration space address of the preset bus protocol, or the input and output address of the preset bus protocol, the peripheral fault belongs to the preset bus protocol related fault; if the peripheral fault belongs to the system function address, the peripheral fault belongs to the processor fault; Wherein, if the fault address belongs to the memory-mapped input / output address, matching the faulty peripheral corresponding to the fault address according to the address information of each peripheral; If the fault address belongs to the configuration space address of the preset bus protocol, determining the bus device function information of the faulty peripheral in the fault address according to the addressing rule of the preset bus protocol; If the fault address belongs to the input / output address of the preset bus protocol, the faulty peripheral device corresponding to the fault address is matched according to the address information of the input / output port.

2. The fault location method according to claim 1, characterized in that: If the fault address belongs to the memory address space address or the memory mapped input / output address, the fault location is performed based on the fault address type and the address information of the server, including: Determine whether the fault address belongs to the memory address space address according to the system address topology; If the fault address belongs to the memory address space address, it is determined that the peripheral fault belongs to a memory fault, and the fault address is translated into a memory address; If the fault address belongs to the memory-mapped input / output address, the faulty peripheral device corresponding to the fault address is matched according to the address information of each peripheral device.

3. The fault location method according to claim 2, characterized in that: The address information of each peripheral includes bus device function information and memory mapped input and output information; Accordingly, matching the faulty peripheral device corresponding to the faulty address according to the address information of each peripheral device includes: The fault address is matched with the memory mapping input and output information of each peripheral device, the successfully matched peripheral device is determined to be the faulty peripheral device, and the bus device function information of the faulty peripheral device is determined.

4. The fault location method according to claim 1, characterized in that: After locating the fault based on the fault address type and the address information of the server, the method further includes: Generate a fault alarm based on the fault location result.

5. The fault location method according to claim 4, characterized in that: Generate fault alarms based on fault location results, including: If the peripheral device fault is a memory fault, a fault alarm of a memory uncorrectable error is generated; wherein the fault alarm includes a memory address of the memory fault.

6. The fault location method according to claim 4, characterized in that: Generate fault alarms based on fault location results, including: If the peripheral device fault is a related fault of the preset bus protocol, a fault alarm information of an unrecoverable error of the faulty peripheral device is generated; wherein the fault alarm includes bus device function information of the faulty peripheral device.

7. The fault location method according to claim 4, characterized in that: Generate fault alarms based on fault location results, including: If the peripheral fault is a processor fault, a processor machine check exception fault alarm is generated.

8. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the fault location method according to any one of claims 1 to 7 when executing the computer program.

9. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a computer program, and when the computer program is executed, the steps of the fault location method according to any one of claims 1 to 7 are implemented.

10. A computer program product, characterized in that It comprises a computer program, which implements the steps of the fault location method according to any one of claims 1 to 7 when being executed.

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