A method, device, equipment and medium for detecting server memory failure

Abstract

The present invention relates to the field of computer technology, and discloses a method, device, equipment and medium for detecting server memory faults, which periodically inspects target memory units with hard faults, and performs offline processing on the memory pages where the target memory units are located. When a hard fault exists in a memory unit adjacent to the target memory unit, the memory page where the hard fault unit is located is processed offline. When the number of hard fault units in the row and column area where the target memory unit and the hard fault unit are located is greater than or equal to a set threshold, the memory page corresponding to the row and column area is processed offline. By detecting the memory units around the target memory unit, the memory units with hard faults can be identified earlier, significantly reducing the delay from the occurrence of the fault to its detection. By performing offline processing on the memory pages corresponding to the row and column areas with high risks, it helps to prevent the spread of errors, reduce the risk of data corruption, and improve the stability and reliability of the overall system.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device, equipment and medium for detecting a server memory failure. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used for fast data storage and retrieval. In DRAM cells, data is stored on capacitors in the form of electric charges, but these charges gradually leak out. To prevent data loss, external memory refresh circuits periodically rewrite the data in the capacitors to restore them to their original charge. However, this mechanism is susceptible to interference from various factors. When a DRAM chip fails, the data read from the cell may be different from the stored value, resulting in memory errors. These memory errors have become a key factor in server component failures, negatively affecting system reliability, availability, and maintainability.

[0003] The common offline strategy is based on the error rate statistics over the past period of time, that is, when X errors are reached in the past T hours, the page is processed offline. Although this implementation method improves the stability and reliability of the system to a certain extent, it requires that the failure must occur repeatedly and accumulate to a certain threshold before it can be identified, resulting in a significant delay from the occurrence of the failure to its detection. This delay may allow errors to spread, affect system performance, and even cause data corruption.

[0004] It can be seen that how to improve the timeliness of memory fault identification is a problem that technical personnel in this field need to solve. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide a method, device, equipment and medium for detecting a server memory fault, which can solve the problem of significant delay in memory fault detection.

[0006] In order to solve the above technical problems, an embodiment of the present invention provides a method for detecting a server memory failure, comprising:

[0007] Periodically inspecting a target memory unit with a hard fault, and performing offline processing on a memory page where the target memory unit is located;

[0008] In the case where a memory cell adjacent to the target memory cell has a hard fault, performing offline processing on the memory page where the hard fault cell is located;

[0009] When the number of hard fault cells in the row and column region where the target memory cell and the hard fault cell are located is greater than or equal to a set threshold, offline processing is performed on the memory page corresponding to the row and column region.

[0010] On the one hand, the target memory units with hard faults that are periodically inspected include:

[0011] periodically determining whether the error correction code reports a memory error according to a set first time interval;

[0012] In the case where there is a first memory unit with a number of failures greater than or equal to a hard failure threshold during the inspection process, the first memory unit is determined to be a hard failure, and the address of the first memory unit is recorded in the first storage space;

[0013] Recording the address of the second memory unit having a number of failures less than the hard failure threshold during the inspection process into the second storage space;

[0014] Perform fault detection on the second memory unit corresponding to the address recorded in the second storage space at a set second time interval, determine the faulty second memory unit as a hard fault, and transfer the address of the faulty second memory unit to the first storage space.

[0015] On the one hand, performing fault detection on the second memory unit corresponding to the address recorded in the second storage space at a set second time interval, and determining the faulty second memory unit as a hard fault includes:

[0016] Determining whether the address of the second memory unit is recorded in the second storage space;

[0017] In a case where the address of the second memory unit is recorded in the second storage space, write-zero and write-one operations are respectively performed on the second memory unit according to the address of the second memory unit to obtain a fault detection result;

[0018] When the fault detection result indicates that a fault exists, the faulty second memory unit is determined to be a hard fault.

[0019] On the one hand, it also includes:

[0020] When the fault detection result is that there is no fault, the address of the second memory unit that does not have the fault is deleted from the second storage space.

[0021] On the one hand, when a memory cell adjacent to the target memory cell has a hard fault, performing offline processing on a memory page where the hard fault cell is located includes:

[0022] Reading the address of the target memory unit from the first storage space;

[0023] According to the address of the target memory cell, determine the memory cell adjacent to the target memory cell, and respectively perform write-zero and write-one operations on the memory cells adjacent to the target memory cell to obtain a fault detection result;

[0024] When the fault detection result indicates that a fault exists, the memory page where the faulty memory unit is located is processed offline, and the address of the faulty memory unit is recorded in the first storage space.

[0025] On the one hand, when the number of hard fault cells in the row and column region where the target memory cell and the hard fault cell are located is greater than or equal to a set threshold, performing offline processing on the memory page corresponding to the row and column region includes:

[0026] Based on the addresses recorded in the first storage space, counting the number of memory cells with hard faults in the same row and the same column;

[0027] In the case of a target row where the number of memory cells with hard failures is greater than or equal to the regional threshold, offline processing is performed on the memory page corresponding to the target row;

[0028] In the case of a target column where the number of memory cells with hard failures is greater than or equal to the regional threshold, offline processing is performed on the memory page corresponding to the target column.

[0029] On the one hand, it also includes:

[0030] Counting all memory units with hard faults according to the addresses recorded in the first storage space;

[0031] Based on the distribution of all memory cells with hard faults, determine the areas to be tested;

[0032] Determine the fault density corresponding to each of the areas to be tested according to the number of memory cells corresponding to each area to be tested and the number of memory cells with hard faults;

[0033] In the case that there is a target to-be-tested area whose fault density is greater than a density threshold, fault processing is performed on a memory page corresponding to the target to-be-tested area.

[0034] On the one hand, based on the distribution of all memory cells with hard faults, the areas to be tested are determined to include:

[0035] Treat each memory cell with hard fault as a test point;

[0036] According to the set k-order distance, determine the k-order neighborhood of each point to be tested;

[0037] Based on the k-order distance and the distance between each to-be-tested point contained in the k-order neighborhood of the target to-be-tested point and the target to-be-tested point, determining the outlier value of the target to-be-tested point; wherein the target to-be-tested point is any one to-be-tested point among all the to-be-tested points;

[0038] In the case that the outlier value is greater than the set outlier threshold, the target to-be-tested point is deleted, and a to-be-tested area is divided based on the remaining to-be-tested points.

[0039] On the one hand, based on the k-order distance and the distance between each to-be-tested point included in the k-order neighborhood of the target to-be-tested point and the target to-be-tested point, determining the outlier value of the target to-be-tested point includes:

[0040] Determine the reachable distance of the target to-be-tested point according to the distance between the target to-be-tested point and its neighborhood point and the k-order distance; wherein the neighborhood point is any one to-be-tested point other than the target to-be-tested point among all to-be-tested points included in the k-order neighborhood of the target to-be-tested point;

[0041] Determining a local reachable density of the target point to be tested based on a reachable distance of the target point to be tested and a k-order neighborhood of the target point to be tested;

[0042] According to the local reachable density corresponding to each neighborhood point and the k-order neighborhood of the target to-be-tested point, the outlier value of the target to-be-tested point is determined.

[0043] On the one hand, according to the number of memory cells corresponding to each to-be-tested area and the number of memory cells with hard faults, the fault density corresponding to each to-be-tested area is determined to include:

[0044] According to the grid division method, determine the minimum square area corresponding to each area to be tested;

[0045] Count the number of memory cells contained in the minimum square area corresponding to each area to be tested and the number of memory cells with hard faults;

[0046] The ratio of the number of memory cells with hard faults contained in each minimum square area to the number of memory cells is used as the fault density of the corresponding area to be tested.

[0047] On the one hand, performing fault processing on the memory page corresponding to the target area to be tested includes:

[0048] The memory page corresponding to the target area to be tested is processed offline.

[0049] On the one hand, performing fault processing on the memory page corresponding to the target area to be tested includes:

[0050] Redundancy repair is performed on the memory pages corresponding to the target area to be tested; wherein the redundancy repair includes single-device data correction, adaptive dual-device data correction, post-packaging repair or memory mirroring.

[0051] The embodiment of the present invention also provides a server memory fault detection device, comprising a patrol unit, a first offline unit, a second offline unit and a third offline unit;

[0052] The inspection unit is used to periodically inspect target memory units with hard faults;

[0053] The first offline unit is used to perform offline processing on the memory page where the target memory unit is located;

[0054] The second offline unit is used to perform offline processing on the memory page where the hard fault unit is located when a hard fault occurs in a memory unit adjacent to the target memory unit;

[0055] The third offline unit is used to perform offline processing on the memory page corresponding to the row and column area when the number of hard fault units in the row and column area where the target memory unit and the hard fault unit are located is greater than or equal to a set threshold.

[0056] On the one hand, the inspection unit includes a judgment subunit, a first judgment subunit, a first recording subunit, a second recording subunit, a second judgment subunit and a migration subunit;

[0057] The judging subunit is used to periodically judge whether the error correction code reports a memory error according to a set first time interval;

[0058] The first determination subunit is configured to determine that the first memory unit is a hard fault if there is a first memory unit with a number of faults greater than or equal to a hard fault threshold during the inspection process;

[0059] The first recording subunit is used to record the address of the first memory unit into the first storage space;

[0060] The second recording subunit is used to record the address of the second memory unit having a number of failures less than the hard failure threshold during the inspection process into the second storage space;

[0061] The second determination subunit is used to perform fault detection on the second memory unit corresponding to the address recorded in the second storage space according to a set second time interval, and determine the faulty second memory unit as a hard fault;

[0062] The migration subunit is used to transfer the address of the second memory unit with a fault to the first storage space.

[0063] On the one hand, the second determination subunit is used to determine whether the address of the second memory unit is recorded in the second storage space;

[0064] In a case where the address of the second memory unit is recorded in the second storage space, write-zero and write-one operations are respectively performed on the second memory unit according to the address of the second memory unit to obtain a fault detection result;

[0065] When the fault detection result indicates that a fault exists, the faulty second memory unit is determined to be a hard fault.

[0066] On the one hand, it also includes deleting units;

[0067] The deleting unit is used to delete the address of the second memory unit without fault from the second storage space when the fault detection result is that there is no fault.

[0068] In one aspect, the second offline unit includes a reading subunit, an operating subunit, and a processing subunit;

[0069] The reading subunit is used to read the address of the target memory unit from the first storage space;

[0070] The operation subunit is used to determine the memory cells adjacent to the target memory cell according to the address of the target memory cell, and respectively perform write-zero and write-one operations on the memory cells adjacent to the target memory cell to obtain a fault detection result;

[0071] The processing subunit is used to perform offline processing on the memory page where the faulty memory unit is located when the fault detection result is that a fault exists, and record the address of the faulty memory unit into the first storage space.

[0072] On the one hand, the third offline unit includes a statistical subunit, a row processing subunit and a column processing subunit;

[0073] The counting subunit is used to count the number of memory cells with hard faults in the same row and the same column based on the addresses recorded in the first storage space;

[0074] The row processing subunit is used to perform offline processing on the memory pages corresponding to the target row when the number of memory cells with hard failures is greater than or equal to the regional threshold value.

[0075] The column processing subunit is used to perform offline processing on the memory page corresponding to the target column when the number of memory cells with hard failures is greater than or equal to the regional threshold of the target column.

[0076] On the one hand, it also includes a statistical unit, an area determination unit, a density determination unit and a fault handling unit;

[0077] The statistical unit is used to count all memory units with hard faults according to the addresses recorded in the first storage space;

[0078] The area determination unit is used to determine each area to be tested based on the distribution of all memory cells with hard faults;

[0079] The density determination unit is used to determine the fault density corresponding to each area to be tested according to the number of memory cells corresponding to each area to be tested and the number of memory cells with hard faults;

[0080] The fault processing unit is used to perform fault processing on the memory page corresponding to the target to-be-tested area when there is a target to-be-tested area with a fault density greater than a density threshold.

[0081] In one aspect, the region determination unit includes a serving subunit, a neighborhood determination subunit, an outlier determination subunit, a deletion subunit, and a division subunit;

[0082] The sub-unit is used to take each memory unit with a hard fault as a point to be tested;

[0083] The neighborhood determination subunit is used to determine the k-order neighborhood of each point to be tested according to a set k-order distance;

[0084] The outlier determination subunit is used to determine the outlier of the target to-be-tested point based on the k-order distance and the distance between each to-be-tested point contained in the k-order neighborhood of the target to-be-tested point and the target to-be-tested point; wherein the target to-be-tested point is any one to-be-tested point among all the to-be-tested points;

[0085] The deleting subunit is used to delete the target point to be tested when the outlier value is greater than a set outlier threshold;

[0086] The division subunit is used to divide the to-be-tested area based on the remaining to-be-tested points.

[0087] On the one hand, the outlier determination subunit is used to determine the reachable distance of the target to-be-tested point according to the distance between the target to-be-tested point and its neighborhood point and the k-order distance; wherein the neighborhood point is any one to-be-tested point other than the target to-be-tested point among all to-be-tested points included in the k-order neighborhood of the target to-be-tested point;

[0088] Determining a local reachable density of the target point to be tested based on a reachable distance of the target point to be tested and a k-order neighborhood of the target point to be tested;

[0089] According to the local reachable density corresponding to each neighborhood point and the k-order neighborhood of the target to-be-tested point, the outlier value of the target to-be-tested point is determined.

[0090] On the one hand, the density determination unit is used to determine the minimum square area corresponding to each area to be tested according to the grid division method;

[0091] Count the number of memory cells contained in the minimum square area corresponding to each area to be tested and the number of memory cells with hard faults;

[0092] The ratio of the number of memory cells with hard faults contained in each minimum square area to the number of memory cells is used as the fault density of the corresponding area to be tested.

[0093] On the one hand, the fault processing unit is used to perform offline processing on the memory page corresponding to the target area to be tested.

[0094] On the one hand, the fault processing unit is used to perform redundant repair on the memory pages corresponding to the target area to be tested; wherein the redundant repair includes single-device data correction, adaptive dual-device data correction, post-packaging repair or memory mirroring.

[0095] The embodiment of the present invention further provides a server memory failure detection device, including:

[0096] Memory for storing computer programs;

[0097] A processor is used to execute the computer program to implement the steps of the server memory failure detection method as described above.

[0098] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned method for detecting a server memory failure are implemented.

[0099] An embodiment of the present invention further provides a computer program product, including a computer program / instruction, which implements the steps of the above-mentioned server memory failure detection method when executed by a processor.

[0100] It can be seen from the above technical solution that the target memory unit with hard faults is periodically inspected, and the memory page where the target memory unit is located is processed offline. Considering that the probability of errors in memory units near the prior errors may increase, the memory units adjacent to the target memory unit can be detected. In the case where a hard fault exists in a memory unit adjacent to the target memory unit, the memory page where the hard fault unit is located is processed offline. In order to identify whether the fault is easy to spread, the row and column area where the target memory unit and the hard fault unit are located can be further detected. In the case where the number of hard fault units in the row and column area where the target memory unit and the hard fault unit are located is greater than or equal to the set threshold, it means that the row and column area is prone to faults. In order to prevent the error from spreading, the memory page corresponding to the row and column area can be processed offline.

[0101] The beneficial effect of the present invention is that after the memory page where the target memory unit with a hard fault is located is processed offline, a more active detection mechanism is introduced to detect the memory units around the target memory unit, so that the memory unit with a hard fault can be identified earlier, and the delay from the occurrence of the fault to its detection is significantly reduced. By processing the memory pages corresponding to the high-risk row and column areas offline, it helps to prevent the spread of errors and reduce the risk of data corruption. The present invention effectively reduces the occurrence of system instability and uncorrectable error events caused by memory failures, and improves the stability and reliability of the overall system. BRIEF DESCRIPTION OF THE DRAWINGS

[0102] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0103] Figure 1 A flow chart of a method for detecting a server memory failure provided by an embodiment of the present invention;

[0104] Figure 2 A flow chart of a method for periodically inspecting a target memory unit with a hard fault provided by an embodiment of the present invention;

[0105] Figure 3 A schematic diagram of testing memory cells in adjacent rows and columns of a target memory cell provided by an embodiment of the present invention;

[0106] Figure 4 A schematic diagram of a test of a row and column region where a memory cell with a hard fault is located is provided in an embodiment of the present invention;

[0107] Figure 5A flowchart of a method for identifying a memory area fault provided by an embodiment of the present invention;

[0108] Figure 6 A schematic diagram of a LOF algorithm for detecting outliers provided by an embodiment of the present invention;

[0109] Figure 7 A schematic diagram of calculating regional density based on a grid division method provided by an embodiment of the present invention;

[0110] Figure 8 A schematic diagram of rapid identification of memory faults provided by an embodiment of the present invention;

[0111] Fig. 9 A schematic diagram of the structure of a server memory failure detection device provided by an embodiment of the present invention;

[0112] Fig.10 A structural diagram of a server memory failure detection device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0113] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0114] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0115] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0116] To reduce the impact of memory errors, researchers developed Error Correcting Codes (ECC) to detect and correct errors. Correctable Errors (CE) are corrected during application execution, while Uncorrectable Errors (UCE) are detected but cannot be corrected. Moderate CE has a negligible impact on system performance. However, memory error storms may cause a denial of service attack that seriously affects server system operations. In addition, since additional bits encounter errors at the same time, errors may become uncorrectable, causing the system to crash or shut down. Therefore, it is valuable to effectively avoid CE in advance because it reduces the probability of error storms or UCE.

[0117] Memory failures are divided into soft failures and hard failures. Soft failures occur randomly and may be recovered, while hard failures usually refer to hardware damage. Errors caused by soft / hard failures are called soft / hard errors. In practice, we follow a common rule of thumb and define hard errors as repeated errors on the same cell. A common strategy to avoid memory errors is to stop using memory cells that show repeated errors, that is, to take the page offline when the page has reached X errors in the past T hours. For the convenience of subsequent description, X / T can be used to represent X errors in T hours. Page offline means that the operating system copies the contents of the page to another location and permanently stops using the original page.

[0118] Page offline can effectively remove more than 94% of UEs by isolating error areas of 4KB or larger capacity without additional hardware cost, and as the smallest memory unit controllable by the system, it helps minimize memory capacity waste. However, DRAM errors strongly depend on the wear level of memory cells and implicit runtime context such as access patterns, data content, etc., which may not be reflected in the error rate over the past period of time. Therefore, the effectiveness of the X / T strategy can be further improved.

[0119] Currently, a more accurate fault identification mechanism is to perform short-cycle inspections through the Baseboard Management Controller (BMC). When repeated error events occur at a certain memory address, the address is diagnosed as a hard fault, and the memory page where the current hard fault unit is located is processed offline.

[0120] Although short-cycle inspections through the BMC improve detection accuracy, they rely on repeated error events at the memory address to confirm hard faults. This means that if a memory unit has a hard fault but has not been accessed again for the time being, its fault state cannot be immediately identified. In addition, when the memory unit is accessed again and triggers a fault, the system is already in a potentially unstable state, increasing the risk of UCE. These shortcomings directly affect the timeliness and efficiency of fault identification, increasing the risk of UCE faced by the system.

[0121] Therefore, the embodiment of the present invention provides a method, device, equipment and medium for detecting server memory failures. In addition to offline processing of the memory page where the target memory unit with hard failure is located, the memory unit adjacent to the target memory unit is detected, which can identify the memory unit with hard failure earlier, significantly reducing the delay from the occurrence of the failure to its detection. And by offline processing of the memory page corresponding to the row and column area with high risk, it helps to prevent the spread of errors, reduce the risk of data corruption, and improve the stability and reliability of the overall system.

[0122] Next, a method for detecting a server memory failure provided by an embodiment of the present invention is described in detail. Figure 1 A flow chart of a method for detecting a server memory failure provided by an embodiment of the present invention, the method comprising:

[0123] S101: Periodically inspect a target memory unit with a hard fault, and perform offline processing on a memory page where the target memory unit is located.

[0124] Considering that hard failures may occur repeatedly and dominate the probability of memory failures, in the embodiment of the present invention, a periodic inspection method can be used to determine whether there are memory units in the server system that have failed multiple times. The cycle time can be flexibly set, for example, it can be set to 1 second (s), that is, all memory units are inspected once every 1 second to count the memory units with errors.

[0125] In combination with actual detection requirements, a memory unit that fails twice in succession can be determined as a hard fault. As detection requirements change, the number of times a memory unit fails can also be adjusted when determining whether a memory unit is a hard fault, which is not specifically limited here.

[0126] The server system includes a large number of memory units. For the sake of distinction, the memory unit with a hard fault may be referred to as a target memory unit. When a target memory unit with a hard fault is detected, in order to reduce the risk caused by the target memory unit, the memory page where the target memory unit is located may be processed offline in a timely manner.

[0127] S102: When a memory unit adjacent to the target memory unit has a hard fault, an offline process is performed on the memory page where the hard fault unit is located.

[0128] When a hard fault occurs in a target memory cell, the probability of errors occurring in the row and column memory cells nearby may increase. Therefore, in an embodiment of the present invention, memory cells adjacent to the target memory cell may be detected to determine whether the adjacent memory cells have a hard fault.

[0129] The memory cells adjacent to the target memory cell may include memory cells at four positions of the upper side, the lower side, the left side and the right side of the target memory cell.

[0130] There are often multiple memory cells adjacent to the target memory cell. For easy distinction, the memory cell with hard faults among these adjacent memory cells can be called a hard fault cell. In the case that a memory cell adjacent to the target memory cell has a hard fault, the memory page where the hard fault cell is located can be processed offline in a timely manner.

[0131] S103: When the number of hard fault cells in the row and column region where the target memory cell and the hard fault cell are located is greater than or equal to a set threshold, offline processing is performed on the memory page corresponding to the row and column region.

[0132] Considering that faults are easy to spread, when there are a large number of memory cells with hard faults in a row or column, the probability of faults in the row or column area will greatly increase. Therefore, the target memory cells and the row and column areas where the hard fault cells are located can be tested.

[0133] When the number of hard fault cells in the target memory cell and the row and column region where the hard fault cells are located is greater than or equal to the set threshold, it indicates that the row and column region is prone to failure. To prevent the error from spreading, the memory page corresponding to the row and column region may be processed offline.

[0134] The row and column area may include the row where the target memory cell and the hard fault cell are respectively located and the column where the target memory cell and the hard fault cell are respectively located.

[0135] The value of the threshold can be set flexibly, for example, it can be set to 3. When the number of hard fault memory cells in a row is 3 or more, the memory page corresponding to the row can be directly processed offline.

[0136] It should be noted that based on the operations of S101 and S102, the memory page where the target memory unit is located and the memory page where the hard fault unit is located have been processed offline. Therefore, when the target memory unit or the hard fault unit is included in the row and column area, it is only necessary to process the remaining memory cells offline, and there is no need to repeat the offline processing of the target memory unit and the hard fault unit.

[0137] It can be seen from the above technical solution that the target memory unit with hard faults is periodically inspected, and the memory page where the target memory unit is located is processed offline. Considering that the probability of errors in memory units near the prior error may increase, the memory units adjacent to the target memory unit can be detected. In the case where a hard fault exists in a memory unit adjacent to the target memory unit, the memory page where the hard fault unit is located is processed offline. In order to identify whether the fault is easy to spread, the row and column area where the target memory unit and the hard fault unit are located can be further detected. In the case where the number of hard fault units in the row and column area where the target memory unit and the hard fault unit are located is greater than or equal to the set threshold, it means that the row and column area is prone to faults. In order to prevent the error from spreading, the memory page corresponding to the row and column area can be processed offline. The beneficial effect of the present invention is that after the memory page where the target memory unit with hard faults is located is processed offline, a more active detection mechanism is introduced to detect the memory units around the target memory unit, so that the memory unit with hard faults can be identified earlier, and the delay from the occurrence of the fault to its detection is significantly reduced. By offline processing the memory pages corresponding to the high-risk row and column areas, it helps prevent the spread of errors and reduce the risk of data corruption. The present invention effectively reduces the occurrence of system instability and uncorrectable error events caused by memory failures, and improves the stability and reliability of the overall system.

[0138] Figure 2 A flowchart of a method for periodically inspecting a target memory unit with a hard fault is provided in an embodiment of the present invention. The method includes:

[0139] S201: Periodically determine whether the error correction code reports a memory error according to a set first time interval.

[0140] The value of the first time interval can be set flexibly, for example, it can be set to 1 second.

[0141] When the error correction code reports a memory error, the address of the memory unit reporting the memory error can be recorded. For each memory unit, the corresponding fault count can be increased by one each time an error occurs.

[0142] S202: If there is a first memory unit with a number of failures greater than or equal to a hard failure threshold during the inspection process, determine the first memory unit as a hard failure, and record the address of the first memory unit in the first storage space.

[0143] For the sake of distinction, a memory unit with a number of failures greater than or equal to the hard failure threshold may be referred to as a first memory unit. There may be multiple first memory units, and since the processing method of each first memory unit is similar, in the embodiments of the present invention, one first memory unit is used as an example for description.

[0144] The value of the hard fault threshold can be flexibly set based on the detection requirements, for example, the default setting is 2. When there is a first memory unit with a number of failures greater than or equal to 2 during the inspection process, the first memory unit can be determined as a hard fault.

[0145] For a memory unit determined to be a hard fault, the memory page where the memory unit is located will be processed offline, and the content on the memory unit is empty. In order to facilitate the server system to timely understand the failure of each memory unit, the address of the first memory unit can be recorded in the first storage space.

[0146] S203: Recording the address of the second memory unit having a number of failures less than the hard failure threshold during the inspection process into the second storage space.

[0147] In the embodiment of the present invention, the memory unit with the number of failures less than the hard failure threshold may be referred to as the second memory unit. There may be multiple second memory units. Since the processing method of each second memory unit is similar, in the embodiment of the present invention, one second memory unit is used as an example for description.

[0148] For a second memory unit whose failure times are less than the hard failure threshold, its address may be recorded in the second storage space.

[0149] S204: Perform fault detection on the second memory unit corresponding to the address recorded in the second storage space at a set second time interval, determine the faulty second memory unit as a hard fault, and transfer the address of the faulty second memory unit to the first storage space.

[0150] In the embodiment of the present invention, there is no specific limitation on the value of the second time interval, as long as the value of the second time interval is greater than the value of the first time interval. For example, the first time interval is set to 1 second, and the second time interval can be set to 5 seconds.

[0151] In practical applications, it can be determined whether the address of the second memory unit is recorded in the second storage space. If the address of the second memory unit is recorded in the second storage space, write-zero and write-one operations are performed on the second memory unit according to the address of the second memory unit to obtain a fault detection result.

[0152] There are many types of memory failures. For example, some memory cells cannot store charge. It may be possible to write 0 and read 0, but write 1 and read 0. Similarly, some memory cells do not have discharge control. It may be correct to write 1, but wrong to write 0. Therefore, by performing write zero and write one operations on the second memory cell, it is possible to identify whether the second memory cell has a fault.

[0153] When the fault detection result is a fault, the faulty second memory unit can be determined as a hard fault. At this time, the memory page where the second memory unit is located can be processed offline and the address of the faulty second memory unit can be transferred to the first storage space.

[0154] When the fault detection result is that there is no fault, in order to save storage space, the address of the second memory unit that does not have a fault may be deleted from the second storage space.

[0155] In actual applications, the BMC inspection engine can be used to periodically verify whether the memory unit in which an error has occurred is a hard fault.

[0156] For example, the BMC can inspect ECC every 1 second to see if it reports a memory error. If a memory unit has an error, the address of the memory error unit is recorded. If a memory unit is found to have failed twice during the inspection, the memory unit is determined to be a hard fault, and the memory page where the hard fault memory unit is located is offline. At the same time, the address of the hard fault memory unit is recorded in the first storage space, i.e., storage space A, and the address of the memory unit that has only a single error is recorded in the second storage space, i.e., storage space B.

[0157] Set the processing cycle T (such as T=5s). If Rem(t / T)=0, check whether there is any error address information recorded in storage space B. Rem is the remainder function. Rem(t / T)=0 means that the remainder of t / T is 0, that is, the processing is performed once every T time. For example, if T is 5s, it is processed once every 5s. If it is checked that there is error address information recorded in storage space B, write 1 and write 0 to the address respectively to detect whether the error occurs again. If the error occurs again, the address is diagnosed as a hard fault, and the address of the hard fault memory unit is recorded in storage space A. Clear the addresses in storage space B that have not caused errors again from storage space B.

[0158] In the embodiment of the present invention, by actively diagnosing the memory status of the memory unit corresponding to each address in the second storage space, it is possible to quickly identify whether the memory unit where the error occurs is a hard fault. By clearing the address that has not caused the error again from the storage space and only using the storage space to record the address of the memory unit where the hard fault occurs, the storage space can be effectively saved and the utilization rate of the storage space can be improved.

[0159] Since the address of the target memory cell with a hard fault is recorded in the first storage unit, based on the memory fault research rule that "the error probability of rows and columns near prior errors may increase", the address of the target memory cell can be read from the first storage space; according to the address of the target memory cell, the memory cells adjacent to the target memory cell are determined, and write-zero and write-one operations are performed on the memory cells adjacent to the target memory cell, respectively, to obtain a fault detection result.

[0160] When the fault detection result indicates that a fault exists, the memory page where the faulty memory unit is located may be processed offline, and the address of the faulty memory unit may be recorded in the first storage space.

[0161] Figure 3 A test schematic diagram of memory cells in adjacent rows and columns of a target memory cell is provided in an embodiment of the present invention, which reads the address of the hard fault memory cell recorded in storage space A, performs read and write tests on the row and column cells near each hard fault memory cell, and detects whether there is an ECC error. Figure 3 The circle in the middle represents the test unit, i.e., the row memory unit and the column memory unit adjacent to the target memory unit, and × represents the target memory unit. The target memory unit represents the memory unit with hard fault, which can also be called hard fault unit. If errors occur in the row and column units near the hard fault unit, it is also diagnosed as a hard fault unit, and the address of the hard fault unit is recorded in the storage space A.

[0162] In the embodiment of the present invention, by detecting the peripheral units of the hard fault, it is identified whether the fault has spread, so that the memory fault unit can be discovered actively and timely.

[0163] The addresses recorded in the first storage space include the addresses of all memory cells with hard faults. In order to prevent the error from spreading, the row and column regions where the memory cells with hard faults are located can be detected.

[0164] In practical applications, the number of memory cells with hard faults in the same row and the same column can be counted based on the addresses recorded in the first storage space; in the case of a target row where the number of memory cells with hard faults is greater than or equal to the regional threshold, the memory page corresponding to the target row is processed offline; in the case of a target column where the number of memory cells with hard faults is greater than or equal to the regional threshold, the memory page corresponding to the target column is processed offline.

[0165] For ease of description, a column where the number of memory cells with hard faults is greater than or equal to the regional threshold may be referred to as a faulty row. A column where the number of memory cells with hard faults is greater than or equal to the regional threshold may be referred to as a faulty column.

[0166] Figure 4 A schematic diagram of a test of a row and column region where a memory cell with a hard fault is located is provided in an embodiment of the present invention. Figure 4 In the figure, × indicates a memory unit with a hard fault. For example, taking the regional threshold value as 3, Figure 4 If there are currently three hard-fault memory cells in the same row, the row can be determined as a faulty row, and the memory page corresponding to the faulty row can be processed offline.

[0167] In an embodiment of the present invention, based on the addresses recorded in the first storage space, it is possible to count whether there are multiple hard fault units in a row or a column on a certain array, so as to quickly determine the faulty row / column, and then perform offline processing on the memory page corresponding to the faulty row / column, thereby effectively avoiding the spread of errors and improving the security of the system.

[0168] In the embodiment of the present invention, based on the identified memory cells with hard faults, the memory regional faults can be accurately identified by calculating the regional fault cell density. Figure 5 A flowchart of a method for identifying a memory area fault provided by an embodiment of the present invention, the method comprising:

[0169] S501: Count all memory units with hard faults according to the addresses recorded in the first storage space.

[0170] By querying the addresses recorded in the first storage space, all memory units with hard faults can be counted.

[0171] S502: Determine each area to be tested based on the distribution of all memory cells with hard faults.

[0172] Considering that memory cells with hard faults are often concentrated, regions may be divided according to the locations of all memory cells with hard faults.

[0173] In practical applications, each memory unit with a hard fault may be used as a point to be tested; and the k-order neighborhood of each point to be tested may be determined according to a set k-order distance.

[0174] The number of points to be tested is often large, and each point to be tested is processed in a similar manner. Taking any one of all the points to be tested, that is, the target point to be tested, as an example, the outlier value of the target point to be tested can be determined based on the k-order distance and the distance between each point to be tested contained in the k-order neighborhood of the target point to be tested and the target point to be tested; when the outlier value is greater than the set outlier threshold, the target point to be tested is deleted, and the area to be tested is divided based on the remaining points to be tested.

[0175] For the outlier of the target to-be-tested point, the reachable distance of the target to-be-tested point can be determined based on the distance between the target to-be-tested point and its neighborhood point and the k-order distance; wherein the neighborhood point is any one of all the to-be-tested points contained in the k-order neighborhood of the target to-be-tested point except the target to-be-tested point. Based on the reachable distance of the target to-be-tested point and the k-order neighborhood of the target to-be-tested point, the local reachable density of the target to-be-tested point is determined; based on the local reachable density corresponding to each neighborhood point and the k-order neighborhood of the target to-be-tested point, the outlier of the target to-be-tested point is determined.

[0176] In the embodiment of the present invention, a Local Outlier Factor (LOF) algorithm may be used to calculate the local reachability density of each point to be tested, thereby quickly identifying memory area faults.

[0177] Figure 6 A schematic diagram of a LOF algorithm for detecting outliers provided by an embodiment of the present invention, Figure 6 In the figure, × represents all memory cells with hard faults. The memory cell corresponding to point p is an outlier. After identifying and removing the outliers through the LOF algorithm, the memory faulty cells can be divided into regions to obtain C1 and C2 regions.

[0178] The LOF algorithm is a density-based local outlier detection algorithm that is suitable for data with different cluster density dispersions. Figure 6 In the memory array, set C1 is a low-density area, and set C2 is a high-density area. According to the traditional density-based outlier detection algorithm, the distance between point p and its neighboring points in C2 is less than the distance between any data point in C1 and its neighboring points, and point p will be regarded as a normal point. However, from a local point of view, point p is actually an outlier. The LOF algorithm can effectively detect outliers in this situation.

[0179] The main steps of the LOF algorithm are as follows:

[0180] Step 1: Calculate the k-order distance - Proximity distance:

[0181] Representation Object of - proximity distance, and The distance between them is defined as ,in , the distance calculation here can be Euclidean distance, Hamming distance, Mahalanobis distance, etc.

[0182] Step 2: Determine the k-order neighborhood, i.e. -Distance Neighborhood:

[0183] Representation Object of -Distance neighborhood, i.e. point As the center of the circle, Draw a circle with radius , the range of this circle is -Distance neighborhood. of -The distance neighborhood includes all The distance is no greater than Other objects, namely .

[0184] Step 3: Calculate the reachable distance:

[0185] Representation Object Relative to the object The reachable distance is defined as:

[0186] .

[0187] Step 4: Calculate the local reachability density (LRD):

[0188] Representation Object The local reachability density is defined as:

[0189] .

[0190] Step 5: Calculate the outlier value or outlier factor:

[0191] Representation Object The outlier factor of is defined as:

[0192] .

[0193] The core idea of ​​the LOF algorithm is to compare the density of a point and its neighborhood. If the density of a point is significantly lower than the density of its neighborhood, then the point may be an outlier. A LOF value greater than 1 indicates that the point is a potential outlier, and the farther the value is from 1, the more likely it is an outlier; while a LOF value close to 1 means that the density of the point is similar to the density of its neighborhood, so it is unlikely to be an outlier.

[0194] S503: Determine the fault density corresponding to each of the to-be-tested regions according to the number of memory cells corresponding to each to-be-tested region and the number of memory cells with hard faults.

[0195] After removing the outliers, the memory fault unit may be divided into regions to obtain at least one region to be tested.

[0196] In an embodiment of the present invention, the minimum square area corresponding to each area to be tested can be determined according to a grid division method; the number of memory cells contained in the minimum square area corresponding to each area to be tested and the number of memory cells with hard faults are counted; and the ratio of the number of memory cells with hard faults contained in each minimum square area to the number of memory cells is used as the fault density of the corresponding area to be tested.

[0197] Figure 7 A schematic diagram of calculating regional density based on a grid partitioning method provided by an embodiment of the present invention. After removing outliers, the remaining memory cells with hard faults can be divided into Figure 7 The two minimum square areas shown in . Figure 7 A small square in the minimum square represents a memory cell. In addition to memory cells with hard faults, each minimum square area also contains memory cells that are operating normally. Taking a minimum square area as an example, the number of memory cells with hard faults contained in it is divided by the number of all memory cells contained in it, and the ratio obtained is the fault density.

[0198] S504: When there is a target to-be-tested area whose fault density is greater than a density threshold, perform fault processing on a memory page corresponding to the target to-be-tested area.

[0199] The value of the density threshold can be flexibly set based on demand and is not limited here.

[0200] There may be multiple areas to be tested. To facilitate distinction, an area to be tested whose fault density is greater than a density threshold may be referred to as a target area to be tested.

[0201] When there is a target test area with a fault density greater than a density threshold, it indicates that the memory cells in the target test area are prone to errors and have a high security risk, so fault processing can be performed on the memory page corresponding to the target test area.

[0202] There are multiple ways to handle the fault of the memory page corresponding to the target area to be tested. One way is to directly handle the memory page corresponding to the target area to be tested offline. Another way is to perform redundant repair on the memory page corresponding to the target area to be tested. Among them, the redundant repair can include single device data correction, adaptive dual device data correction, post-packaging repair or memory mirroring.

[0203] After removing isolated outliers based on the LOF algorithm, the present invention calculates the fault density of each area to be tested. When the fault area density is greater than the density threshold, it is quickly diagnosed as a regional fault and the page is taken offline or repaired redundantly, which greatly improves the stability and reliability of the system.

[0204] Figure 8 A schematic diagram of rapid identification of memory faults provided by an embodiment of the present invention, memory fault detection can be performed through the BMC inspection engine. For memory cells with repeated errors, their addresses can be recorded in storage space A. For memory cells with single errors, their addresses can be recorded in storage space B. The memory cells corresponding to each address in storage space B can be tested again to see if an error occurs. If a memory cell with an error is found in the retest, the address of the memory cell is transferred from storage space B to storage space A. All memory cells recorded in storage space A have hard faults, and the memory pages where these memory cells are located are processed offline. On this basis, the memory cells corresponding to the row and column addresses around the hard fault can be further detected, so that the memory pages where the memory cells with hard faults are located are processed offline. Fault detection can also be performed on rows, columns, and regions, and the memory pages corresponding to the faulty rows and faulty columns can be processed offline, and the memory cells contained in the faulty area can be processed offline or repaired, effectively avoiding the spread of errors.

[0205] In an embodiment of the present invention, a detection process that can quickly respond to and identify memory faulty units is designed based on the research rules of memory faults. By real-time monitoring and data analysis of memory units, abnormal signals can be captured at the early stage of faults. The LOF algorithm is introduced to identify outliers in the memory, and the fault area is accurately located by analyzing the differences between the faulty unit and the surrounding units, thereby preventing the spread of errors and reducing the risk of data corruption. The system of the present invention is applicable to all server products that use memory.

[0206] In actual applications, when there is a target area to be tested with a fault density greater than a density threshold, before performing fault processing on the memory page corresponding to the target area to be tested, read and write detection can also be performed on the memory cells contained in the target area to be tested. If the number of failed memory cells exceeds the set upper limit value among all memory cells contained in the target area to be tested, it means that the target area to be tested has a high risk, and at this time, the memory page corresponding to the target area to be tested can be fault processed.

[0207] When the fault density of the target area to be tested is greater than the density threshold, the probability of errors in the memory cells contained in the target area to be tested can be further evaluated by performing read and write tests on the memory cells contained in the target area to be tested. If the number of faulty memory cells exceeds the set upper limit of all memory cells contained in the target area to be tested, it means that the probability of errors is high. At this time, the memory page corresponding to the target area to be tested can be fault processed, which improves the accuracy of server memory fault detection while ensuring system security.

[0208] Fig. 9 A schematic diagram of the structure of a server memory failure detection device provided by an embodiment of the present invention, which includes a patrol unit 91, a first offline unit 92, a second offline unit 93 and a third offline unit 94;

[0209] A patrol unit 91, used for periodically patrolling target memory units with hard faults;

[0210] A first offline unit 92, used for performing offline processing on the memory page where the target memory unit is located;

[0211] A second offline unit 93, configured to perform offline processing on a memory page where a hard fault unit is located when a hard fault occurs in a memory unit adjacent to the target memory unit;

[0212] The third offline unit 94 is used to perform offline processing on the memory page corresponding to the row and column area when the number of hard fault cells in the row and column area where the target memory cell and the hard fault cell are located is greater than or equal to a set threshold.

[0213] In some embodiments, the inspection unit includes a judgment subunit, a first judgment subunit, a first recording subunit, a second recording subunit, a second judgment subunit, and a migration subunit;

[0214] A judging subunit, used for periodically judging whether the error correction code reports a memory error according to a set first time interval;

[0215] A first determination subunit is used to determine the first memory unit as a hard fault if there is a first memory unit with a number of failures greater than or equal to a hard fault threshold during the inspection process;

[0216] A first recording subunit, used for recording the address of the first memory unit into the first storage space;

[0217] A second recording subunit is used to record the address of the second memory unit having a number of failures less than a hard failure threshold during the inspection process into the second storage space;

[0218] A second determination subunit is used to perform fault detection on a second memory unit corresponding to an address recorded in the second storage space at a set second time interval, and determine the faulty second memory unit as a hard fault;

[0219] The migration subunit is used to transfer the address of the second memory unit with a fault to the first storage space.

[0220] In some embodiments, the second determination subunit is used to determine whether the address of the second memory unit is recorded in the second storage space;

[0221] In a case where the address of the second memory unit is recorded in the second storage space, write-zero and write-one operations are respectively performed on the second memory unit according to the address of the second memory unit to obtain a fault detection result;

[0222] When the fault detection result indicates that a fault exists, the faulty second memory unit is determined to be a hard fault.

[0223] In some embodiments, a deletion unit is also included;

[0224] The deleting unit is used to delete the address of the second memory unit without fault from the second storage space when the fault detection result is that there is no fault.

[0225] In some embodiments, the second offline unit includes a reading subunit, an operation subunit, and a processing subunit;

[0226] A reading subunit, used for reading the address of the target memory unit from the first storage space;

[0227] An operation subunit, used for determining a memory cell adjacent to the target memory cell according to the address of the target memory cell, and performing write-zero and write-one operations on the memory cells adjacent to the target memory cell respectively, so as to obtain a fault detection result;

[0228] The processing subunit is used for, when the fault detection result is that a fault exists, performing offline processing on the memory page where the faulty memory unit is located, and recording the address of the faulty memory unit into the first storage space.

[0229] In some embodiments, the third offline unit includes a statistics subunit, a row processing subunit, and a column processing subunit;

[0230] A counting subunit, used for counting the number of memory cells with hard faults in the same row and the same column based on the addresses recorded in the first storage space;

[0231] A row processing subunit, for performing offline processing on a memory page corresponding to a target row when the number of memory cells with hard failures is greater than or equal to a region threshold value;

[0232] The column processing subunit is used to perform offline processing on the memory page corresponding to the target column when the number of memory cells with hard failure is greater than or equal to the target column of the regional threshold.

[0233] In some embodiments, it further includes a statistical unit, an area determination unit, a density determination unit, and a fault processing unit;

[0234] A statistical unit, used for counting all memory units with hard faults according to the addresses recorded in the first storage space;

[0235] A region determination unit, used to determine each region to be tested based on the distribution of all memory cells with hard faults;

[0236] A density determination unit, used to determine the fault density corresponding to each of the to-be-tested areas according to the number of memory cells corresponding to each to-be-tested area and the number of memory cells with hard faults;

[0237] The fault processing unit is used to perform fault processing on the memory page corresponding to the target to-be-tested area when there is a target to-be-tested area with a fault density greater than a density threshold.

[0238] In some embodiments, the region determination unit includes an as subunit, a neighborhood determination subunit, an outlier determination subunit, a deletion subunit, and a partitioning subunit;

[0239] As a sub-unit, it is used to treat each memory unit with hard fault as a point to be tested;

[0240] A neighborhood determination subunit is used to determine the k-order neighborhood of each point to be tested according to a set k-order distance;

[0241] An outlier determination subunit is used to determine the outlier of the target to-be-tested point based on the k-order distance and the distance between each to-be-tested point contained in the k-order neighborhood of the target to-be-tested point and the target to-be-tested point; wherein the target to-be-tested point is any one to-be-tested point among all the to-be-tested points;

[0242] A deletion subunit is used to delete the target point to be tested when the outlier value is greater than the set outlier threshold;

[0243] The division subunit is used to divide the to-be-tested area based on the remaining to-be-tested points.

[0244] In some embodiments, the outlier determination subunit is used to determine the reachable distance of the target to-be-tested point according to the distance between the target to-be-tested point and its neighborhood point and the k-order distance; wherein the neighborhood point is any one to-be-tested point other than the target to-be-tested point among all to-be-tested points included in the k-order neighborhood of the target to-be-tested point;

[0245] Determine the local reachability density of the target point to be tested based on the reachable distance of the target point to be tested and the k-order neighborhood of the target point to be tested;

[0246] According to the local reachable density corresponding to each neighborhood point and the k-order neighborhood of the target point to be tested, the outlier value of the target point to be tested is determined.

[0247] In some embodiments, the density determination unit is used to determine the minimum square area corresponding to each to-be-tested area according to a grid division method;

[0248] Count the number of memory cells contained in the minimum square area corresponding to each area to be tested and the number of memory cells with hard faults;

[0249] The ratio of the number of memory cells with hard faults contained in each minimum square area to the number of memory cells is used as the fault density of the corresponding area to be tested.

[0250] In some embodiments, the fault processing unit is used to perform offline processing on the memory page corresponding to the target to-be-tested area.

[0251] In some embodiments, the fault processing unit is used to perform redundant repair on the memory pages corresponding to the target area to be tested; wherein the redundant repair includes single-device data correction, adaptive dual-device data correction, post-packaging repair or memory mirroring.

[0252] Fig. 9 The description of the features in the corresponding embodiments can be found in Figure 1 The relevant descriptions of the corresponding embodiments will not be repeated here one by one.

[0253] It can be seen from the above technical solution that the target memory unit with hard faults is periodically inspected, and the memory page where the target memory unit is located is processed offline. Considering that the probability of errors in memory units near the prior error may increase, the memory units adjacent to the target memory unit can be detected. In the case where a hard fault exists in a memory unit adjacent to the target memory unit, the memory page where the hard fault unit is located is processed offline. In order to identify whether the fault is easy to spread, the row and column area where the target memory unit and the hard fault unit are located can be further detected. In the case where the number of hard fault units in the row and column area where the target memory unit and the hard fault unit are located is greater than or equal to the set threshold, it means that the row and column area is prone to faults. In order to prevent the error from spreading, the memory page corresponding to the row and column area can be processed offline. The beneficial effect of the present invention is that after the memory page where the target memory unit with hard faults is located is processed offline, a more active detection mechanism is introduced to detect the memory units around the target memory unit, so that the memory unit with hard faults can be identified earlier, and the delay from the occurrence of the fault to its detection is significantly reduced. By offline processing the memory pages corresponding to the high-risk row and column areas, it helps prevent the spread of errors and reduce the risk of data corruption. The present invention effectively reduces the occurrence of system instability and uncorrectable error events caused by memory failures, and improves the stability and reliability of the overall system.

[0254] Fig.10 A structural diagram of a server memory failure detection device provided by an embodiment of the present invention, such as Fig.10 As shown, the server memory failure detection device includes: a memory 100, for storing a computer program;

[0255] The processor 101 is used to implement the steps of the method for detecting a server memory failure in the above embodiment when executing a computer program.

[0256] The server memory failure detection device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer, or a desktop computer.

[0257] Among them, the processor 101 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 101 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 101 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 101 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 101 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0258] The memory 100 may include one or more computer-readable storage media, which may be non-transitory. The memory 100 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 100 is at least used to store the following computer program 1001, wherein, after the computer program is loaded and executed by the processor 101, it can implement the relevant steps of the server memory failure detection method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 100 may also include an operating system 1002 and data 1003, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 1002 may include Windows, Unix, Linux, etc. Data 1003 may include, but is not limited to, addresses, thresholds, etc. of memory units with hard failures.

[0259] In some embodiments, the server memory failure detection device may further include a display screen 102 , an input / output interface 103 , a communication interface 104 , a power supply 105 , and a communication bus 106 .

[0260] Those skilled in the art will understand that Fig.10 The structure shown in the figure does not constitute a limitation on the device for detecting server memory failure, and may include more or less components than those shown in the figure.

[0261] It is understandable that if the server memory failure detection method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk or optical disk, etc. Various media that can store program codes.

[0262] Based on this, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the server memory failure detection method as described above are implemented.

[0263] An embodiment of the present invention further provides a computer program product, including a computer program / instruction, which implements the steps of the above-mentioned server memory failure detection method when executed by a processor.

[0264] The above is a detailed introduction to a server memory failure detection method, device, equipment, computer-readable storage medium and computer program product provided by an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0265] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0266] The above is a detailed introduction to a server memory failure detection method, device, equipment, computer-readable storage medium and computer program product provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A method for detecting a server memory failure, characterized in that: include: Periodically inspecting a target memory unit with a hard fault, and performing offline processing on a memory page where the target memory unit is located; In the case where a memory cell adjacent to the target memory cell has a hard fault, performing offline processing on the memory page where the hard fault cell is located; When the number of hard fault cells in the target memory cell and the row and column region where the hard fault cell is located is greater than or equal to a set threshold, offline processing is performed on the memory page corresponding to the row and column region; The target memory units with hard faults during periodic inspection include: periodically determining whether the error correction code reports a memory error according to a set first time interval; In the case where there is a first memory unit with a number of failures greater than or equal to a hard failure threshold during the inspection process, the first memory unit is determined to be a hard failure, and the address of the first memory unit is recorded in the first storage space; Recording the address of the second memory unit having a number of failures less than the hard failure threshold during the inspection process into the second storage space; performing fault detection on the second memory unit corresponding to the address recorded in the second storage space according to a set second time interval, determining the second memory unit with a fault as a hard fault, and transferring the address of the second memory unit with a fault to the first storage space; the second time interval is greater than the first time interval; Performing fault detection on the second memory unit corresponding to the address recorded in the second storage space at a set second time interval, and determining the faulty second memory unit as a hard fault includes: Determining whether the address of the second memory unit is recorded in the second storage space; In a case where the address of the second memory unit is recorded in the second storage space, write-zero and write-one operations are respectively performed on the second memory unit according to the address of the second memory unit to obtain a fault detection result; When the fault detection result indicates that a fault exists, the faulty second memory unit is determined to be a hard fault.

2. The method for detecting server memory failure according to claim 1, characterized in that: Also includes: When the fault detection result is that there is no fault, the address of the second memory unit that does not have the fault is deleted from the second storage space.

3. The method for detecting server memory failure according to claim 1, characterized in that: In the case that a memory unit adjacent to the target memory unit has a hard fault, performing offline processing on a memory page where the hard fault unit is located includes: Reading the address of the target memory unit from the first storage space; According to the address of the target memory cell, determine the memory cell adjacent to the target memory cell, and respectively perform write-zero and write-one operations on the memory cells adjacent to the target memory cell to obtain a fault detection result; When the fault detection result indicates that a fault exists, the memory page where the faulty memory unit is located is processed offline, and the address of the faulty memory unit is recorded in the first storage space.

4. The method for detecting server memory failure according to claim 3, characterized in that: When the number of hard fault cells in the target memory cell and the row and column region where the hard fault cell is located is greater than or equal to a set threshold, performing offline processing on the memory page corresponding to the row and column region includes: Based on the addresses recorded in the first storage space, counting the number of memory cells with hard faults in the same row and the same column; In the case of a target row where the number of memory cells with hard failures is greater than or equal to the regional threshold, offline processing is performed on the memory page corresponding to the target row; In the case of a target column where the number of memory cells with hard failures is greater than or equal to the regional threshold, offline processing is performed on the memory page corresponding to the target column.

5. The method for detecting server memory failure according to any one of claims 2 to 4, characterized in that: Also includes: Counting all memory units with hard faults according to the addresses recorded in the first storage space; Based on the distribution of all memory cells with hard faults, determine the areas to be tested; Determine the fault density corresponding to each of the areas to be tested according to the number of memory cells corresponding to each area to be tested and the number of memory cells with hard faults; In the case that there is a target to-be-tested area whose fault density is greater than a density threshold, fault processing is performed on a memory page corresponding to the target to-be-tested area.

6. The method for detecting server memory failure according to claim 5, characterized in that: Based on the distribution of all memory cells with hard faults, the areas to be tested are determined to include: Treat each memory cell with hard fault as a test point; According to the set k-order distance, determine the k-order neighborhood of each point to be tested; Based on the k-order distance and the distance between each to-be-tested point contained in the k-order neighborhood of the target to-be-tested point and the target to-be-tested point, determining the outlier value of the target to-be-tested point; wherein the target to-be-tested point is any one to-be-tested point among all the to-be-tested points; In the case that the outlier value is greater than the set outlier threshold, the target to-be-tested point is deleted, and a to-be-tested area is divided based on the remaining to-be-tested points.

7. The method for detecting server memory failure according to claim 6, characterized in that: Determining the outlier value of the target to-be-tested point based on the k-order distance and the distance between each to-be-tested point included in the k-order neighborhood of the target to-be-tested point and the target to-be-tested point includes: Determine the reachable distance of the target to-be-tested point according to the distance between the target to-be-tested point and its neighborhood point and the k-order distance; wherein the neighborhood point is any one to-be-tested point other than the target to-be-tested point among all to-be-tested points included in the k-order neighborhood of the target to-be-tested point; Determining a local reachable density of the target point to be tested based on a reachable distance of the target point to be tested and a k-order neighborhood of the target point to be tested; According to the local reachable density corresponding to each neighborhood point and the k-order neighborhood of the target to-be-tested point, the outlier value of the target to-be-tested point is determined.

8. The method for detecting server memory failure according to claim 5, characterized in that: According to the number of memory cells corresponding to each area to be tested and the number of memory cells with hard faults, the fault density corresponding to each area to be tested is determined to include: According to the grid division method, determine the minimum square area corresponding to each area to be tested; Count the number of memory cells contained in the minimum square area corresponding to each area to be tested and the number of memory cells with hard faults; The ratio of the number of memory cells with hard faults contained in each minimum square area to the number of memory cells is used as the fault density of the corresponding area to be tested.

9. The method for detecting server memory failure according to claim 5, characterized in that: Performing fault processing on the memory page corresponding to the target area to be tested includes: The memory page corresponding to the target area to be tested is processed offline.

10. The method for detecting server memory failure according to claim 5, characterized in that: Performing fault processing on the memory page corresponding to the target area to be tested includes: Redundancy repair is performed on the memory pages corresponding to the target area to be tested; wherein the redundancy repair includes single-device data correction, adaptive dual-device data correction, post-packaging repair or memory mirroring.

11. A server memory failure detection device, characterized in that: It includes an inspection unit, a first offline unit, a second offline unit and a third offline unit; The inspection unit is used to periodically inspect target memory units with hard faults; The first offline unit is used to perform offline processing on the memory page where the target memory unit is located; The second offline unit is used to perform offline processing on the memory page where the hard fault unit is located when a hard fault occurs in a memory unit adjacent to the target memory unit; The third offline unit is used to perform offline processing on the memory page corresponding to the row and column area when the number of hard fault units in the row and column area where the target memory unit and the hard fault unit are located is greater than or equal to a set threshold; Wherein, the inspection unit comprises: A determination unit, configured to periodically determine whether the error correction code reports a memory error according to a set first time interval; A first determination subunit is used to determine that the first memory unit is a hard fault if there is a first memory unit with a number of failures greater than or equal to a hard fault threshold during the inspection process; A first recording subunit, used for recording the address of the first memory unit into a first storage space; A second recording subunit is used to record the address of the second memory unit having a number of failures less than a hard failure threshold during the inspection process into the second storage space; a second determination subunit, configured to perform fault detection on a second memory unit corresponding to an address recorded in the second storage space according to a set second time interval, and determine the faulty second memory unit as a hard fault; the second time interval is greater than the first time interval; a migration subunit, configured to transfer the address of the second memory unit having a fault to the first storage space; The second determination subunit is specifically used to determine whether the address of the second memory unit is recorded in the second storage space; if the address of the second memory unit is recorded in the second storage space, write-zero and write-one operations are performed on the second memory unit according to the address of the second memory unit to obtain a fault detection result; if the fault detection result is that a fault exists, the faulty second memory unit is determined to be a hard fault.

12. A server memory failure detection device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the method for detecting a server memory failure as claimed in any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for detecting a server memory failure as claimed in any one of claims 1 to 10 are implemented.

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