Apparatus, method, device and storage medium based on software and hardware joint verification

Abstract

The application provides a device, method, equipment and storage medium based on software and hardware joint verification, the device comprises: a verification platform, the verification platform is provided with an interface, the verification platform is electrically connected with an NPU to be verified based on the interface; the verification platform is used for obtaining configuration information; the configuration information is transmitted to the NPU through the interface; the configuration information is obtained based on a software language; the configuration information comprises clock parameters, interrupt parameters, mode parameters and processing parameters; the verification platform is also used for obtaining a verification result based on the interface; the verification result indicates whether the NPU is normal, the verification result is obtained by analyzing a running result of the software language, the running result is obtained by the NPU based on an interrupt source and a processing result, and the processing result is obtained by the NPU based on the clock, the working mode and the processing data mode, and processing verification data. The technical scheme of the application can improve the operator verification efficiency of the NPU.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip verification technical field, in particular to a device and method based on software and hardware joint verification, equipment and storage medium. BACKGROUND

[0002] NPU (Natural Processing Unit, neural network processing unit) verification usually includes module verification and operator verification two parts, the two parts of verification have important significance for guaranteeing the accuracy of NPU code. Among them, the operator verification refers to verifying whether the actual application algorithm running on the NPU is correct, so the configuration information required for NPU running in the operator verification needs to be provided by software personnel. Module verification is used to ensure the accuracy of each single module, but the running of NPU needs the cooperation of multiple modules, and the cooperation of multiple modules needs operator verification to ensure its correctness.

[0003] In related technologies, most of the operator verification environment is a pure hardware environment, which is responsible for building the operator verification environment by hardware personnel, and the software personnel provides the configuration information file required for operator running.

[0004] However, the above verification method, because the hardware personnel also needs to be responsible for module verification, leads to the time point of starting operator verification is relatively late, and the increase of communication cost between software personnel and hardware personnel also leads to the slow speed of operator verification. SUMMARY

[0005] The embodiments of the present application provide a device and method based on software and hardware joint verification, equipment and storage medium, which can start operator verification in advance, and reduce the communication cost between software personnel and hardware personnel, and further improve the efficiency of operator verification. The technical scheme is as follows:

[0006] According to the first aspect of the embodiments of the present application, a device based on software and hardware joint verification is provided, which comprises:

[0007] A verification platform is provided with an interface, and the verification platform is electrically connected with the NPU to be verified based on the interface; the interface is obtained based on hardware language;

[0008] The verification platform is used for obtaining configuration information; the configuration information is transmitted to the NPU through the interface; the configuration information is obtained based on software language; the configuration information includes clock parameters, interrupt parameters, mode parameters and processing parameters; the clock parameters are used to configure the clock of the NPU, the interrupt parameters are used to configure the interrupt source of the NPU, the mode parameters are used to configure the working mode of the NPU, and the processing parameters are used to configure the processing data mode of the NPU;

[0009] The verification platform is further configured to obtain a verification result based on the interface, the verification result indicating whether the NPU is normal, the verification result being obtained based on a software language analysis result, the analysis result being obtained based on a processing result of the NPU based on the clock, the working mode, and the processing data mode, the processing result being obtained based on the interrupt source.

[0010] In a possible implementation, the interface is a basic interface function, and the basic interface function is obtained based on the hardware language.

[0011] In a possible implementation, the verification platform is further configured to obtain a write address and write information of a register based on the software language, obtain the configuration information, and call a write function to process the write address and write information; the register is arranged in the NPU.

[0012] In a possible implementation, the verification platform is further configured to obtain a preset configuration file, and analyze the preset configuration file based on the software language to obtain the processing parameter.

[0013] In a possible implementation, the NPU comprises a clock module, a synchronization management module, and an execution module.

[0014] The clock module is electrically connected to the synchronization management module and the execution module, and the synchronization management module is electrically connected to the execution module.

[0015] The clock module is configured to provide a clock signal to the synchronization management module and the execution module based on the clock parameter.

[0016] The execution module is configured to process the verification data based on the processing parameter to obtain the processing result.

[0017] The synchronization management module is configured to obtain the processing result and coordinate the work of each execution module, generate an interrupt enable signal based on the interrupt source, and generate the analysis result based on the processing result and the interrupt enable signal.

[0018] In a possible implementation, the NPU is electrically connected to a CPU, and the NPU further comprises a control module.

[0019] The mode parameter comprises a first mode and a second mode.

[0020] The first mode is that the CPU, the control module, and the execution module are sequentially electrically connected, the CPU is configured to control the control module, and the control module is configured to control the execution module.

[0021] The second mode is that the CPU is electrically connected to the execution module, and the CPU is configured to control the execution module.

[0022] In a possible implementation, the execution module includes a plurality of execution units.

[0023] The processing result of the execution module includes a calculation result of each execution unit and an execution interruption.

[0024] In a possible implementation, the running result is obtained based on the execution interruption of each execution unit and the corresponding interruption enabling signal.

[0025] In a possible implementation, the configuration information further includes a reset parameter and a start parameter.

[0026] The reset parameter is used to reset the NPU.

[0027] The start parameter is used to start the NPU.

[0028] According to a second aspect of the embodiments of the present application, a method based on soft and hardware joint verification is provided, which is applied to the above-mentioned device based on soft and hardware joint verification, and the method includes:

[0029] obtaining configuration information; transmitting the configuration information to the NPU through an interface; the configuration information is obtained based on a software language; the configuration information includes a clock parameter, an interruption parameter, a mode parameter and a processing parameter; the clock parameter is used to configure a clock of the NPU, the interruption parameter is used to configure an interruption source of the NPU, the mode parameter is used to configure a working mode of the NPU, and the processing parameter is used to configure a processing data mode of the NPU; and the interface is obtained based on a hardware language;

[0030] The verification platform is further configured to obtain a verification result based on the interface; the verification result indicates whether the NPU is normal, the verification result is obtained by the software language analyzing a running result, the running result is obtained by the NPU based on the interruption source and a processing result, and the processing result is obtained by the NPU based on the clock, the working mode and the processing data mode, and processing verification data.

[0031] According to a third aspect of the embodiments of the present application, a computer device is provided, which includes a processor and a memory, the memory is used to store at least one program, the at least one program is loaded and executed by the processor to implement the method based on soft and hardware joint verification as described above.

[0032] According to a fourth aspect of the embodiments of the present application, a computer readable storage medium is provided, which stores at least one program, the at least one program is loaded and executed by a processor to implement the method based on soft and hardware joint verification as described above.

[0033] In the embodiments of the present application, the embodiments of the present application provide a device based on software and hardware joint verification, the NPU is configured based on a software language and operator verification, and a hardware personnel only needs to provide an interface for data interaction of the NPU and a verification platform, so that a software personnel can independently perform operator verification, thereby reducing communication of the software personnel and the hardware personnel, reducing communication cost of the software personnel and the hardware personnel, and improving an NPU operator verification rate. In addition, because the software personnel is flexible relative to the hardware personnel, when the software personnel performs operator verification on the NPU based on the software language, the software personnel does not need to wait until about 80% of module verification is completed before starting operator verification, but can start operator verification after a small part of modules are verified, so that the operator verification starting time is relatively early relative to related art. When a problem is found in the operator verification process, the module verification is far from being completed, so that at this time, the module with the problem is modified, which is relatively easy, thereby further improving the operator verification rate. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0035] Figure 1 is a schematic diagram of an implementation environment according to an embodiment of the present application;

[0036] Figure 2 is a principle schematic diagram of operator verification in NPU verification in related art;

[0037] Figure 3 is a structure schematic diagram of a device based on software and hardware joint verification according to an embodiment of the present application;

[0038] Figure 4 is a principle schematic diagram of configuring an NPU according to an embodiment of the present application;

[0039] Figure 5 is a first structure schematic diagram of an NPU according to an embodiment of the present application.

[0040] Figure 6 is a second structure schematic diagram of an NPU according to an embodiment of the present application.

[0041] Figure 7 is a principle schematic diagram of processing a verification result according to an embodiment of the present application;

[0042] Figure 8is a flowchart of a method for software and hardware joint verification according to an embodiment of the present application;

[0043] Figure 9 is a structural diagram of a terminal according to an embodiment of the present application;

[0044] Figure 10 is a structural diagram of a server according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] For the purpose of making the objects, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0046] The exemplary embodiments will be described in detail herein below with reference to the drawings. The following description is with reference to the drawings, wherein like numerals refer to like elements throughout the several drawings. The embodiments described in the following exemplary embodiments are not meant to represent all embodiments consistent with the present application.

[0047] The terms "first", "second", and the like in the present application are used to distinguish between the same or similar items or elements having substantially the same function and should be understood that there is no logical or chronological dependency between "first", "second", and "n", nor is the quantity and execution order limited. It should also be understood that although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms.

[0048] These terms are only used to distinguish one element from another. For example, without departing from the scope of the various examples, a first action can be called a second action, and similarly, a second action can also be called a first action. The first action and the second action can both be actions, and in some cases, can be separate and distinct actions.

[0049] Wherein, at least one refers to one or more than one, for example, at least one action can be one action, two actions, three actions, etc. any integer greater than or equal to one action. And multiple refers to two or more than two, for example, multiple actions can be two actions, three actions, etc. any integer greater than or equal to two actions.

[0050] Figure 1 is a schematic diagram of an implementation environment according to an embodiment of the present application, which can include a terminal 101 and a server 102.

[0051] In the terminal 101, a device based on software and hardware joint verification is provided, which is used to perform operator verification in NPU verification through the device based on software and hardware joint verification.

[0052] For example, the operator can be a convolution operator, a pooling operator, a fully connected operator, and the like.

[0053] The terminal 101 can be a smart phone with a device based on joint software and hardware verification, a wearable device, a personal computer, a laptop computer, a tablet computer, a smart television, a vehicle-mounted terminal, and the like.

[0054] The server 102 can be a server, a server cluster composed of multiple servers, or a cloud processing center.

[0055] The terminal 101 is connected to the server 102 through a wired or wireless network.

[0056] In some embodiments, the wireless or wired network uses standard communication technologies and / or protocols. The network is usually the Internet, but can also be any network, including but not limited to a local area network (LAN), a metropolitan area network (MAN), a wide area network (WAN), a mobile, wired or wireless network, a private network or any combination of virtual private networks. In some embodiments, technologies and / or formats including HyperText Mark-up Language (HTML), Extensible Markup Language (XML), and the like are used to represent data exchanged through the network. In addition, all or some links can be encrypted using conventional encryption technologies such as Secure Socket Layer (SSL), Transport Layer Security (TLS), Virtual Private Network (VPN), Internet Protocol Security (IPsec), and the like. In other embodiments, custom and / or dedicated data communication technologies can be used instead of or in addition to the above data communication technologies.

[0057] Figure 2 is a schematic diagram of the principle of operator verification in NPU verification in the related art.

[0058] In the related art, when performing operator verification in NPU verification, a verification platform is started, and a main program is entered. A phase-locked loop and a clock frequency of the NPU are configured based on a hardware language, and then the NPU is reset, and the clock of each module in the NPU is turned on. The interrupt source of each module is configured based on the hardware language. The working mode of the NPU is configured based on the hardware language. A preset configuration file is parsed based on the hardware language, and the preset configuration file is used to configure each execution unit. An execution result of each execution unit is obtained, and a verification result is obtained based on the execution result of each execution unit. The verification result is parsed based on the hardware language. The preset configuration file is obtained based on a software language. The main program is ended, and the verification platform ends running.

[0059] In the above verification method, since the configuration and verification of the NPU are both implemented based on the hardware language, the configuration and verification of the NPU both need the participation of hardware personnel.

[0060] However, since the hardware personnel is relatively scarce and cannot be flexibly configured, the hardware personnel configured for a project is often configured for the next project after the project is completed. Therefore, the hardware personnel needs to wait until about 80% of the module verification is completed before starting the operator verification. As a result, the operator verification starts relatively late, and the operator verification involves a large number of modules. When a problem is found in the operator verification process, the module verification is basically completed. Therefore, it is very difficult to modify the module with the problem at this time, and thus the speed of the operator verification is reduced.

[0061] In addition, the communication cost between the software personnel and the hardware personnel is large, which further reduces the speed of the operator verification.

[0062] To solve the above technical problems in the related art, embodiments of the present application provide the following technical solutions.

[0063] Figure 3 is a structural schematic diagram of a device based on software and hardware joint verification provided by an embodiment of the present application, and the device comprises:

[0064] The verification platform 300 is provided with an interface 301, and the verification platform 300 is electrically connected to the NPU 400 to be verified based on the interface 301. The interface 301 is obtained based on a hardware language.

[0065] The verification platform 300 is built based on a software language. The NPU 400 is also built based on a hardware language.

[0066] It should be noted that the hardware language can be obtained from the related art, and embodiments of the present application will not be described again.

[0067] Figure 4is a principle schematic diagram of configuring an NPU 400 according to an embodiment of the present application.

[0068] By comparison Figure 3 and Figure 4 It can be known that, an embodiment of the present application is based on software language to configure the NPU 400 and to verify the operators in the NPU 400 verification, and the related art is based on hardware language to configure the NPU 400 and to verify the operators in the NPU 400 verification. That is, in the embodiment of the present application, the software personnel can independently configure the operators NPU 400 and verify the operators based on the software language. Compared with the related art, the communication between the software personnel and the hardware personnel is greatly reduced, thereby greatly reducing the communication cost between the software personnel and the hardware personnel, and further improving the verification rate of the operators.

[0069] The principle of configuring the NPU 400 will be exemplarily described below. Figure 4

[0070] In some embodiments, the verification platform 300 is configured to obtain configuration information, transmit the configuration information to the NPU 400 through the interface 301, wherein the configuration information is obtained based on a software language, and the configuration information includes clock parameters, interrupt parameters, mode parameters, and processing parameters, the clock parameters are used to configure the clock of the NPU 400, the interrupt parameters are used to configure the interrupt source of the NPU 400, the mode parameters are used to configure the working mode of the NPU 400, and the processing parameters are used to configure the processing data mode of the NPU 400.

[0071] In one example, the software personnel obtains the configuration information based on the software language.

[0072] For example, the software language can be C language or C++.

[0073] In one example, the interface 301 is a basic interface 301 function, and the basic interface 301 function is obtained based on a hardware language.

[0074] In one example, the hardware personnel can configure the basic interface 301 function through the hardware language.

[0075] In the embodiment of the present application, only the hardware personnel needs to configure the interface 301, and the interface 301 basically does not need to be changed after being configured. Therefore, after the interface 301 is configured, the hardware personnel does not need to participate in the configuration and verification of the NPU 400, thereby reducing the communication cost between the software personnel and the hardware personnel, and further improving the verification rate of the operators.

[0076] ​In one example, since the configuration information is obtained based on the software language and the NPU 400 is hardware, the NPU 400 cannot directly identify the configuration information configured by the software language. Therefore, in order to facilitate the NPU 400 to identify the configuration information, the embodiments of the present application introduce a DPI (Direct Programming Interface) mechanism.

[0077] The DPI mechanism can be understood as being used to interact with external C / C++ code in verilog or system verilog. The interface 301 is the DPI interface. After the interface 301 obtains the configuration information, the interface 301 calls a basic interface 301 function to convert the data format of the configuration information to obtain configuration information that can be identified by the NPU 400. That is, the DPI mechanism is used to realize data interaction between the NPU 400 and the verification platform 300.

[0078] In one example, the interrupt source can include error interrupts and end interrupts of each module in the NPU 400. The error interrupt indicates that an error occurs in the running of the corresponding module. The end interrupt indicates that the running of the corresponding module ends.

[0079] It can be understood that at least one of the following situations can cause an error in the running of the module in the actual running process of the NPU 400. At least one of the following situations can cause the running of the module to end.

[0080] In some embodiments, the verification platform 300 is further configured to obtain a write address and write information of a register based on the software language, to obtain the configuration information, and to call a write function to process the write address and the write information. The register is arranged in the NPU.

[0081] In one example, the verification platform 300 writes the write address into a write address position of the write function and writes the write information into a write information position of the write function based on the software language.

[0082] It should be noted that the write function can be obtained from related technologies, and the embodiments of the present application will not be described in detail.

[0083] In one example, the clock parameter can include a clock write address and clock write information written into the write function.

[0084] In one example, the interrupt parameter can include an interrupt write address and interrupt write information written into the write function.

[0085] In one example, the mode parameter can include a mode write address and mode write information written into the write function.

[0086] In one example, the processing parameter can include a processing write address of writing a write function and processing write information.

[0087] Figure 5 is a first structure schematic diagram of the NPU 400 provided according to an embodiment of the present application.

[0088] The following will be described in combination with Figure 5 The first structure of the NPU 400 is exemplarily described.

[0089] In some embodiments, the NPU 400 includes a clock module 403, a synchronization management module 401, and an execution module 402.

[0090] The clock module 403 is electrically connected with the synchronization management module 401 and the execution module 402 respectively, and the synchronization management module 401 is electrically connected with the execution module 402.

[0091] The clock module 403 is configured to provide clock signals to the synchronization management module 401 and the execution module 402 based on clock parameters.

[0092] The execution module 402 is configured to process the verification data based on the processing parameter to obtain a processing result.

[0093] The synchronization management module 401 is configured to obtain the processing result and coordinate the work of each execution module 402, generate an interrupt enable signal based on an interrupt source, and generate a running result based on the processing result and the interrupt enable signal.

[0094] The following will be described in combination with two examples to exemplarily describe the function of the synchronization management module 401.

[0095] In the first example, the synchronization management module 401 performs a synchronization function. The synchronization management module 401 is electrically connected with a first function module and a second function module. The first function module and the second function module are arranged in the NPU 400. The second function module runs based on the output result of the first function module. At least one enable register is arranged in the synchronization management module 401. The NPU 400 can be provided with a plurality of function registers. The first function module and the second function module correspond to at least one function register respectively.

[0096] For example, the second function module executes a wait instruction, that is, the second function module waits for the output result of the first function module. When the first function module obtains the output result, the first register in the synchronization management module 401 is written with “1”. When the second function module recognizes that the value of the first register in the synchronization management module 401 is updated to “1”, the value in the corresponding function register is obtained. After the second function module completes the configuration, the second function module is started.

[0097] In a second example, the synchronization management module 401 performs an interrupt function. In this case, the synchronization management module 401 performs an operation on the interrupt of each module in the NPU 400 to obtain a running result.

[0098] The running result can be understood as an NPU 400 interrupt.

[0099] For example, the synchronization management module 401 obtains an error interrupt or an end interrupt of each module of the NPU 400, and performs an OR operation on the error interrupt or the end interrupt of each module to obtain the NPU 400 interrupt.

[0100] The NPU 400 interrupt can include an NPU 400 error interrupt and an NPU 400 end interrupt. The NPU 400 error interrupt indicates that an error occurs in the running of the NPU 400. The NPU 400 end interrupt indicates that the running of the NPU 400 ends.

[0101] For example, the synchronization management module 401 can be a SM (Sync Manager).

[0102] The configurations of the modules of the NPU 400 will be described below in combination with several examples.

[0103] It can be understood that the clock module 403, the synchronization management module 401, and the execution module 402 each correspond to at least one function register.

[0104] In a first example, after obtaining the configuration information, the NPU 400 identifies the configuration information to obtain a clock parameter. Based on a clock write address, a corresponding function register is determined, and clock write information is written into the function register corresponding to the clock parameter. The clock parameter corresponding write information can include a phase-locked loop and a clock frequency, etc.

[0105] In a second example, after obtaining the configuration information, the NPU 400 identifies the configuration information to obtain an interrupt parameter. Based on an interrupt write address, a corresponding enable register is determined, and interrupt write information is written into the enable register corresponding to the interrupt parameter.

[0106] For example, the interrupt write information can be “0” or “1”.

[0107] In a third example, after obtaining the configuration information, the NPU 400 identifies the configuration information to obtain a mode parameter. Based on a mode write address, a corresponding function register is determined, and mode write information is written into the function register corresponding to the mode parameter.

[0108] In the fourth example, after obtaining the configuration information, the NPU 400 identifies the configuration information to obtain the processing parameter. Based on the processing write address, the corresponding function register is determined, and the processing write information is written into the function register corresponding to the processing parameter.

[0109] In some embodiments, the execution module 402 includes a plurality of execution units (EU). The processing result of the execution module 402 includes the calculation result of each execution unit and the execution interrupt.

[0110] In one example, after processing the corresponding verification data, each execution unit obtains the calculation result and the execution interrupt.

[0111] For one execution unit, the execution unit writes the calculation result into the corresponding function register and sends the execution interrupt to the synchronization management module 401.

[0112] In some embodiments, the running result is obtained based on the execution interrupt of each execution unit and the corresponding interrupt enable signal.

[0113] In one example, an execution unit is taken as an example for explanation. After obtaining the execution interrupt of one execution unit, the synchronization management module 401 generates the interrupt enable signal based on the interrupt write information in the corresponding enable register. The synchronization management module 401 performs the first operation on the execution interrupt of the execution unit and the interrupt enable signal to obtain the first operation result. When the interrupt write information is “1”, the interrupt enable signal is enabled.

[0114] Similarly, the first operation result of each execution unit can be obtained.

[0115] Then, the synchronization management module 401 performs the second operation on the operation result corresponding to each execution unit to obtain the NPU 400 interrupt and output to the NPU 400.

[0116] For example, the first operation can be the AND operation. The second operation can be the OR operation.

[0117] For example, the AND operation is performed on the execution interrupt corresponding to the execution unit and the interrupt enable signal to obtain the interrupt enable signal. That is, when the interrupt enable signal is enabled, the first operation result is enabled. When the interrupt enable signal is not enabled, the first operation result is not enabled.

[0118] Next, the NPU 400 outputs the NPU 400 interrupt to the verification platform 300 through the interface 301, and the verification platform 300 analyzes the NPU 400 interrupt based on the software language to obtain the verification result.

[0119] Figure 6Fig. 2 is a second structural schematic diagram of the NPU 400 according to an embodiment of the present application.

[0120] The following will be described in combination with Figure 6 The second structure of the NPU 400 is exemplarily described.

[0121] In some embodiments, the NPU 400 is electrically connected with a CPU 500 (Central Processing Unit). The NPU 400 further includes a control module 404.

[0122] The mode parameters include a first mode and a second mode.

[0123] The first mode is that the CPU 500, the control module 404 and the execution module 402 are sequentially electrically connected; the CPU 500 is configured to control the control module 404, and the control module 404 is configured to control the execution module 402.

[0124] The second mode is that the CPU 500 is electrically connected with the execution module 402. The CPU 500 is configured to control the execution module 402.

[0125] The control module 404 is electrically connected with a clock module 403. The clock module 403 provides a clock signal to the control module 404 during the running of the NPU.

[0126] It can be understood that, in the first mode, the control module 404 is not started. In the second mode, the control module 404 is started.

[0127] For example, the control module 404 can be a dsptch module. The dsptch module can be configured to configure running information and starting information of the execution module 402, etc.

[0128] It should be noted that, in addition to the above-mentioned several modules, the NPU 400 can further include other modules, and the embodiments of the present application will not be described in detail.

[0129] In some embodiments, the verification platform 300 is further configured to obtain a preset configuration file, parse the preset configuration file based on a software language to obtain a processing parameter.

[0130] In one example, the preset configuration file can include processing information required by an operator running. The processing information is obtained by parsing the preset configuration file based on the software language. The processing information includes a processing write address and a processing write information. The verification platform 300 writes the processing write address into a write address position of a write function and writes the processing write information into a write information position of the write function based on the software language, to obtain the processing parameter.

[0131] The processing parameter is configured to indicate how the execution unit runs.

[0132] For example, the preset configuration file can include information required by the operator to run and verification data. The verification data can include the size of the image, etc.

[0133] In some embodiments, the configuration information further includes a reset parameter and a start parameter.

[0134] The reset parameter is used to reset the NPU 400.

[0135] The start parameter is used to start the NPU 400.

[0136] In one example, the NPU 400 writes the reset write information in the reset parameter into the function register corresponding to each module, and then each module can call the reset write information in the corresponding function register to realize the reset.

[0137] In one example, the NPU 400 writes the start write information in the start parameter into the function register corresponding to each module, and then each module can call the start write information in the corresponding function register to realize the start of each module, and then start the NPU 400.

[0138] For example, the start write information can be used to start the clock module 403, the synchronization management module 401, and the execution module 402, etc.

[0139] In some embodiments, the verification platform 300 is further configured to obtain a verification result based on the interface 301; the verification result indicates whether the NPU 400 is normal, the verification result is obtained by software language parsing a running result, the running result is obtained by the NPU 400 based on an interrupt source and a processing result, and the processing result is obtained by the NPU 400 based on a clock, a working mode, and a processing data mode, and processing the verification data.

[0140] In one example, the verification platform 300 is started, and the main program is entered. The NPU 400 resets the clock module 403, the synchronization management module 401, the control module 404, and the execution module 402 based on the reset write information in the at least one function register. The NPU 400 configures the first mode based on the mode write information in the at least one function register, and then starts the clock module 403, the synchronization management module 401, the control module 404, and each execution unit.

[0141] In one example, after starting each execution unit, each execution unit processes the configured verification data based on the configured processing data mode under the control of the clock signal provided by the clock module 403 and the control module 404, to obtain a calculation result and an execution interrupt. Each execution unit sends the execution interrupt to the synchronization management module 401.

[0142] In one example, for one execution unit, the synchronization management module 401 calls the interrupt write information in the enable register corresponding to the execution unit, generates a corresponding interrupt enable signal. The synchronization management module 401 performs an and operation on the execution interrupt of the execution unit and the interrupt enable signal, and obtains a first operation result corresponding to the execution unit. The synchronization management module 401 performs an or operation on all first operation results, obtains an NPU 400 interrupt, and outputs to the NPU 400. After obtaining the NPU 400 interrupt, the NPU 400 sends the NPU 400 interrupt to the verification platform 300 through the interface 301.

[0143] In one example, the verification platform 300 parses the NPU 400 interrupt based on the software language, obtains a verification result, ends the main program, and the verification platform 300 ends running. When the NPU 400 interrupt is an error interrupt, the verification result indicates that the operator verification fails. When the NPU 400 interrupt is an end interrupt, the verification result indicates that the operator verification succeeds.

[0144] In one example, when the verification result indicates that the operator verification fails, the reason for the failure is parsed based on the software language, and the failure reason is obtained. The failure reason can include software errors and hardware errors.

[0145] When the failure reason is a software error, the failure reason is fed back to the software personnel for solving. When the failure reason is a hardware error, the failure reason is fed back to the hardware personnel for solving.

[0146] In one example, the verification platform 300 can generate a verification pass rate table based on the verification results of multiple operator verifications. The verification pass rate, that is, the probability of successful operator verification.

[0147] In one example, the verification platform 300 can display the verification pass rate table on the user interface, so that the software personnel or the hardware personnel can view the verification result.

[0148] Figure 7 is a schematic diagram of a principle for processing a verification result according to an embodiment of the present application.

[0149] The following will be described in conjunction with Figure 7 The principle of processing the verification result is exemplarily described.

[0150] In one example, a test / regression of one operator verification is taken as an example for explanation and description. When the test / regression of the operator verification passes, that is, the operator verification succeeds, the main program ends, and the verification platform 300 ends running.

[0151] In one example, still taking the test / regression of one operator verification as an example for explanation and illustration. When the test / regression of the operator verification fails, that is, the operator verification fails, it is determined whether it is a software error or a hardware error based on the software language.

[0152] If it is a software error, the software error is fed back to the software personnel. After the software personnel solves the software error, the verification platform 300 re-executes the operator verification.

[0153] If it is a hardware error, the hardware error is fed back to the hardware personnel. After the hardware personnel solves the hardware error, the verification platform 300 re-executes the operator verification.

[0154] For example, the software error can be an error in the software language parsing a preset configuration file. The hardware error can be an error of the NPU 400.

[0155] After the operator verification is completed, the main program ends, and the verification platform 300 ends running.

[0156] In the embodiments of the present application, the NPU is configured based on the software language and the operator verification. The hardware personnel only needs to provide an interface for data interaction between the NPU and the verification platform, so that the software personnel can independently perform the operator verification, thereby reducing the communication between the software personnel and the hardware personnel, reducing the communication cost of the software personnel and the hardware personnel, and improving the NPU operator verification rate. In addition, since the software personnel is more flexible in configuration than the hardware personnel, when the software personnel performs the operator verification on the NPU based on the software language, the software personnel does not need to wait until about 80% of the module verification is completed before starting the operator verification, but can start the operator verification after a small part of the module verification is completed, so that the operator verification starts earlier than in the related art. When a problem is found in the operator verification process, the module verification is far from being completed, so that it is relatively easy to modify the module with the problem at this time, thereby further improving the operator verification rate.

[0157] Figure 8 is a flowchart of a method of software and hardware joint verification according to an embodiment of the present application, as shown in Figure 8 In the embodiments of the present application, a terminal with a device based on software and hardware joint verification is taken as an example for illustration. The method includes the following steps:

[0158] In step 801, the terminal acquires configuration information; transmits the configuration information to the NPU through an interface; the configuration information is obtained based on a software language; the configuration information includes clock parameters, interrupt parameters, mode parameters, and processing parameters; the clock parameters are used to configure the clock of the NPU, the interrupt parameters are used to configure the interrupt source of the NPU, the mode parameters are used to configure the working mode of the NPU, and the processing parameters are used to configure the processing data mode of the NPU; and the interface is obtained based on a hardware language.

[0159] In step 802, the verification platform of the terminal is further configured to acquire a verification result based on the interface; the verification result indicates whether the NPU is normal, the verification result is obtained by analyzing a running result of the software language, the running result is obtained by the NPU based on the interrupt source and a processing result, and the processing result is obtained by the NPU based on the clock, the working mode, and the processing data mode, by processing verification data.

[0160] In some embodiments, the interface is a basic interface function, which is obtained based on the hardware language.

[0161] In some embodiments, the method further includes: acquiring a write address and write information of a register based on the software language, obtaining the configuration information, and calling a write function to process the write address and write information; and the register is arranged in the NPU.

[0162] In some embodiments, the method further includes: acquiring a preset configuration file, and analyzing the preset configuration file based on the software language to obtain the processing parameters.

[0163] In some embodiments, the method further includes: providing a clock signal to the synchronization management module and the execution module based on the clock parameters;

[0164] processing the verification data based on the processing parameters to obtain the processing result;

[0165] acquiring the processing result and coordinating the work of each execution module; generating an interrupt enable signal based on the interrupt source, and generating the running result based on the processing result and the interrupt enable signal.

[0166] In some embodiments, the mode parameters include a first mode and a second mode.

[0167] The first mode is that the CPU, the control module, and the execution module are sequentially electrically connected; the CPU is used to control the control module, and the control module is used to control the execution module.

[0168] The second mode is that the CPU is electrically connected with the execution module; and the CPU is used to control the execution module.

[0169] In some embodiments, the processing result of the execution module includes a calculation result of each execution unit and an execution interruption.

[0170] In some embodiments, the running result is obtained based on the execution interruption of each execution unit and the corresponding interruption enabling signal.

[0171] In some embodiments, the configuration information further includes a reset parameter and a start parameter.

[0172] The reset parameter is used to reset the NPU.

[0173] The start parameter is used to start the NPU.

[0174] It should be noted that the device based on the soft and hardware joint verification provided in the above embodiments and the method based on the soft and hardware joint verification belong to the same concept, and the specific implementation process is detailed in the device embodiment, which will not be repeated here.

[0175] Embodiments of the present application configure and operator verify the NPU based on the software language, and hardware personnel only need to provide an interface for data interaction between the NPU and the verification platform, so that software personnel can independently perform operator verification, thereby reducing the communication between software personnel and hardware personnel, reducing the communication cost of software personnel and hardware personnel, and improving the NPU operator verification rate. In addition, since the software personnel are more flexible in configuration than the hardware personnel, when the software personnel perform operator verification on the NPU based on the software language, they do not need to wait until about 80% of the module verification is completed before starting operator verification, but can start operator verification after a small part of the module is verified, so that the operator verification start time is relatively early compared with related technologies. When problems are found during operator verification, module verification is far from being completed, so at this time, it is relatively easy to modify the module with problems, thereby further improving the operator verification rate.

[0176] Embodiments of the present application also provide a computer device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the above method when executing the computer program.

[0177] Taking the computer device as an example, Figure 9 is a structural schematic diagram of a terminal provided by an embodiment of the present application, referring to Figure 9The terminal 900 can be a smartphone, a tablet computer, an MP3 player (Moving Picture Experts Group Audio Layer III), an MP4 player (Moving Picture Experts Group Audio Layer IV), a notebook computer, or a desktop computer. The terminal 900 can also be referred to as a user equipment, a portable terminal, a laptop terminal, a desktop terminal, or other names.

[0178] Generally, the terminal 900 includes a processor 901 and a memory 902.

[0179] The processor 901 can include one or more processing cores, such as a 4-core processor, a 9-core processor, and the like. The processor 901 can be implemented in the form of at least one of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), a PLA (Programmable Logic Array). The processor 901 can also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also referred to as a CPU (Central Processing Unit). The coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 901 can be integrated with a GPU (Graphics Processing Unit) for rendering and drawing content required to be displayed on a display screen. In some embodiments, the processor 901 can further include an AI (Artificial Intelligence) processor for processing machine learning-related computing operations.

[0180] The memory 902 can include one or more computer-readable storage media, which can be non-transitory. The memory 902 can also include a high-speed random access memory, and a non-volatile memory such as one or more disk storage devices, flash storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 902 is used to store at least one program code for being executed by the processor 901 to implement a process performed by a terminal in a method for mixed-precision floating-point multiplication and accumulation operation provided by the method embodiments in the present application.

[0181] In some embodiments, the terminal 900 can further optionally include a peripheral device interface 903 and at least one peripheral device. The processor 901, the memory 902 and the peripheral device interface 903 can be connected through a bus or a signal line. Each peripheral device can be connected to the peripheral device interface 903 through a bus, a signal line or a circuit board. Specifically, the peripheral device includes at least one of a display screen 904, a camera component 905, an audio circuit 906 and a power supply 907.

[0182] The peripheral device interface 903 can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 901 and the memory 902. In some embodiments, the processor 901, the memory 902 and the peripheral device interface 903 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 901, the memory 902 and the peripheral device interface 903 can be implemented on a separate chip or circuit board, and the embodiments of the present application do not limit this.

[0183] The display screen 904 is used to display a UI (User Interface). The UI can include graphics, text, icons, video and any combination thereof. When the display screen 904 is a touch display screen, the display screen 904 also has the ability to collect touch signals on or above the surface of the display screen 904. The touch signals can be input to the processor 901 as control signals for processing. At this time, the display screen 904 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 904 can be one, arranged on the front panel of the terminal 900; in some other embodiments, the display screen 904 can be at least two, arranged on different surfaces of the terminal 900 or in a folding design; in some other embodiments, the display screen 904 can be a flexible display screen, arranged on a curved surface or a folding surface of the terminal 900. Even, the display screen 904 can also be arranged in an irregular shape, that is, a special-shaped screen. The display screen 904 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0184] The camera component 905 is configured to capture images or videos. In some embodiments, the camera component 905 includes a front-facing camera and a rear-facing camera. Generally, the front-facing camera is disposed on the front panel of the terminal, and the rear-facing camera is disposed on the back of the terminal. In some embodiments, the rear-facing camera is at least two, which is any one of a main camera, a depth-of-field camera, a wide-angle camera, and a telephoto camera, to realize the background blur function of the main camera and the depth-of-field camera, the panorama shooting and VR (Virtual Reality) shooting function of the main camera and the wide-angle camera, or other fusion shooting functions. In some embodiments, the camera component 905 can also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. The dual-color temperature flash refers to the combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0185] The audio circuit 906 can include a microphone and a speaker. The microphone is configured to capture sound waves of a user and an environment, and convert the sound waves into an electrical signal input to the processor 901 for processing. For the purpose of stereo sound capture or noise reduction, the microphone can be multiple, which are respectively disposed at different parts of the terminal 900. The microphone can also be an array microphone or an omnidirectional capture microphone. The speaker is configured to convert an electrical signal from the processor 901 into sound waves. The speaker can be a traditional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert an electrical signal into a sound wave audible to humans, but also convert an electrical signal into an inaudible sound wave to humans for ranging purposes. In some embodiments, the audio circuit 906 can also include a headphone jack.

[0186] The power supply 907 is configured to supply power to each component in the terminal 900. The power supply 907 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery. When the power supply 907 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0187] Those skilled in the art can understand that the structure shown in the foregoing embodiments is not a limitation on the terminal 900, and the terminal 900 can include more or fewer components than those shown in the drawings, or combine certain components, or use a different arrangement of components. Figure 9 The structure shown in the foregoing embodiments is not a limitation on the terminal 900, and the terminal 900 can include more or fewer components than those shown in the drawings, or combine certain components, or use a different arrangement of components.

[0188] Taking a computer device as an example, Figure 10This is a structural diagram of a server provided in an embodiment of the present application. The server 1000 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 1001 and one or more memories 1002, wherein at least one computer program is stored in the one or more memories 1002, and the at least one computer program is loaded and executed by the one or more processors 1001 to implement the above-mentioned method based on joint verification of software and hardware. Of course, the server 1000 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The server 1000 may also include other components for realizing device functions, which will not be described in detail here.

[0189] An embodiment of the present application further provides a computer-readable storage medium, the computer-readable storage medium including a stored computer program, wherein when the computer program is executed, the device containing the computer-readable storage medium is controlled to execute the above-described method for generating an image processing model. Optionally, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, or the like.

[0190] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0191] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A device based on hardware-software joint verification, characterized in that, The application relates to a verification platform and an NPU. The verification platform is electrically connected with the NPU to be verified based on an interface obtained based on a hardware language. The verification platform obtains configuration information and transmits the configuration information to the NPU through the interface; the configuration information is obtained based on a software language; the configuration information comprises clock parameters, interruption parameters, mode parameters and processing parameters; the clock parameters are used for configuring the clock of the NPU, the interruption parameters are used for configuring the interruption source of the NPU, the mode parameters are used for configuring the working mode of the NPU, and the processing parameters are used for configuring the processing data mode of the NPU. The verification platform obtains a verification result based on the interface; the verification result indicates whether the NPU is normal; the verification result is obtained by analyzing a running result of the software language; the running result is obtained by the NPU based on the interruption source and a processing result; the processing result is obtained by the NPU based on the clock, the working mode and the processing data mode.

2. The apparatus of claim 1, wherein, The interface is a basic interface function obtained based on the hardware language.

3. The apparatus of claim 1, wherein, The verification platform obtains the write address and write information of a register based on the software language, obtains the configuration information, and calls a write function to process the write address and write information; the register is arranged in the NPU.

4. The apparatus of claim 1, wherein, The verification platform obtains a preset configuration file, analyzes the preset configuration file based on the software language, and obtains the processing parameters.

5. The apparatus of claim 1, wherein, The NPU comprises a clock module, a synchronization management module and an execution module. The clock module is electrically connected with the synchronization management module and the execution module; the synchronization management module is electrically connected with the execution module. The clock module provides clock signals to the synchronization management module and the execution module based on the clock parameters. The execution module processes the verification data based on the processing parameters to obtain the processing result. The synchronization management module obtains the processing result and coordinates the work of each execution module. An interruption enable signal is generated based on the interruption source; the running result is generated based on the processing result and the interruption enable signal.

6. The apparatus of claim 5, wherein, The NPU is electrically connected with a CPU; the NPU further comprises a control module. The mode parameters comprise a first mode and a second mode. The first mode is that the CPU, the control module and the execution module are sequentially electrically connected; the CPU is used for controlling the control module, and the control module is used for controlling the execution module. The second mode is that the CPU is electrically connected with the execution module; the CPU is used for controlling the execution module.

7. The apparatus of claim 5, wherein, The execution module comprises a plurality of execution units. The processing result of the execution module comprises the calculation result of each execution unit and an execution interruption.

8. The apparatus of claim 7, wherein, The running result is obtained based on the execution interruption of each execution unit and the corresponding interruption enable signal.

9. The apparatus of claim 1, wherein, The configuration information further comprises a reset parameter and a start parameter; The reset parameter is used for resetting the NPU; The start parameter is used for starting the NPU. 10.A method based on soft and hardware joint verification, applied to the device based on soft and hardware joint verification in any one of claims 1 to 9, characterized in that, Comprise: Obtaining configuration information; Transmitting the configuration information to the NPU through an interface; The configuration information is obtained based on a software language; The configuration information comprises a clock parameter, an interrupt parameter, a mode parameter and a processing parameter; the clock parameter is used for configuring a clock of the NPU, the interrupt parameter is used for configuring an interrupt source of the NPU, the mode parameter is used for configuring a working mode of the NPU, and the processing parameter is used for configuring a processing data mode of the NPU; and the interface is obtained based on a hardware language; The verification platform is further configured to obtain a verification result based on the interface; the verification result indicates whether the NPU is normal; the verification result is obtained based on an analysis result of the software language; the analysis result is obtained based on a processing result of the NPU; the processing result is obtained based on the clock, the working mode and the processing data mode.

11. A computer device, comprising: The computer device comprises a processor and a memory; the memory is used for storing at least one program; the at least one program is loaded and executed by the processor to implement the method for joint verification based on software and hardware as claimed in claim 10.

12. A computer-readable storage medium, characterized in that, The computer readable storage medium stores at least one program; the at least one program is loaded and executed by the processor to implement the method for joint verification based on software and hardware as claimed in claim 10.

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