A method, device, equipment and storage medium for optimizing communication between storage controllers

Abstract

The present application discloses a method, device, equipment and storage medium for optimizing communication between storage controllers, and relates to the field of storage technology. The method includes: determining the non-consistent memory access node corresponding to the source data as the first node, and determining the non-consistent memory access node corresponding to the non-transparent bridge device as the second node; judging whether the source data meets the migration conditions according to the data migration rules based on the physical distance between the first node and the second node; if the migration conditions are met, the source data is moved from the first node to the target central processor where the second node is located; through the non-transparent bridge device, the source data is read from the target central processor, and the source data is transmitted to the opposite storage controller. It can reduce the delay of the non-transparent bridge device in reading the source data and improve the efficiency of data synchronization between storage controllers.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a method, device, equipment and storage medium for optimizing communication between storage controllers. Background Art

[0002] In the storage field, the reliability of the entire storage system is inseparable from the devices attached to it, and the transmission of data depends on the support of various storage components. Among them, the non-transparent bridge (NTB) device plays the role of synchronizing data between storage controllers. However, with the continuous development of chips, the central processing unit (CPU) architecture has changed. The change in processor architecture has led to a significant decline in the performance of non-transparent bridge devices, which in turn has led to a decline in the transmission performance of storage controllers. Summary of the invention

[0003] In view of this, the purpose of the present invention is to provide a method, device, equipment and storage medium for optimizing communication between storage controllers, which can reduce the delay of non-transparent bridge devices reading source data and improve the efficiency of data synchronization between storage controllers. The specific scheme is as follows:

[0004] In a first aspect, the present application discloses a method for optimizing communication between storage controllers, which is applied to a storage controller, comprising:

[0005] Determine a non-consistent memory access node corresponding to the source data as a first node, and determine a non-consistent memory access node corresponding to the non-transparent bridge device as a second node;

[0006] According to the physical distance between the first node and the second node, judging whether the source data meets the migration condition according to the data migration rule;

[0007] If the migration condition is met, the source data is migrated from the first node to the target central processor where the second node is located;

[0008] The source data is read from the target central processor through the non-transparent bridge device, and the source data is transmitted to the opposite end storage controller.

[0009] Optionally, judging whether the source data meets the migration condition according to a data migration rule based on a physical distance between the first node and the second node includes:

[0010] determining whether the first node and the second node are in the same central processing unit;

[0011] If they are in different CPUs, it is determined that the source data meets the migration conditions;

[0012] If they are in the same CPU, it is determined that the source data does not meet the migration conditions.

[0013] Optionally, moving the source data from the first node to a target central processor where the second node is located includes:

[0014] The source data is moved from the first node to the target central processor where the second node is located by using the direct memory access thread corresponding to the cache where the source data is located.

[0015] Optionally, before the source data is moved from the first node to the target central processor where the second node is located, the method further includes:

[0016] Allocate two or more direct memory access threads to each cache;

[0017] Moving the source data from the first node to a target central processor where the second node is located includes:

[0018] The source data is moved from the first node to the target central processor where the second node is located by using all direct memory access threads corresponding to the cache where the source data is located.

[0019] Optionally, the direct memory access thread is an asynchronous thread.

[0020] Optionally, moving the source data from the first node to a target central processor where the second node is located includes:

[0021] By calling a memory copy function, the source data is moved from the first node to the target central processor where the second node is located.

[0022] Optionally, reading the source data from the target central processor and transmitting the source data to a peer storage controller includes:

[0023] Mirroring the source data in the target central processor through the non-transparent bridge device to obtain mirrored source data;

[0024] The mirror source data is transmitted to the opposite end storage controller.

[0025] Optionally, the non-transparent bridge device is built-in or plugged into a central processing unit.

[0026] Optionally, moving the source data from the first node to a target central processor where the second node is located includes:

[0027] Select any non-uniform memory access node from the target central processor where the second node is located as the target node;

[0028] The source data is moved from the first node to the target node.

[0029] Optionally, the architecture of the central processing unit enables non-uniform memory access nodes by default.

[0030] Optionally, moving the source data from the first node to a target central processor where the second node is located includes:

[0031] Determine a storage address of the source data at the first node to obtain a first storage address, and associate the source data with the first storage address;

[0032] The method comprises: reading the source data from the target central processor through the non-transparent bridge device, and transmitting the source data to the opposite end storage controller, including:

[0033] The source data is read from the target central processor through the non-transparent bridge device, and the source data and the first storage address are transmitted together to the opposite storage controller, so that the opposite storage controller determines the second storage address corresponding to the first storage address in the opposite storage controller according to the first storage address, and stores the source data in the second storage address.

[0034] Optionally, storing the source data to the second storage address includes:

[0035] The source data is stored in the second storage address in parallel through a plurality of direct memory access threads.

[0036] In a second aspect, the present application discloses a computer program product, including a computer program, which implements the aforementioned method for optimizing communication between storage controllers when executed by a processor.

[0037] In a third aspect, the present application discloses an electronic device, including:

[0038] Memory, used to store computer programs;

[0039] The processor is used to execute the computer program to implement the aforementioned method for optimizing communication between storage controllers.

[0040] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned method for optimizing communication between storage controllers.

[0041] In the present application, a non-consistent memory access node corresponding to source data is determined as a first node, and a non-consistent memory access node corresponding to a non-transparent bridge device is determined as a second node; based on the physical distance between the first node and the second node, whether the source data meets the migration conditions is judged according to data migration rules; if the migration conditions are met, the source data is moved from the first node to the target central processor where the second node is located; through the non-transparent bridge device, the source data is read from the target central processor, and the source data is transmitted to the opposite storage controller.

[0042] Since the non-transparent bridge device is used to transmit data between storage controllers, the farther the node storing the source data is from the node where the non-transparent bridge device is located, the longer the time required for the non-transparent bridge to read the data. Therefore, by analyzing the distance between the first node where the source data is located and the second node where the non-transparent bridge device is located, when the data migration conditions are met, before the non-transparent bridge device reads the data, the source data is first moved from the first node to the central processing unit where the non-transparent bridge device is located, so as to reduce the delay of the non-transparent bridge device in reading the source data, thereby improving the efficiency of data synchronization between storage controllers. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0044] FIG1 is a flow chart of a method for optimizing communication between storage controllers provided by the present application;

[0045] Figure 2 A schematic diagram of a specific internal structure of a storage controller provided in this application;

[0046] Figure 3 A specific schematic diagram of the relationship between the CPU core and memory provided for this application;

[0047] FIG4 is a schematic diagram of the structure of a storage controller communication optimization device provided by the present application;

[0048] FIG5 is a structural diagram of an electronic device provided in this application. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] In the existing technology, the speed and amount of data generation are growing exponentially, from personal users' social media content to corporate operational data, and then to the accumulation of data in scientific research and healthcare. With the application and development of cloud computing and big data, the amount of information in various fields has exploded, and the amount of data is huge, which places great demands on the data processing of storage devices. With the continuous acceleration of digital transformation, facing the exponential growth of massive data, how to store data more safely, reliably and efficiently has brought greater challenges to storage. The increase in data volume requires storage systems to have high-speed data transmission capabilities and low-latency response speeds to avoid performance degradation in order to quickly process a large number of read and write operations, especially in the scenario of real-time data analysis and processing, so as to meet the storage and access requirements of large-scale data. In the field of storage, how to be stable, secure and not lose data, data reliability and efficiency are particularly important. The reliability of the storage machine is inseparable from the mounted devices, and the transmission of data depends on the support of each storage component; among them, the non-transparent bridge device plays the role of synchronizing data between storage controllers to ensure that the control data can be effectively saved, so as to achieve redundancy between storage device controllers. With the development of storage and available chips, there are more choices in chip architecture and types. With the continuous development of chips, the central processor architecture has changed. The change of processor architecture has led to a significant decline in the performance of non-transparent bridge devices, which in turn has led to a decline in the transmission performance of storage controllers. In order to overcome the above technical problems, this application proposes a communication optimization method between storage controllers, which can reduce the delay of non-transparent bridge devices reading source data and improve the efficiency of data synchronization between storage controllers.

[0051] The embodiment of the present application discloses a method for optimizing communication between storage controllers, which is applied to a storage controller. Referring to FIG1 , the method may include the following steps:

[0052] Step S11: determine the non-uniform memory access node corresponding to the source data as the first node, and determine the non-uniform memory access node corresponding to the non-transparent bridge device as the second node.

[0053] In this embodiment, first, the non-uniform memory access node (i.e., NUMA node) of the source data in the central processing unit of the storage controller is determined, and the node is used as the first node. Similarly, the non-uniform memory access node of the non-transparent bridge device in the central processing unit of the storage controller is determined, and the node is used as the second node.

[0054] The architecture of the above CPU is to enable non-consistent memory access nodes by default. It is understandable that the CPU architecture changes, and some architectures enable non-consistent memory access nodes by default. The distribution of the CPU, hardware memory sticks, and peripherals results in the non-consistent memory access nodes being far away and near. The memory transmission efficiency is high for the memory close to the non-consistent memory access node where the non-transparent bridge device is located, and the transmission efficiency is low for the memory far away, resulting in fluctuations in transmission performance. For example Figure 2 The figure shows a specific schematic diagram of the internal structure of a storage controller. The chip has two central processors, each of which has four cores (die), namely die0, die1, die2, and die3. Each core corresponds to a non-consistent memory access node, and there are eight non-consistent memory access nodes in total. The transmission delay of accessing memory increases with the distance across cores and central processors. Cross-core means that the non-transparent bridge device and the source data correspond to different cores, and cross-central processor means that the non-transparent bridge device and the source data correspond to different central processors. In other words, the memory access delay of the non-transparent bridge device across central processors is greater than the memory access delay without crossing central processors; within a single processor, the memory access delay of the non-transparent bridge device across cores is greater than the memory access delay without crossing cores.

[0055] A specific relationship between the CPU core and memory is as follows Figure 3 As shown, 0, 1, 2, and 3 are four cores respectively. CH-A, CH-B, CH-C, CH-D, CH-E, CH-F, CH-G, and CH-H are used to insert memory sticks. G0-Tx, G1-Tx, G2-Tx, G3-Tx, G0-Rx, G1-Rx, G2-Rx, G3-Rx, P0-Tx, P1-Tx, P2-Tx, P3-Tx, P0-Rx, P1-Rx, P2-Rx, and P3-Rx can be connected to non-transparent bridge devices. The IO processing flow is: front-end driver → scsi target -> io forwarding → local copy → cache → storage pool → raid- → colv -> io interface framework → back-end card and driver. The source data transmitted by non-transparent bridge devices usually comes from cache (CA, cache).

[0056] The above-mentioned non-transparent bridge device can be built-in or external to the central processing unit. For example, the non-transparent bridge card built into the central processing unit is a PCIe (PCI-Express (peripheral component interconnect express), a high-speed serial computer expansion bus standard) card, which is a hardware device that can be used to implement the non-transparent bridge communication mode. It can be used to connect PCIe devices and NPU (Neural Processing Unit) to achieve direct communication between the two without the intervention of the central processing unit; or an external non-transparent bridge acceleration (accelerate, ACC) card is a type of non-transparent bridge external card that can realize the non-transparent bridge function. The hardware structure of the IO (input / output) environment based on the non-transparent bridge device is as follows: Figure 2 As shown, the server is directly connected to the storage device, and the storage device is inserted with an ACC card or a storage controller with an onboard non-transparent bridge card.

[0057] Step S12: judging whether the source data meets the migration conditions according to the physical distance between the first node and the second node and the data migration rule.

[0058] In this embodiment, considering that the latency of the non-transparent bridge device reading the source data is affected by the physical distance, the physical distance between the first node and the second node is analyzed, and the source data meets the migration conditions according to the data migration rule. The above data migration rule can be that if the first node and the second node are in different central processing units, the migration conditions are met; if the first node and the second node are not in different central processing units, the migration conditions are not met. It can also be that if the first node and the second node are in different cores, the migration conditions are met; it can also be that if the first node and the second node are in different cores, the migration conditions are not met.

[0059] In some embodiments, judging whether the source data meets the migration conditions according to the data migration rules based on the physical distance between the first node and the second node may include: judging whether the first node and the second node are in the same central processing unit; if they are in different central processing units, judging that the source data meets the migration conditions; if they are in the same central processing unit, judging that the source data does not meet the migration conditions.

[0060] Step S13: If the migration condition is met, the source data is migrated from the first node to the target central processing unit where the second node is located.

[0061] In this embodiment, the distance is defined according to the data migration rule. If the nodes are considered to be far apart, data migration is performed to move the source data to a location closer to the non-transparent bridge device, that is, the central processor where the non-transparent bridge device is located; the above migration can be understood as copying and pasting, that is, the source data is still retained in the first node after the migration, but the source data can be read from the target central processor where the second node is located later. If the migration rule is not met, the original processing strategy remains unchanged; thus, through different processing strategies in different situations, the synchronization of data stored between the two controllers is achieved, which greatly optimizes the transmission efficiency.

[0062] In some embodiments, moving the source data from the first node to the target central processor where the second node is located may include: using the direct memory access thread corresponding to the cache where the source data is located to move the source data from the first node to the target central processor where the second node is located; that is, using the direct memory access (DMA, Direct Memory Access) thread to perform data movement. In addition, the source data can also be moved from the first node to the target central processor where the second node is located by calling the memory copy function (cpu memcpy); the source data movement method is not specifically limited in this application, and any method that can be implemented is acceptable.

[0063] When using direct memory access threads to perform data migration, it is necessary to pre-allocate direct memory access threads for each cache, that is, allocate memory access threads according to caches, and one or more memory access threads can be allocated. However, in order to improve migration efficiency, two or more direct memory access threads can be allocated; further, when data is migrated, all direct memory access threads corresponding to the cache where the source data is located can be used to migrate the source data from the first node to the target central processor where the second node is located. The above-mentioned direct memory access threads can be asynchronous threads, and by asynchronously executing data migration, the migration efficiency can be improved for multiple migration tasks.

[0064] In some embodiments, moving the source data from the first node to the target central processor where the second node is located may include: selecting any non-consistent memory access node from the target central processor where the second node is located as the target node; moving the source data from the first node to the target node. That is, selecting any node from the target central processor where the second node is located as the node to which the source data is to be moved, and after the move, the non-transparent bridge device can read the source data without crossing the central processor. Among them, in the preferred solution, the source data can be moved to the second node, and after the move, the non-transparent bridge device can read the source data without crossing the kernel, and the data access efficiency without crossing the kernel is the highest at this time.

[0065] In some embodiments, moving the source data from the first node to the target central processor where the second node is located may specifically include: determining the target storage address closest to the physical location of the non-transparent bridge device according to the physical location of the non-transparent bridge device, and using the non-consistent memory access node corresponding to the target storage address as the target node; and moving the source data from the first node to the target storage address of the target node. It should be noted that the target storage address is idle, and the nearest and idle storage address is found according to the physical location of the non-transparent bridge device to store the moved source data. It can be understood that in the same central processor, the time required for data reading when the non-transparent bridge device and the source data are in the same core is different from the time required for data reading when the non-transparent bridge device and the source data are in different cores. The shortest time is the case corresponding to the same core. The time used for different cores in the same processor is related to the internal structure of the processor. Therefore, the present application can determine the optimal storage address and maximize the efficiency of data access by finding the nearest and idle storage address according to the physical location of the non-transparent bridge device to store the moved source data.

[0066] Step S14: reading the source data from the target central processor through the non-transparent bridge device, and transmitting the source data to the opposite end storage controller.

[0067] After the data is moved, the source data is read from the target central processor using a non-transparent bridge device and transmitted to the peer storage controller to achieve synchronization of the source data between the two storage devices. The data movement is asynchronously processed without affecting the non-transparent bridge device, achieving efficient data synchronization.

[0068] It can be seen that the present application proposes a performance optimization method for a non-transparent bridge. According to the characteristics of the processor architecture, the data synchronization of the non-transparent bridge is preferably non-cross-memory access. Based on the conclusion of the lowest transmission delay, through development and optimization, by adding multiple asynchronous direct memory access data migration threads to the memory far away from the non-transparent bridge device, the memory data to be moved is moved to the nearby memory in advance, which greatly optimizes the performance of the non-transparent bridge data transmission, enables storage on more platforms, and completes the protection of stored data.

[0069] In some embodiments, reading the source data from the target CPU and transmitting the source data to the peer storage controller may include: mirroring the source data in the target CPU through the non-transparent bridge device to obtain mirrored source data; and transmitting the mirrored source data to the peer storage controller. Specifically, the mirror of the source data may be generated by mirroring the source data, and then the mirrored source data may be sent to the peer storage controller to achieve synchronization of the source data between the two storage devices.

[0070] In some embodiments, moving the source data from the first node to the target central processor where the second node is located may include: determining the storage address of the source data at the first node to obtain a first storage address, and associating the source data with the first storage address; reading the source data from the target central processor through the non-transparent bridge device, and transmitting the source data to the opposite storage controller, including: reading the source data from the target central processor through the non-transparent bridge device, and transmitting the source data and the first storage address together to the opposite storage controller, so that the opposite storage controller determines the second storage address corresponding to the first storage address in the opposite storage controller according to the first storage address, and stores the source data in the second storage address. It can be understood that in order to avoid data confusion, when synchronizing data, try to synchronize to the same storage address, therefore, the storage address of the source data at the first node, that is, the first storage address, is sent to the opposite storage controller at the same time, and the first storage address can be determined by recording the index / flag and other information of the source data; the opposite storage controller restores the source data to the second storage address corresponding to the first storage address. For example, storage controller A sends source data to peer B and the first storage address 0x1000, and storage controller B recovers the source data to the 0x1000 address space of storage controller B. The storing of the source data to the second storage address may include: storing the source data to the second storage address in parallel through multiple direct memory access threads. That is, data recovery is performed in parallel through multiple direct memory access threads to improve data transfer efficiency.

[0071] This application develops a storage system based on a non-transparent bridge device. At the beginning of the design and development code, by adding method logic scripts in the IO stack code development stage, the efficiency and reliability of data transmission during the development process are guaranteed, and the development efficiency and flexibility are improved; the storage device can complete the storage of data on more platforms, thereby improving reliability and availability.

[0072] As can be seen from the above, in this embodiment, the non-consistent memory access node corresponding to the source data is determined as the first node, and the non-consistent memory access node corresponding to the non-transparent bridge device is determined as the second node; according to the physical distance between the first node and the second node, the source data is judged whether it meets the migration condition according to the data migration rule; if it meets the migration condition, the source data is moved from the first node to the target central processor where the second node is located; through the non-transparent bridge device, the source data is read from the target central processor, and the source data is transmitted to the opposite storage controller. Since the non-transparent bridge device is used for data transmission between storage controllers, the farther the node storing the source data is from the node where the non-transparent bridge device is located, the longer the time required for the non-transparent bridge to read the data. Therefore, by analyzing the distance between the first node where the source data is located and the second node where the non-transparent bridge device is located, when the data migration condition is met, before the non-transparent bridge device reads the data, the source data is first moved from the first node to the central processor where the non-transparent bridge device is located, so as to reduce the delay of the non-transparent bridge device reading the source data, thereby improving the efficiency of data synchronization between storage controllers.

[0073] Correspondingly, the embodiment of the present application further discloses a device for optimizing communication between storage controllers, as shown in FIG4 , the device includes:

[0074] A node determination module 11, configured to determine a non-uniform memory access node corresponding to source data as a first node, and determine a non-uniform memory access node corresponding to a non-transparent bridge device as a second node;

[0075] A migration condition judgment module 12, configured to judge whether the source data meets the migration condition according to the physical distance between the first node and the second node and the data migration rule;

[0076] A data migration module 13, configured to migrate the source data from the first node to a target central processor where the second node is located if a migration condition is met;

[0077] The data transmission module 14 is used to read the source data from the target central processor through the non-transparent bridge device and transmit the source data to the opposite end storage controller.

[0078] As can be seen from the above, in this embodiment, the non-consistent memory access node corresponding to the source data is determined as the first node, and the non-consistent memory access node corresponding to the non-transparent bridge device is determined as the second node; according to the physical distance between the first node and the second node, the source data is judged whether it meets the migration condition according to the data migration rule; if it meets the migration condition, the source data is moved from the first node to the target central processor where the second node is located; through the non-transparent bridge device, the source data is read from the target central processor, and the source data is transmitted to the opposite storage controller. Since the non-transparent bridge device is used for data transmission between storage controllers, the farther the node storing the source data is from the node where the non-transparent bridge device is located, the longer the time required for the non-transparent bridge to read the data. Therefore, by analyzing the distance between the first node where the source data is located and the second node where the non-transparent bridge device is located, when the data migration condition is met, before the non-transparent bridge device reads the data, the source data is first moved from the first node to the central processor where the non-transparent bridge device is located, so as to reduce the delay of the non-transparent bridge device reading the source data, thereby improving the efficiency of data synchronization between storage controllers.

[0079] In some specific embodiments, the moving condition judgment module 12 may specifically include:

[0080] a determination unit, configured to determine whether the first node and the second node are in the same central processor;

[0081] A compliance determination unit, used for determining that the source data meets the migration condition if the source data is in different central processing units;

[0082] The non-compliance determination unit is used to determine that the source data does not comply with the migration condition if the source data are in the same central processing unit.

[0083] In some specific embodiments, the data migration module 13 may specifically include:

[0084] The data moving unit is used to move the source data from the first node to the target central processor where the second node is located by using the direct memory access thread corresponding to the cache where the source data is located.

[0085] In some specific embodiments, the storage controller communication optimization device may specifically include:

[0086] a thread allocation unit, configured to allocate two or more direct memory access threads to each cache before moving the source data from the first node to a target central processor where the second node is located;

[0087] The data migration module 13 may specifically include:

[0088] The data moving unit is used to move the source data from the first node to the target central processor where the second node is located by using all direct memory access threads corresponding to the cache where the source data is located.

[0089] In some specific embodiments, the direct memory access thread may be an asynchronous thread.

[0090] In some specific embodiments, the data migration module 13 may specifically include:

[0091] The data moving unit is used to move the source data from the first node to the target central processing unit where the second node is located by calling a memory copy function.

[0092] In some specific embodiments, the data transmission module 14 may specifically include:

[0093] A mirror cache unit, used for mirror caching the source data in the target central processor through the non-transparent bridge device to obtain mirror source data;

[0094] The data transmission unit is used to transmit the mirror source data to the opposite end storage controller.

[0095] In some specific embodiments, the non-transparent bridge device may be built-in or externally plugged into a central processing unit.

[0096] In some specific embodiments, the data migration module 13 may specifically include:

[0097] A target node determination unit, configured to select any non-uniform memory access node from the target central processor where the second node is located as a target node;

[0098] The data migration module unit is used to migrate the source data from the first node to the target node.

[0099] In some specific embodiments, the CPU architecture enables non-uniform memory access nodes by default.

[0100] In some specific embodiments, the data migration module 13 may specifically include:

[0101] an associating unit, configured to determine a storage address of the source data at the first node to obtain a first storage address, and associate the source data with the first storage address;

[0102] The data transmission module 14 may specifically include:

[0103] A data transmission unit is used to read the source data from the target central processing unit through the non-transparent bridge device, and transmit the source data and the first storage address together to the opposite storage controller, so that the opposite storage controller can determine the second storage address corresponding to the first storage address in the opposite storage controller based on the first storage address, and store the source data in the second storage address.

[0104] In some specific embodiments, the opposite storage controller is used to store the source data to the second storage address in parallel through multiple direct memory access threads.

[0105] Furthermore, an embodiment of the present application also discloses an electronic device, as shown in FIG5 . The content in the figure cannot be regarded as any limitation on the scope of use of the present application.

[0106] FIG5 is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to determine the non-consistent memory access node corresponding to the source data as the first node, and the non-consistent memory access node corresponding to the non-transparent bridge device as the second node; according to the physical distance between the first node and the second node, determine whether the source data meets the migration condition according to the data migration rule; if the migration condition is met, move the source data from the first node to the target central processor where the second node is located; read the source data from the target central processor through the non-transparent bridge device, and transmit the source data to the opposite storage controller; and the steps of the storage controller communication optimization method disclosed in any of the above embodiments. By analyzing the distance between the first node where the source data is located and the second node where the non-transparent bridge device is located, when the data migration conditions are met, before the non-transparent bridge device reads the data, the source data is first moved from the first node to the central processor where the non-transparent bridge device is located, so as to reduce the delay of the non-transparent bridge device in reading the source data, thereby improving the efficiency of data synchronization between storage controllers.

[0107] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0108] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system 221, a computer program 222, and data 223 including source data, etc. The storage method can be temporary storage or permanent storage.

[0109] The operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, so as to realize the operation and processing of the massive data 223 in the memory 22 by the processor 21, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the storage controller communication optimization method executed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0110] Furthermore, the embodiment of the present application also discloses a computer program product, the computer program product includes a computer program, when the computer program product is loaded and executed by the processor, it is realized to determine the non-consistent memory access node corresponding to the source data as the first node, and determine the non-consistent memory access node corresponding to the non-transparent bridge device as the second node; according to the physical distance between the first node and the second node, according to the data migration rule, whether the source data meets the migration condition; if the migration condition is met, the source data is moved from the first node to the target central processor where the second node is located; through the non-transparent bridge device, the source data is read from the target central processor, and the source data is transmitted to the opposite end storage controller; and the steps of the storage controller communication optimization method disclosed in any of the above embodiments. By analyzing the distance between the first node where the source data is located and the second node where the non-transparent bridge device is located, when the data migration condition is met, before the non-transparent bridge device reads the data, the source data is first moved from the first node to the central processor where the non-transparent bridge device is located, so as to reduce the delay of the non-transparent bridge device reading the source data, thereby improving the efficiency of data synchronization between storage controllers.

[0111] Furthermore, the embodiment of the present application also discloses a computer storage medium, in which a computer executable instruction is stored. When the computer executable instruction is loaded and executed by the processor, the non-consistent memory access node corresponding to the source data is determined as the first node, and the non-consistent memory access node corresponding to the non-transparent bridge device is determined as the second node; according to the physical distance between the first node and the second node, the source data is judged whether it meets the migration condition according to the data migration rule; if it meets the migration condition, the source data is moved from the first node to the target central processor where the second node is located; through the non-transparent bridge device, the source data is read from the target central processor, and the source data is transmitted to the opposite storage controller; and the steps of the storage controller communication optimization method disclosed in any of the above embodiments. By analyzing the distance between the first node where the source data is located and the second node where the non-transparent bridge device is located, when the data migration condition is met, before the non-transparent bridge device reads the data, the source data is first moved from the first node to the central processor where the non-transparent bridge device is located, so as to reduce the delay of the non-transparent bridge device reading the source data, thereby improving the efficiency of data synchronization between storage controllers.

[0112] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0113] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0114] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0115] The above is a detailed introduction to the storage controller communication optimization method, device, equipment and storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for optimizing communication between storage controllers, characterized in that: Applicable to storage controllers, including: Determine a non-consistent memory access node corresponding to the source data as a first node, and determine a non-consistent memory access node corresponding to the non-transparent bridge device as a second node; According to the physical distance between the first node and the second node, judging whether the source data meets the migration condition according to the data migration rule; If the migration condition is met, the source data is migrated from the first node to the target central processor where the second node is located; Reading the source data from the target central processor through the non-transparent bridge device and transmitting the source data to the opposite end storage controller; Wherein, judging whether the source data meets the migration condition according to the physical distance between the first node and the second node and the data migration rule includes: determining whether the first node and the second node are in the same central processing unit; If they are in different CPUs, it is determined that the source data meets the migration conditions; If they are in the same CPU, it is determined that the source data does not meet the migration conditions.

2. The method for optimizing communication between storage controllers according to claim 1, characterized in that: Moving the source data from the first node to a target central processor where the second node is located includes: The source data is moved from the first node to the target central processor where the second node is located by using the direct memory access thread corresponding to the cache where the source data is located.

3. The method for optimizing communication between storage controllers according to claim 2, characterized in that: Before the source data is moved from the first node to the target central processor where the second node is located, the method further includes: Allocate two or more direct memory access threads to each cache; Moving the source data from the first node to a target central processor where the second node is located includes: The source data is moved from the first node to the target central processor where the second node is located by using all direct memory access threads corresponding to the cache where the source data is located.

4. The method for optimizing communication between storage controllers according to claim 2, characterized in that: The direct memory access thread is an asynchronous thread.

5. The method for optimizing communication between storage controllers according to claim 1, characterized in that: Moving the source data from the first node to a target central processor where the second node is located includes: By calling a memory copy function, the source data is moved from the first node to the target central processor where the second node is located.

6. The method for optimizing communication between storage controllers according to claim 1, characterized in that: Reading the source data from the target central processor and transmitting the source data to the opposite end storage controller includes: Mirroring the source data in the target central processor through the non-transparent bridge device to obtain mirrored source data; The mirror source data is transmitted to the opposite end storage controller.

7. The method for optimizing communication between storage controllers according to claim 1, characterized in that: The non-transparent bridge device is built-in or plugged into the central processing unit.

8. The method for optimizing communication between storage controllers according to claim 1, characterized in that: Moving the source data from the first node to a target central processor where the second node is located includes: Select any non-uniform memory access node from the target central processor where the second node is located as the target node; The source data is moved from the first node to the target node.

9. The method for optimizing communication between storage controllers according to claim 1, characterized in that: The architecture of the central processing unit enables non-uniform memory access nodes by default.

10. The method for optimizing communication between storage controllers according to any one of claims 1 to 9, characterized in that: Moving the source data from the first node to a target central processor where the second node is located includes: Determine a storage address of the source data at the first node to obtain a first storage address, and associate the source data with the first storage address; The method comprises: reading the source data from the target central processor through the non-transparent bridge device, and transmitting the source data to the opposite end storage controller, including: The source data is read from the target central processor through the non-transparent bridge device, and the source data and the first storage address are transmitted together to the opposite storage controller, so that the opposite storage controller determines the second storage address corresponding to the first storage address in the opposite storage controller according to the first storage address, and stores the source data in the second storage address.

11. The method for optimizing communication between storage controllers according to claim 10, characterized in that: Storing the source data to the second storage address includes: The source data is stored in the second storage address in parallel through a plurality of direct memory access threads.

12. A computer program product, characterized in that It comprises a computer program, which, when executed by a processor, implements the method for optimizing communication between storage controllers as described in any one of claims 1 to 11.

13. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the method for optimizing communication between storage controllers as described in any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein when the computer programs are executed by a processor, the method for optimizing communication between storage controllers as described in any one of claims 1 to 11 is implemented.

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