FPGA synthesis tool logic optimization method, computer readable storage medium and electronic device

Abstract

The present invention provides a FPGA synthesis tool logic optimization method, comprising: traversing each logic unit c in a circuit netlist, storing a mapping relationship from an output port signal of the logic unit c to the logic unit c in a logic unit mapping relationship set, and setting an initial fan-out of each logic unit to 0; traversing each logic unit c, for an input signal sig_i of each logic unit c, searching for a logic unit cell_i whose output signal is sig_i in the logic unit mapping relationship set, adding 1 to the fan-out count of the logic unit cell_i, and storing the mapping relationship from the signal sig_i to the logic unit c in a signal fan-out logic unit set; traversing each logic unit c in the circuit netlist again, if the fan-out number of the logic unit c exceeds the maximum fan-out number of the synthesis tool, inserting the logic unit c into an optimization queue, and reallocating the fan-out of each logic unit c in the optimization queue.

Description

Technical Field

[0001] The present invention belongs to the field of FPGA technology, and in particular relates to an FPGA synthesis tool logic optimization method, a computer-readable storage medium and an electronic device. Background Art

[0002] Logic synthesis is an important step in the FPGA EDA software design process. It converts the Verilog / VHDL circuit files at the behavioral level or register transfer level (RTL) input by the user into a netlist file composed of FPGA basic logic units such as lookup tables (LUTs) and flip-flops (FFs). FPGA logic synthesis includes two stages: synthesis and mapping. Synthesis is to convert the circuit files at the behavioral level or RTL into a logic netlist composed of gate circuits; mapping is to map the logic netlist composed of gate circuits into a netlist file composed of FPGA basic logic units.

[0003] In FPGA design, "fan-out" refers to the number of connections from the output of a logic gate or trigger to the inputs of multiple other logic gates or triggers. The maximum fan-out number refers to the maximum number of loads that a logic unit can drive, that is, the maximum number of lower-level logic units that it can effectively drive without causing excessive signal delays or levels that do not meet requirements. The main function of specifying the maximum fan-out number of FPGA is to constrain the circuit netlist generated by the synthesis tool so that the number of output edges of the same signal does not exceed a maximum value.

[0004] Users often use the maximum fan-out constraint of FPGA synthesis tools to constrain the maximum number of output edges of the same signal, which not only helps the convergence of the application circuit timing, but also facilitates users to debug and optimize the circuit. Therefore, how to meet the constraint of the maximum fan-out number is a technical problem that FPGA synthesis tools need to solve. Summary of the invention

[0005] The present invention provides an FPGA synthesis tool logic optimization method, a computer-readable storage medium and an electronic device, which distributes the maximum fan-out number of logic units and optimizes the fan-out number of logic units to meet the maximum fan-out constraint.

[0006] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0007] To achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides a method for optimizing logic of an FPGA synthesis tool, including: traversing each logic cell c in the circuit netlist, storing the mapping relationship from the output port signal of the logic cell c to the logic cell c in the logic cell mapping relationship set, and setting the initial fan-out of each logic cell to 0; traversing each logic cell c, for each input signal sig_i of the logic cell c, searching the logic cell cell_i whose output signal is sig_i in the logic cell mapping relationship set, and adding 1 to the fan-out count of the logic cell cell_i, and storing the mapping relationship from the signal sig_i to the logic cell c in the signal fan-out logic cell set; traversing each logic cell c in the circuit netlist again, if the fan-out number of the logic cell c exceeds the maximum value, inserting the logic cell c into the optimization queue, and reallocating the fan-out of each logic cell c in the optimization queue. The beneficial effect of this technical solution is that

[0008] If there is no logic unit c in the optimization queue, the logic optimization of the FPGA synthesis tool is exited.

[0009] The method for redistributing the fan-out of the logic unit c is to take out the first logic unit c of the optimization queue, calculate the number of logic units N that need to be copied for the logic unit c, copy N logic units c1 that are identical to the logic unit c in the netlist, distribute the fan-out of the logic unit c to the N new logic units c1, update the fan-out value of the logic unit from which each input signal of the logic unit c comes, and update the optimization queue.

[0010] The method for calculating the number of logical units N that need to be copied for the logical unit c is: if the fan-out number of the logical unit c is an integer multiple of the maximum fan-out number, the number of logical units N that need to be copied is the ratio of the fan-out number of the logical unit c to the maximum fan-out number minus 1; if the fan-out number of the logical unit c is not an integer multiple of the maximum fan-out number, the number of logical units N that need to be copied is the ratio of the fan-out number of the logical unit c to the maximum fan-out number.

[0011] The method for copying N logic cells c1 identical to logic cell c in a netlist is as follows: adding a new logic cell c1 in a circuit netlist, setting the type of logic cell c1 equal to the type of logic cell c; traversing each input port p and input signal sig_i of logic cell c, setting the signal of input port p of logic cell c1 to sig_i; traversing each parameter and value of logic cell c, generating a parameter value pair consisting of parameter and value for logic cell c1; repeatedly generating N logic cells c1, generating input port signal and parameter value pairs for N logic cells c1.

[0012] If the fan-out number of logic unit c is divisible by N+1, the fan-out number M of logic unit c that can be allocated to each logic unit c1 is the ratio of the fan-out number of logic unit c to N+1; if the fan-out number of logic unit c is not divisible by N+1, the fan-out number M of logic unit c that can be allocated to each logic unit c1 is the ratio of the fan-out number of logic unit c to N+1 plus 1.

[0013] The method for distributing the fan-out of logic unit c to N new logic units c1 includes the following steps: step 1: obtaining the output port signal sig_o of logic unit c, and obtaining the fan-out logic unit set of signal sig_o; step 2: the newly copied logic units c1 are in the order of i=0 to N-1, and for each newly copied logic unit c1, the output port signal sig_o1 of logic unit c1 is obtained, and processed as follows: for each logic unit j in the fan-out logic unit set of sig_o, j=i*M The loop processing is carried out sequentially from (i+1)*M. The loop processing method is to reduce the fan-out number of the original logic unit c by 1, delete the logic unit j from the fan-out logic unit set of the signal sig_o; increase the fan-out number of the logic unit c1 by 1, and add the logic unit j to the fan-out logic unit set of the signal sig_o1; Step 3: traverse each input signal sig_j of the logic unit j. If sig_j=sig_o, replace the input port signal sig_j of the logic unit j with the signal sig_o1.

[0014] Updating the fan-out value of the logic unit from which each input signal of the logic unit c comes, and updating the optimization queue includes the following steps: Step 1: traverse each input port signal sig_i of the logic unit c, and search for the logic unit cell_i whose output port signal is sig_i from the logic unit mapping relationship set; Step 2: increase the fan-out number of the logic unit cell_i by N; Step 3: for each copied logic unit c1 in the order of i=0 to N-1, add the logic unit c1 to the fan-out logic unit set of the sig_i signal; Step 4: if the fan-out count of the updated logic unit cell_i is greater than the maximum value, insert the logic unit cell_i into the optimization queue.

[0015] A technical solution of the present invention provides a computer-readable storage medium, in which program code is stored. The program code is called by a processor to execute the FPGA synthesis tool logic optimization method described above.

[0016] An electronic device provided by a technical solution of the present invention includes one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the FPGA synthesis tool logic optimization method described above.

[0017] Compared with the prior art, the beneficial effects of the present invention mainly include: the present invention can reduce the fan-out number of the logic unit output signal according to the maximum fan-out constraint, which not only helps to optimize the back-end layout and routing algorithm, making the timing performance of the application circuit easier to converge, but also facilitates users to debug and optimize the circuit.

[0018] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 The present invention is a flow chart of a method for optimizing logic of an FPGA synthesis tool that satisfies the maximum fan-out constraint.

[0021] Figure 2 The figure is a flow chart of a method for duplicating N identical logic units in a netlist according to the present invention.

[0022] Figure 3 The figure is a flow chart of a method for distributing the fan-out of a logic unit to N replicated logic units according to the present invention.

[0023] Figure 4 A schematic diagram of a flow chart of updating the fan-out value of the logic unit from which each input signal of the logic unit c comes and optimizing the queue according to the present invention. DETAILED DESCRIPTION

[0024] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0025] Embodiment 1

[0026] Embodiment 1 provides a method for optimizing logic of FPGA synthesis tool. The method first traverses each logic unit c in the circuit netlist, stores the mapping relationship between the output signal of the logic unit c and the logic unit c in the logic unit mapping relationship set wire_driven; sets the fan-out value of each logic unit c in the logic unit mapping relationship set wire_driven to 0, and

[0027] The specific process of the present invention is described in detail below with reference to the accompanying drawings.

[0028] See also Figure 1-4 The FPGA synthesis tool logic optimization method of the present invention that satisfies the maximum fan-out constraint comprises the following steps:

[0029] Step 1: Traverse each logic cell c in the circuit netlist, store the mapping relationship from the output signal of each logic cell c to each logic cell c in the mapping relationship set wire_driven; initialize the fan-out value of each logic cell c in the logic cell mapping relationship set wire_driven, set the fan-out value of the logic cell c to 0, and

[0030] Step 2: Traverse each logic cell c in the circuit netlist, and for each input port signal sig_i of each logic cell c, find the logic cell cell_i with output port signal sig_i from the mapping relationship set wire_driven, and execute fanout[cell_i]++ (increase the fan-out count of logic cell cell_i by 1); and store the mapping relationship from sig_i to c in the signal fan-out logic cell set wire_to.

[0031] Step 3: Traverse each logic cell c in the circuit netlist. If fanout[c]>Max (the fanout of logic cell c is greater than the set maximum value), c is inserted into the optimization queue deque, where the maximum value Max is an input parameter, indicating the maximum fanout number that the synthesis tool needs to meet.

[0032] Step 4: If the optimization queue deque is not empty, take out the first element c of the queue and execute step 5; otherwise exit the optimization.

[0033] Step 5: Calculate the number of logical units N that need to be replicated for logical unit c; if fanout[c]%Max=0 (the fanout number of logical unit c is an integer multiple of the maximum fanout number), N=fanout[c] / Max–1 (the number of logical units N that need to be replicated is the ratio of the fanout number of logical unit c to the maximum fanout number minus 1); otherwise N=fanout[c] / Max (the number of logical units N that need to be replicated is the ratio of the fanout number of logical unit c to the maximum fanout number).

[0034] Step 6: Duplicate N logic cells c1 that are identical to logic cell c in the netlist.

[0035] Step 7: Allocate the fan-out of logic unit c to N new logic units c1.

[0036] Step 8: Update the fanout value of each input signal of logic unit c from the logic unit and update the optimized queue deque.

[0037] See also Figure 2 In step 6, N logic cells c1 identical to logic cell c are copied in the netlist. The main steps include the following:

[0038] Step 6.1: Execute steps 6.2-6.7 in the order of i=1 to N (indicating the number and order of loops, iterating from the first logic unit c to the Nth logic unit).

[0039] Step 6.2: Add a new logic cell c1 to the circuit netlist.

[0040] Step 6.3: Set the logical unit type of the logical unit c1 to be equal to the logical unit type of the logical unit c.

[0041] Step 6.4: Traverse each input port p and input signal sig_i of the logic unit c and execute step 6.5.

[0042] Step 6.5: Set the signal of the input port p of the logic unit c1 to sig_i.

[0043] Step 6.6: Traverse each parameter key and value value of the logic unit c and execute step 6.7.

[0044] Step 6.7: Generate a parameter-value pair for logical unit c1

[0045] See also Figure 3 In step 7, the method for distributing the fan-out of the logic unit c to the replicated N logic units c1 mainly includes the following steps:

[0046] Step 7.1 Step 1: If fanout[c] % (N+1) = 0 (the fan-out number of logic unit c is divisible by N+1), then set the fan-out number M of logic unit c that can be allocated to logic unit c1 to be M=fanout[c] / (N+1) (the fan-out number M of logic unit c that can be allocated to each logic unit c1 is the ratio of the fan-out number of logic unit c to N+1, indicating that the original logic unit and the copied logic unit can drive exactly M loads); otherwise set M=fanout[c] / (N+1) + 1 (the fan-out number M of logic unit c that can be allocated to each logic unit c1 is the ratio of the fan-out number of logic unit c to N+1 plus 1).

[0047] Step 7.2: Get the output port signal sig_o of logic unit c.

[0048] Step 7.3: Get the logic unit set wire_to[sig_o] of the signal sig_o fan-out.

[0049] Step 7.4: According to i=0 to N-1 (indicating the number and order of loops, iterating from the 0th logic unit c1 to the N-1th logic unit), execute step 7.5 for each replicated logic unit c1.

[0050] Step 7.5: Get the signal sig_o1 of the output port of c1.

[0051] Step 7.6: For the logic unit j in the logic unit set wire_to[sig_o] fanned out by the sig_o signal, perform loop iterations from j=i*M to (i+1)*M, including steps 7.7 and 7.8.

[0052] Step 7.7: fanout[c]--(the fan-out number of logic unit c is reduced by 1), and logic unit j is removed from the logic unit set wire_to[sig_o] of the sig_o signal fan-out.

[0053] Step 7.8: fanout[c1]++ (the fan-out number of logic cell c1 increases by 1), and logic cell j is added to the set of logic cells wire_to[sig_o1] that fan out from the sig_o1 signal.

[0054] Step 7.9: Traverse each input signal sig_j of logic unit j and execute step 7.10.

[0055] Step 7.10: If sig_j=sig_o, then replace the input port signal sig_j of logic j with the signal sig_o'.

[0056] See also Figure 4In step 8, the fan-out value of the logic unit from which each input signal of the logic unit c comes is updated and the queue is optimized, including the following specific steps:

[0057] Step 8.1: Traverse each input port signal sig_i of the logic unit c and execute step 8.2.

[0058] Step 8.2: Find the logic cell cell_i whose output port signal is sig_i from the mapping relationship set wire_driven.

[0059] Step 8.3: Increase the fanout number of the logic cell cell_i by N, that is, fanout[cell_i]+=N.

[0060] Step 8.4: for i=0 to N-1, for each replicated logic cell c1, add the logic cell c1 to the fan-out logic cell set wire_to[sig_i] of signal sig_i.

[0061] Step 8.5: If the updated fanout[cell_i]>Max (the fanout of logic cell cell_i is greater than the maximum fanout number of the FPGA synthesis tool), execute step 8.6.

[0062] Step 8.6: Insert the logical unit cell_i into the optimized queue deque.

[0063] Embodiment 2

[0064] Embodiment 2 provides a computer-readable storage medium, in which a program code is stored. The program code is called by a processor to execute the FPGA synthesis tool logic optimization method in Embodiment 1.

[0065] Embodiment 3

[0066] Embodiment three provides an electronic device, which includes one or more processors; and a memory; and one or more applications are also provided, wherein the one or more applications are stored in the memory and are configured to be executed by the one or more processors, and the one or more applications are configured to execute the FPGA synthesis tool logic optimization method as in Embodiment 1.

[0067] The above is a detailed introduction to a FPGA synthesis tool logic optimization method, a computer-readable storage medium, and an electronic device provided by the present invention. This article uses specific examples to illustrate the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for optimizing logic of an FPGA synthesis tool, characterized in that: include: Traverse each logic cell c in the circuit netlist, store the mapping relationship from the output port signal of the logic cell c to the logic cell c in the logic cell mapping relationship set, and set the initial fan-out of each logic cell to 0; Traverse each logic cell c, for each input signal sig_i of the logic cell c, search for the logic cell cell_i whose output signal is sig_i in the logic cell mapping relationship set, add 1 to the fan-out count of the logic cell cell_i, and store the mapping relationship from the signal sig_i to the logic cell c in the signal fan-out logic cell set; Traverse each logic cell c in the circuit netlist again. If the fan-out number of the logic cell c exceeds the maximum fan-out number of the synthesis tool, insert the logic cell c into the optimization queue, and reallocate the fan-out of each logic cell c in the optimization queue. The fan-out reallocation method of the logic unit c is to take out the first logic unit c of the optimization queue, calculate the number of logic units N that the logic unit c needs to copy, copy N logic units c1 that are identical to the logic unit c in the netlist, allocate the fan-out of the logic unit c to the N new logic units c1, update the fan-out value of the logic unit from which each input signal of the logic unit c comes, and update the optimization queue; Updating the fan-out value of the logic unit from which each input signal of the logic unit c comes, and updating the optimization queue includes the following steps: Step 1: traverse each input port signal sig_i of the logic unit c, and search for the logic unit cell_i whose output port signal is sig_i from the logic unit mapping relationship set; Step 2: increase the fan-out number of the logic unit cell_i by N; Step 3: for each copied logic unit c1 in the order of i=0 to N-1, add the logic unit c1 to the fan-out logic unit set of the sig_i signal; Step 4: if the fan-out count of the updated logic unit cell_i is greater than the maximum value, insert the logic unit cell_i into the optimization queue.

2. The FPGA synthesis tool logic optimization method according to claim 1, characterized in that: If there is no logic unit c in the optimization queue, the logic optimization of the FPGA synthesis tool is exited.

3. The FPGA synthesis tool logic optimization method according to claim 1, characterized in that: The method for calculating the number of logical units N that need to be replicated for the logical unit c is that if the fan-out number of the logical unit c is an integer multiple of the maximum fan-out number, the number of logical units N that need to be replicated is the ratio of the fan-out number of the logical unit c to the maximum fan-out number minus 1; If the fan-out number of the logic unit c is not an integer multiple of the maximum fan-out number, the number N of logic units that need to be replicated is the ratio of the fan-out number of the logic unit c to the maximum fan-out number.

4. The FPGA synthesis tool logic optimization method according to claim 1, characterized in that: The method of duplicating N logic units c1 identical to logic unit c in the netlist is to add a new logic unit c1 in the circuit netlist and set the type of logic unit c1 to be equal to the type of logic unit c; Traverse each input port p and input signal sig_i of logic unit c, and set the signal of input port p of logic unit c1 to sig_i; Traverse each parameter and value of the logic unit c, and generate a parameter value pair consisting of the parameter and the value for the logic unit c1; N logic cells c1 are repeatedly generated, and input port signals and parameter value pairs are generated for the N logic cells c1.

5. The FPGA synthesis tool logic optimization method according to claim 1, characterized in that: If the fan-out number of logic unit c is divisible by N+1, then the fan-out number M of logic unit c that can be allocated to each logic unit c1 is the ratio of the fan-out number of logic unit c to N+1; If the fan-out number of logic unit c is not divisible by N+1, each logic unit c1 may be allocated a fan-out number M of logic unit c which is the ratio of the fan-out number of logic unit c to N+1 plus 1.

6. The FPGA synthesis tool logic optimization method according to claim 5, characterized in that: The method for distributing the fan-out of the logic unit c to N new logic units c1 comprises the following steps: Step 1: Get the output port signal sig_o of logic unit c, and get the fan-out logic unit set of signal sig_o. Step 2: The newly copied logic units c1 are in the order of i=0 to N-1, and the output port signal sig_o1 of the logic unit c1 is obtained for each newly copied logic unit c1, and processed as follows: For each logic unit j in the fan-out logic unit set of sig_o, loop processing is performed in the order of j=i*M to (i+1)*M. The loop processing method is to reduce the fan-out number of the original logic unit c by 1, and delete the logic unit j from the fan-out logic unit set of signal sig_o; Increase the fan-out number of logic unit c1 by 1, and add logic unit j to the fan-out logic unit set of signal sig_o1; Step 3: Traverse each input signal sig_j of logic unit j. If sig_j=sig_o, replace the input port signal sig_j of logic unit j with signal sig_o1.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, and the program code is called by a processor to execute the FPGA synthesis tool logic optimization method according to any one of claims 1 to 6.

8. An electronic device, characterized in that: comprising one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the FPGA synthesis tool logic optimization method as described in any one of claims 1-6.

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