A verification method, system and vehicle for an on-vehicle SerDes chip

Abstract

The present invention provides a verification method, system and vehicle for an on-vehicle SerDes chip. It relates to the technical field of data transmission. The specific implementation scheme is: a master device deployed outside the first SerDes chip determines the corresponding slave device, and a register is configured for the target object where the slave device is located; wherein the target object includes but is not limited to the first SerDes chip, the second SerDes chip and the sensor; based on the register, the master device is verified to communicate normally with the slave devices deployed at different locations in a write-first-read-later manner. The technical solution disclosed in the present invention determines the corresponding slave device by a master device deployed outside the first SerDes chip, and a register is configured for the target object where the slave device is located. The register can be used to verify the slave devices deployed at different locations in the uplink path, which helps to improve the flexibility and accuracy of the verification of the on-vehicle SerDes chip.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a verification method and system for a vehicle-mounted SerDes chip, and a vehicle. Background Art

[0002] With the development of intelligent driving technology, there is an urgent need for data transmission chips with long channels and low interference. Therefore, high-performance automotive serializer and deserializer (Serializer / Deserializer, SerDes) chips have become an important component of intelligent driving systems. The Inter-Integrated Circuit (I2C) bus in the automotive SerDes chip is usually used to configure the registers in the chip. The I2C master device is located on the receiving side and belongs to the uplink path in the link. Since the I2C slave device may be deployed at the receiving end, the transmitting end or the sensor. Therefore, there is a certain degree of difficulty in verifying the I2C bus of the automotive SerDes chip. Summary of the invention

[0003] The purpose of the present invention is to provide a verification method, system and vehicle for an on-vehicle SerDes chip. A master control device deployed outside a first SerDes chip determines a corresponding slave device, configures registers for a target object where the slave device is located, and can verify slave devices deployed at different positions in an uplink path through registers, which helps to improve the flexibility and accuracy of on-vehicle SerDes chip verification.

[0004] In a first aspect, the present invention provides a verification method for a vehicle-mounted SerDes chip, comprising:

[0005] Determine a corresponding slave device through a master device deployed outside the first SerDes chip, and configure a register for a target object where the slave device is located; wherein the target object includes but is not limited to the first SerDes chip, the second SerDes chip, and a sensor;

[0006] Based on the register, the master device is verified to communicate normally with the slave devices deployed in different locations in a write-before-read manner.

[0007] In some embodiments, when the first slave device is deployed inside the first SerDes chip, the target object is the first SerDes chip; the corresponding slave device is determined by a master control device deployed outside the first SerDes chip, and registers are configured for the target object where the slave device is located, including: sending the first I2C bus data to the first slave device through a driver of a first verification unit; wherein the first verification unit is used to simulate an I2C interface to generate the first I2C bus data; the first slave device converts the first I2C bus data into first target data corresponding to the APB bus; and the registers of the first SerDes chip are configured based on the first target data.

[0008] In some embodiments, when the second slave device is deployed inside a second SerDes chip, the method includes a first mode, wherein the first mode includes: decoding the first A-PHY bus data sent by the master device through a monitor of a second verification unit to obtain second target data; the second target data is used to compare with the first target data to obtain a verification result; and the first SerDes chip is connected to the monitor of the second verification unit.

[0009] In some embodiments, when the second slave device is deployed inside the second SerDes chip, the target object is the second SerDes chip; the corresponding slave device is determined by the master device deployed outside the first SerDes chip, and the register configuration for the target object where the slave device is located includes: a second mode and a third mode; wherein the second mode includes: sending the second A-PHY bus data to the second slave device through the driver of the second verification unit; the second verification unit is used to simulate the A-PHY interface to generate the second A-PHY bus data; the second slave device converts the second A-PHY bus data into the third target data corresponding to the APB bus; based on the third The target data configures the register of the second SerDes chip; the second SerDes chip is connected to the driver of the second verification unit; the third mode includes: sending the second I2C bus data to the first SerDes chip through the driver of the first verification unit; the first SerDes chip encodes the second I2C bus data into third A-PHY bus data and sends it to the second SerDes chip; the second SerDes chip converts the third A-PHY bus data into fourth target data corresponding to the APB bus; configuring the register of the second SerDes chip based on the fourth target data; the first SerDes chip is connected to the second SerDes chip.

[0010] In some embodiments, when the third slave device is deployed inside the sensor, the method includes a fourth mode, wherein the fourth mode includes: decoding the third I2C bus data sent by the master device through the monitor of the first verification unit to obtain fifth target data; the fifth target data is used to compare with the first target data to obtain a verification result; and the second SerDes chip is connected to the monitor of the first verification unit.

[0011] In some embodiments, the monitor of the first verification unit is used to simulate a third slave device deployed inside the sensor.

[0012] In some embodiments, when the third slave device is deployed inside the sensor, the target object is the sensor; the corresponding slave device is determined by the master device deployed outside the first SerDes chip, and the register configuration for the target object where the slave device is located includes: the fifth mode; wherein the fifth mode includes: sending the fourth I2C bus data to the first SerDes chip through the driver of the first verification unit; the first SerDes chip encodes the second I2C bus data into fourth A-PHY bus data and sends it to the second SerDes chip; the second SerDes chip converts the fourth A-PHY bus data into sixth target data corresponding to the APB bus; the register of the sensor is configured based on the sixth target data; the first SerDes chip is connected to the second SerDes chip.

[0013] In some embodiments, the register-based write-before-read method is used to verify whether the master device of the first SerDes chip communicates normally with slave devices deployed at different locations, including: the master device sends a write instruction to the slave device, the write instruction includes write content and write address; and the master device sends a read instruction to the slave device to obtain a read result returned by the register of the slave device; the read result is compared with the write content to obtain a verification result.

[0014] In a second aspect, the present invention provides a verification system for a vehicle-mounted SerDes chip, comprising:

[0015] A first verification unit is used to simulate an I2C interface to configure registers for a target object where the first slave device and the third slave device are located;

[0016] A second verification unit, configured to simulate an A-PHY interface to configure a register of a target object where a second slave device is located;

[0017] A control unit, used to control the master device to send write instructions to the first slave device, the second slave device and the third slave device respectively, wherein the write instructions include write content and write address; and control the master device to send read instructions to the first slave device, the second slave device and the third slave device to obtain read results returned by registers of the first slave device, the second slave device and the third slave device;

[0018] The processing unit is used to compare the read result with the written content to obtain a verification result.

[0019] In a third aspect, the present invention provides a vehicle having a verification system for an on-vehicle SerDes chip as described in the second aspect.

[0020] The beneficial effect of the solution provided by the embodiment of the present disclosure is that: by determining the corresponding slave device through a master control device deployed outside the first SerDes chip, configuring registers for the target object where the slave device is located, it is possible to verify the slave devices deployed at different positions in the uplink path through the registers, which helps to improve the flexibility and accuracy of the vehicle-mounted SerDes chip verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of a flow chart of a method for verifying a vehicle-mounted SerDes chip provided by an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of a framework for configuring a register for a first slave device provided by an embodiment of the present invention;

[0023] Figure 3 A schematic diagram of a framework of a first mode provided by an embodiment of the present invention;

[0024] Figure 4 A schematic diagram of a framework of a second mode provided by an embodiment of the present invention;

[0025] Figure 5 A schematic diagram of a framework of a third mode provided by an embodiment of the present invention;

[0026] Figure 6 A schematic diagram of a fourth mode of the present invention;

[0027] Figure 7 A schematic diagram of a fifth mode provided by an embodiment of the present invention;

[0028] Figure 8 A schematic diagram of a verification system for an in-vehicle SerDes chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0030] In related technologies, vehicle-mounted SerDes chips generally appear in pairs, namely the first SerDes chip (receiving end) and the second SerDes chip (transmitting end). The second SerDes chip mainly receives audio or image data from the sensor and then encodes it into the format of the automotive serializer-deserializer physical layer specification (Automotive Serial Interface - Physical Layer, A-PHY) for output. The first SerDes chip mainly receives and decodes data in A-PHY format and transmits it to the subsequent processor for subsequent processing. Usually, the first SerDes chip and the second SerDes chip are developed at the same time to ensure that the data link can be unobstructed.

[0031] In the prior art, the I2C bus in the vehicle-mounted SerDes chip is usually used to configure the registers in the SerDes chip. The I2C master device is located on the side of the first SerDes chip and belongs to the uplink path in the link. Since the I2C slave device may exist in the first SerDes chip, the second SerDes chip or the sensor. Therefore, the I2C bus verification of the vehicle-mounted SerDes chip has the following problems:

[0032] 1. If two sets of verification environments are developed at the same time on the first SerDes chip (receiving end) and the second SerDes chip (transmitting end), there will be problems such as large workload, long verification cycle, and difficulty in convergence;

[0033] 2. If the first SerDes chip (receiving end) and the second SerDes chip (transmitting end) are directly connected for verification, the two chips may have a misunderstanding of the protocol, resulting in the first SerDes chip and the second SerDes chip being able to connect normally, but there is a problem of inconsistent protocol description. In addition, the handling of abnormal situations in the connection verification is not flexible enough, which is not conducive to improving the robustness of the verification.

[0034] In order to at least partially solve one or more of the above problems and other potential problems, the present disclosure proposes a verification method for an in-vehicle SerDes chip, the method comprising: determining the corresponding slave device through a master device deployed outside the first SerDes chip, and configuring registers for the target object where the slave device is located; wherein the target object includes but is not limited to the first SerDes chip, the second SerDes chip, and the sensor; based on the register, verifying whether the master device and the slave devices deployed at different locations communicate normally in a write-first-read-later manner. The technical solution of the present disclosure, by determining the corresponding slave device through a master device deployed outside the first SerDes chip, and configuring registers for the target object where the slave device is located, can realize the verification of slave devices deployed at different locations in the uplink path, which helps to improve the flexibility and accuracy of the verification of in-vehicle SerDes chips.

[0035] Figure 1 FIG. 1 is a flow chart of a verification method for a vehicle-mounted SerDes chip according to an embodiment of the present disclosure, Figure 1 As shown, the method comprises at least the following steps:

[0036] S101: Determine a corresponding slave device through a master device deployed outside the first SerDes chip, and configure a register for a target object where the slave device is located; wherein the target object includes but is not limited to the first SerDes chip, the second SerDes chip, and a sensor;

[0037] S102: Verify whether the master device and the slave devices deployed at different locations communicate normally based on registers in a write-first-read-later manner.

[0038] In some embodiments, the first SerDes chip refers to a SerDes chip used to receive data in an intelligent driving system. In an intelligent driving system, SerDes chips usually appear in pairs; wherein the first SerDes chip is used to receive data in the intelligent driving system; and the second SerDes chip is used to send data in the intelligent driving system. Under normal circumstances, the main task of the first SerDes chip (receiving end) is to receive a serialized and possibly encoded (such as using A-PHY and other formats) data stream from the second SerDes chip (transmitting end). After receiving the data, the second SerDes chip will perform deserialization and decoding operations, convert the serial data back to the original parallel data format, and then output it to the subsequent processor or other device for processing.

[0039] In some embodiments, the master device refers to a core device for data processing deployed outside the first SerDes chip. The master device can be connected and exchange data with the slave device through a target interface (such as a parallel interface, a serial interface or other high-speed communication interface). The master device can be used for:

[0040] 1. Data processing: The master device receives data from slave devices deployed inside the first SerDes chip, slave devices deployed inside the SerDes chip, and sensors, and processes and analyzes the data. Data processing methods may include data filtering, format conversion, algorithm operation, etc. to meet the specific data requirements of the intelligent driving system.

[0041] 2. Performance monitoring: The master control device is also used to monitor the performance status of the SerDes chip, including key indicators such as data transmission rate, error rate, power consumption, etc. Through real-time monitoring and feedback, they can ensure the stable operation and efficient performance of the intelligent driving system.

[0042] In some embodiments, the slave device refers to a device deployed in the target object (i.e., the first SerDes chip (receiving end), the second SerDes chip (transmitting end) and the sensor) for responding to the master device. The slave device can be used for:

[0043] 1. Data reception and processing: The slave device is mainly responsible for receiving data or instructions sent by the master device or other slave devices, and performing corresponding processing based on these data. For example, in SerDes communication, the slave device of the first SerDes chip will receive serial data from the second SerDes chip and convert it into parallel data for subsequent processing.

[0044] 2. Task execution: According to the request of the master device, the slave device will perform the corresponding task. The task may include data conversion, storage, transmission, etc. For example, in the scenario where the sensor is a slave device, the sensor will collect environmental data according to the instruction of the master device and send this data to the master device for processing.

[0045] 3. System coordination: In complex systems, multiple slave devices may work together to complete more complex tasks. These devices may communicate and coordinate through the master control device to ensure the stable operation of the intelligent driving system.

[0046] In some embodiments, when the slave device is deployed inside the first SerDes chip, the slave device may be integrated into the chip in some form and is responsible for receiving and processing serial data from the sender. When the slave device is deployed in a sensor, it can collect environmental data (such as temperature, pressure, light intensity, etc.) according to the instructions of the master device, and send the above data to the master device for processing in some way (such as wireless transmission, wired connection, etc.).

[0047] In some embodiments, the register refers to a storage unit associated with a slave device for storing configuration information. These registers may be located inside the slave device, or in an interface or controller between the master device and the slave device. The register may be used to:

[0048] 1. Configuration control: Registers are used to store configuration information sent from the master device to the slave device. This configuration information may include the device's operating mode, parameter settings, data format, etc. to control the behavior and performance of the slave device.

[0049] 2. Status monitoring: The registers of slave devices may also contain status information of the device, such as whether it is ready, whether an error has occurred, etc. The master device can monitor the operating status of the slave device by reading these status registers and take corresponding actions accordingly.

[0050] 3. Data interaction: In some cases, registers are also used to transfer data between the master device and the slave device. Although SerDes chips are mainly used for high-speed serial-to-parallel / parallel-to-serial data conversion, registers can be used to temporarily store data before or after data conversion.

[0051] 4. Device identification and addressing: In a complex system, there may be multiple slave devices. Registers can be used to identify and address devices, ensuring that the master device can accurately communicate with a specific slave device.

[0052] Among them, the registers for configuring the slave device may include: the registers are usually accessed through a specific interface or protocol, such as I2C; the master device configures and controls the slave device by sending configuration commands and data to the corresponding register address; after the configuration is completed, the slave device will perform corresponding operations according to the register settings and return status information or data to the master device.

[0053] In some embodiments, the write-before-read approach may include: the master device writes specific data or instructions to a register of the slave device; the master device reads data from the same or another register of the slave device. By comparing the read data with the written data, it can be verified whether the master device and the slave devices deployed at different locations communicate normally.

[0054] The solution of the embodiment of the present disclosure determines the corresponding slave device through the master device deployed outside the first SerDes chip, configures registers for the target object where the slave device is located, and verifies whether the master device and the slave devices deployed at different locations communicate normally in a write-first-read-later manner based on the register. In this way, the register can verify the slave devices deployed at different locations in the uplink path, which helps to improve the flexibility and accuracy of the vehicle-mounted SerDes chip verification.

[0055] In an embodiment of the present disclosure, when the first slave device is deployed inside the first SerDes chip, the target object is the first SerDes chip; the corresponding slave device is determined by a master control device deployed outside the first SerDes chip, and registers are configured for the target object where the slave device is located, including: sending the first I2C bus data to the first slave device through a driver of a first verification unit; wherein the first verification unit is used to simulate an I2C interface to generate the first I2C bus data; the first slave device converts the first I2C bus data into first target data corresponding to an Advanced Peripheral Bus (APB); and the registers of the first SerDes chip are configured based on the first target data.

[0056] Reference Figure 2, a register is configured for the first SerDes chip by a first slave device deployed inside the first SerDes chip. Among them, the first verification unit (I2C_AGENT) refers to a verification unit for verifying the I2C protocol. In the Universal Verification Methodology (UVM) architecture, Agent represents a functional unit (such as an interface, processor, or memory, etc.) in the verification design. For the I2C bus, I2C_AGENT is a verification unit for simulating the I2C interface to verify the communication behavior of the I2C bus. Here, the I2C interface defines the interface specification for how devices communicate through the I2C bus. The first verification unit encapsulates the verification logic related to the I2C communication protocol, including components such as a sequencer, a driver, and a monitor. The driver is used to simulate the I2C interface to realize the transmission of I2C bus data. Specifically, in the first verification unit, the Driver is used to convert the data generated and defined by the Sequence component into a physical signal compatible with the I2C bus, and send the first I2C bus data to the component (such as the first slave device) of the Design Under Test (DUT). The first I2C bus data refers to the data generated by the Driver of the first verification unit according to the instruction of the Sequence. In the I2C communication process, the first I2C bus data refers to a series of data units sent in sequence, and these data units are transmitted from the sending end (first verification unit) to the receiving end (first slave device) through the I2C bus. Among them, the first verification unit is used to simulate the master device sending the first I2C bus data to the first slave device. The first I2C bus data is in bytes, and its data content can be a control command, configuration parameters, data payload, etc. The specific data content included in the first I2C bus data is determined by the verification purpose and the function of the I2C interface. The first I2C bus data is transmitted to the first slave device through the I2C bus, triggering the first slave device to perform a corresponding operation. The first slave device converts the first I2C bus data into the first target data corresponding to the APB bus. The APB bus is a bus used to connect a high-performance microcontroller and its various peripheral devices. Through the APB bus, the microcontroller can efficiently control and manage these peripheral devices to achieve fast data transmission and precise control of the device. The first target data is data that complies with the APB bus protocol specification. The first target data is used to configure the register of the first SerDes chip.

[0057] In this way, by configuring registers for the first SerDes chip through a slave device deployed inside the first SerDes chip, it is possible to verify whether the master device and the slave device deployed inside the first SerDes chip communicate normally, which helps to improve the accuracy of vehicle-mounted SerDes chip verification.

[0058] In an embodiment of the present disclosure, when the second slave device is deployed inside the second SerDes chip, the method includes a first mode, wherein the first mode includes: decoding the first A-PHY bus data sent by the master device through the monitor of the second verification unit to obtain second target data; the second target data is used to compare with the first target data to obtain a verification result; the first SerDes chip is connected to the monitor of the second verification unit.

[0059] Reference Figure 3 , the second verification unit (A-PHY_AGENT) refers to a verification unit for verifying the A-PHY protocol. In the UVM architecture, Agent represents a functional unit (such as an interface, processor, or memory) in the verification design. For the A-PHY bus, A-PHY_AGENT is a verification unit for simulating the A-PHY interface to verify the communication behavior of the A-PHY bus. Here, the A-PHY interface defines the interface specification of how devices communicate through the A-PHY bus. The second verification unit encapsulates the verification logic related to the A-PHY communication protocol, including components such as Sequencer, Driver, and Monitor. The Monitor is used to monitor and collect interface data. The first SerDes chip (receiving end) is verified separately, including: the Monitor of the second verification unit decodes the first A-PHY bus data sent by the master device to obtain the second target data. The first A-PHY bus data refers to the data sent by the master device through the A-PHY bus captured by the Monitor of the second verification unit. The first A-PHY bus data is in bytes, and its data content can be control commands, configuration parameters, data payloads, etc. The specific data content included in the first A-PHY bus data is determined by the verification purpose. The first A-PHY bus data is transmitted from the main control device to the second verification unit via the A-PHY bus, and the second verification unit decodes the first A-PHY bus data to obtain the second target data. The second target data is used to compare with the first target data to obtain a verification result. Here, the first target data is data processed by the first verification unit. By comparing the consistency of the second target data with the first target data, the correctness and reliability of the A-PHY protocol and the I2C protocol during the data transmission process are verified. If the data of the two are consistent, it indicates that the communication is normal; if not, it is necessary to further analyze the cause and adjust the verification environment or protocol implementation.

[0060] In this way, whether the master device and the slave device deployed inside the second SerDes chip communicate normally is verified by a separate verification method, which helps to improve the accuracy of the vehicle-mounted SerDes chip verification.

[0061] In the embodiment of the present disclosure, when the second slave device is deployed inside the second SerDes chip, the target object is the second SerDes chip; the corresponding slave device is determined by the master device deployed outside the first SerDes chip, and the register configuration for the target object where the slave device is located includes: a second mode and a third mode; wherein the second mode includes: sending the second A-PHY bus data to the second slave device through the driver of the second verification unit; the second verification unit is used to simulate the A-PHY interface to generate the second A-PHY bus data; the second slave device converts the second A-PHY bus data into the third target data corresponding to the APB bus; based on the third The target data configures the register of the second SerDes chip; the second SerDes chip is connected to the driver of the second verification unit; the third mode includes: sending the second I2C bus data to the first SerDes chip through the driver of the first verification unit; the first SerDes chip encodes the second I2C bus data into third A-PHY bus data and sends it to the second SerDes chip; the second SerDes chip converts the third A-PHY bus data into fourth target data corresponding to the APB bus; configuring the register of the second SerDes chip based on the fourth target data; the first SerDes chip is connected to the second SerDes chip.

[0062] Reference Figure 4, the registers of the second SerDes chip are configured by a second slave device deployed inside the second SerDes chip. Specifically, in the second verification unit, the Driver is used to convert the data defined by the test sequence into a physical signal compatible with the A-PHY bus, and send the second A-PHY bus data to the component of the DUT (such as the second slave device). The second A-PHY bus data refers to the data generated by the Driver of the second verification unit according to the instructions of the test sequence. In the A-PHY bus communication process, the second A-PHY bus data refers to a series of data units sent in sequence, and these data units are transmitted from the transmitting end (the second verification unit) to the receiving end (the second slave device) through the A-PHY bus. The second SerDes chip (transmitting end) is verified separately, including: the second verification unit simulates the master device to send the second A-PHY bus data to the second slave device; the second slave device converts the second A-PHY bus data into the third target data corresponding to the APB bus; the third target data is used to configure the registers of the second SerDes chip. The second A-PHY bus data is in bytes, and its data content may be a control command, a configuration parameter, a data payload, etc. The specific data content included in the second A-PHY bus data is determined by the verification purpose and the function of the A-PHY interface. The second A-PHY bus data is transmitted to the third slave device via the A-PHY bus, triggering the second slave device to perform a corresponding operation.

[0063] Reference Figure 5 , the second SerDes chip is configured with a register through a second slave device deployed inside the second SerDes chip. The docking verification is performed based on the first SerDes chip (receiving end) and the second SerDes chip (transmitting end), including: sending the second I2C bus data to the first SerDes chip through the driver of the first verification unit; the first SerDes chip encodes the second I2C bus data into the third A-PHY bus data and sends it to the second SerDes chip; the second SerDes chip converts the third A-PHY bus data into the fourth target data corresponding to the APB bus; and the register of the second SerDes chip is configured based on the fourth target data.

[0064] In this way, by combining separate verification with docking verification, it is possible to verify whether the master device and the slave device deployed inside the second SerDes chip are communicating normally, which helps to improve the accuracy and efficiency of vehicle-mounted SerDes chip verification.

[0065] In the embodiment of the present disclosure, when the third slave device is deployed inside the sensor, the method includes a fourth mode, wherein the fourth mode includes: decoding the third I2C bus data sent by the master device through the monitor of the first verification unit to obtain fifth target data; the fifth target data is used to compare with the first target data to obtain a verification result; and the second SerDes chip is connected to the monitor of the first verification unit.

[0066] Reference Figure 6 , the third I2C bus data is in bytes, and its data content can be control commands, configuration parameters, data payloads, etc. The specific data content included in the third I2C bus data is determined by the verification purpose. The first verification unit decodes the third I2C bus data to obtain the fifth target data. The fifth target data is used to compare with the first target data to obtain a verification result. Here, the first target data is data processed by the first verification unit. By comparing the consistency of the second target data with the first target data, the correctness and reliability of the I2C protocol during the data transmission process are verified. If the data of the two are consistent, it indicates that the communication is normal; if not, it is necessary to further analyze the cause and adjust the verification environment or protocol implementation.

[0067] In this way, it is possible to verify the slave device deployed inside the sensor in the uplink path, which helps to improve the accuracy of vehicle-mounted SerDes chip verification.

[0068] In the disclosed embodiment, the monitor of the first verification unit is used to simulate a third slave device deployed inside the sensor.

[0069] In some embodiments, the Monitor is used to simulate a slave device at the sensor end, and the Monitor decodes the received third I2C bus data into register configuration.

[0070] In this way, the Monitor can simulate a variety of different Sensor or I2C slave devices, which helps improve the reusability of the in-vehicle SerDes chip verification method.

[0071] In the embodiment of the present disclosure, when the third slave device is deployed inside the sensor, the target object is the sensor; the corresponding slave device is determined by the master device deployed outside the first SerDes chip, and the register configuration for the target object where the slave device is located includes: the fifth mode; wherein the fifth mode includes: sending the fourth I2C bus data to the first SerDes chip through the driver of the first verification unit; the first SerDes chip encodes the fourth I2C bus data into fourth A-PHY bus data and sends it to the second SerDes chip; the second SerDes chip converts the fourth A-PHY bus data into sixth target data corresponding to the APB bus; the register of the sensor is configured based on the sixth target data; the first SerDes chip is connected to the second SerDes chip.

[0072] Reference Figure 7 , a register is configured for the sensor through a third slave device deployed inside the sensor.

[0073] In this way, it is possible to verify whether the master device and the slave device deployed inside the sensor are communicating normally, which helps to improve the flexibility and accuracy of vehicle-mounted SerDes chip verification.

[0074] In the disclosed embodiment, the register-based write-before-read method is used to verify whether the master device of the first SerDes chip communicates normally with slave devices deployed at different locations, including: the master device sends a write instruction to the slave device, the write instruction includes write content and write address; and the master device sends a read instruction to the slave device to obtain a read result returned by the register of the slave device; the read result is compared with the write content to obtain a verification result.

[0075] In some embodiments, the master device A sends a write instruction to the slave device a through the I2C communication protocol, and the write instruction includes writing content "0xAB" and writing a register with address "0x02"; the slave device a receives the write instruction sent by the master device A; the slave device a stores the written content in the corresponding register according to the write address "0x02"; the slave device a sends a confirmation response to the master device, indicating that the write operation is successfully completed; the master device A sends a read instruction to the slave device a through the I2C communication protocol, and the read instruction includes reading the register address " 0x02"; slave device a receives the read instruction sent by master device A; reads the value from the corresponding register according to the read address "0x02"; slave device a returns the read result to master device A through the communication protocol; master device A receives the read result "0xAB" returned by slave device a; compares the read result with the written content; if the read result is consistent with the written content, the verification is passed, indicating that the communication between the master device and the slave device is normal; if the read result is inconsistent with the written content, the verification fails, indicating that there is a communication error or a register problem.

[0076] In this way, verifying whether the communication between the master device and the slave device is normal by writing first and then reading helps to improve the reliability and intuitiveness of vehicle-mounted SerDes chip verification.

[0077] Figure 8 is a schematic diagram of a verification system for an in-vehicle SerDes chip according to an embodiment of the present disclosure, such as Figure 8 As shown, the system at least includes:

[0078] A first verification unit is used to simulate an I2C interface to configure registers for a target object where the first slave device and the third slave device are located;

[0079] A second verification unit, configured to simulate an A-PHY interface to configure a register of a target object where a second slave device is located;

[0080] A control unit, used to control the master device to send write instructions to the first slave device, the second slave device and the third slave device respectively, wherein the write instructions include write content and write address; and control the master device to send read instructions to the first slave device, the second slave device and the third slave device to obtain read results returned by registers of the first slave device, the second slave device and the third slave device;

[0081] The processing unit is used to compare the read result with the written content to obtain a verification result.

[0082] In this way, by configuring registers for slave devices deployed at different locations, it is possible to support verification of slave devices deployed at different locations in the uplink path, which helps to improve the flexibility and accuracy of vehicle-mounted SerDes chip verification.

[0083] According to an embodiment of the present disclosure, the present disclosure also provides a vehicle having a verification system of the vehicle-mounted SerDes chip as described above.

[0084] In some embodiments, the type of the vehicle includes but is not limited to an autonomous driving vehicle and a new energy vehicle.

[0085] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A verification method for an in-vehicle SerDes chip, characterized in that: The method comprises: Determine a corresponding slave device through a master device deployed outside the first SerDes chip, and configure a register for a target object where the slave device is located; wherein the target object includes but is not limited to the first SerDes chip, the second SerDes chip, and a sensor; Verifying whether the master device and slave devices deployed at different locations communicate normally based on the register in a write-first-read-later manner; When the first slave device is deployed inside the first SerDes chip, the target object is the first SerDes chip; The determining the corresponding slave device by a master device deployed outside the first SerDes chip, and configuring a register for a target object where the slave device is located, includes: Sending the first I2C bus data to the first slave device through a driver of the first verification unit; wherein the first verification unit is used to simulate an I2C interface to generate the first I2C bus data; The first slave device converts the first I2C bus data into first target data corresponding to the APB bus; configures the register of the first SerDes chip based on the first target data; and the first SerDes chip is connected to the driver of the first verification unit.

2. The method according to claim 1, characterized in that When the second slave device is deployed inside the second SerDes chip, the method includes a first mode, wherein the first mode includes: The first A-PHY bus data sent by the main control device is decoded by the monitor of the second verification unit to obtain second target data; the second target data is used to compare with the first target data to obtain a verification result; the first SerDes chip is connected to the monitor of the second verification unit.

3. The method according to claim 2, characterized in that When the second slave device is deployed inside the second SerDes chip, the target object is the second SerDes chip; The method of determining the corresponding slave device by the master device deployed outside the first SerDes chip and configuring the register for the target object where the slave device is located includes: a second mode and a third mode; wherein, The second mode includes: sending the second A-PHY bus data to the second slave device through the driver of the second verification unit; the second verification unit is used to simulate the A-PHY interface to generate the second A-PHY bus data; the second slave device converts the second A-PHY bus data into third target data corresponding to the APB bus; configuring the register of the second SerDes chip based on the third target data; the second SerDes chip is connected to the driver of the second verification unit; The third mode includes: sending the second I2C bus data to the first SerDes chip through the driver of the first verification unit; the first SerDes chip encodes the second I2C bus data into third A-PHY bus data and sends it to the second SerDes chip; the second SerDes chip converts the third A-PHY bus data into fourth target data corresponding to the APB bus; configuring the register of the second SerDes chip based on the fourth target data; the first SerDes chip is connected to the second SerDes chip.

4. The method according to claim 3, characterized in that When the third slave device is deployed inside the sensor, the method includes a fourth mode, wherein the fourth mode includes: The third I2C bus data sent by the main control device is decoded by the monitor of the first verification unit to obtain fifth target data; the fifth target data is used to compare with the first target data to obtain a verification result; the second SerDes chip is connected to the monitor of the first verification unit.

5. The method according to claim 4, characterized in that The monitor of the first verification unit is used to simulate the third slave device deployed inside the sensor.

6. The method according to claim 4, characterized in that When the third slave device is deployed inside the sensor, the target object is the sensor; The method of determining the corresponding slave device by a master device deployed outside the first SerDes chip and configuring a register for the target object where the slave device is located includes: a fifth mode; wherein, The fifth mode includes: sending the fourth I2C bus data to the first SerDes chip through the driver of the first verification unit; the first SerDes chip encodes the fourth I2C bus data into fourth A-PHY bus data and sends it to the second SerDes chip; the second SerDes chip converts the fourth A-PHY bus data into sixth target data corresponding to the APB bus; configuring the register of the sensor based on the sixth target data; the first SerDes chip is connected to the second SerDes chip.

7. The method according to claim 1, characterized in that The verifying whether the master device of the first SerDes chip communicates normally with slave devices deployed at different locations in a write-before-read manner based on the register includes: The master device sends a write instruction to the slave device, wherein the write instruction includes a write content and a write address; and The master device sends a read instruction to the slave device, and obtains a read result returned by a register of the slave device; The read result is compared with the written content to obtain a verification result.

8. A verification system for an in-vehicle SerDes chip, characterized in that: The system comprises: A first verification unit is used to simulate an I2C interface to configure registers for a target object where the first slave device and the third slave device are located; A second verification unit, configured to simulate an A-PHY interface to configure a register of a target object where a second slave device is located; a control unit, configured to control the master device to send write instructions to the first slave device, the second slave device, and the third slave device, respectively, wherein the write instructions include write content and write addresses; and control the master device to send read instructions to the first slave device, the second slave device, and the third slave device, and obtain read results returned by registers of the first slave device, the second slave device, and the third slave device; A processing unit, used to compare the read result with the written content to obtain a verification result; When the first slave device is deployed inside the first SerDes chip, the target object is the first SerDes chip; The first verification unit is further used to send the first I2C bus data to the first slave device through the driver of the first verification unit; wherein the first verification unit is used to simulate the I2C interface to generate the first I2C bus data; The first slave device converts the first I2C bus data into first target data corresponding to the APB bus; configures the register of the first SerDes chip based on the first target data; and the first SerDes chip is connected to the driver of the first verification unit.

9. A vehicle, characterized in that: The vehicle has the verification system of the vehicle-mounted SerDes chip as described in claim 8 above.

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