Chiplet interface circuit, instantiation method and alignment method

Abstract

The present application relates to the field of integrated circuit technology and provides a core particle interface circuit, instantiation method and alignment method. The alignment of the core particle interface circuit includes: firstly using the first channel module and the second channel module in a corresponding relationship to cooperate with each other to complete the internal alignment of the channel module, and then using the whole of the at least one first channel module and the whole of the at least one second channel module to cooperate with each other to complete the alignment between the channel modules. In this way, through modular design and splicing, the bandwidth that meets the user's needs is quickly achieved, and the increase in physical layer area caused by the increase in bandwidth demand can be flexibly adapted, the interconnection performance is maintained, the complexity of the control logic is reduced, the training of data link alignment is simplified, and the response speed is improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a chip interface circuit, an instantiation method and an alignment method. Background Art

[0002] With the development of integrated circuit technology, the increase in chip resource density and data logic clock frequency requires increasing chip area to improve integration. This makes the die, that is, the small pieces cut from the wafer and not packaged, increasingly challenged in terms of area and yield. In the prior art, chiplet technology is applied to improve the yield and reduce the production cost by dividing the large chip into smaller chips, while adapting to various chiplet interconnection technologies. In terms of data transmission of the chiplet, the routing delay introduced by the clock tree and the accompanying signal limits the performance of the physical layer, and may also cause data misalignment due to the delay difference. The solutions of the prior art require complex control logic and are difficult to flexibly adapt to the bandwidth requirements for adjustment.

[0003] To this end, the present application provides a chip interface circuit, instantiation method and alignment method to address the technical difficulties in the prior art. Summary of the invention

[0004] In a first aspect, the present application provides a core particle interface circuit. The core particle interface circuit is used for interconnection between a first core particle and a second core particle, the first core particle includes a first physical layer, the first physical layer includes at least one first channel module instantiated according to a channel module template, the second core particle includes a second physical layer, the second physical layer includes at least one second channel module instantiated according to the channel module template, the at least one first channel module corresponds to the at least one second channel module one by one, the number of single-ended data links included in each first channel module in the at least one first channel module is equal to the number of single-ended data links included in the second channel module corresponding to the first channel module in the at least one second channel module, and the alignment of the core particle interface circuit includes: firstly using the corresponding first channel module and the second channel module to cooperate with each other to complete the internal alignment of the channel module, and then using the whole of the at least one first channel module and the whole of the at least one second channel module to cooperate with each other to complete the alignment between the channel modules.

[0005] Through the first aspect of the present application, a bandwidth that meets user needs is quickly achieved through modular design and splicing, and the increase in physical layer area caused by the increase in bandwidth demand can be flexibly adapted, while maintaining interconnection performance, reducing the complexity of control logic, simplifying data link alignment training, and improving response speed.

[0006] In a possible implementation of the first aspect of the present application, a given first channel module in the at least one first channel module corresponds to a given second channel module in the at least one second channel module, and the given first channel module and the given second channel module cooperate with each other to complete the internal alignment of the channel modules, including: using the single-ended data link included in the given first channel module as the sending end, recording the initial position of the read pointer when the single-ended data link included in the given second channel module is correctly received, thereby obtaining the initial position configuration of the read pointer of the given second channel module; using the single-ended data link included in the given second channel module as the sending end, recording the initial position of the read pointer when the single-ended data link included in the given first channel module is correctly received, thereby obtaining the initial position configuration of the read pointer of the given first channel module.

[0007] In a possible implementation of the first aspect of the present application, the whole of the at least one first channel module and the whole of the at least one second channel module are used to cooperate with each other to complete the alignment between the channel modules, including: using the whole of the at least one first channel module as a transmitting end, simultaneously sending a code pattern with a fixed length, and using the whole of the at least one second channel module as a receiving end, outputting the respective received data valid signals of the at least one second channel module, and then using the latest received data valid signal among the respective received data valid signals of the at least one second channel module as a reference to obtain a compensation calculation result, and using the compensation calculation result to update the respective read pointer initial position configuration of the at least one second channel module; using the whole of the at least one second channel module as a transmitting end, simultaneously sending a code pattern with the fixed length, and using the whole of the at least one first channel module as a receiving end, outputting the respective received data valid signals of the at least one first channel module, and then using the latest received data valid signal among the respective received data valid signals of the at least one first channel module as a reference to obtain a compensation calculation result, and using the compensation calculation result to update the respective read pointer initial position configuration of the at least one first channel module.

[0008] In a possible implementation manner of the first aspect of the present application, the given first channel module is any first channel module among the at least one first channel module.

[0009] In a possible implementation of the first aspect of the present application, the initial position of the read pointer when each single-ended data link included in the given second channel module is correctly received is determined by adding one initial position of the read pointer until the code comparison result is correct.

[0010] In a possible implementation of the first aspect of the present application, the compensation calculation result includes the deviation value compensation of the second channel module corresponding to other received data valid signals other than the latest received data valid signal in the received data valid signals of each of the at least one second channel modules, calculated with the latest received data valid signal as a reference.

[0011] In a possible implementation of the first aspect of the present application, the compensation calculation result is used to update the initial position configuration of the read pointer of each of the at least one first channel modules, including, based on the deviation value compensation, delaying the initial position of the read pointer of the second channel module corresponding to the other received data valid signals in the received data valid signals of the at least one second channel module except for the latest received data valid signal.

[0012] In a possible implementation of the first aspect of the present application, the channel module template includes a sending data signal channel, a sending clock signal channel, a sending valid indication signal channel, a receiving data signal channel, a receiving clock signal channel, and a receiving valid indication signal channel.

[0013] In a possible implementation of the first aspect of the present application, the channel module template includes a data sending unit, and the data sending unit includes a training unit, a code generator, a multiplexer, a delay unit, a parallel-to-serial conversion unit, and a high-speed analog sending unit.

[0014] In a possible implementation of the first aspect of the present application, the channel module template includes a data receiving unit, and the data receiving unit includes a training unit, a code comparator, a multiplexer, a read pointer control unit, a serial-to-parallel conversion unit, and a high-speed analog receiving unit.

[0015] In a possible implementation manner of the first aspect of the present application, the number of single-ended data links included in each of the at least one first channel module corresponds to the data bandwidth of the first channel module.

[0016] In a possible implementation of the first aspect of the present application, the alignment between the channel modules is achieved by an alignment circuit between the first channel modules and an alignment circuit between the second channel modules, the alignment circuit between the first channel modules is located in the first physical layer and is independent of the at least one first channel module, and the alignment circuit between the second channel modules is located in the second physical layer and is independent of the at least one second channel module.

[0017] In a possible implementation of the first aspect of the present application, the chip interface circuit is used for physical layer interconnection of parallel single-ended signals, or for physical layer interconnection of serial differential signals.

[0018] In a second aspect, an embodiment of the present application further provides an instantiation method for a core particle interface circuit. The instantiation method includes: using a channel module template, instantiating at least one first channel module included in the first physical layer of the first core particle, and instantiating at least one second channel module included in the second physical layer of the second core particle, wherein the first core particle and the second core particle are interconnected through a core particle interface circuit, the core particle interface circuit includes the first physical layer and the second physical layer, the at least one first channel module corresponds to the at least one second channel module one by one, the number of single-ended data links included in each first channel module in the at least one first channel module is equal to the number of single-ended data links included in the second channel module corresponding to the first channel module in the at least one second channel module, and the alignment of the core particle interface circuit includes: first using the corresponding first channel module and the second channel module to cooperate with each other to complete the internal alignment of the channel module, and then using the entirety of the at least one first channel module and the entirety of the at least one second channel module to cooperate with each other to complete the alignment between the channel modules.

[0019] Through the second aspect of the present application, a bandwidth that meets user needs is quickly achieved through modular design and splicing, and the increase in physical layer area caused by the increase in bandwidth demand can be flexibly adapted, while maintaining interconnection performance, reducing the complexity of control logic, simplifying data link alignment training, and improving response speed.

[0020] In a third aspect, an embodiment of the present application further provides an alignment method for a core particle interface circuit. The core particle interface circuit is used for interconnection between a first core particle and a second core particle, the first core particle includes a first physical layer, the first physical layer includes at least one first channel module instantiated according to a channel module template, the second core particle includes a second physical layer, the second physical layer includes at least one second channel module instantiated according to the channel module template, the at least one first channel module corresponds to the at least one second channel module one by one, the number of single-ended data links included in each first channel module in the at least one first channel module is equal to the number of single-ended data links included in the second channel module corresponding to the first channel module in the at least one second channel module, and the alignment method includes: firstly using the corresponding first channel module and the second channel module to cooperate with each other to complete the internal alignment of the channel module, and then using the whole of the at least one first channel module and the whole of the at least one second channel module to cooperate with each other to complete the alignment between the channel modules.

[0021] Through the third aspect of the present application, a bandwidth that meets user needs is quickly achieved through modular design and splicing, and the increase in physical layer area caused by the increase in bandwidth demand can be flexibly adapted, while maintaining interconnection performance, reducing the complexity of control logic, simplifying data link alignment training, and improving response speed.

[0022] In a possible implementation of the third aspect of the present application, a given first channel module in the at least one first channel module corresponds to a given second channel module in the at least one second channel module, and the given first channel module and the given second channel module cooperate with each other to complete the internal alignment of the channel modules, including: using the single-ended data link included in the given first channel module as the sending end, recording the initial position of the read pointer when the single-ended data link included in the given second channel module is correctly received, thereby obtaining the initial position configuration of the read pointer of the given second channel module; using the single-ended data link included in the given second channel module as the sending end, recording the initial position of the read pointer when the single-ended data link included in the given first channel module is correctly received, thereby obtaining the initial position configuration of the read pointer of the given first channel module.

[0023] In a possible implementation of the third aspect of the present application, the at least one first channel module and the at least one second channel module are used as a whole to cooperate with each other to complete the alignment between the channel modules, including: using the at least one first channel module as a transmitting end, simultaneously sending a code pattern with a fixed length, and using the at least one second channel module as a receiving end, outputting the received data valid signal of each of the at least one second channel modules, and then using the latest received data valid signal among the received data valid signals of each of the at least one second channel modules as a reference to obtain a compensation calculation result, and using the compensation calculation result to update the initial position configuration of the read pointer of each of the at least one second channel modules; using the at least one second channel module as a transmitting end, simultaneously sending a code pattern with the fixed length, and using the at least one first channel module as a receiving end, outputting the received data valid signal of each of the at least one first channel modules, and then using the latest received data valid signal among the received data valid signals of each of the at least one first channel modules as a reference to obtain a compensation calculation result, and using the compensation calculation result to update the initial position configuration of the read pointer of each of the at least one first channel modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic diagram of a chip interface circuit provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of a data sending unit provided in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of a data receiving unit provided in an embodiment of the present application;

[0028] Figure 4 A schematic flow chart of an instantiation method for a chip interface circuit provided in an embodiment of the present application;

[0029] Figure 5 A schematic flow chart of an alignment method for a chip interface circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0031] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0032] Figure 1 Schematic diagram of a chip interface circuit provided in an embodiment of the present application. Figure 1As shown, the chiplet interface circuit 100 is used for interconnection between a first chiplet (chiplet A110) and a second chiplet (chiplet B120). The first chiplet (chiplet A110) includes a first physical layer (physical layer A112), and the first physical layer (physical layer A112) includes at least one first channel module (first channel module A114, first channel module B116, first channel module C118) instantiated according to a channel module template. The second chiplet (chiplet B120) includes a second physical layer (physical layer B122), and the second physical layer (physical layer B122) includes at least one second channel module (second channel module A124, second channel module B126, second channel module C128) instantiated according to the channel module template. The at least one first channel module corresponds to the at least one second channel module. Specifically, the first channel module A114 corresponds to the second channel module A124, the first channel module B116 corresponds to the second channel module B126, and the first channel module C118 corresponds to the second channel module C128.

[0033] Continue reading Figure 1, the number of single-ended data links included in each of the at least one first channel module is equal to the number of single-ended data links included in the second channel module corresponding to the first channel module in the at least one second channel module. The number of single-ended data links included in the first channel module A114, for example, the number is 16, is equal to the number of single-ended data links included in the second channel module A124. The number of single-ended data links included in the first channel module B116, for example, the number is 32, is equal to the number of single-ended data links included in the second channel module B126. The number of single-ended data links included in the first channel module C118, for example, the number is 64, is equal to the number of single-ended data links included in the second channel module C128. It should be understood that a single first channel module or a single second channel module is instantiated according to the same channel module template, so the number of single-ended data links of the final channel module instance can be determined by adjusting the instantiation parameters. Here, a certain number of data links contained in a single channel module, such as 16, 32 or 64, represents the maximum data transmission efficiency that can be achieved by the channel module, that is, the data bandwidth. A single-ended data link is a 1-bit data link, so 32 single-ended data links correspond to a 32-bit data link bandwidth. In addition, the physical layers of the first core (core A110) and the second core (core B120), that is, the first physical layer (physical layer A112) and the second physical layer (physical layer B122), are respectively implemented by instantiating at least one corresponding channel module. Therefore, a higher data bandwidth can be achieved by instantiating more channel modules in one physical layer. When the required bandwidth increases exponentially, multiple channel modules can be directly instantiated in one physical layer for splicing, so as to flexibly adapt to the scalable bandwidth requirements. In addition, as long as the number of single-ended data links of the two corresponding channel modules is equal, for example, if a channel module as a transmitting end includes 16 data links for sending data, then the channel module as the opposite end as a receiving end should include 16 data links for receiving data, the number of single-ended data links of multiple channel modules of the same physical layer can be equal or unequal. For example, the number of single-ended data links included in the first channel module A114 under the same physical layer A112 is 16, and the number of single-ended data links included in the first channel module B116 is 32. Therefore, by instantiating the channel module under the same physical layer according to the same channel module template, the number of single-ended data links of the obtained channel module instance can be flexibly determined by adjusting the instantiation parameters, so that the bandwidth requirements of the communication protocol and the usage scenario as well as the customer customization requirements can be flexibly adapted, and at the same time, a physical layer modular design method of the core interface circuit is provided by multiplexing the channel module template, simplifying the design complexity and improving the response speed.

[0034] Continue reading Figure 1 In the layout and routing stage, the performance of the physical layer is affected by the routing delay, and the delay difference may cause data misalignment problems. In order to simplify the control logic and be able to flexibly adapt to scalable bandwidth requirements, based on the above-mentioned physical layer module design method, that is, by reusing the channel module template to instantiate the channel module under the same physical layer, the resulting core interface circuit 100 can adopt an optimized data transmission alignment mechanism. Specifically, the alignment of the core interface circuit 100 includes: first using the corresponding first channel module and the second channel module to cooperate with each other to complete the internal alignment of the channel module, and then using the entirety of the at least one first channel module and the entirety of the at least one second channel module to cooperate with each other to complete the alignment between the channel modules. Figure 1Take at least one first channel module (first channel module A114, first channel module B116, first channel module C118) included in the first physical layer (physical layer A112) and at least one second channel module (second channel module A124, second channel module B126, second channel module C128) included in the second physical layer (physical layer B122) as an example. First, the first channel module and the second channel module in a corresponding relationship cooperate with each other to complete the internal alignment of the channel module. As mentioned above, the first channel module A114 corresponds to the second channel module A124, the first channel module B116 corresponds to the second channel module B126, and the first channel module C118 corresponds to the second channel module C128. Therefore, the first channel module A114 cooperates with the second channel module A124 to complete the internal alignment of the channel module, the first channel module B116 cooperates with the second channel module B126 to complete the internal alignment of the channel module, and the first channel module C118 cooperates with the second channel module C128 to complete the internal alignment of the channel module. Then, the whole of the at least one first channel module and the whole of the at least one second channel module are used to cooperate with each other to complete the alignment between the channel modules. In each channel module, the data link inside the channel module can be finely delayed by a controllable delay unit, so that the delay adjustment at the unit of interval (UI) level can be achieved, such as generating a delay of the transmission interval of multiple serial data, and the delay adjustment at the sub-UI level can also be achieved, that is, flow control is performed within the range of the transmission interval of a single serial data. As long as the two interconnected core particles in the core particle interface circuit 100 have an equal physical layer, this can be achieved by keeping the number of single-ended data links of the two corresponding channel modules equal. In terms of the data transmission alignment mechanism, the training of the alignment inside the channel module is completed first, and then the training of the alignment between the channel modules is completed. This means that the design of the control logic is simplified. In the first stage of training, that is, the training of the alignment inside the channel module, only involves the two corresponding channel modules, that is, the first channel module and the second channel module in the corresponding relationship are used to cooperate with each other to complete the alignment inside the channel module. In this way, the training of the initial position configuration of the read pointer of the first channel module and the second channel module in the corresponding relationship is completed, and the code pattern comparison can be used to ensure the correct reception of the code pattern for testing. Then, the second stage of training, which is the alignment training between channel modules, is after the first stage, which is the alignment training within the module, is completed. Therefore, this means that the output within a single channel module is aligned, but the data outputs of multiple channel modules on the same physical layer may be misaligned at the boundary. Therefore, by utilizing the cooperation between the at least one first channel module as a whole and the at least one second channel module as a whole, compensation can be performed at the receiving level to offset the impact of the boundary misalignment factor.It can be seen that the optimized data transmission alignment mechanism and training process can flexibly adapt to any number of channel modules and any number of data links within the channel module. Therefore, the channel module under the same physical layer can be obtained by combining the above instantiation according to the same channel module template. The number of single-ended data links of the obtained channel module instance can be flexibly determined by adjusting the instantiation parameters. In this way, the communication protocol and usage scenarios can be flexibly adapted to the bandwidth requirements and customer customization requirements. At the same time, the physical layer modular design method of the core interface circuit is provided by reusing the channel module template, simplifying the design complexity and improving the response speed. In this way, through modular design and splicing, the bandwidth that meets user needs is quickly achieved, and the increase in physical layer area caused by the increase in bandwidth requirements can be flexibly adapted, maintaining the interconnection performance, reducing the complexity of the control logic, simplifying the training of data link alignment, and improving the response speed.

[0035] In a possible implementation, a given first channel module in the at least one first channel module is in a corresponding relationship with a given second channel module in the at least one second channel module, and the given first channel module and the given second channel module are used to cooperate with each other to complete the internal alignment of the channel module, including: using the single-ended data link included in the given first channel module as the sending end, recording the initial position of the read pointer when the single-ended data link included in the given second channel module is correctly received, thereby obtaining the initial position configuration of the read pointer of the given second channel module; using the single-ended data link included in the given second channel module as the sending end, recording the initial position of the read pointer when the single-ended data link included in the given first channel module is correctly received, thereby obtaining the initial position configuration of the read pointer of the given first channel module. The training in the first stage, that is, the training of the internal alignment of the channel module, only involves two corresponding channel modules, that is, the first channel module and the second channel module in a corresponding relationship are first used to cooperate with each other to complete the internal alignment of the channel module, and the training of the initial position configuration of the read pointer of the first channel module and the second channel module in a corresponding relationship is completed, and the code pattern comparison can be used to ensure the correct reception of the code pattern for testing. Here, the data inside the channel module is sent out after being aligned at the transmission level. Considering the deviation in the distance of the chiplet interconnection bus, link delay may be introduced, that is, the data transmission rate between the high-speed serial data buses received at the same time may be different, for example, there is an offset of one to four transmission intervals. To this end, for a given first channel module and a given second channel module in a corresponding relationship, for example Figure 1The first channel module A114 and the second channel module A124 shown, each channel module includes a high-speed data transmitter and a receiver, the two serve as the transmitter and the receiver for each other, the transmitter completes the initialization of the circuit, including the code configuration, the transmission length, the number of transmissions and the transmission interval, and notifies the receiver through the sideband message to prepare for reception; then, the receiver turns on the circuit reception enable, and sets the initial position of the read pointer of each data link to zero, samples the data by using the clock rising and falling edges, and generates the control of the read pointer through the data valid signal, and sends the data corresponding to the read pointer to the code comparator for detection; the code comparator compares the received data with the internally generated code and outputs the detection result; if the data valid signal Keeping it at a low level for a long time means that the transmission is over, otherwise continue to detect; by recording all the code comparison results of this transmission, if all are correct, it means correct reception, so the initial position of the read pointer when it is correctly received can be recorded; if it is incorrect, the receiving end circuit is reset, including resetting the serial-to-parallel conversion circuit and the code comparator, preparing for the next transmission, and adding 1 to the initial position of the read pointer of the data link for reception detection, and repeating the adjustment of the initial position of the read pointer until all data links are correctly received. In this way, the initial position of the read pointer when all data links inside the channel module as the receiving end are recorded when they are correctly received is completed, thereby outputting the initial position configuration of the read pointer of the channel module as the receiving end. In this way, by using the single-ended data link included in the given first channel module as the transmitting end, that is, using the single-ended data link included in the given second channel module as the receiving end, the initial position of the read pointer when the single-ended data link included in the given second channel module is correctly received is obtained; by using the single-ended data link included in the given second channel module as the transmitting end, that is, using the single-ended data link included in the given first channel module as the receiving end, the initial position of the read pointer when the single-ended data link included in the given first channel module is correctly received is obtained. In this way, the first stage of training, that is, the training of internal alignment of the channel module, is completed, and the initial position configuration of the read pointer of the given first channel module and the initial position configuration of the read pointer of the given second channel module are obtained. In this way, the first channel module and the second channel module in a corresponding relationship are first used to cooperate with each other to complete the internal alignment of the channel module, and the initial position configuration of the read pointer of each of the at least one first channel module and the initial position configuration of the read pointer of each of the at least one second channel module are obtained, which is conducive to reducing the complexity of the control logic, simplifying the training of data link alignment, and improving the response speed.

[0036] In some embodiments, utilizing the entirety of the at least one first channel module and the entirety of the at least one second channel module to cooperate with each other to complete alignment between the channel modules includes: utilizing the entirety of the at least one first channel module as a transmitting end to simultaneously transmit a code pattern having a fixed length, and utilizing the entirety of the at least one second channel module as a receiving end to output a respective received data valid signal of the at least one second channel module, and then utilizing the latest received data valid signal among the respective received data valid signals of the at least one second channel module as a reference to obtain a compensation calculation result, and utilizing the compensation calculation result to update the respective initial position configuration of a read pointer of the at least one second channel module; utilizing the entirety of the at least one second channel module as a transmitting end to simultaneously transmit a code pattern having the fixed length, and utilizing the entirety of the at least one first channel module as a receiving end to output a respective received data valid signal of the at least one first channel module, and then utilizing the latest received data valid signal among the respective received data valid signals of the at least one first channel module as a reference to obtain a compensation calculation result, and utilizing the compensation calculation result to update the respective initial position configuration of a read pointer of the at least one first channel module. The second stage of training is the training of alignment between channel modules. This is after the first stage, which is the training of alignment within the module, is completed. Therefore, this means that the output within a single channel module is aligned, but the data outputs of multiple channel modules on the same physical layer may be misaligned at the boundary. Here, the entirety of the at least one first channel module is used as the transmitting end to simultaneously send a code type with a fixed length, which is then parsed by the entirety of the at least one second channel module on the other end as the receiving end. After the serial-to-parallel conversion process is completed, each channel module on the receiving side outputs parallel data and the corresponding received data valid signal. By detecting the alignment status of the received data valid signals output by each of the multiple channel modules, the deviation between these received data valid signals can be determined. Therefore, the latest received data valid signal among the received data valid signals of each of the at least one second channel module is used as a reference to obtain the compensation calculation result. The data of other channel modules can be aligned by adding additional delays, that is, calculating the corresponding compensation values. Figure 1Taking at least one second channel module (second channel module A124, second channel module B126, second channel module C128) as an example, assuming that the received data valid signal of the second channel module A124 arrives two clock cycles earlier than the received data valid signal of the second channel module C128, this means that the serial-to-parallel conversion unit of the second channel module A124 needs to delay two clock cycles when reading data later, and this deviation value can be compensated to the read pointer control unit. In this way, the latest received data valid signal among the received data valid signals of the at least one second channel module is used as a reference to obtain the compensation calculation result, and the initial position configuration of the read pointer of the at least one second channel module is updated using the compensation calculation result, so as to realize the updating of the initial position configuration of the read pointer of the at least one second channel module through deviation value compensation and read pointer control, thereby realizing compensation at the receiving level to offset the influence caused by the boundary misalignment factor. In contrast, the entirety of at least one second channel module is used as the transmitting end, and then the entirety of at least one first channel module of the opposite end is used as the receiving end for parsing, and finally the initial position configuration of the read pointer of each of the at least one first channel modules is updated through deviation value compensation and read pointer control, thereby achieving compensation at the receiving level to offset the impact of the boundary misalignment factor. In this way, through modular design and splicing, the bandwidth that meets user needs is quickly achieved, and the increase in physical layer area caused by the increase in bandwidth demand can be flexibly adapted, maintaining interconnection performance, reducing the complexity of control logic, simplifying data link alignment training, and improving response speed.

[0037] In some embodiments, the given first channel module is any first channel module of the at least one first channel module. In this way, through modular design and splicing, the bandwidth that meets user needs is quickly achieved, and the increase in physical layer area caused by the increase in bandwidth demand can be flexibly adapted, the interconnection performance is maintained, the complexity of the control logic is reduced, the training of data link alignment is simplified, and the response speed is improved.

[0038] In some embodiments, the initial position of the read pointer when the single-ended data link included in the given second channel module is correctly received is determined by adding one initial position of the read pointer until the pattern comparison result is correct. In this way, pattern comparison and pattern matching can be used to detect whether it is correctly received to determine the initial position of the read pointer, and the required training pattern can be generated by the pattern generator. The corresponding pattern can also be used in combination with the communication protocol, usage scenario, etc., such as special characters.

[0039] In some embodiments, the compensation calculation result includes the deviation value compensation of the second channel module corresponding to other received data valid signals other than the latest received data valid signal in the received data valid signals of the at least one second channel module calculated by taking the latest received data valid signal as the reference. In this way, the initial position configuration of the read pointer of each of the at least one second channel module is updated through the deviation value compensation and the read pointer control, thereby achieving compensation at the receiving level to offset the influence caused by the boundary misalignment factor.

[0040] In some embodiments, using the compensation calculation result to update the initial position configuration of the read pointer of each of the at least one first channel module includes, based on the deviation value compensation, delaying the initial position of the read pointer of the second channel module corresponding to other received data valid signals except the latest received data valid signal in the received data valid signals of each of the at least one second channel module. In this way, the initial position configuration of the read pointer of each of the at least one second channel module is updated through deviation value compensation and read pointer control, thereby achieving compensation at the receiving level to offset the influence caused by the boundary misalignment factor.

[0041] In a possible implementation, the channel module template includes a data signal transmission channel, a clock signal transmission channel, a valid indication signal transmission channel, a data signal reception channel, a clock signal reception channel, and a valid indication signal reception channel. Here, the data signal transmission channel corresponds to a certain number of data links contained in the channel module, which are used to transmit data payloads, and various suitable encoding methods can be used, and the data from the link layer or the adaptation layer can be mapped to each data link of the data signal transmission channel in bytes, for example, the lowest 8 bits of data are mapped to one data link and the second lowest 8 bits of data are mapped to the next data link. Taking 16 data links as an example, the data bit width from the controller or adapter is 128 bits, so every 16 bits are mapped to a data link, and so on. The clock signal transmission channel can be a clock differential signal, that is, it corresponds to a pair of differential clock channels. The valid indication signal transmission channel is used to provide a valid indication of data transmission. If the valid indication signal transmission channel is high, it indicates that data transmission is in progress. If the valid indication signal transmission channel is pulled low, it indicates that no data has been sent. For data links that send clock signals by sending clock differential signals, the operating frequency can be half or one-quarter of the link rate. When sampling in double-edge mode at double data rate (DDR), the clock frequency is half of the link frequency. When sampling in quad data rate (QDR), the clock frequency is one-quarter of the link frequency. The sending clock can work in continuous mode or burst mode. In continuous mode, the clock always maintains a flipping state, while in burst mode, the clock flips only when there is data to send. For the receiving direction, the descriptions of the receiving data signal channel, the receiving clock signal channel, and the receiving valid indication signal channel correspond to the sending direction. The pins in the receiving direction correspond to the pins in the sending direction one-to-one, and the sending data from the opposite end physical layer maintains a one-to-one connection relationship.

[0042] In a possible implementation, the channel module template includes a data transmission unit, which includes a training unit, a pattern generator, a multiplexer, a delay unit, a parallel-to-serial conversion unit, and a high-speed analog transmission unit. Here, the training unit is used to control the pattern generator to generate the required training pattern. The pattern generator is used to generate various patterns required for training, and the length and number of transmissions of the pattern are configurable. The multiplexer is used to complete the selection between the parallel data bus and the training pattern. The delay unit is used to complete the delay training of the internal input and output of the physical layer, including providing the data delay of the link, responsible for generating the transmission interval level delay and the higher precision sub-transmission interval level delay, thereby providing the transmission interval level delay adjustment. The parallel-to-serial conversion unit is used for parallel-to-serial conversion of data, converting the parallel input data under the low-speed clock to the serial signal under the high-speed clock. The high-speed analog transmission unit is used to convert the high-speed signal in the digital domain into an analog signal, and has a corresponding driving circuit and a pre-emphasis and bias circuit inside. For the data flow in the sending direction, the first is the configuration bus, which is generally configured or obtained in the form of registers. The other is the data bus. For the data link for sending data, for example, an 8-bit wide data bus and the corresponding data valid signal can be used. When in the physical layer initialization phase, the training process is completed by selecting the data generated by the internal pattern generator through the configuration bus, and in the normal working phase of the physical layer, it is switched to the input data bus. In this way, the channel module under the same physical layer is instantiated according to the same channel module template, and the number of single-ended data links of the obtained channel module instance can be flexibly determined by adjusting the instantiation parameters, so that the communication protocol and the bandwidth requirements of the use scenario and the customer customization requirements can be flexibly adapted. At the same time, the physical layer modular design method of the core interface circuit is provided by multiplexing the channel module template, simplifying the design complexity and improving the response speed. In this way, through modular design and splicing, the bandwidth that meets the user's needs is quickly realized, and the increase in the physical layer area caused by the increase in bandwidth requirements can be flexibly adapted, the interconnection performance is maintained, the complexity of the control logic is reduced, the training of data link alignment is simplified, and the response speed is improved.

[0043] In a possible implementation, the channel module template includes a data receiving unit, which includes a training unit, a pattern comparator, a multiplexer, a read pointer control unit, a serial-to-parallel conversion unit, and a high-speed analog receiving unit. The training unit is used to determine the optimal delay parameter by comparing the detection results, and feed back the training results to the opposite end sending side through the sideband or out-of-band signal to complete the training process. The pattern comparator is used to check whether the received data is consistent with the pattern generated locally, and send the detection result to the training unit. The multiplexer is used to receive the distribution of data. In the training scenario, the received data is sent to the pattern comparator for inspection, and in the normal working mode, it is transmitted to the controller or the adaptation layer through the data bus. The read pointer control unit is used to generate the required read pointer through the effective signal or the frame header signal of the accompanying path, in conjunction with the offset control configured by the software. The serial-to-parallel conversion unit is used to sample the data through the high-speed accompanying path clock sent from the opposite end, write it into the serial-to-parallel conversion unit, and take out the parallel data of the corresponding address bit through the low-speed clock and the read pointer at the other end to complete the serial-to-parallel conversion of the data. The high-speed analog receiving unit is used to realize the conversion from analog signals to digital signals. It has a variable gain amplifier and a feedback decision equalizer (DFE) circuit inside. In this way, the channel module under the same physical layer is instantiated according to the same channel module template. The number of single-ended data links of the obtained channel module instance can be flexibly determined by adjusting the instantiation parameters. In this way, the bandwidth requirements of the communication protocol and the usage scenario as well as the customer customization requirements can be flexibly adapted. At the same time, the physical layer modular design method of the core interface circuit is provided by multiplexing the channel module template, simplifying the design complexity and improving the response speed. In this way, through modular design and splicing, the bandwidth that meets the user's needs is quickly achieved, and the increase in the physical layer area caused by the increase in bandwidth requirements can be flexibly adapted, the interconnection performance is maintained, the complexity of the control logic is reduced, the training of data link alignment is simplified, and the response speed is improved.

[0044] In a possible implementation, the number of single-ended data links included in each of the at least one first channel module corresponds to the data bandwidth of the first channel module, thereby achieving flexible adaptation to scalable bandwidth requirements.

[0045] In a possible implementation, the alignment between the channel modules is achieved by an alignment circuit between the first channel modules and an alignment circuit between the second channel modules, wherein the alignment circuit between the first channel modules is located in the first physical layer and is independent of the at least one first channel module, and the alignment circuit between the second channel modules is located in the second physical layer and is independent of the at least one second channel module. In this way, the channel modules under the same physical layer are instantiated according to the same channel module template, and the number of single-ended data links of the obtained channel module instance can be flexibly determined by adjusting the instantiation parameters, so that the bandwidth requirements of the communication protocol and the usage scenario as well as the customer customization requirements can be flexibly adapted. At the same time, a physical layer modular design method for the core interface circuit is provided by reusing the channel module template, and the alignment circuit between the channel modules independent of the channel module is used to simplify the design complexity and improve the response speed.

[0046] In a possible implementation, the chiplet interface circuit is used for physical layer interconnection of parallel single-ended signals, or for physical layer interconnection of serial differential signals. In this way, the bandwidth requirements of communication protocols and usage scenarios as well as customer customization requirements can be flexibly adapted.

[0047] Figure 2 A schematic diagram of a data sending unit provided in an embodiment of the present application. Figure 2 As shown, the data transmission unit 200 includes a training unit A202, a pattern generator 204, a multiplexer 206, a delay unit 208, a parallel-to-serial conversion unit 210, and a high-speed analog transmission unit 212. The training unit A202 is used to control the pattern generator to generate the required training pattern. The pattern generator 204 is used to generate various patterns required for training, and the length and number of transmission times of the pattern are configurable. The multiplexer 206 is used to complete the selection between the parallel data bus A207 and the training pattern, and connect the data bus A207 and the pattern generator 204. The delay unit 208 is used to complete the delay training of the internal input and output of the physical layer, including providing the data delay of the link, responsible for generating the transmission interval level delay and the higher precision sub-transmission interval level delay, thereby providing the delay adjustment of the transmission interval level. The parallel-to-serial conversion unit 210 is used for the parallel-to-serial conversion of data, converting the parallel input data under the low-speed clock into the serial signal under the high-speed clock, and the receiving system clock A211 is used for conversion. The high-speed analog transmission unit 212 is used to convert the high-speed signal in the digital domain into an analog signal, and has a corresponding driving circuit as well as a pre-emphasis and bias circuit inside.

[0048] In this way, the channel module under the same physical layer can be instantiated according to the same channel module template. The number of single-ended data links of the obtained channel module instance can be flexibly determined by adjusting the instantiation parameters. This can flexibly adapt to the bandwidth requirements of the communication protocol and usage scenarios as well as customer customization requirements. At the same time, the physical layer modular design method of the core interface circuit is provided by reusing the channel module template, which simplifies the design complexity and improves the response speed. In this way, through modular design and splicing, the bandwidth that meets the user's needs is quickly achieved, and the increase in physical layer area caused by the increase in bandwidth requirements can be flexibly adapted, maintaining the interconnection performance, reducing the complexity of the control logic, simplifying the training of data link alignment, and improving the response speed.

[0049] Figure 3 A schematic diagram of a data receiving unit provided in an embodiment of the present application. Figure 3 As shown, the data receiving unit 300 includes a training unit B302, a code comparator 304, a multiplexer 306, a read pointer control unit 308, a serial-to-parallel conversion unit 310, and a high-speed analog receiving unit 312. The training unit B302 is used to determine the optimal delay parameter by comparing the detection results, and feed back the training results to the opposite end sending side through the sideband or out-of-band signal to complete the training process. The code comparator 304 is used to check whether the received data is consistent with the locally generated code type, and send the detection result to the training unit B302. The multiplexer 306 is used to distribute the received data. In the training scenario, the received data is sent to the code comparator 304 for inspection, and in the normal working mode, it is transmitted to the controller or the adaptation layer through the data bus B307. The read pointer control unit 308 is used to generate the required read pointer through the effective signal or the frame header signal of the accompanying channel, in conjunction with the offset control configured by the software. The serial-to-parallel conversion unit 310 is used to sample the data through the high-speed accompanying clock sent from the other end, write it into the serial-to-parallel conversion unit 310, and take out the parallel data of the corresponding address bit through the low-speed clock and the read pointer at the other end to complete the serial-to-parallel conversion of the data, and receive the system clock B311 for conversion. The high-speed analog receiving unit 312 is used to realize the conversion from analog signal to digital signal, and has a variable gain amplifier and a feedback decision equalizer (DFE) circuit inside.

[0050] In this way, the channel module under the same physical layer can be instantiated according to the same channel module template. The number of single-ended data links of the obtained channel module instance can be flexibly determined by adjusting the instantiation parameters. This can flexibly adapt to the bandwidth requirements of the communication protocol and usage scenarios as well as customer customization requirements. At the same time, the physical layer modular design method of the core interface circuit is provided by reusing the channel module template, which simplifies the design complexity and improves the response speed. In this way, through modular design and splicing, the bandwidth that meets the user's needs is quickly achieved, and the increase in physical layer area caused by the increase in bandwidth requirements can be flexibly adapted, maintaining the interconnection performance, reducing the complexity of the control logic, simplifying the training of data link alignment, and improving the response speed.

[0051] Figure 4 The following is a flow chart of a method for instantiating a chip interface circuit provided in an embodiment of the present application. Figure 4 As shown, the instantiation method includes: step S410: determining a channel module template; step S420: using the channel module template, instantiating at least one first channel module included in the first physical layer of the first core particle, and instantiating at least one second channel module included in the second physical layer of the second core particle. The first core particle and the second core particle are interconnected through a core particle interface circuit, the core particle interface circuit includes the first physical layer and the second physical layer, the at least one first channel module corresponds to the at least one second channel module one by one, the number of single-ended data links included in each first channel module in the at least one first channel module is equal to the number of single-ended data links included in the second channel module corresponding to the first channel module in the at least one second channel module, and the alignment of the core particle interface circuit includes: first using the corresponding first channel module and the second channel module to cooperate with each other to complete the internal alignment of the channel module, and then using the whole of the at least one first channel module and the whole of the at least one second channel module to cooperate with each other to complete the alignment between the channel modules.

[0052] In this way, through modular design and splicing, the bandwidth that meets user needs is quickly achieved, and the increase in physical layer area caused by the increase in bandwidth demand can be flexibly adapted, maintaining interconnection performance, reducing the complexity of control logic, simplifying data link alignment training, and improving response speed.

[0053] Figure 5A flow chart of an alignment method for a core grain interface circuit provided in an embodiment of the present application. The core grain interface circuit is used for interconnection between a first core grain and a second core grain, the first core grain includes a first physical layer, the first physical layer includes at least one first channel module instantiated according to a channel module template, the second core grain includes a second physical layer, the second physical layer includes at least one second channel module instantiated according to the channel module template, the at least one first channel module corresponds to the at least one second channel module one-to-one, and the number of single-ended data links included in each first channel module in the at least one first channel module is equal to the number of single-ended data links included in the second channel module corresponding to the first channel module in the at least one second channel module. Figure 5 As shown, the alignment method includes step S510: utilizing the first channel module and the second channel module in a corresponding relationship to cooperate with each other to complete the internal alignment of the channel module; step S520: utilizing the entirety of at least one first channel module and the entirety of at least one second channel module to cooperate with each other to complete the alignment between the channel modules.

[0054] In this way, through modular design and splicing, the bandwidth that meets user needs is quickly achieved, and the increase in physical layer area caused by the increase in bandwidth demand can be flexibly adapted, maintaining interconnection performance, reducing the complexity of control logic, simplifying data link alignment training, and improving response speed.

[0055] In a possible implementation, a given first channel module in the at least one first channel module is in a corresponding relationship with a given second channel module in the at least one second channel module, and the given first channel module and the given second channel module are used to cooperate with each other to complete the internal alignment of the channel module, including: using the single-ended data link included in the given first channel module as the sending end, recording the initial position of the read pointer when the single-ended data link included in the given second channel module is correctly received, thereby obtaining the initial position configuration of the read pointer of the given second channel module; using the single-ended data link included in the given second channel module as the sending end, recording the initial position of the read pointer when the single-ended data link included in the given first channel module is correctly received, thereby obtaining the initial position configuration of the read pointer of the given first channel module. In this way, the first channel module and the second channel module in a corresponding relationship are first used to cooperate with each other to complete the internal alignment of the channel module, and the initial position configuration of the read pointer of each of the at least one first channel module and the initial position configuration of the read pointer of each of the at least one second channel module are obtained, which is conducive to reducing the complexity of the control logic, simplifying the training of data link alignment, and improving the response speed.

[0056] In some embodiments, utilizing the entirety of the at least one first channel module and the entirety of the at least one second channel module to cooperate with each other to complete alignment between the channel modules includes: utilizing the entirety of the at least one first channel module as a transmitting end to simultaneously transmit a code pattern having a fixed length, and utilizing the entirety of the at least one second channel module as a receiving end to output a respective received data valid signal of the at least one second channel module, and then utilizing the latest received data valid signal among the respective received data valid signals of the at least one second channel module as a reference to obtain a compensation calculation result, and utilizing the compensation calculation result to update the respective initial position configuration of a read pointer of the at least one second channel module; utilizing the entirety of the at least one second channel module as a transmitting end to simultaneously transmit a code pattern having the fixed length, and utilizing the entirety of the at least one first channel module as a receiving end to output a respective received data valid signal of the at least one first channel module, and then utilizing the latest received data valid signal among the respective received data valid signals of the at least one first channel module as a reference to obtain a compensation calculation result, and utilizing the compensation calculation result to update the respective initial position configuration of a read pointer of the at least one first channel module. In this way, through modular design and splicing, the bandwidth that meets user needs is quickly achieved, and the increase in physical layer area caused by the increase in bandwidth demand can be flexibly adapted, maintaining interconnection performance, reducing the complexity of control logic, simplifying data link alignment training, and improving response speed.

[0057] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0058] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0059] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A chip interface circuit, characterized in that: The core grain interface circuit is used for interconnection between a first core grain and a second core grain, the first core grain includes a first physical layer, the first physical layer includes at least one first channel module instantiated according to a channel module template, the second core grain includes a second physical layer, the second physical layer includes at least one second channel module instantiated according to the channel module template, the at least one first channel module corresponds to the at least one second channel module one by one, the number of single-ended data links included in each first channel module in the at least one first channel module is equal to the number of single-ended data links included in the second channel module corresponding to the first channel module in the at least one second channel module, and the alignment of the core grain interface circuit includes: firstly using the corresponding first channel module and the second channel module to cooperate with each other to complete the internal alignment of the channel module, and then using the whole of the at least one first channel module and the whole of the at least one second channel module to cooperate with each other to complete the alignment between the channel modules, A given first channel module in the at least one first channel module corresponds to a given second channel module in the at least one second channel module, and the given first channel module and the given second channel module cooperate with each other to complete the internal alignment of the channel modules, including: Using the single-ended data link included in the given first channel module as the sending end, recording the initial position of the read pointer when each of the single-ended data links included in the given second channel module is correctly received, thereby obtaining the initial position configuration of the read pointer of the given second channel module; Using the single-ended data link included in the given second channel module as the sending end, recording the initial position of the read pointer when each of the single-ended data links included in the given first channel module is correctly received, thereby obtaining the initial position configuration of the read pointer of the given first channel module, Utilizing the entirety of the at least one first channel module and the entirety of the at least one second channel module to cooperate with each other so as to complete the alignment between the channel modules, comprising: Using the entirety of the at least one first channel module as a transmitting end, simultaneously transmitting a code pattern having a fixed length, and using the entirety of the at least one second channel module as a receiving end, outputting a respective received data valid signal of the at least one second channel module, and then using the latest received data valid signal among the respective received data valid signals of the at least one second channel module as a reference to obtain a compensation calculation result, and using the compensation calculation result to update the respective read pointer initial position configuration of the at least one second channel module; The at least one second channel module as a whole is used as a transmitting end to simultaneously transmit a code type having the fixed length, and the at least one first channel module as a whole is used as a receiving end to output a received data valid signal of each of the at least one first channel modules, and then the latest received data valid signal among the received data valid signals of each of the at least one first channel modules is used as a reference to obtain a compensation calculation result, and the initial position configuration of the read pointer of each of the at least one first channel modules is updated using the compensation calculation result.

2. The chip interface circuit according to claim 1, characterized in that: The given first channel module is any first channel module among the at least one first channel module.

3. The chip interface circuit according to claim 1, characterized in that: The initial position of the read pointer when each of the single-ended data links included in the given second channel module is correctly received is determined by adding one initial position of the read pointer until the code pattern comparison result is correct.

4. The chip interface circuit according to claim 1, characterized in that: The compensation calculation result includes the deviation value compensation of the second channel module corresponding to other received data valid signals except the latest received data valid signal in the received data valid signals of the at least one second channel module calculated based on the latest received data valid signal.

5. The chip interface circuit according to claim 4, characterized in that: The compensation calculation result is used to update the initial position configuration of the read pointer of each of the at least one first channel modules, including, based on the deviation value compensation, delaying the initial position of the read pointer of the second channel module corresponding to other received data valid signals among the received data valid signals of the at least one second channel module except for the latest received data valid signal.

6. The chip interface circuit according to claim 1, characterized in that: The channel module template includes a sending data signal channel, a sending clock signal channel, a sending valid indication signal channel, a receiving data signal channel, a receiving clock signal channel, and a receiving valid indication signal channel.

7. The chip interface circuit according to claim 1, characterized in that: The channel module template comprises a data sending unit, and the data sending unit comprises a training unit, a pattern generator, a multiplexer, a delay unit, a parallel-serial conversion unit, and a high-speed analog sending unit.

8. The chip interface circuit according to claim 1, characterized in that: The channel module template comprises a data receiving unit, and the data receiving unit comprises a training unit, a code type comparator, a multiplexer, a read pointer control unit, a serial-to-parallel conversion unit, and a high-speed analog receiving unit.

9. The chip interface circuit according to claim 1, characterized in that: The number of single-ended data links included in each of the at least one first channel module corresponds to the data bandwidth of the first channel module.

10. The chip interface circuit according to claim 1, characterized in that: The alignment between the channel modules is achieved by an alignment circuit between the first channel modules and an alignment circuit between the second channel modules. The alignment circuit between the first channel modules is located in the first physical layer and is independent of the at least one first channel module, and the alignment circuit between the second channel modules is located in the second physical layer and is independent of the at least one second channel module.

11. The chip interface circuit according to claim 1, characterized in that: The chip interface circuit is used for physical layer interconnection of parallel single-ended signals, or for physical layer interconnection of serial differential signals.

12. A method for instantiating a chiplet interface circuit, characterized in that: The instantiation method includes: Using a channel module template, instantiate at least one first channel module included in a first physical layer of a first core particle, and instantiate at least one second channel module included in a second physical layer of a second core particle, wherein the first core particle and the second core particle are interconnected via a core particle interface circuit, the core particle interface circuit includes the first physical layer and the second physical layer, the at least one first channel module corresponds to the at least one second channel module one by one, the number of single-ended data links included in each first channel module in the at least one first channel module is equal to the number of single-ended data links included in the second channel module corresponding to the first channel module in the at least one second channel module, and alignment of the core particle interface circuit includes: firstly utilizing the corresponding first channel module and the second channel module to cooperate with each other so as to complete internal alignment of the channel modules, and then utilizing the entirety of the at least one first channel module and the entirety of the at least one second channel module to cooperate with each other so as to complete alignment between the channel modules, A given first channel module in the at least one first channel module corresponds to a given second channel module in the at least one second channel module, and the given first channel module and the given second channel module cooperate with each other to complete the internal alignment of the channel modules, including: Using the single-ended data link included in the given first channel module as the sending end, recording the initial position of the read pointer when each of the single-ended data links included in the given second channel module is correctly received, thereby obtaining the initial position configuration of the read pointer of the given second channel module; Using the single-ended data link included in the given second channel module as the sending end, recording the initial position of the read pointer when each of the single-ended data links included in the given first channel module is correctly received, thereby obtaining the initial position configuration of the read pointer of the given first channel module, Utilizing the entirety of the at least one first channel module and the entirety of the at least one second channel module to cooperate with each other so as to complete the alignment between the channel modules, comprising: Using the entirety of the at least one first channel module as a transmitting end, simultaneously transmitting a code pattern having a fixed length, and using the entirety of the at least one second channel module as a receiving end, outputting a respective received data valid signal of the at least one second channel module, and then using the latest received data valid signal among the respective received data valid signals of the at least one second channel module as a reference to obtain a compensation calculation result, and using the compensation calculation result to update the respective read pointer initial position configuration of the at least one second channel module; The at least one second channel module as a whole is used as a transmitting end to simultaneously transmit a code type having the fixed length, and the at least one first channel module as a whole is used as a receiving end to output a received data valid signal of each of the at least one first channel modules, and then the latest received data valid signal among the received data valid signals of each of the at least one first channel modules is used as a reference to obtain a compensation calculation result, and the initial position configuration of the read pointer of each of the at least one first channel modules is updated using the compensation calculation result.

13. A method for aligning a chip interface circuit, characterized in that: The core grain interface circuit is used for interconnection between a first core grain and a second core grain, the first core grain includes a first physical layer, the first physical layer includes at least one first channel module instantiated according to a channel module template, the second core grain includes a second physical layer, the second physical layer includes at least one second channel module instantiated according to the channel module template, the at least one first channel module corresponds to the at least one second channel module in a one-to-one manner, the number of single-ended data links included in each first channel module in the at least one first channel module is equal to the number of single-ended data links included in the second channel module corresponding to the first channel module in the at least one second channel module, and the alignment method includes: First, the first channel module and the second channel module in a corresponding relationship cooperate with each other to complete the internal alignment of the channel modules, and then, the entirety of at least one first channel module and the entirety of at least one second channel module cooperate with each other to complete the alignment between the channel modules. A given first channel module in the at least one first channel module corresponds to a given second channel module in the at least one second channel module, and the given first channel module and the given second channel module cooperate with each other to complete the internal alignment of the channel modules, including: Using the single-ended data link included in the given first channel module as the sending end, recording the initial position of the read pointer when each of the single-ended data links included in the given second channel module is correctly received, thereby obtaining the initial position configuration of the read pointer of the given second channel module; Using the single-ended data link included in the given second channel module as the sending end, recording the initial position of the read pointer when each of the single-ended data links included in the given first channel module is correctly received, thereby obtaining the initial position configuration of the read pointer of the given first channel module, Utilizing the entirety of the at least one first channel module and the entirety of the at least one second channel module to cooperate with each other so as to complete the alignment between the channel modules, comprising: Using the entirety of the at least one first channel module as a transmitting end, simultaneously transmitting a code pattern having a fixed length, and using the entirety of the at least one second channel module as a receiving end, outputting a respective received data valid signal of the at least one second channel module, and then using the latest received data valid signal among the respective received data valid signals of the at least one second channel module as a reference to obtain a compensation calculation result, and using the compensation calculation result to update the respective read pointer initial position configuration of the at least one second channel module; The at least one second channel module as a whole is used as a transmitting end to simultaneously transmit a code type having the fixed length, and the at least one first channel module as a whole is used as a receiving end to output a received data valid signal of each of the at least one first channel modules, and then the latest received data valid signal among the received data valid signals of each of the at least one first channel modules is used as a reference to obtain a compensation calculation result, and the initial position configuration of the read pointer of each of the at least one first channel modules is updated using the compensation calculation result.

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