Electron source structure and manufacturing method

Abstract

The present invention provides an electron source structure and manufacturing method, comprising: providing a first substrate, on which a first porous layer and a second porous layer are stacked; forming a back gate layer on the second porous layer; providing a second substrate, bonding the back gate layer to the second substrate; peeling off the first porous layer to remove the first substrate; etching the second porous layer to form a groove, filling the groove with an insulating dielectric layer, and forming a top electrode and a back electrode, the top electrode being electrically connected to the second porous layer, and the back electrode penetrating the insulating dielectric layer and electrically connected to the back gate layer. The present invention utilizes the first porous layer to facilitate the transfer of the second porous layer, which serves as the active layer, thereby effectively improving the transfer success rate of the active layer. Furthermore, by transferring the active layer through the first porous layer, the flexibility of the substrate is enhanced, allowing for flexible selection of the substrate's material type, structure type, and functional type, thereby enhancing the integration flexibility of the electron source with other auxiliary functional systems, such as CMOS systems and MEMS systems.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to an electron source structure and a manufacturing method. Background Art

[0002] With the development of the semiconductor micro-fabrication industry, the requirements for electron beam direct writing technology are becoming increasingly higher. For example, ensuring the accuracy of fine graphics imaging and improving the direct writing speed are required. The imaging of high-tech node graphics requires not only finer and more accurate direct writing, but also high-speed direct writing when the amount of graphic data increases dramatically. From the perspective of accurate direct writing of fine graphics, the electron beam spot needs to be smaller to facilitate precise scanning. When the current density remains unchanged, reducing the electron beam spot means reducing the current of the electron beam, which results in a longer direct writing time. In order to improve the production capacity of electron beam direct writing equipment per unit time, a multi-electron beam direct writing machine that uses multiple electron beams to write simultaneously has become a necessary tool. The number of direct writing electron beams in a multi-electron beam direct writing machine needs to be around hundreds of thousands.

[0003] Based on porous silicon materials, electron sources with high current density, high current collimation and concentrated electron energy can be prepared, and they can be processed into dense electron source arrays for multi-electron beam direct writing. When forming a multi-beam electron source array, the following considerations need to be considered: 1) The electron source array requires an external CMOS control circuit to provide a driving signal. In order to reduce signal delay and increase the direct writing rate, it is necessary to package and interconnect it with the CMOS circuit. When preparing the electron source array, the feasibility of its packaging with the CMOS circuit needs to be considered; 2) For electron sources in different areas of the array, the movement path of the electrons emitted by them in the direct writing device is related to the position. Under normal circumstances, it is necessary to apply targeted control signals, bias voltages, etc. to the electron sources in different positions to adjust the electron initial velocity, electron beam current intensity, etc., to correct the imaging deviation caused by the position of the electron source and improve the final electron beam direct writing effect.

[0004] In the existing technology, in order to integrate porous silicon electron source devices with CMOS, it is necessary to first prepare a porous silicon electron source array on an SOI substrate, then realize the back electrode extraction through silicon via technology, and finally bond it to the CMOS control chip. This method has a relatively complex process flow and is difficult to process: 1) It is difficult to prepare porous silicon materials on SOI substrates; 2) When preparing through-holes on the back of the SOI substrate, they need to be aligned with the top device; 3) The process flow uses through-silicon vias, and the diameter of the through-holes passing through the silicon substrate is relatively large (for example, >5μm), which limits the integration density of the electron source array.

[0005] Therefore, how to provide an electron source structure and a manufacturing method to improve process flexibility and reduce process difficulty has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide an electron source structure and a manufacturing method for solving the problems of the prior art in that the process flow is relatively complicated and the process is difficult when preparing the electron source.

[0007] To achieve the above-mentioned and other related purposes, the present invention provides a method for manufacturing an electron source structure, comprising the following steps:

[0008] providing a first substrate on which a first porous layer and a second porous layer are stacked;

[0009] forming a back gate layer on a side of the second porous layer away from the first porous layer;

[0010] Providing a second substrate, bonding the back gate layer to the second substrate, with an insulating layer disposed between the back gate layer and the second substrate;

[0011] peeling off the first porous layer to remove the first substrate, and removing the first porous layer remaining on the second porous layer;

[0012] The second porous layer is etched to form a groove that penetrates the first porous layer, the groove is filled with an insulating dielectric layer, and a top electrode and a back electrode are formed on the side of the second porous layer away from the second substrate, the top electrode is electrically connected to the second porous layer, and the back electrode penetrates the insulating dielectric layer and is electrically connected to the back gate layer.

[0013] Optionally, a portion of the grooves penetrate the first porous layer and the back gate layer, so as to isolate the back gate layer into a plurality of back gate layer units.

[0014] Optionally, the first porous layer comprises a porous silicon layer, and the second porous layer comprises a porous silicon layer.

[0015] Optionally, the back gate layer comprises a heavily doped polycrystalline layer with a doping concentration not less than 1E18 / cm 3 .

[0016] Optionally, the second substrate includes a semiconductor wafer, a glass substrate, a metal substrate, a composite substrate or a substrate containing a functional module.

[0017] The present invention also provides an electron source structure, comprising:

[0018] a second substrate;

[0019] an insulating layer, located on the second substrate;

[0020] a back gate layer, located on the insulating layer;

[0021] a second porous layer, located on the back gate layer;

[0022] a plurality of grooves, wherein the grooves penetrate the second porous layer;

[0023] an insulating dielectric layer, located in the groove;

[0024] a top electrode, located on the second porous layer and electrically connected to the second porous layer;

[0025] A back electrode is located in the insulating dielectric layer, and the back electrode penetrates the insulating dielectric layer and is electrically connected to the back gate layer.

[0026] Optionally, a portion of the grooves penetrate the first porous layer and the back gate layer, so as to isolate the back gate layer into a plurality of back gate layer units.

[0027] Optionally, the second porous layer comprises a porous silicon layer.

[0028] Optionally, the back gate layer comprises a heavily doped polysilicon layer with a doping concentration not less than 1E18 / cm 3 .

[0029] Optionally, the second substrate includes a semiconductor wafer, a glass substrate, a metal substrate, a composite substrate or a substrate containing a functional module.

[0030] As described above, in the electron source structure and manufacturing method of the present invention, the first porous layer is cracked to assist in the transfer of the second porous layer serving as the active layer, thereby effectively improving the transfer success rate of the active layer; and, by transferring the active layer through the cracking of the first porous layer, the flexibility of the substrate solution is improved, and the material type, structure type, and function type of the substrate can be flexibly selected, thereby improving the integration flexibility of the electron source with other auxiliary functional systems such as CMOS systems and MEMS systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Shown is a process flow chart of the method for manufacturing the electron source structure of the present invention.

[0032] Figure 2 It is a schematic diagram showing a first substrate provided in the method for manufacturing the electron source structure of the present invention.

[0033] Figure 3 It is a schematic diagram showing the formation of a back gate layer on the second porous layer in the method for manufacturing the electron source structure of the present invention.

[0034] Figure 4 It is a schematic diagram showing the steps of providing a second substrate and bonding a back gate layer and an insulating layer in the method for manufacturing an electron source structure of the present invention.

[0035] Figure 5It is a schematic diagram showing the peeling off of the first porous layer in the method for manufacturing the electron source structure of the present invention.

[0036] Figure 6 It is a schematic diagram showing the removal of the first porous layer remaining on the second porous layer in the method for manufacturing the electron source structure of the present invention.

[0037] Figure 7 It is a schematic diagram showing the formation of a top electrode and a back electrode in the method for manufacturing an electron source structure of the present invention.

[0038] Component number description

[0039] 1. First substrate

[0040] 2. First porous layer

[0041] 3 Second porous layer

[0042] 4 Back gate layer

[0043] 5. Second substrate

[0044] 6 Insulation layer

[0045] 7 Insulation dielectric layer

[0046] 8 Top electrode

[0047] 9 Back electrode

[0048] Steps S1 to S5 DETAILED DESCRIPTION

[0049] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] See also Figures 1 to 7 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0051] Example 1

[0052] This embodiment provides a method for manufacturing an electron source structure. Figure 1 , which is a process flow chart of a method for manufacturing the electron source structure, comprising the following steps:

[0053] S1: providing a first substrate, on which a first porous layer and a second porous layer are stacked;

[0054] S2: forming a back gate layer on a side of the second porous layer away from the first porous layer;

[0055] S3: providing a second substrate, bonding the back gate layer to the second substrate, with an insulating layer disposed between the back gate layer and the second substrate;

[0056] S4: peeling off the first porous layer to remove the first substrate, and removing the first porous layer remaining on the second porous layer;

[0057] S5: Etching the second porous layer to form a groove penetrating the second porous layer, the groove is filled with an insulating dielectric layer, and a top electrode and a back electrode are formed on a side of the second porous layer away from the second substrate, the top electrode is electrically connected to the second porous layer, and the back electrode penetrates the insulating dielectric layer and is electrically connected to the back gate layer.

[0058] First, see Figure 2 , performing step S1: providing a first substrate 1 , on which a first porous layer 2 and a second porous layer 3 are stacked.

[0059] As an example, the first substrate 1 includes a semiconductor wafer, a glass substrate, a metal substrate, a composite substrate, or any other suitable substrate. The first porous layer 2 is a porous silicon layer, and the second porous layer 3 is a porous silicon layer. The first porous layer 2 is in contact with the first substrate 1, and the second porous layer 3 is located on a side of the first porous layer 2 away from the first substrate 1.

[0060] As an example, the porosity of the first porous layer 2 is greater than the porosity of the second porous layer 3 , so as to facilitate the subsequent peeling and cracking of the first porous layer 2 .

[0061] Next, see Figure 3 , executing step S2 : forming a back gate layer 4 on a side of the second porous layer 3 away from the first porous layer 2 .

[0062] As an example, the back gate layer 4 is a heavily doped polycrystalline layer, which can be N-type doped or P-type doped, with a doping concentration of not less than 1E18 / cm 3 The back gate layer 4 is a conductive layer and is electrically connected to the second porous layer 3. Preferably, the back gate layer 4 is made of heavily doped polysilicon. In other examples, the back gate layer 4 can also be made of a metal conductive layer, which is not limited to this embodiment.

[0063] As an example, according to requirements, a bonding material layer may be formed on the side of the back gate layer 4 away from the second porous layer 3 .

[0064] Next, see Figure 4 , performing step S3: providing a second substrate 5 , bonding the back gate layer 4 to the second substrate 5 , and providing an insulating layer 6 between the back gate layer 4 and the second substrate 5 .

[0065] As an example, the second substrate 5 includes a semiconductor wafer, a glass substrate, a metal substrate, a composite substrate, a substrate containing a functional module, or other suitable substrates.

[0066] Specifically, in this embodiment, the insulating layer 6 is formed on the second substrate 5, and the back gate layer 4 is bonded to the second substrate 5 through the insulating layer 6; in another example, after the back gate layer 4 is formed, the insulating layer 6 is formed on the side of the back gate layer 4 away from the first substrate 1, and then the second substrate 5 is provided, and the back gate layer 4 is bonded to the second substrate 5 through the insulating layer 6.

[0067] As an example, the bonding process includes surface activated bonding or high temperature reinforcement bonding, etc. Preferably, in this embodiment, the back gate layer 4 and the insulating layer 6 are bonded using the surface activated bonding process to avoid the high temperature reinforcement process.

[0068] Next, see Figure 5 and Figure 6 , executing step S4: peeling off the first porous layer 2 to remove the first substrate 1 , and removing the first porous layer 2 remaining on the second porous layer 3 .

[0069] As an example, see Figure 5 , peeling along the first porous layer 2 to crack the first porous layer 2 to achieve the transfer of the second porous layer 3.

[0070] As an example, during peeling, a wedge may be inserted to assist in cracking the first porous layer 2 , or water flow or air flow may be used to form damage on the edge of the first porous layer 2 to assist in cracking.

[0071] As an example, see Figure 6 , the first porous layer 2 remaining on the second porous layer 3 is removed by etching, chemical mechanical polishing, corrosion or other appropriate methods.

[0072] As an example, the second porous layer 3 serves as an active layer of an electron source structure, for generating and emitting electrons.

[0073] As an example, the second porous layer 3 has a higher specific surface area due to the presence of pores, which can improve the electron emission efficiency.

[0074] Next, see Figure 7 , execute step S5: etch the second porous layer 3 to form a groove penetrating the second porous layer 3, the groove is filled with an insulating dielectric layer 7, and a top electrode 8 and a back electrode 9 are formed on the side of the second porous layer 3 away from the second substrate 5, the top electrode 8 is electrically connected to the second porous layer 3, and the back electrode 9 penetrates the insulating dielectric layer 7 and is electrically connected to the back gate layer 4.

[0075] As an example, there are multiple grooves, and the insulating dielectric layer 7 in the multiple grooves isolates the second porous layer 3 into multiple second porous layer units to form multiple electron emission sources; wherein, the thickness of the top electrode 8 is relatively small, allowing accelerated electrons to pass through the top electrode 8 and be emitted, and the back electrode 9 is used to apply a back bias to the back of the second porous layer 3 to assist in electron acceleration.

[0076] As an example, the back electrode 9 can be a shared back electrode or a plurality of independent back electrodes. For example, a portion of the grooves can be provided to penetrate the second porous layer 3 and the back gate layer 4, so as to isolate the back gate layer 4 into multiple independent back gate regions, each of which leads to the back electrode 9. In an electron source array, the bias voltages applied to electron sources at different emission points are also different. By leading the back electrode 9 to each back gate region, different bias voltages can be applied to electron sources at different locations to meet application requirements.

[0077] As an example, the steps of forming the groove, the insulating dielectric layer 7, the top electrode 8 and the back electrode 9 include:

[0078] (1) forming the groove by etching or other suitable process;

[0079] (2) filling the insulating dielectric layer 7 in the groove using a deposition process;

[0080] (3) forming a back electrode through hole by an etching process or other suitable process;

[0081] (IV) The top electrode 8 and the back electrode 9 are formed by a deposition process. The top electrode 8 and the back electrode 9 can be formed simultaneously or in steps, depending on actual needs.

[0082] As an example, the top electrode 8 is electrically connected to the front surface (upper surface) of the second porous layer 3 , and the back electrode 9 is electrically connected to the back surface (lower surface) of the second porous layer 3 through the back gate layer 4 .

[0083] As an example, by providing the back gate layer 4 below the second porous layer 3 , an electrical interconnection structure can be flexibly developed based on the back gate layer 4 , thereby avoiding a deep through silicon via process, simplifying the process, and reducing costs.

[0084] As an example, porous silicon has weak mechanical strength, which can easily lead to transfer failure. The present invention effectively improves the transfer success rate of the active layer by cracking the first porous layer 2 to assist in the transfer of the second porous layer 3 serving as the active layer; and, by transferring the active layer through the cracking of the first porous layer 2, the flexibility of the substrate solution is improved, and the material type, structure type, and function type of the substrate can be flexibly selected, thereby improving the integration flexibility of the electron source with other auxiliary functional systems such as CMOS systems and MEMS systems.

[0085] At this point, an electron source structure is obtained. Figure 7 The electron source structure includes a second substrate 5, an insulating layer 6, a back gate layer 4, a second porous layer 3, multiple grooves, an insulating dielectric layer 7, a top electrode 8 and a back electrode 9. The insulating layer 6 is located on the second substrate 5, the back gate layer 4 is located on the insulating layer 6, the second porous layer 3 is located on the back gate layer 4, the grooves penetrate the second porous layer 3, the insulating dielectric layer 7 is located in the grooves, the top electrode 8 is located on the second porous layer 3 and is electrically connected to the second porous layer 3, the back electrode 9 is located in the insulating dielectric layer 7, and the back electrode 9 penetrates the insulating dielectric layer 7 and is electrically connected to the back gate layer 4.

[0086] As an example, the second substrate 5 includes a semiconductor wafer, a glass substrate, a metal substrate, a composite substrate, a substrate containing a functional module, or other suitable substrates.

[0087] As an example, the back gate layer 4 is a heavily doped polycrystalline layer, which can be N-type doped or P-type doped, with a doping concentration of not less than 1E18 / cm 3 The back gate layer 4 is a conductive layer and is electrically connected to the second porous layer 3. Preferably, the back gate layer 4 is made of heavily doped polysilicon. In other examples, the back gate layer 4 can also be made of a metal conductive layer, which is not limited to this embodiment.

[0088] As an example, the second porous layer 3 is a porous silicon layer. The second porous layer 3 serves as an active layer of the electron source structure for generating and emitting electrons. The second porous layer 3 has a higher specific surface area due to the presence of pores, which can improve the electron emission efficiency.

[0089] As an example, the insulating dielectric layer 7 in the multiple grooves isolates the second porous layer 3 into multiple second porous layer units to form multiple electron emission sources; wherein, the thickness of the top electrode 8 is relatively small, allowing accelerated electrons to pass through the top electrode 8 and be emitted, and the back electrode 9 is used to apply a back bias to the back of the second porous layer 3 to assist in electron acceleration.

[0090] As an example, the back electrode 9 can be a shared back electrode or a plurality of independent back electrodes. For example, a portion of the grooves can be provided to penetrate the second porous layer 3 and the back gate layer 4, so as to isolate the back gate layer 4 into multiple independent back gate regions, each of which leads to the back electrode 9. In an electron source array, the bias voltages applied to electron sources at different emission points are also different. By leading the back electrode 9 to each back gate region, different bias voltages can be applied to electron sources at different locations to meet application requirements.

[0091] As an example, the top electrode 8 is electrically connected to the front surface (upper surface) of the second porous layer 3 , and the back electrode 9 is electrically connected to the back surface (lower surface) of the second porous layer 3 through the back gate layer 4 .

[0092] In summary, the electron source structure and fabrication method of the present invention utilizes the cleavage of the first porous layer to facilitate the transfer of the second porous layer, which serves as the active layer. This effectively improves the success rate of active layer transfer. Furthermore, transferring the active layer through the cleavage of the first porous layer enhances substrate design flexibility, allowing for flexible selection of substrate material, structure, and functional type, thereby enhancing the integration flexibility of the electron source with other auxiliary functional systems, such as CMOS and MEMS systems. Therefore, the present invention effectively overcomes the shortcomings of existing technologies and possesses high industrial value.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing an electron source structure, characterized in that: The following steps are involved: providing a first substrate on which a first porous layer and a second porous layer are stacked; forming a back gate layer on a side of the second porous layer away from the first porous layer; Providing a second substrate, bonding the back gate layer to the second substrate, with an insulating layer disposed between the back gate layer and the second substrate; peeling off the first porous layer to decompose the first porous layer, thereby removing the first substrate and removing the first porous layer remaining on the second porous layer; The second porous layer is etched to form a groove penetrating the second porous layer, the groove is filled with an insulating dielectric layer, and a top electrode and a back electrode are formed on a side of the second porous layer away from the second substrate, the top electrode is electrically connected to the second porous layer, and the back electrode is electrically connected to the back gate layer through the insulating dielectric layer.

2. The method for manufacturing an electron source structure according to claim 1, wherein: A portion of the grooves penetrates the first porous layer and the back gate layer, so as to isolate the back gate layer into a plurality of back gate layer units.

3. The method for manufacturing an electron source structure according to claim 1, wherein: The first porous layer includes a porous silicon layer, and the second porous layer includes a porous silicon layer.

4. The method for manufacturing an electron source structure according to claim 1, wherein: The back gate layer includes a heavily doped polycrystalline layer with a doping concentration not less than 1E18 / cm 3 .

5. The method for manufacturing an electron source structure according to claim 1, wherein: The second substrate includes a semiconductor wafer, a glass substrate, a metal substrate, a composite substrate or a substrate containing a functional module.

6. An electron source structure, characterized in that: The electron source structure is manufactured by the method for manufacturing an electron source structure according to any one of claims 1 to 5, comprising: a second substrate; an insulating layer, located on the second substrate; a back gate layer, located on the insulating layer; a second porous layer, located on the back gate layer; a plurality of grooves, wherein the grooves penetrate the second porous layer; an insulating dielectric layer, located in the groove; a top electrode, located on the second porous layer and electrically connected to the second porous layer; A back electrode is located in the insulating dielectric layer, and the back electrode penetrates the insulating dielectric layer and is electrically connected to the back gate layer.

7. The electron source structure according to claim 6, characterized in that: A portion of the grooves penetrates the first porous layer and the back gate layer, so as to isolate the back gate layer into a plurality of back gate layer units.

8. The electron source structure according to claim 6, characterized in that: The second porous layer includes a porous silicon layer.

9. The electron source structure according to claim 6, characterized in that: The back gate layer includes a heavily doped polycrystalline layer with a doping concentration not less than 1E18 / cm 3 .

10. The electron source structure according to claim 6, characterized in that: The second substrate includes a semiconductor wafer, a glass substrate, a metal substrate, a composite substrate or a substrate containing a functional module.

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