Method of manufacturing a semiconductor structure

Abstract

Embodiments of the present disclosure provide a method for preparing a semiconductor structure, comprising: providing a substrate having opposite first and second surfaces; forming a first bonding layer on the first surface; implanting hydrogen ions into the substrate on one side of the first surface to form a hydrogen-containing release layer in the substrate; providing a carrier and forming a second bonding layer on a surface of one side of the carrier; fusion bonding the first bonding layer and the second bonding layer; forming a semiconductor device on the second surface of the substrate; and treating the release layer to separate the release layer from the substrate. The method for preparing a semiconductor structure according to embodiments of the present disclosure can improve the layout density of the semiconductor device, improve the electrical performance of the semiconductor device, and avoid damaging the semiconductor device during debonding, thereby improving the yield of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor fabrication technology, and in particular to a method for fabricating a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing, various semiconductor devices are fabricated on the front side of a semiconductor substrate. At this stage, the back side of the semiconductor substrate needs to be temporarily bonded to glass. During bonding, an adhesive layer is used to bond the back side of the semiconductor substrate to the glass. However, the use of an adhesive layer results in a large total thickness variation (TTV), leading to larger linewidths and spacing when fabricating semiconductor devices on the front side. This reduces the layout density and lowers the electrical performance of the semiconductor structure. Furthermore, debonding can easily damage the semiconductor device, further reducing the yield of the semiconductor structure.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute related technology known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure that can improve the layout density of semiconductor devices, enhance their electrical performance, and increase their yield.

[0005] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate having opposing first and second surfaces; forming a first bonding layer on the first surface; implanting hydrogen ions into the substrate on one side of the first surface to form a hydrogen-containing release layer in the substrate; providing a carrier and forming a second bonding layer on one side of the carrier surface; fusion bonding the first bonding layer and the second bonding layer; forming a semiconductor device on the second surface of the substrate; and treating the release layer to separate the release layer from the substrate.

[0006] In some embodiments of this disclosure, processing the release layer to separate it from the substrate includes: heat-treating the substrate on which the semiconductor device is formed and the carrier to separate the release layer from the substrate, thereby separating the carrier from the substrate.

[0007] In some embodiments of this disclosure, the temperature at which the substrate and the carrier on which the semiconductor device is formed is heat-treated is 300°C to 450°C.

[0008] In some embodiments of this disclosure, the first bonding layer and the second bonding layer are melt-bonded, including: bonding the first bonding layer and the second bonding layer at room temperature and pressure; and annealing at a temperature below 250°C to melt-bond the first bonding layer and the second bonding layer.

[0009] In some embodiments of this disclosure, the method further includes: after the release layer is separated from the substrate, removing the first bonding layer and residual substrate material located on the second bonding layer using a chemical mechanical polishing process.

[0010] In some embodiments of this disclosure, the material of the first bonding layer includes silicon oxide; and / or, the material of the second bonding layer includes at least one of silicon oxide, silicon carbonitride, and silicon nitride.

[0011] In some embodiments of this disclosure, the thickness of the first bonding layer is 0.8–1.2 μm.

[0012] In some embodiments of this disclosure, the thickness of the second bonding layer is 0.1 to 1 μm.

[0013] In some embodiments of this disclosure, the hydrogen ions are implanted into the substrate to a depth of 1–5 μm in the vertical direction.

[0014] In some embodiments of this disclosure, the amount of hydrogen ions injected is 2 × 10⁻⁶. 16 ~1×10 17 pcs / cm 2 .

[0015] In some embodiments of this disclosure, the material of the carrier is the same as the material of the substrate; or, the material of the carrier is glass.

[0016] As can be seen from the above technical solutions, the method for fabricating the semiconductor structure according to the embodiments of this disclosure has at least one of the following advantages and positive effects:

[0017] In this embodiment, a first bonding layer is formed on a first surface of the substrate, and a second bonding layer is formed on one side of the carrier. The first and second bonding layers are fused together, reducing the total thickness deviation after bonding. Therefore, when forming a semiconductor device on the second surface of the substrate, the layout density of the semiconductor device can be increased, thereby improving the electrical performance of the semiconductor structure. Furthermore, by implanting hydrogen ions into the substrate to form a hydrogen-containing release layer, debonding the substrate and carrier is easier, avoiding damage to the semiconductor device and improving the yield of the semiconductor structure. Attached Figure Description

[0018] The above and other features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0019] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of this disclosure;

[0020] Figure 2 This is a schematic diagram of a substrate shown in some embodiments of this disclosure;

[0021] Figure 3 This is a schematic diagram illustrating the formation of a first bonding layer on a substrate according to some embodiments of the present disclosure;

[0022] Figure 4 This is a schematic diagram illustrating the implantation of hydrogen ions into a substrate, as shown in some embodiments of this disclosure;

[0023] Figure 5 This is a schematic diagram illustrating a carrier according to some embodiments of this disclosure;

[0024] Figure 6 This is a schematic diagram illustrating the formation of a second bonding layer on a carrier according to some embodiments of the present disclosure;

[0025] Figure 7 This is a schematic diagram illustrating the fusion bonding of a first bonding layer and a second bonding layer according to some embodiments of this disclosure;

[0026] Figure 8 This is a schematic diagram illustrating the formation of a semiconductor device on the second surface of a substrate, as shown in some embodiments of this disclosure;

[0027] Figure 9 This is a schematic diagram illustrating the separation of the substrate and the carrier in some embodiments of this disclosure;

[0028] Figure 10 This is a schematic diagram illustrating the chemical mechanical grinding of the separated carrier as shown in some embodiments of this disclosure.

[0029] Explanation of reference numerals in the attached figures:

[0030] 1. Substrate; 11. First surface; 12. Second surface; 2. First bonding layer; 3. Release layer; 4. Carrier; 5. Second bonding layer; 6. Semiconductor device; 7. Insulating layer; 100. Grinding head; Y, vertical direction. Detailed Implementation

[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0032] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form part of the present disclosure and illustrate, by way of example, different exemplary structures that can implement various aspects of the present disclosure. It should be understood that other specific embodiments of components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. Moreover, the terms “first,” “second,” etc., in the claims are used only as illustrative marks and not as numerical limitations on the object.

[0033] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0034] In addition, in the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0035] During semiconductor manufacturing, various semiconductor devices, such as RDLs (redistribution layers) or other devices, are fabricated on the front side of a semiconductor substrate. At this stage, the back side of the semiconductor substrate needs to be temporarily bonded to glass. During this temporary bonding, an adhesive layer and a release layer are sequentially formed on the back side of the semiconductor substrate. The adhesive layer adheres to the back side of the semiconductor substrate, and the release layer adheres to both the adhesive layer and the surface of the glass, thus achieving a temporary bond between the semiconductor substrate and the glass.

[0036] However, the study found that due to the relatively thick adhesive layer, typically tens of micrometers, the total thickness deviation is significant, reaching the micrometer level, for example, 5 micrometers. The total thickness deviation can be understood as the distribution of surface thickness, i.e., the difference between the maximum and minimum thickness values ​​among multiple thickness measurements. Therefore, the surface of the adhesive layer is uneven. This significantly affects the fabrication of semiconductor devices on the front side of the semiconductor substrate after temporary bonding with the glass, resulting in larger feature sizes and spacing, reduced layout density, and consequently, decreased electrical performance of the semiconductor structure.

[0037] Furthermore, since the bonding is temporary, the semiconductor substrate and glass need to be debonded after the semiconductor device is fabricated. This is done by irradiating the semiconductor substrate with a laser to generate localized high temperatures, causing the release layer to carbonize and thus achieving debonding. However, the localized high temperatures generated by laser irradiation may be transferred to the semiconductor device, affecting its performance and reducing yield. Moreover, after debonding, the glass becomes unusable and needs to be replaced for the next bonding, resulting in higher costs.

[0038] Based on this, embodiments of this disclosure provide a method for fabricating a semiconductor structure, such as... Figures 1 to 10 As shown, where Figure 1 This is a flowchart of the preparation method according to an embodiment of the present disclosure. Figures 2 to 10 This is a schematic diagram illustrating the semiconductor structure at different steps in the fabrication process. (Example) Figure 1 As shown, the method includes the following steps S110 to S170.

[0039] S110: Provide a substrate 1, which has a first surface 11 and a second surface 12 opposite to each other.

[0040] S120: A first bonding layer 2 is formed on the first surface 11.

[0041] S130: On one side of the first surface 11, hydrogen ions are injected into the substrate 1 to form a hydrogen-containing release layer 3 in the substrate 1.

[0042] S140: Provide a carrier 4 and form a second bonding layer 5 on one side of the surface of the carrier 4.

[0043] S150: Melt-bond the first bonding layer 2 and the second bonding layer 5.

[0044] S160: A semiconductor device 6 is formed on the second surface 12 of the substrate 1.

[0045] S170: Process the release layer 3 to separate the release layer 3 from the substrate 1.

[0046] In this embodiment, a first bonding layer 2 is formed on the first surface 11 of the substrate 1, and a second bonding layer 5 is formed on one side of the carrier 4. The first bonding layer 2 and the second bonding layer 5 are fused together, reducing the total thickness deviation after bonding. Therefore, when forming the semiconductor device 6 on the second surface 12 of the substrate 1, the layout density of the semiconductor device 6 can be increased, thereby improving the electrical performance of the semiconductor structure. Furthermore, by implanting hydrogen ions into the substrate to form a hydrogen-containing release layer, the debonding of the substrate and the carrier is made easier, avoiding damage to the semiconductor device and improving the yield of the semiconductor structure.

[0047] The method for fabricating the semiconductor structure according to the embodiments of this disclosure will be described in detail below.

[0048] S110: Provide a substrate 1, which has a first surface 11 and a second surface 12 opposite to each other.

[0049] like Figure 1 and Figure 2 As shown, a substrate 1 is provided. The material of the substrate 1 can be silicon, silicon carbide, silicon-on-insulator, silicon-on-insulator stacked, silicon-on-insulator stacked germanium, silicon-on-insulator, or germanium-on-insulator, etc. Shallow trench isolation can be formed in the substrate 1, and active regions are provided between the shallow trench isolations. For ease of explanation, Figure 2 The above structure is not shown in substrate 1.

[0050] In the vertical direction Y, substrate 1 has a first surface 11 and a second surface 12 facing each other. The vertical direction Y is perpendicular to substrate 1. The first surface 11 of substrate 1 is used for temporary bonding. The second surface 12 may be provided with an active region and a device region.

[0051] S120: A first bonding layer 2 is formed on the first surface 11.

[0052] like Figure 3 As shown, a first bonding layer 2 can be formed on the first surface 11 of the substrate 1 using a deposition process. The material of the first bonding layer 2 may include silicon oxide (SiO2).

[0053] In some embodiments, silicon oxide can be formed on the first surface 11 of the substrate 1 using a deposition process. The deposition process may include chemical vapor deposition, physical vapor deposition, and atomic layer deposition, etc., and is not specifically limited here.

[0054] In some embodiments, when the substrate 1 is made of Si, a silicon oxide layer can be formed on the Si surface by thermal oxidation as the first bonding layer 2. The thickness of the formed silicon oxide layer can be controlled by adjusting parameters such as oxygen concentration, amount, and temperature. Regardless of the process used, as long as the first bonding layer 2 can be formed, no specific process is limited here.

[0055] In some embodiments, the thickness of the first bonding layer 2 can be 0.8–1.2 μm. Specifically, in addition to the two values ​​mentioned above, the thickness of the first bonding layer 2 can also be 0.9 μm, 1 μm, 1.05 μm, 1.1 μm, or 1.15 μm, without any particular limitation here. The thickness of the first bonding layer 2 refers to its dimension in the vertical Y direction.

[0056] In this embodiment, the first bonding layer 2 is made of SiO2, which has a tetrahedral crystal structure. Silicon atoms are located at the center of the tetrahedron, and four oxygen atoms are located at its four vertices. Many such tetrahedra are connected by the oxygen atoms at their vertices, with each oxygen atom shared by two tetrahedra. This tetrahedral crystal structure of SiO2 facilitates hydrogen ion implantation in subsequent processes and improves the uniformity of the implantation. Furthermore, setting the thickness of the first bonding layer 2 to 0.8–1.2 μm further facilitates hydrogen ion implantation.

[0057] S130: On one side of the first surface 11, hydrogen ions are injected into the substrate 1 to form a hydrogen-containing release layer 3 in the substrate 1.

[0058] like Figure 4 As shown, hydrogen ions (H+) can be implanted into the side of the substrate 1 where the first bonding layer 2 is formed using an ion implantation process. + Specifically, a hydrogen ion beam is used to irradiate substrate 1. Hydrogen ions are implanted into substrate 1 through the first bonding layer 2. The hydrogen ions are gradually slowed down by the resistance of the solid material of substrate 1, causing them to eventually remain in substrate 1 at a certain depth. The first bonding layer 2 is a tetrahedral silicon oxide crystal, which facilitates the implantation of hydrogen ions into substrate 1. In the vertical Y direction, the depth of hydrogen ion implantation into substrate 1 is 1–5 μm.

[0059] like Figure 4As shown, the depth of substrate 1 can be understood as the distance extending from the first surface 11 of substrate 1 towards the second surface 12 in the vertical direction Y. Due to process limitations, hydrogen ions are not injected into the first surface 11. Instead, after extending a certain distance from the first surface 11 towards the second surface 12 in the vertical direction Y, hydrogen ions begin to be injected into substrate 1 and disperse to a certain depth in the direction towards the second surface 12 to form the release layer 3.

[0060] In some embodiments, the depth of hydrogen ion implantation into the substrate 1 can be 2μm, 2.5μm, 3μm, 3.5μm, 4μm, or 4.5μm, in addition to the two values ​​mentioned above. The depth of hydrogen ion implantation into the substrate 1 can be adjusted according to the size of the substrate 1 and the process requirements, and no special limitation is made here.

[0061] In some embodiments, the depth of hydrogen ion implantation into the substrate 1 can be controlled by adjusting parameters such as the ion implantation rate and temperature.

[0062] After hydrogen ion injection, microcavities can be formed in the release layer 3. That is, after hydrogen ion injection, bubbles can be formed inside the substrate 1. In other words, the release layer 3 contains bubbles. In subsequent processes, heat treatment of the substrate 1 can increase the pressure of the bubbles, and the entire microcavity can be connected, thus realizing the separation of the release layer 3 from the substrate 1.

[0063] In some embodiments, the amount of hydrogen ions injected is 2 × 10⁻⁶. 16 ~1×10 17 pcs / cm 2 (ions / cm 2 Specifically, in addition to the two endpoints mentioned above, the amount of hydrogen ions injected can also be 2 × 10⁻⁶. 16 pcs / cm 2 3×10 16 pcs / cm 2 5×10 16 pcs / cm 2 6×10 16 pcs / cm 2 7×10 16 pcs / cm 2 8×10 16 pcs / cm 2 9×10 16 pcs / cm 2 No special restrictions are imposed here.

[0064] The amount of hydrogen ion implantation needs to be controlled within a certain range. If the amount of hydrogen ion implantation is too large, hydrogen ion escape will occur, causing porous defects in the substrate 1, which will affect the fabrication and electrical properties of the semiconductor structure and reduce the yield of the semiconductor structure. If the amount of hydrogen ion implantation is too small, continuous bubbles cannot be formed inside the substrate 1, making it difficult for the release layer 3 to separate from the substrate 1 during subsequent heat treatment. In this embodiment, the amount of hydrogen ion implantation is set to the above-mentioned range (2×10⁻⁶). 16 ~1×10 17 pcs / cm 2 This method can avoid causing pore-like defects to the substrate 1, and at the same time, it can make the release layer 3 easier to separate from the substrate 1 in subsequent processing.

[0065] S140: Provide a carrier 4 and form a second bonding layer 5 on one side of the surface of the carrier 4.

[0066] like Figure 5 As shown, a carrier 4 is provided for bonding to a substrate 1. The material of the carrier 4 is the same as the material of the substrate 1; or, the material of the carrier 4 is glass. In some embodiments, the material of the carrier 4 may also be the same as the material of the semiconductor substrate 1, for example, the material of the carrier 4 may be silicon, silicon carbide, silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, silicon-germanium-on-insulator, or germanium-on-insulator, etc.

[0067] In some embodiments, the material of the carrier 4 may be different from that of the substrate 1. For example, the material of the carrier 4 may be glass. As long as the second bonding layer 5 in the subsequent process can be formed on the carrier 4, no special limitation is made here.

[0068] like Figure 6 As shown, a second bonding layer 5 can be formed on the surface of the carrier 4 using a deposition process. The deposition process can be at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition, without any particular limitation here.

[0069] In some embodiments, the thickness of the second bonding layer 5 can be 0.1–1 μm. Specifically, in addition to the two values ​​mentioned above, it can also be 0.2 μm, 0.4 μm, 0.5 μm, 0.7 μm, 0.8 μm, or 0.9 μm, without any particular limitation here. By setting the thickness of the second bonding layer 5 to the above range, after the first bonding layer 2 and the second bonding layer 5 are melt-bonded in subsequent processes, the thickness of the first bonding layer 2 and the second bonding layer 5 becomes relatively thin, thereby reducing the overall thickness deviation and improving the layout density during the fabrication of the semiconductor device 6, thus improving the electrical performance of the semiconductor structure.

[0070] In some embodiments, the material of the second bonding layer 5 may include at least one of silicon oxide (SiO2), silicon carbonitride (SiNC), and silicon nitride (Si3N4).

[0071] The first bonding layer 2 is made of silicon oxide, which facilitates hydrogen ion implantation. Since the second bonding layer 5 needs to undergo fusion bonding with the first bonding layer 2 in subsequent processes, the material of the second bonding layer 5 can be at least one of silicon oxide, silicon carbonitride, and silicon nitride. These materials can all undergo relatively stable and uniform fusion bonding with silicon oxide, making the temporary bonding between the substrate 1 and the carrier 4 more stable, and the total thickness deviation of the first bonding layer 2 and the second bonding layer 5 after fusion bonding is smaller.

[0072] S150: Melt-bond the first bonding layer 2 and the second bonding layer 5.

[0073] like Figure 7 As shown, the first bonding layer 2 and the second bonding layer 5 are melt-bonded, including: bonding the first bonding layer 2 and the second bonding layer 5 at room temperature and pressure; and annealing at a temperature below 250°C to melt-bond the first bonding layer 2 and the second bonding layer 5.

[0074] Specifically, ambient temperature and pressure can be understood as a temperature of 25°C and a pressure of one atmosphere. Of course, ambient temperature is not strictly 25°C; due to weather changes, temperature can fluctuate, for example, by + / - 5°C. Similarly, ambient pressure is not strictly one atmosphere; due to weather conditions, air pressure can fluctuate within a certain range, and these are all acceptable. In other words, when the first bonding layer 2 and the second bonding layer 5 are bonded together for initial fusion, neither the first bonding layer 2 nor the second bonding layer 5 is heated, cooled, or subjected to pressure changes; instead, they bond directly at ambient temperature and pressure through van der Waals forces or atomic forces.

[0075] At room temperature and pressure, the first bonding layer 2 and the second bonding layer 5 are bonded together, and the two undergo preliminary molten bonding. Then, annealing is carried out at a temperature below 250°C, and the first bonding layer 2 and the second bonding layer 5 undergo further molten bonding, so that the two can be bonded more stably.

[0076] The annealing temperature can be between 100℃ and 250℃. Besides these two extremes, other annealing temperatures include 120℃, 140℃, 150℃, 160℃, 180℃, 200℃, 220℃, and 240℃, without specific limitations. Annealing essentially heats the initially bonded first bonding layer 2 and the second bonding layer 5, increasing their molecular activity and further promoting their bonding, thus making the bond more stable.

[0077] S160: A semiconductor device 6 is formed on the second surface 12 of the substrate 1.

[0078] like Figure 8 As shown, after the substrate 1 and the carrier 4 are temporarily bonded, a semiconductor device 6 can be fabricated on the second surface 12 of the substrate 1. The semiconductor device 6 can be a word line structure, a bit line structure, a capacitor structure, or other conductive connection structure, and an insulating layer 7 is formed between the semiconductor devices 6. Since the substrate 1 and the carrier 4 are bonded by the fusion bonding of the first bonding layer 2 and the second bonding layer 5, the total thickness deviation of the first bonding layer 2 and the second bonding layer 5 is small, less than 500 nm, or even less than 5 nm, and the flatness is good. Therefore, the feature size and spacing of the semiconductor device 6 formed on the second surface 12 of the substrate 1 are reduced, the layout density of the semiconductor device is increased, more semiconductor devices 6 can be fabricated on the substrate 1, and the electrical performance of the semiconductor structure is improved.

[0079] S170: Process the release layer 3 to separate the release layer 3 from the substrate 1.

[0080] like Figure 9 As shown, the process of separating the release layer 3 from the substrate 1 includes: performing heat treatment on the substrate 1 on which the semiconductor device 6 is formed and the carrier 4 to separate the release layer 3 from the substrate 1, thereby separating the carrier 4 from the substrate 1.

[0081] Because bubbles form in the release layer 3, when the substrate 1 and the carrier 4 are heat-treated, the bubble pressure increases, which can also be understood as the bubbles growing larger. A microcavity layer forms inside the release layer 3, and as multiple bubbles grow larger, the microcavity layer gradually connects, causing the release layer 3 to detach and separate from the substrate 1. This leads to the separation of the carrier 4 from the substrate 1, a process also known as the debonding of the carrier 4 from the substrate 1. After the substrate 1 separates from the carrier 4, as... Figure 9 As shown, the second bonding layer 5 and the first bonding layer 2 are located on the carrier 4 side. The second bonding layer 5 is attached with the first bonding layer 2, some residual substrate 1 material, and even some residual release layer 3.

[0082] In some embodiments, the temperature for heat treatment of the substrate 1 and the carrier 4 on which the semiconductor device 6 is formed is 300°C to 450°C. Specifically, the heat treatment can be an annealing process, and the temperature of the heat treatment can be 320°C, 350°C, 380°C, 400°C, 420°C, or 430°C, in addition to the two values ​​mentioned above, as long as the release layer 3 can be successfully separated from the substrate 1, no special limitation is made here.

[0083] The substrate 1 and carrier 4 are heat-treated at temperatures that are neither too high nor too low. If the temperature is too high, excessive local bubble pressure may occur, leading to premature peeling of the release layer 3 and a discontinuous surface on the substrate 1 after peeling. If the temperature is too low, the peeling effect will not be achieved. Therefore, in this embodiment, the heat treatment temperature is set within the aforementioned range to control the bubble pressure within the release layer 3, ensuring uniform peeling of the release layer 3. After peeling, the surface of the substrate 1 remains continuous, preventing damage to the substrate 1 surface. All bubbles within the release layer 3 are interconnected, allowing for complete peeling and ensuring the smoothness of the substrate 1 surface. Furthermore, low-temperature annealing is used to separate the release layer 3 from the substrate 1, achieving debonding of the carrier 4 and the substrate 1. This method is gentler and avoids the localized high temperatures caused by laser irradiation of the substrate 1, thus preventing damage to the semiconductor device 6 and increasing the yield of the semiconductor structure.

[0084] In some embodiments, the method for fabricating a semiconductor structure may further include: after the release layer 3 is separated from the substrate 1, removing the first bonding layer 2 located on the second bonding layer 5 and the remaining material of the substrate 1 by a chemical mechanical polishing process.

[0085] like Figure 9 As shown, after the carrier 4 is separated from the substrate 1, in the vertical direction Y, the surface of the carrier 4 has a second bonding layer 5 and a first bonding layer 2 bonded together. The surface of the first bonding layer 2 has residual substrate 1 material, and there may even be a very small amount of hydrogen-containing stripping layer 3 above the substrate 1 material.

[0086] To achieve the reuse of the carrier 4, a chemical mechanical polishing (CMP) process can be used to remove the very small amount of hydrogen-containing release layer 3, residual substrate 1 material, and the first bonding layer 2, leaving a smooth second bonding layer 5. Therefore, the carrier 4 and the second bonding layer 5 thereon can be used for fusion bonding with the next substrate, enabling the carrier 4 to be reused multiple times. This significantly reduces costs compared to replacing the glass carrier each time, and is also more environmentally friendly.

[0087] Chemical mechanical polishing (CMP) is a process that combines chemical reaction and mechanical polishing. For example... Figure 10As shown, during the grinding process, the grinding head 100 applies a certain pressure to the side of the carrier 4 that does not have the second bonding layer 5, causing the grinding surface of the carrier 4 (the surface on the second bonding layer 5) to adhere tightly to the grinding pad. The grinding pad itself rotates, and simultaneously, the grinding head 100 drives the carrier 4 to rotate in the same direction as the grinding pad. During this process, a grinding slurry containing tiny abrasive particles is used, causing mechanical friction between the grinding surface of the carrier 4 and the surface of the grinding pad. During the grinding process, a series of complex mechanical and chemical actions remove the residual hydrogen-containing stripping layer 3, residual substrate 1 material, and the first bonding layer 2 on the second bonding layer 5. Grinding is stopped when the surface of the second bonding layer 5 is reached, achieving the purpose of removing the aforementioned film layers and planarizing the surface, enabling the carrier 4 with the second bonding layer 5 to be recycled multiple times.

[0088] In summary, the fabrication method of this disclosure forms a first bonding layer 2 on the first surface 11 of the substrate 1 and a second bonding layer 5 on one side of the carrier 4. The first bonding layer 2 and the second bonding layer 5 are then fused together, reducing the total thickness deviation after bonding. This allows for increased layout density of the semiconductor device 6 on the second surface 12 of the substrate 1, thereby improving the electrical performance of the semiconductor structure. Furthermore, the separation of the release layer 3 from the substrate 1 to debond the carrier 4 is a gentler method, avoiding the localized high temperatures caused by laser irradiation of the substrate 1, thus preventing damage to the semiconductor device 6 and increasing the yield of the semiconductor structure. The chemical mechanical polishing process used to polish the surface of the carrier 4 enables its reusability. This significantly reduces costs compared to replacing the glass carrier each time and is more environmentally friendly.

[0089] This disclosure also provides a semiconductor structure, which may be, for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), or ROM (Read Only Memory). This semiconductor structure can be fabricated using the methods described in any of the above embodiments, thereby improving the layout density of the semiconductor structure, enhancing the electrical performance and yield of the semiconductor, and simultaneously saving costs. Specific steps of the fabrication method can be found in the descriptions of any of the above embodiments, and will not be repeated here.

[0090] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to adopt this disclosure.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The application relates to a method for manufacturing a semiconductor device, comprising the following steps: providing a substrate, the substrate having opposite first and second surfaces; forming a first bonding layer on the first surface, the first bonding layer being a silicon oxide crystal with a tetrahedral structure; implanting hydrogen ions into the substrate on one side of the first surface to form a hydrogen-containing separation layer in the substrate; providing a carrier and forming a second bonding layer on a surface of one side of the carrier; fusion bonding the first bonding layer and the second bonding layer; forming a semiconductor device on the second surface of the substrate; separating the separation layer from the substrate, including: performing a heat treatment on the substrate on which the semiconductor device is formed and the carrier to separate the separation layer from the substrate, so as to separate the carrier from the substrate, and the temperature of the heat treatment is 300-450 DEG C.

2. The method of claim 1, wherein, The fusion bonding of the first bonding layer and the second bonding layer comprises the following steps: attaching the first bonding layer and the second bonding layer at normal temperature and pressure; performing annealing at a temperature lower than 250 DEG C to fusion bond the first bonding layer and the second bonding layer.

3. The method of any one of claims 1-2, wherein, The application further comprises the following steps: after the separation layer is separated from the substrate, removing the first bonding layer on the second bonding layer and the residual material of the substrate by using a chemical mechanical polishing process.

4. The method of any one of claims 1 to 2, characterized in that, The material of the second bonding layer comprises at least one of silicon oxide, silicon carbon nitride and silicon nitride.

5. The method of claim 1, wherein, The thickness of the first bonding layer is 0.8-1.2 mu m.

6. The method of claim 1, wherein, The thickness of the second bonding layer is 0.1-1 mu m.

7. The method of claim 1, wherein, In the vertical direction, the depth of the hydrogen ions implanted into the substrate is 1-5 mu m.

8. The method of claim 1, wherein, The amount of hydrogen ions injected is 2 x 10 16 ~ 1 x 10 17 cm-2 2 .

9. The method of claim 1, wherein, The material of the carrier is the same as that of the substrate; or the material of the carrier is glass.

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