Semiconductor package structure and method of manufacturing the same

Abstract

Disclosed are a semiconductor package structure and a manufacturing method thereof. The semiconductor package structure includes a support substrate, a chip stack including chips stacked on the support substrate, a first terminal in a first edge region of the support substrate and having a first circuit layer, a second terminal in a second edge region of the support substrate and having a second circuit layer, the chip stack being between the first terminal and the second terminal, a first bonding wire connected to a first chip and having a first contact at a terminal end thereof, a second bonding wire connected to a second chip and having a second contact at a terminal end thereof, an encapsulation layer surrounding the chip stack, the first terminal, the second terminal, the first bonding wire, and the second bonding wire on the support substrate and exposing the first contact, the second contact, the first circuit layer, and the second circuit layer, and a redistribution layer on the encapsulation layer and electrically connecting the first contact and the second contact to the first circuit layer and the second circuit layer, respectively.

Description

Technical Field

[0001] Example embodiments of the inventive concepts relate to the field of semiconductor packaging, and in particular, to a semiconductor packaging structure based on wire bonding technology and a manufacturing method thereof. Background Art

[0002] The existing vertical wire bonding (also known as vertical wire bonding or vertical wire bonding) process is prone to wire sweeping (i.e., wires drooping or bending, causing contact and short circuiting). This affects the accuracy of the redistribution layer (RDL) wiring of fan-out packages, resulting in poor package yield and difficulty in reducing the pitch.

[0003] The above information disclosed in this Background section is only for enhancement of understanding of the background of the inventive concept and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Summary of the Invention

[0004] To solve the above problems, example embodiments of the inventive concept disclose a semiconductor package structure and a manufacturing method thereof based on a wire bonding technology to improve process yield.

[0005] According to one aspect of the inventive concept, a semiconductor packaging structure is provided, which includes: a supporting substrate; a chip stack including a plurality of chips stacked on the supporting substrate; a first joint arranged in a first edge region of the supporting substrate, a first circuit layer being formed on an upper surface of the first joint; a second joint arranged in a second edge region of the supporting substrate opposite to the first edge region, a second circuit layer being formed on an upper surface of the second joint, the chip stack being located between the first joint and the second joint; a first bonding wire connected to a first chip among the plurality of chips and having a first contact at an end thereof; a second bonding wire connected to a second chip among the plurality of chips and having a second contact at an end thereof; an encapsulation layer surrounding the chip stack, the first joint, the second joint, the first bonding wire and the second bonding wire on the supporting substrate and exposing the first contact, the second contact, the first circuit layer and the second circuit layer; and a redistribution layer arranged on the encapsulation layer and electrically connecting the first contact and the second contact to the first circuit layer and the second circuit layer, respectively.

[0006] Preferably, each of the plurality of chips may include an active surface and an inactive surface, the active surface may face the redistribution layer, and the inactive surface may face the supporting substrate.

[0007] Preferably, the first solder pad on the effective surface of the first chip can be set between the first joint and the chip stack and connected to the first bonding wire, and the second solder pad on the effective surface of the second chip can be set between the second joint and the chip stack and connected to the second bonding wire.

[0008] Preferably, the first chips and the second chips may be alternately stacked on the supporting substrate and aligned in a horizontal direction.

[0009] Preferably, the first chip may be disposed between the support substrate and the second chip and each of the first chip and the second chip may be offset in a horizontal direction.

[0010] Preferably, an uppermost chip among the plurality of chips may be connected to the redistribution layer via pads provided on the active surface.

[0011] Preferably, the encapsulation layer may cover the active surface of the uppermost chip and expose the pads of the uppermost chip.

[0012] Preferably, an upper surface of the pad of the uppermost chip, an upper surface of the first circuit layer, an upper surface of the second circuit layer, and an upper surface of the encapsulation layer may be located at the same level.

[0013] Preferably, the redistribution layer may include a first portion and a second portion, the first portion electrically connecting the first contact to the first circuit layer, and the second portion electrically connecting the second contact and the pad of the uppermost chip to the second circuit layer.

[0014] Preferably, the semiconductor package structure may further include: external terminals disposed on the first circuit layer and the second circuit layer and spaced apart from the redistribution layer in a horizontal direction.

[0015] Another aspect of the inventive concept provides a method for manufacturing a semiconductor packaging structure, the method comprising: respectively arranging a first joint and a second joint in a first edge region of a supporting substrate and a second edge region opposite to the first edge region, wherein a first circuit layer is formed on an upper surface of the first joint, and a second circuit layer is formed on an upper surface of the second joint; arranging a first chip on the supporting substrate, the first chip being located between the first joint and the second joint; electrically connecting the first chip to the first circuit layer using a first bonding wire, wherein a portion of the first bonding wire extending above the first circuit layer forms a first wire arc; arranging a second chip on the first chip to form a chip stack; electrically connecting the second chip to the second circuit layer using a second bonding wire, wherein a portion of the second bonding wire extending above the second circuit layer forms a second wire arc; using an encapsulation layer to surround the chip stack, the first joint, the second joint, the first bonding wire and the second bonding wire on the supporting substrate; removing the upper portion of the encapsulation layer to expose the first circuit layer and the second circuit layer, and simultaneously removing the first wire arc and the second wire arc to form a first contact and a second contact exposed to the encapsulation layer, respectively; and providing a redistribution layer on the encapsulation layer to electrically connect the first contact and the second contact to the first circuit layer and the second circuit layer, respectively.

[0016] Preferably, each of the first chip and the second chip may include an active surface and an inactive surface, the active surface may face the redistribution layer, and the inactive surface may face the supporting substrate.

[0017] Preferably, the first pad on the active surface of the first chip may be adjacent to the first joint and connected to the first bonding wire, and the second pad on the active surface of the second chip may be adjacent to the second joint and connected to the second bonding wire.

[0018] Preferably, the steps of setting the first chip and electrically connecting it to the first circuit layer and the steps of setting the second chip and electrically connecting it to the second circuit layer can be repeated so that a plurality of the first chips and a plurality of the second chips are alternately stacked on the supporting substrate and aligned in the horizontal direction.

[0019] Preferably, the step of setting the first chip may include setting a plurality of the first chips and electrically connecting the plurality of the first chips to the first circuit layer, and the step of setting the second chip may include setting a plurality of the second chips and electrically connecting the plurality of the second chips to the second circuit layer, so that the plurality of the first chips are set between the supporting base and the plurality of the second chips, and each of the first chip and the second chip is offset in the horizontal direction.

[0020] Preferably, before using the encapsulation layer, the method may further include: forming a chip stack, the chip stack including the first chip, the second chip and an uppermost chip, the uppermost chip being connected to the redistribution layer via pads provided on the active surface.

[0021] Preferably, the encapsulation layer may cover the active surface of the uppermost chip and expose the pads of the uppermost chip.

[0022] Preferably, an upper surface of the pad of the uppermost chip, an upper surface of the first circuit layer, an upper surface of the second circuit layer, and an upper surface of the encapsulation layer may be located at the same level.

[0023] Preferably, the redistribution layer may include a first portion and a second portion, the first portion electrically connecting the first contact to the first circuit layer, and the second portion electrically connecting the second contact and the pad of the uppermost chip to the second circuit layer.

[0024] Preferably, the method may further include: providing external terminals on the first circuit layer and the second circuit layer, wherein the external terminals are spaced apart from the redistribution layer in a horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other aspects, features and advantages of the inventive concept will become clear through the following detailed description of exemplary embodiments of the inventive concept in conjunction with the accompanying drawings. In the accompanying drawings, like reference numerals will always indicate like elements.

[0026] Figure 1 A semiconductor package structure according to a comparative example is shown.

[0027] Figure 2 A semiconductor package structure according to a first embodiment of the inventive concept is shown.

[0028] Figure 3 A semiconductor package structure according to a second embodiment of the inventive concept is shown.

[0029] Figure 4 Shown according to Figure 3 A semiconductor package structure of a comparative example.

[0030] Figure 5 Shown according to Figure 3 The semiconductor package structure of the second embodiment.

[0031] Figure 6 A process flow chart of a method for manufacturing a semiconductor package structure according to a first embodiment of the inventive concept is shown.

[0032] Figures 7 to 12 Various steps of a method for manufacturing a semiconductor package structure according to a first embodiment of the inventive concept are shown. DETAILED DESCRIPTION

[0033] Hereinafter, various embodiments of the present inventive concept will be more fully described with reference to the accompanying drawings, which illustrate some embodiments. However, the present inventive concept can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this description will be thorough and complete, and will convey the scope of the present inventive concept to those skilled in the art. In the drawings, the dimensions of layers and regions may be exaggerated for clarity.

[0034] For ease of description, spatially relative terms such as "under," "beneath," "below," "above," and "above" may be used herein to describe the relationship of one element to other elements as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" another element would then be oriented "above" the other element. Thus, the term "under" can include both the orientations of "above" and "under." The device can be oriented otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0035] Figure 1 FIG. 1 shows a semiconductor package structure according to a comparative example. Figure 1 The manufacturing method of the semiconductor packaging structure may include the following steps: first, stacking multiple chips 2 on the upper surface of the substrate 1 in a vertical direction; second, using vertical wire bonding technology to electrically connect the multiple chips 2 through multiple leads 3, each of the multiple leads 3 having a vertical loop; then, after encapsulating the resulting structure using a resin 4 such as EMC, removing excess loops of the multiple leads 3 located at a surface higher than the bottommost chip 2 to form exposed interconnect metal contacts 5 at the same level; finally, connecting the exposed interconnect metal contacts 5 using RDL 6, and forming solder balls 7 that can be used for external interconnection on the lower surface of the RDL 6.

[0036] The above-mentioned semiconductor packaging structure has the following problems: First, due to the difficulty of the vertical wire bonding process, it is easy to cause lead deformation, and the lead hanging and touching during the packaging process are serious, which will affect the rewiring accuracy of the package; Second, because the vertical wire arc is not easy to form a large fan-out area, it is necessary to adjust the arrangement of the lower chip to achieve a larger area.

[0037] Figure 2 FIG. 1 shows a semiconductor package structure according to a first embodiment of the inventive concept. Figure 2 As shown in the figure, the semiconductor package structure 100 includes: a supporting substrate 110; a chip stack body STK, including a plurality of chips 120 stacked on the supporting substrate 110; a first joint 130, arranged in a first edge region ER1 of the supporting substrate 110, and a first circuit layer 131 is formed on the upper surface of the first joint 130; a second joint 140, arranged in a second edge region ER2 of the supporting substrate 110 opposite to the first edge region ER1, and a second circuit layer 141 is formed on the upper surface of the second joint 140, and the chip stack body STK is located between the first joint 130 and the second joint 140; a first bonding wire 150, connected to the first chip 121 of the plurality of chips 120, and 50 has a first contact 151 at the end; a second bonding wire 160, which is connected to the second chip 122 among the multiple chips 120 and has a second contact 161 at the end of the second bonding wire 160; an encapsulation layer 170, which encapsulates (for example, surrounds, surrounds or encapsulates) the chip stack STK, the first joint 130, the second joint 140, the first bonding wire 150 and the second bonding wire 160 on the supporting substrate 110 and exposes the first contact 151, the second contact 161, the first circuit layer 131 and the second circuit layer 141; and a redistribution layer 180, which is arranged on the encapsulation layer 170 and electrically connects the first contact 151 and the second contact 161 to the first circuit layer 131 and the second circuit layer 141, respectively.

[0038] The semiconductor package structure according to the first embodiment of the inventive concept can improve the wire overhang and touch problem caused by implementing a fan-out package structure based on wire bonding technology. For example, by disposing first and second connectors 130 and 140, each including an interconnect layer formed by a first circuit layer 131, a second circuit layer 141, and a redistribution layer 180, near a chip stack STK including a plurality of chips 120, wiring accuracy can be improved and a shortened interconnect path can be achieved. In some example embodiments, the first and second bonding wires 150 and 160 can include a metal material such as copper (Cu), aluminum (Al), or the like.

[0039] In this embodiment, the support base 110 may include, for example, a multilayer printed circuit board. The plurality of chips 120 may include, for example, a memory chip or a controller chip. Each of the first joint 130 and the second joint 140 may include an insulating material. The first joint 130 and the second joint 140 may be formed in a column shape having a certain height. For example, the first joint 130 and the second joint 140 may have a similar height (for example, the top surface of the first joint 130 may be at the same distance from the top surface of the support base 110 as the top surface of the second joint 140). The first circuit layer 131 and the second circuit layer 141 may be formed on the upper surfaces of the first joint 130 and the second joint 140, respectively, and include multilayer wiring and vias.

[0040] In this embodiment, the semiconductor package structure 100 may further include external terminals 190. The external terminals 190 are disposed on the first circuit layer 131 and the second circuit layer 141 and are spaced apart from the redistribution layer 180 in the horizontal direction. The external terminals 190 may be formed as solder balls. External signals may be transmitted to the first circuit layer 131 and the second circuit layer 141 of the semiconductor package structure 100 via the external terminals 190, and further transmitted to the first chip 121 and the second chip 122 via the redistribution layer 180 electrically connected to the first circuit layer 131 and the second circuit layer 141.

[0041] In this embodiment, each of the plurality of chips 120 may include an active surface and an inactive surface opposite to the active surface. The active surface of each chip 120 may face the redistribution layer 180, and the inactive surface thereof may face the support substrate 110. Input / output pads may be provided on the active surface of each chip 120.

[0042] In this embodiment, the plurality of chips 120 may include a first chip 121 and a second chip 122 sequentially stacked on a supporting substrate 110. A first pad located on the active surface of the first chip 121 may be provided between the first joint 130 and the chip stack body STK and connected to the first bonding wire 150. A second pad located on the active surface of the second chip 122 may be provided between the second joint 140 and the chip stack body STK and connected to the second bonding wire 160. For example, the first pad and the second pad may be respectively provided on both sides of the chip stack body STK. For example, the first pad may be provided on a side of the chip stack body STK close to the first joint 130, and the second pad may be provided on a side of the chip stack body STK close to the second joint 140. The first pad may be located at a level lower than that of the second pad, so that the length of the first bonding wire 150 may be greater than the length of the second bonding wire 160. However, example embodiments are not limited thereto, and for example, the first pad may be located at a level higher than that of the second pad, so that the length of the first bonding wire 150 may be smaller than that of the second bonding wire 160 .

[0043] In this embodiment, the plurality of chips 120 may include a plurality of first chips 121 and a plurality of second chips 122. The plurality of first chips 121 and the plurality of second chips 122 may be alternately stacked on the support substrate 110 and aligned horizontally. For example, the bottommost first chip among the plurality of first chips 121 may be disposed on the support substrate 110 and in contact with the upper surface of the support substrate 110. The bottommost second chip among the plurality of second chips 122 may be disposed on the bottommost first chip with an adhesive layer AL positioned therebetween. For example, the adhesive layer AL may be a die attach film (DAF). In this case, the first pads of the bottommost first chip may be covered by the adhesive layer AL, and the portions of the first bonding wires 150 that contact the first pads may be embedded in the adhesive layer AL. That is, the first bonding wires 150 may extend in the adhesive layer AL between the adjacent first and second chips 121, 122.

[0044] In this embodiment, the plurality of chips 120 may further include an uppermost chip 120M. The size and function of the uppermost chip 120M may be different from those of the first and second chips. The uppermost chip 120M may be connected to the redistribution layer 180 via pads PAD provided on its active surface.

[0045] In this embodiment, the encapsulation layer 170 can cover the effective surface of the topmost chip 120M and expose the pads PAD of the topmost chip 120M. Therefore, the topmost chip 120M, which is arranged adjacent to the second joint 140, can be electrically connected to the second circuit layer 141, the second bonding wire 160, and the second chip 122 via the pads PAD and the redistribution layer 180. However, the example embodiments of the inventive concept are not limited thereto. Although not shown, the pads of the topmost chip 120M can be arranged adjacent to the first joint 130 and can be electrically connected to the first circuit layer 131, the first bonding wire 150, and the first chip 121 via the redistribution layer 180.

[0046] In this embodiment, since a planarization process such as chemical mechanical polishing (CMP) is performed on the encapsulation layer 170, the upper surface of the pad PAD of the uppermost chip 120M, the upper surface of the first circuit layer 131, the upper surface of the second circuit layer 141, and the upper surface of the encapsulation layer 170 can be located at the same level.

[0047] In this embodiment, the redistribution layer 180 may include a first portion 180A disposed on the first connector 130 and a second portion 180B disposed on the second connector 140. The first portion 180A may electrically connect the first contact 151 to the first circuit layer 131. The second portion 180B may electrically connect the second contact 161 and the pad PAD of the uppermost chip 120M to the second circuit layer 141. In some example embodiments, the first portion 180A and the second portion 180B may be spaced apart from each other in the horizontal direction. Accordingly, the solder balls 190 may include a first solder ball 190A connected to the first portion 180A of the redistribution layer 180 and a second solder ball 190B connected to the second portion 180B of the redistribution layer 180. The first solder ball 190A and the second solder ball 190B may receive or output different signals, wherein the different signals may be input to the first chip 121 and the second chip 122, respectively, or output from the first chip 121 and the second chip 122, respectively.

[0048] Figure 3 FIG2 shows a semiconductor package structure according to a second embodiment of the inventive concept. Figure 2 The same elements as those shown in FIG. 1 are omitted, and the description will focus on the differences from the first embodiment.

[0049] like Figure 3As shown in FIG, in this embodiment, the plurality of chips 120 may include a plurality of first chips 121 and a plurality of second chips 122. The plurality of first chips 121 may be disposed between the support substrate 110 and the plurality of second chips 122. In other words, the plurality of first chips 121 may be sequentially stacked on the support substrate 110 and the plurality of second chips 122 may be sequentially stacked on the uppermost first chip.

[0050] In this embodiment, each of the plurality of first chips 121 and the plurality of second chips 122 can be offset in a horizontal direction to expose each first pad and each second pad. For example, the plurality of first chips 121 can be offset in a first horizontal direction, and the plurality of second chips 122 can be offset in a second horizontal direction opposite to the first horizontal direction, so that the chip stack STK is not easily collapsed. That is, some of the plurality of first chips 121 and the plurality of second chips 122 can be offset from each other in a horizontal direction so that the upper surfaces of the plurality of first chips 121 and the upper surfaces of the plurality of second chips 122 are exposed. The first bonding wire 150 can be connected to the exposed first pad of the first chip 121. The second bonding wire 160 can be connected to the exposed second pad of the second chip 122. In this case, the shortest length of the first bonding wire 150 can be greater than the longest length of the second bonding wire 160, but the example embodiments of the inventive concept are not limited thereto.

[0051] In this embodiment, the adhesive layer AL may not be disposed between the multiple chips 120, thereby further reducing the thickness of the semiconductor package structure 200. That is, the bottom surface of the upper chip among the multiple chips 120 may contact (e.g., directly contact) the top surface of the lower chip among the multiple chips 120. Furthermore, because the first pads of the first chip 121 and the second pads of the second chip 122 are exposed rather than buried in the adhesive layer AL, the connection reliability of the first bonding wires 150 and the second bonding wires 160 can be improved.

[0052] In the following, Figure 3 The second embodiment shown in FIG. 1 is an example to describe the advantageous effect that the semiconductor package structure according to the inventive concept can reduce the length of the interconnection path. Figure 4 Shown according to Figure 3 Comparative example of semiconductor package structure. Figure 5 Shown according to Figure 3 The semiconductor package structure of the second embodiment.

[0053] like Figure 4 As shown in FIG, in the comparative example, in addition to the first bonding wire 150A and the second bonding wire 160A, the semiconductor package structure 200A may be Figure 3The semiconductor package structure 200 shown in FIG. In the comparative example, multiple first chips 121A included in the semiconductor package structure 200A are connected to the first portion 180A of the redistribution layer 180 via first bonding wires 150A using a vertical wire bonding process. Multiple second chips 122A included in the semiconductor package structure 200A are connected to the second portion 180B of the redistribution layer 180 via second bonding wires 160A using a vertical wire bonding process. Taking the bottommost first chip 121A as an example, the bottommost first chip 121A is connected to the first solder ball 190A of the external terminal 190 via an interconnection path AB. The first bonding wire 150A is connected to the first chip 121A at point A. The first solder ball 190A is connected to the first portion 180A of the redistribution layer 180 at point B. The interconnection path AB has a first distance from point A to point B.

[0054] like Figure 5 As shown in FIG, in the second embodiment, a plurality of first chips 121 included in a semiconductor package structure 200 are connected to a first portion 180A of a redistribution layer 180 via first bonding wires 150 using a wire-arc wire bonding process. A plurality of second chips 122 included in the semiconductor package structure 200 are connected to a second portion 180B of the redistribution layer 180 via second bonding wires 160 using a wire-arc wire bonding process. Taking the bottommost first chip 121 as an example, the bottommost first chip 121 is connected to a first solder ball 190A of an external terminal 190 via an interconnection path A'B'. The first bonding wire 150 is connected to the first chip 121 at point A'. The first solder ball 190A is connected to the first portion 180A of the redistribution layer 180 at point B'. The interconnection path A'B' has a second distance from point A' to point B'.

[0055] It can be seen that the second distance is smaller than the first distance. Therefore, the semiconductor package structure formed by the wire-arc wire bonding process can shorten the interconnection path to speed up signal transmission.

[0056] Below, we will refer to Figures 6 to 12 The method for manufacturing a semiconductor package structure according to the first embodiment of the inventive concept will be described below. However, the manufacturing methods of the second embodiment and other embodiments of the inventive concept will become clear and apparent from the following description.

[0057] Figure 6 A process flow chart of a method for manufacturing a semiconductor package structure according to a first embodiment of the inventive concept is shown. Figures 7 to 12 Various steps of a method for manufacturing a semiconductor package structure according to a first embodiment of the inventive concept are shown.

[0058] and Figure 2 See together Figure 6 and Figure 7The method for manufacturing a semiconductor package structure 100 includes the following steps: Step S100, respectively providing a first connector 130 and a second connector 140 in a first edge region ER1 and a second edge region ER2 opposite to the first edge region ER1 of a support substrate 110. A first circuit layer 131 is formed on an upper surface of the first connector 130. A second circuit layer 141 is formed on an upper surface of the second connector 140.

[0059] See also Figure 8 , step S200, a first chip 121 is provided on the supporting substrate 110. The first chip 121 is located between the first connector 130 and the second connector 140. In this embodiment, the first chip 121 may be Figure 2 The first chip 121 is a lowermost chip among the plurality of chips 120 included in the semiconductor package structure 100 shown in FIG. The first chip 121 may be a memory chip or a controller chip.

[0060] In step S300, the first chip 121 is electrically connected to the first circuit layer 131 using a first bonding wire 150. The portion of the first bonding wire 150 that extends above the first circuit layer 131 forms a first wire loop 150C. In this embodiment, the first connector 130 may be at a higher level than the first chip 121, so that the first bonding wire 150 extends upward from a first pad disposed on the upper surface of the first chip 121 for a certain distance, then bends and changes direction to extend downward to connect to the first circuit layer 131 located on the upper surface of the first connector 130, thereby forming the first wire loop 150C.

[0061] Next, see Figure 9 In step S400 , a second chip 122 is provided on the first chip 121 . In this embodiment, the size and function of the second chip 122 may be different from those of the first chip 121 , but example embodiments of the inventive concept are not limited thereto. In other embodiments, the second chip 122 may be the same as the first chip 121 .

[0062] In step S500, the second chip 122 is electrically connected to the second circuit layer 141 using the second bonding wire 160, wherein the portion of the second bonding wire 160 extending above the second circuit layer 141 forms a second wire loop 160C. In this embodiment, the second joint 140 may be at a higher level than the second chip 122, so that the second bonding wire 160 extends upward from a second pad provided on the upper surface of the second chip 122 for a certain distance, then bends and changes direction to extend downward to connect to the second circuit layer 141 located on the upper surface of the second joint 140, thereby forming the second wire loop 160C.

[0063] See also Figure 10In step S600, the chip stack STK, the first connector 130, the second connector 140, the first bonding wire 150, and the second bonding wire 160 are encapsulated on the support substrate 110 using an encapsulation layer 170. In this embodiment, the material of the encapsulation layer 170 can be a resin such as EMC. The encapsulation layer 170 can completely cover the first wire loop 150C and the second wire loop 160C, thereby securing the first bonding wire 150 and the second bonding wire 160 to prevent deformation.

[0064] See also Figure 11 In step S700, the upper portion of encapsulation layer 170 is removed to expose first circuit layer 131 and second circuit layer 141. Simultaneously, first and second loops 150C and 160C are removed to form first and second contacts 151 and 161, respectively, exposed to encapsulation layer 170. In this embodiment, a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed on the structure obtained in step S600 until the upper surfaces of first and second circuit layers 131 and 141, as well as the upper surface of pad PAD of topmost chip 120M, are exposed. During this planarization process, first loop 150C of first bonding wire 150 and second loop 160C of second bonding wire 160 are removed together with the upper portion of encapsulation layer 170, thereby exposing first and second contacts 151 and 161. For example, the first and second bonding wires 150 and 160 may extend at an oblique angle with respect to the top surfaces of the first and second chips 121 and 122 .

[0065] See also Figure 12 In step S800, a redistribution layer 180 is provided on the encapsulation layer 170 to electrically connect the first contact 151 and the second contact 161 to the first circuit layer 131 and the second circuit layer 141, respectively. In this embodiment, the redistribution layer 180 may include multiple layers of wiring and vias. The first contact 151 of the first bonding wire 150 and the second contact 161 of the second bonding wire 160 may be electrically connected to external components via the redistribution layer 180.

[0066] As the integration density of semiconductor packaging structures increases, the distances between components within them decrease. Consequently, the distances between the wire loops of multiple bonding wires also decrease, leading to wire dangling and sweeping, which reduces the yield of the package. According to example embodiments of the present invention, a method for manufacturing a semiconductor package structure utilizes first and second connectors to route the bonding wires of multiple chips, increasing the fan-out area while shortening the interconnect path. Furthermore, this method improves the alignment accuracy of rerouting in the back-end-of-line (BEOL) process.

[0067] See also Figure 12In this embodiment, the method of manufacturing the semiconductor package structure 100 may further include providing external terminals 190 on the first circuit layer 131 and the second circuit layer 141. The external terminals 190 are spaced apart from the redistribution layer 180 in a horizontal direction.

[0068] Return to see Figure 2 In this embodiment, each of the first chip 121 and the second chip 122 may include an active surface and an inactive surface. The active surface may face the redistribution layer 180, and the inactive surface may face the support substrate 110. In addition, in this embodiment, the first pad on the active surface of the first chip 121 may be adjacent to the first joint 130 and connected to the first bonding wire 150. The second pad on the active surface of the second chip 122 may be adjacent to the second joint 140 and connected to the second bonding wire 160.

[0069] Return to see Figure 8 and Figure 9 In this embodiment, the steps of disposing and electrically connecting the first chip 121 to the first circuit layer 131 and disposing and electrically connecting the second chip 122 to the second circuit layer 141 can be repeated, so that a plurality of first chips 121 and a plurality of second chips 122 are alternately stacked on the support substrate 110 and aligned in the horizontal direction. Adjacent first chips 121 and second chips 122 can be connected to each other via an adhesive layer AL located therebetween.

[0070] Return to see Figure 3 In the method of manufacturing the semiconductor package structure 200 according to the second embodiment of the inventive concept, a first number of steps of disposing the first chip 121 and electrically connecting it to the first circuit layer 131 may be performed first, followed by a second number of steps of disposing the second chip 122 and electrically connecting it to the second circuit layer 141, such that a plurality of first chips 121 corresponding to the first number are stacked on the supporting substrate 110, and a plurality of second chips 122 corresponding to the second number are stacked on the uppermost first chip of the plurality of first chips 121. In other words, the plurality of first chips 121 may be disposed between the supporting substrate 110 and the plurality of second chips 122, and each of the first chip 121 and the second chip 122 may be offset in a horizontal direction to expose the first and second pads.

[0071] Return to see Figure 9 and Figure 10 Before using the encapsulation layer 170, the method for manufacturing the semiconductor package structure 100 may further include: forming a chip stack body STK. The chip stack body STK may include a first chip 121, a second chip 122, and an uppermost chip 120M. Figure 2As shown in FIG, the uppermost chip 120M may be connected to the redistribution layer 180 via pads PAD provided on an active surface thereof.

[0072] Return to see Figure 11 After undergoing a planarization process, the encapsulation layer 170 may cover the active surface of the uppermost chip 120M and expose the pads PAD of the uppermost chip 120M.

[0073] In this embodiment, due to the planarization process, the upper surface of the pad PAD of the uppermost chip 120M, the upper surface of the first circuit layer 131, the upper surface of the second circuit layer 141 and the upper surface of the encapsulation layer 170 can be located at the same level.

[0074] Return to see Figure 12 In the step of providing the redistribution layer 180, the redistribution layer 180 may include a first portion 180A and a second portion 180B. The first portion 180A of the redistribution layer 180 may electrically connect the first contact 151 of the first bonding wire 150 to the first circuit layer 131, and the second portion 180B of the redistribution layer 180 may electrically connect the second contact 161 of the second bonding wire 160 and the pad PAD of the uppermost chip 120M to the second circuit layer 141.

[0075] To summarize and review, according to exemplary embodiments of the inventive concept, by disposing first and second connectors comprising an interconnect layer formed by a first circuit layer, a second circuit layer, and a redistribution layer alongside a chip stack comprising multiple chips, the wire overhang and touch problem that can easily arise when implementing a fan-out packaging structure based on wire bonding technology can be alleviated. Furthermore, by utilizing the first and second connectors to route the bonding wires of the multiple chips, the fan-out area can be increased, the interconnect paths can be shortened, and the alignment accuracy of the redistribution can be improved during back-end manufacturing processes.

[0076] While embodiments of the inventive concept have been shown and described herein, it will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor package structure, comprising: Support substrate; A chip stack comprising a plurality of chips stacked on the supporting substrate; a first connector, disposed in a first edge region of the support substrate, wherein a first circuit layer is formed on an upper surface of the first connector; a second connector disposed in a second edge region of the support substrate opposite to the first edge region, a second circuit layer being formed on an upper surface of the second connector, and the chip stack being located between the first connector and the second connector; a first bonding wire connected to a first chip of the plurality of chips and having a first contact at an end thereof; a second bonding wire connected to a second chip of the plurality of chips and having a second contact at an end thereof; an encapsulation layer, surrounding the chip stack, the first joint, the second joint, the first bonding wire, and the second bonding wire on the supporting substrate and exposing the first contact, the second contact, the first circuit layer, and the second circuit layer; as well as A redistribution layer is disposed on the encapsulation layer and electrically connects the first contact and the second contact to the first circuit layer and the second circuit layer respectively.

2. The semiconductor package structure according to claim 1, wherein: Each of the plurality of chips includes an active surface and an inactive surface, the active surface facing the redistribution layer and the inactive surface facing the supporting substrate.

3. The semiconductor package structure according to claim 2, wherein: A first pad on the active surface of the first chip is provided at a side of the chip stack close to the first joint and connected to the first bonding wire, and A second pad on the active surface of the second chip is provided at a side of the chip stack close to the second joint and connected to the second bonding wire.

4. The semiconductor package structure according to claim 3, wherein: The first chips and the second chips are alternately stacked on the supporting substrate and aligned in a horizontal direction.

5. The semiconductor package structure according to claim 3, wherein: The first chip is disposed between the supporting substrate and the second chip, and Each of the first chip and the second chip is offset in a horizontal direction.

6. The semiconductor package structure according to claim 2, wherein: An uppermost chip of the plurality of chips is connected to the redistribution layer via pads provided on the active surface.

7. The semiconductor package structure according to claim 6, wherein: The encapsulation layer covers the active surface of the uppermost chip and exposes the pads of the uppermost chip.

8. The semiconductor package structure according to claim 7, wherein: An upper surface of the pad of the uppermost chip, an upper surface of the first circuit layer, an upper surface of the second circuit layer, and an upper surface of the encapsulation layer are located at the same level.

9. The semiconductor package structure according to claim 6, wherein: The redistribution layer includes a first portion and a second portion, The first portion electrically connects the first contact to the first circuit layer, and The second portion electrically connects the second contact and the pad of the uppermost chip to the second circuit layer.

10. The semiconductor package structure according to claim 1, further comprising: The external terminal is disposed on the first circuit layer and the second circuit layer and is spaced apart from the redistribution layer in a horizontal direction.

11. A method for manufacturing a semiconductor package structure, comprising: A first connector and a second connector are respectively provided in a first edge region of the supporting substrate and a second edge region opposite to the first edge region, wherein a first circuit layer is formed on an upper surface of the first connector and a second circuit layer is formed on an upper surface of the second connector; Disposing a first chip on the supporting substrate, wherein the first chip is located between the first connector and the second connector; Using a first bonding wire to electrically connect the first chip to the first circuit layer, wherein a portion of the first bonding wire extending above the first circuit layer forms a first wire arc; Disposing a second chip on the first chip to form a chip stack; electrically connecting the second chip to the second circuit layer using a second bonding wire, wherein a portion of the second bonding wire extending above the second circuit layer forms a second wire arc; encapsulating the chip stack, the first connector, the second connector, the first bonding wire, and the second bonding wire on the support substrate with an encapsulation layer; removing an upper portion of the encapsulation layer to expose the first circuit layer and the second circuit layer, and simultaneously removing the first wire loop and the second wire loop to form a first contact and a second contact respectively exposed to the encapsulation layer; and A redistribution layer is disposed on the encapsulation layer to electrically connect the first contact and the second contact to the first circuit layer and the second circuit layer, respectively.

12. The method according to claim 11, wherein Each of the first chip and the second chip includes an active surface and an inactive surface, the active surface facing the redistribution layer, and the inactive surface facing the supporting substrate.

13. The method according to claim 12, wherein: A first pad on the active surface of the first chip is adjacent to the first contact and connected to the first bonding wire, and A second pad on the active surface of the second chip is adjacent to the second contact and connected to the second bonding wire.

14. The method according to claim 13, wherein Repeat the steps of setting the first chip and electrically connecting it to the first circuit layer and the step of setting the second chip and electrically connecting it to the second circuit layer, so that multiple first chips and multiple second chips are alternately stacked on the supporting substrate and aligned in the horizontal direction.

15. The method according to claim 13, wherein The step of providing the first chip includes providing a plurality of the first chips and electrically connecting the plurality of the first chips to the first circuit layer. The step of arranging the second chip includes arranging a plurality of the second chips and electrically connecting the plurality of the second chips to the second circuit layer, so that the plurality of the first chips are arranged between the supporting substrate and the plurality of the second chips, and each of the first chip and the second chip is offset in a horizontal direction.

16. The method according to claim 12, wherein: Before using the encapsulation layer, the method further comprises: A chip stack is formed, the chip stack including the first chip, the second chip, and an uppermost chip connected to the redistribution layer via pads provided on an active surface.

17. The method according to claim 16, wherein The encapsulation layer covers the active surface of the uppermost chip and exposes the pads of the uppermost chip.

18. The method according to claim 17, wherein: An upper surface of the pad of the uppermost chip, an upper surface of the first circuit layer, an upper surface of the second circuit layer, and an upper surface of the encapsulation layer are located at the same level.

19. The method according to claim 16, wherein The redistribution layer includes a first portion and a second portion, The first portion electrically connects the first contact to the first circuit layer, and The second portion electrically connects the second contact and the pad of the uppermost chip to the second circuit layer.

20. The method of claim 11, further comprising: External terminals are provided on the first circuit layer and the second circuit layer, and are spaced apart from the redistribution layer in a horizontal direction.

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