All-around gate field effect transistor and method of manufacturing the same

Abstract

The application discloses a kind of all-enclosing gate field effect transistor and preparation method thereof, it is related to semiconductor technical field, including substrate, source, gate structure, drain and extension structure, extension structure includes source extension structure and / or drain extension structure, source, gate structure, drain, source extension structure and drain extension structure are all set in the same side of substrate, gate structure is set between source and drain, source extension structure is set between source and gate structure, drain extension structure is set between drain and gate structure, source and drain are respectively ion-doped source and ion-doped drain, source extension structure and drain extension structure are all P-type ion-doped extension structure, the ion doping concentration of source and source extension structure is different, the ion doping concentration of drain and drain extension structure is different.The application can optimize transistor performance, improve the flexibility of circuit design.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a fully enclosed gate field-effect transistor and its fabrication method. Background Technology

[0002] As the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) in integrated circuits shrinks to below 5nm, nanosheet-type fully enclosed gate field-effect transistors (NAAFETs) are considered the preferred solution due to their controllable gate. However, gate-induced drain leakage current (GIDL) is a significant problem faced by nanosheet GAAFETs, which not only increases the chip's static power consumption but also affects the transistor's reliability. Secondly, because electron mobility is significantly greater than hole mobility, P-type field-effect transistors (PMOS) require an aspect ratio approximately 2.5-3.5 times that of N-type field-effect transistors (NMOS) to maintain performance comparable to N-type field-effect transistors. This drastically limits the number of transistors per unit area.

[0003] Existing fully enclosed gate field-effect transistor structures, such as Figure 20 As shown, doping is performed on both the source and drain. To ensure that the PMOS and NMOS have roughly the same on-state current, the on-state current of this device is adjusted by changing the width-to-length ratio of the PMOS, which places very large area requirements on it. Summary of the Invention

[0004] The purpose of this invention is to provide a fully enclosed gate field-effect transistor and its fabrication method to solve the problems existing in the prior art. It can improve the on-state current and off-state leakage current of N-type and P-type field-effect transistors, significantly optimize the transistor's operating performance, and the P-type field-effect transistor does not require an increase in width-to-length ratio, thereby increasing the transistor density per unit area; it also increases the flexibility of circuit design.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] This invention provides a fully enclosed gate field-effect transistor, comprising a substrate, a source, a gate structure, a drain, and an extended structure. The extended structure includes a source extended structure and / or a drain extended structure. The source, the gate structure, the drain, the source extended structure, and the drain extended structure are all disposed on the same side of the substrate. The gate structure is disposed between the source and the drain. The source extended structure is disposed between the source and the gate structure. The drain extended structure is disposed between the drain and the gate structure. The source and the drain are respectively ion-doped. The source extended structure and the drain extended structure are both P-type ion-doped extended structures. The ion doping concentrations of the source and the source extended structure are different, and the ion doping concentrations of the drain and the drain extended structure are also different.

[0007] Preferably, the extended structure includes the source extended structure and the drain extended structure.

[0008] Preferably, the source and drain of the N-type field-effect transistor are respectively N-type ion-doped source and N-type ion-doped drain, and the P-type ion doping concentration of the source extension structure of the N-type field-effect transistor is higher than the N-type ion doping concentration of the source, and the P-type ion doping concentration of the drain extension structure of the N-type field-effect transistor is higher than the N-type ion doping concentration of the drain.

[0009] Preferably, the source and drain of the P-type field-effect transistor are respectively a source doped with P-type ions and a drain doped with P-type ions, wherein the P-type ion doping concentration of the source extension structure of the P-type field-effect transistor is higher than that of the source, and the P-type ion doping concentration of the drain extension structure of the P-type field-effect transistor is higher than that of the drain.

[0010] Preferably, the gate structure includes a channel, the source extension structure is disposed between the source and the channel, and the drain extension structure is disposed between the drain and the channel.

[0011] This invention provides a method for fabricating a fully enclosed gate field-effect transistor, comprising the following steps:

[0012] A substrate is obtained, and a source, gate, drain, and extended structure are fabricated on one side of the substrate. The extended structure includes a source extended structure and / or a drain extended structure. The gate structure is disposed between the source and the drain, the source extended structure is disposed between the source and the gate structure, and the drain extended structure is disposed between the drain and the gate structure. Before the source fabrication is completed, P-type ion doping is performed on the source extended structure, and before the drain fabrication is completed, P-type ion doping is performed on the drain extended structure. Ion doping is performed on the source and the drain, and the ion doping concentrations of the source and the source extended structure are different, and the ion doping concentrations of the drain and the drain extended structure are also different.

[0013] Preferably, when processing an N-type field-effect transistor, N-type ions are doped into the source and the drain, such that the P-type ion doping concentration of the source extension structure is higher than the N-type ion doping concentration of the source, and the P-type ion doping concentration of the drain extension structure is higher than the N-type ion doping concentration of the drain; when processing a P-type field-effect transistor, P-type ions are doped into the source and the drain, such that the P-type ion doping concentration of the source extension structure is higher than the P-type ion doping concentration of the source, and the P-type ion doping concentration of the drain extension structure is higher than the P-type ion doping concentration of the drain.

[0014] Preferably, the source extension structure and the drain extension structure are processed by etching, and ion doping is performed on the source extension structure and the drain extension structure by ion implantation.

[0015] Preferably, the fabrication method of the source extension structure and the drain extension structure includes:

[0016] S1. Obtain the substrate, and alternately and stack SiGe layers and Si layers on the substrate to form an extended layer;

[0017] S2. A groove is processed in the middle of the extended layer, and the remaining part of the extended layer forms two fin structures, and a virtual gate is set in the groove;

[0018] S3. An isolation layer is processed on one end of each fin structure near the virtual gate. Using one isolation layer as a hard mask, the material of the corresponding fin structure away from the virtual gate is removed by an etching process to form the source extension structure. Using the other isolation layer as a hard mask, the material of the corresponding fin structure away from the virtual gate is removed by an etching process to form the drain extension structure.

[0019] Preferably, the P-type ion doping method for the source extension structure and the drain extension structure includes: doping the source extension structure or the drain extension structure with P-type ions before processing the isolation layer of the source extension structure or the drain extension structure.

[0020] The present invention achieves the following technical effects compared to the prior art:

[0021] This invention provides a fully enclosed gate field-effect transistor and its fabrication method, comprising a substrate, a source, a gate structure, a drain, and an extended structure. The extended structure includes a source extended structure and / or a drain extended structure. The source, gate structure, drain, source extended structure, and drain extended structure are all disposed on the same side of the substrate. The gate structure is disposed between the source and the drain. The source extended structure is disposed between the source and the gate structure. The drain extended structure is disposed between the drain and the gate structure. The source and the drain are respectively ion-doped source and ion-doped drain. Both the source extended structure and the drain extended structure are P-type ion-doped extended structures. The ion doping concentrations of the source and the source extended structure are different, and the ion doping concentrations of the drain and the drain extended structure are also different.

[0022] This embodiment sets up a source extension structure and / or a drain extension structure. By changing the doping concentration of the source extension structure and / or the drain extension structure, the transistor performance can be changed. This can improve the on-state current and off-state leakage current of N-type and P-type field-effect transistors, significantly optimize the transistor's operating performance, and the P-type field-effect transistor does not need to increase the aspect ratio, thereby increasing the transistor density per unit area; it also increases the flexibility of circuit design. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of the fully enclosed gate field-effect transistor provided in Example 1;

[0025] Figure 2 A flowchart of the fabrication method of the fully enclosed gate field-effect transistor provided in Example 1;

[0026] Figure 3 The simulation results of NMOS in Example 1 are shown in the figure.

[0027] Figure 4 The simulation results of PMOS in Example 1 are shown in the figure.

[0028] Figure 5 This is a schematic diagram illustrating the substrate selection steps in Example 2;

[0029] Figure 6 This is a schematic diagram of the steps for epitaxially stacking SiGe / Si on the substrate in Example 2;

[0030] Figure 7 This is a schematic diagram of the etching steps for the finned structure in Example 2;

[0031] Figure 8 This is a schematic diagram of the shallow trench isolation steps in Example 2;

[0032] Figure 9 This is a schematic diagram of the wet etching process for exposing the fin structure in Example 2;

[0033] Figure 10 This is a schematic diagram of the virtual gate patterning steps in Example 2. Figure 1 ;

[0034] Figure 11 This is a schematic diagram of the virtual gate patterning steps in Example 2. Figure 2 ;

[0035] Figure 12 Schematic diagram of the steps for boron doping of the source and drain extension structures in Example 2. Figure 2 ;

[0036] Figure 13 This is a schematic diagram of the steps involved in forming the isolation layer in Example 2. Figure 2 ;

[0037] Figure 14 This is a schematic diagram of the SiGe / Si high aspect ratio etching steps in Example 2. Figure 2 ;

[0038] Figure 15 This is a schematic diagram of the epitaxial growth process for forming the source and drain electrodes in Example 2;

[0039] Figure 16 This is a schematic diagram of the source and drain ion implantation steps in Example 2;

[0040] Figure 17 This is a schematic diagram of the virtual gate removal steps in Example 2;

[0041] Figure 18 This is a schematic diagram of the channel release steps in Example 2;

[0042] Figure 19 This is a schematic diagram of the gate deposition steps in Example 2;

[0043] Figure 20This is a schematic diagram of the structure of a fully enclosed gate field-effect transistor in the background art;

[0044] In the picture:

[0045] 100. Fully enclosed gate field-effect transistor; 1. Substrate; 2. Source; 3. Gate structure; 301. Channel; 4. Drain; 5. Source extension structure; 6. Drain extension structure; 7. Isolation layer; 8. Oxide layer. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] The purpose of this invention is to provide a fully enclosed gate field-effect transistor and its fabrication method to solve the problems existing in the prior art. It can improve the on-state current and off-state leakage current of N-type and P-type field-effect transistors, significantly optimize the transistor's operating performance, and the P-type field-effect transistor does not require an increase in width-to-length ratio, thereby increasing the transistor density per unit area; it also increases the flexibility of circuit design.

[0048] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] Example 1

[0050] like Figure 1 As shown, this embodiment provides a fully enclosed gate field-effect transistor 100, characterized in that it includes a substrate 1, a source 2, a gate structure 3, a drain 4, and an extension structure. The extension structure includes a source extension structure 5 and / or a drain extension structure 6. The source 2, gate structure 3, drain 4, source extension structure 5, and drain extension structure 6 are all disposed on the same side of the substrate 1. The gate structure 3 is disposed between the source 2 and the drain 4. The source extension structure 5 is disposed between the source 2 and the gate structure 3. The drain extension structure 6 is disposed between the drain 4 and the gate structure 3. The source 2 and the drain 4 are respectively ion-doped source and ion-doped drain. The source extension structure 5 and the drain extension structure 6 are both P-type ion-doped extension structures. The ion doping concentrations of the source 2 and the source extension structure 5 are different, and the ion doping concentrations of the drain 4 and the drain extension structure 6 are different.

[0051] This embodiment incorporates a source extension structure 5 and / or a drain extension structure 6. By altering the doping concentration of the source extension structure 5 and / or the drain extension structure 6, the transistor performance is changed. From an electronic current perspective, due to the different ion doping concentrations of the source 2 and the source extension structure 5, and the different ion doping concentrations of the drain 4 and the drain extension structure 6, the source extension structure 5 and / or the drain extension structure 6 can smooth out changes in doping concentration and reduce the peak electric field. The suppression effect of this structure on off-state leakage current can be attributed to the parasitic bipolar junction transistor (BJT). The source 2, drain 4, and channel 301 of the gate structure 3 of the Nanosheet GAAFET constitute the parasitic BJT. Channel 301 serves as the base, and the carrier current of channel 301 serves as the base current, which is amplified by the gain of the parasitic BJT. The source 2 and drain 4 serve as the emitter and collector of the BJT, respectively. From the perspective of band structure diagrams, PMOS exhibits greater band overlap than NMOS. In NMOS, higher concentrations of source extension structure 5 and / or drain extension structure 6 doping lead to a reverse increase in the tunneling width of channel 301-drain 4. This implies an increase in the tunneling width and effective base width of the parasitic BJT, thereby suppressing electron tunneling from channel 301 to drain 4, reducing the hole concentration in channel 301, and consequently reducing the parasitic BJT and improving off-state leakage current. In PMOS, higher concentrations of source extension structure 5 and / or drain extension structure 6 doping slightly reduce the tunneling width of channel 301-drain 4, i.e., reducing the tunneling width and effective base width of the parasitic BJT. This facilitates hole tunneling, enhances the parasitic BJT, and increases off-state leakage current. This invention can improve the on-state current and off-state leakage current of N-type and P-type field-effect transistors, significantly optimize transistor performance, and P-type field-effect transistors do not require an increase in aspect ratio, thereby increasing transistor density per unit area; it also increases the flexibility of circuit design.

[0052] In this embodiment, the extended structure includes a source extended structure 5 and a drain extended structure 6.

[0053] In this embodiment, the source 2 and drain 4 of the N-type field-effect transistor are respectively the source and drain doped with N-type ions. The P-type ion doping concentration of the source extension structure 5 of the N-type field-effect transistor is higher than the N-type ion doping concentration of the source 2, and the P-type ion doping concentration of the drain extension structure 6 of the N-type field-effect transistor is higher than the N-type ion doping concentration of the drain 4.

[0054] In this embodiment, the source 2 and drain 4 of the P-type field-effect transistor are respectively the source and drain doped with P-type ions. The P-type ion doping concentration of the source extension structure 5 of the P-type field-effect transistor is higher than that of the source 2, and the P-type ion doping concentration of the drain extension structure 6 of the P-type field-effect transistor is higher than that of the drain 4.

[0055] In this embodiment, the gate structure 3 includes a channel 301, the source extension structure 5 is disposed between the source 2 and the channel 301, and the drain extension structure 6 is disposed between the drain 4 and the channel 301. The source extension structure 5 and the drain extension structure 6 are respectively in contact with both sides of the channel 301.

[0056] The simulation results of the Sentaurus TCAD software for the fully enclosed gate field-effect transistor 100 are as follows: Figure 3 and 4 As shown, where, Figure 3 The figures show NMOS simulation results. The left side of the graph represents the off-state leakage current at various doping concentrations, and the right side represents the on-state current at various doping concentrations. (The last part, "1×10," appears to be an incomplete sentence or fragment and doesn't translate directly. It likely refers to a 1×10^10 NMOS simulation and is omitted from the translation.) 19 ~1.1×10 20 Within the range of additional P-type doping concentrations, the off-state leakage current of NMOS decreases significantly with increasing additional doping concentration, and the on-state current also decreases significantly with increasing additional doping concentration. Figure 4 The simulation results for PMOS are shown. The right side of the figure represents the off-state leakage current at various doping concentrations, and the left side represents the on-state current at various doping concentrations. The off-state leakage current of PMOS increases slightly with the increase of additional doping concentration, and the on-state current also increases slightly with the increase of additional doping concentration.

[0057] Example 2

[0058] This embodiment provides a method for fabricating a fully enclosed gate field-effect transistor 100, including the following steps:

[0059] A substrate 1 is obtained, and a source electrode 2, a gate structure 3, a drain electrode 4, and an extension structure are fabricated on one side of the substrate 1. The extension structure includes a source extension structure 5 and / or a drain extension structure 6. The gate structure 3 is disposed between the source electrode 2 and the drain electrode 4, the source extension structure 5 is disposed between the source electrode 2 and the gate structure 3, and the drain extension structure 6 is disposed between the drain electrode 4 and the gate structure 3. Before the source electrode 2 is fabricated, P-type ion doping is performed on the source extension structure 5, and before the drain electrode 4 is fabricated, P-type ion doping is performed on the drain extension structure 6. Ion doping is performed on the source electrode 2 and the drain electrode 4, and the ion doping concentrations of the source electrode 2 and the source extension structure 5 are different, as are the ion doping concentrations of the drain electrode 4 and the drain extension structure 6.

[0060] In this embodiment, when processing an N-type field-effect transistor, N-type ions are doped into the source 2 and drain 4, so that the P-type ion doping concentration of the source extension structure 5 is higher than the N-type ion doping concentration of the source 2, and the P-type ion doping concentration of the drain extension structure 6 is higher than the N-type ion doping concentration of the drain 4; when processing a P-type field-effect transistor, P-type ions are doped into the source 2 and drain 4, so that the P-type ion doping concentration of the source extension structure 5 is higher than the P-type ion doping concentration of the source 2, and the P-type ion doping concentration of the drain extension structure 6 is higher than the P-type ion doping concentration of the drain 4.

[0061] In this embodiment, the source extension structure 5 and the drain extension structure 6 are fabricated using an etching process, and the source 2, drain 4, source extension structure 5 and drain extension structure 6 are ion-doped using an ion implantation process.

[0062] In this embodiment, the fabrication method of the source extension structure 5 and the drain extension structure 6 includes:

[0063] S1. Obtain substrate 1, and grow SiGe layers and Si layers alternately and stacked on substrate 1 to form an extension layer;

[0064] S2. A groove is processed in the middle of the extended layer, and the remaining part of the extended layer forms two fin structures. A virtual gate is set in the groove.

[0065] S3. An isolation layer 7 is processed on the end of each fin structure near the virtual gate. Using one isolation layer 7 as a hard mask, the material of the end of the corresponding fin structure away from the virtual gate is removed by etching process to form the source extension structure 5. Using another isolation layer 7 as a hard mask, the material of the end of the corresponding fin structure away from the virtual gate is removed by etching process to form the drain extension structure 6.

[0066] In this embodiment, the P-type ion doping method for the source extension structure 5 and the drain extension structure 6 includes: before processing the isolation layer 7 of the source extension structure 5 or the drain extension structure 6, doping the source extension structure 5 or the drain extension structure 6 with P-type ions to ensure that the implantation is not blocked by the isolation layer 7.

[0067] This invention is primarily applicable to a fully enclosed gate field-effect transistor 100 with a channel 301 consisting of a nanowire structure and a nanosheet structure, including single-layer nanosheet / nanowire structures and multi-layer vertically stacked nanosheet / nanowire structures. Taking a single-layer nanosheet structure as an example, the complete fabrication steps in this embodiment include:

[0068] Step 1: Select a suitable Si wafer as substrate 1, such as... Figure 5 As shown.

[0069] Step 2: Epitaxially stacked SiGe / Si on Si substrate 1. Remote plasma chemical vapor deposition (RPCVD) was used for growth, with Si grown at 650℃ and SiGe grown at 600℃. Figure 6 As shown.

[0070] Step 3: Under low-temperature conditions, a fin structure is defined using Self-Aligned Double Patterning (SADP) technology. The fin structure is then etched using Inductively Coupled Plasma-Reactive Ion Etching (ICP-RIE) technology, as shown below. Figure 7 As shown.

[0071] Step 4: Shallow Trench Isolation (STI): SiN and SiO2 are deposited separately using low-pressure chemical vapor deposition, such as... Figure 8 As shown.

[0072] Step 5: Wet etching exposes the fin structure. SiO2 is etched using a buffered oxide etchant (BOE). SiN is then etched using a hot phosphoric acid solution. Figure 9 As shown.

[0073] Step 6: Virtual Gate Patterning. Polycrystalline Si and SiN are deposited using Low Pressure Chemical Vapor Deposition (LPCVD), such as... Figure 10 As shown; then, excess SiN and polycrystalline Si are etched, as... Figure 11 As shown.

[0074] Step 7: Source extension structure 5 and drain extension structure 6 are boron doped using ion implantation, such as... Figure 12 As shown.

[0075] Step 8: Formation of isolation layer 7. SiO2 is grown by thermal oxidation as isolation layer 7, such as... Figure 13 As shown.

[0076] Step 9: SiGe / Si high aspect ratio etching. The SiO2 isolation layer 7 can act as a hard mask to protect the underlying source extension structure 5 and the extension structure, thus saving the photolithography steps that would otherwise be required. Figure 14 As shown.

[0077] Step 10: Epitaxial growth to form source 2 and drain 4, as shown Figure 15 As shown.

[0078] Step 11: Ion implantation at source 2 and drain 4, as follows Figure 16 As shown, the material was subjected to high-concentration doping, with boron doping using high-temperature (400°C) ion implantation and phosphorus doping using room-temperature ion implantation. The doping was then activated using rapid annealing at 1035°C.

[0079] Step 12: Remove the virtual gate, as shown Figure 17 As shown.

[0080] Step 13: Release channel 301, as follows Figure 18 As shown, SiGe / Si etching with high etching selectivity is performed using HCl, with an etching selectivity of approximately 90:1 between SiGe and Si.

[0081] Step 14: Deposit gate oxide layer 8 (SiO2 layer), HfO2 layer 6, and work function metal layer, commonly TiN, TiC, etc. Figure 19 As shown.

[0082] This embodiment uses isolation layer 7 as a hard mask, saving a photolithography step and thus saving one mask. In other words, the fabrication method provided in this embodiment does not require an additional photolithography step, resulting in no significant increase in overall process complexity compared to the original process. Simultaneously, it saves substantial costs associated with additional mask fabrication and photolithography processes. This process method allows for effective control of the off-state leakage current and on-state current in Nanosheet GAAFETs with simple process variations, thereby enabling adjustment of transistor device performance. Furthermore, this process allows for independent adjustment of the doping concentration of the source extension structure 5 and the drain extension structure 6, i.e., additional asymmetric doping concentration, providing greater flexibility in transistor device performance control.

[0083] Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. Furthermore, those skilled in the art will recognize that, based on the ideas of this invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A fully enclosed gate field-effect transistor, characterized in that: The device includes a substrate, a source, a gate structure, a drain, and an extended structure. The extended structure includes a source extended structure and / or a drain extended structure. The source, the gate structure, the drain, the source extended structure, and the drain extended structure are all disposed on the same side of the substrate. The gate structure is disposed between the source and the drain. The source extended structure is disposed between the source and the gate structure. The drain extended structure is disposed between the drain and the gate structure. The source and the drain are respectively ion-doped. Both the source extended structure and the drain extended structure are P-type ion-doped extended structures. The ion doping concentrations of the source and the source extended structure are different, and the ion doping concentrations of the drain and the drain extended structure are also different. The P-type ion doping concentration of the source extended structure is higher than that of the source, and the P-type ion doping concentration of the drain extended structure is higher than that of the drain.

2. The fully enclosed gate field-effect transistor according to claim 1, characterized in that: The source and drain of the N-type field-effect transistor are respectively N-type ion-doped source and N-type ion-doped drain. The P-type ion doping concentration of the source extension structure of the N-type field-effect transistor is higher than the N-type ion doping concentration of the source, and the P-type ion doping concentration of the drain extension structure of the N-type field-effect transistor is higher than the N-type ion doping concentration of the drain.

3. The fully enclosed gate field-effect transistor according to claim 1, characterized in that: The source and drain of the P-type field-effect transistor are respectively P-type ion doped source and P-type ion doped drain. The P-type ion doping concentration of the source extension structure of the P-type field-effect transistor is higher than that of the source, and the P-type ion doping concentration of the drain extension structure of the P-type field-effect transistor is higher than that of the drain.

4. The fully enclosed gate field-effect transistor according to claim 1, characterized in that: The gate structure includes a channel, the source extension structure is disposed between the source and the channel, and the drain extension structure is disposed between the drain and the channel.

5. A method for fabricating a fully enclosed gate field-effect transistor, characterized in that: Includes the following steps: A substrate is obtained, and a source, gate, drain, and extended structure are fabricated on one side of the substrate. The extended structure includes a source extended structure and / or a drain extended structure. The gate structure is disposed between the source and the drain, the source extended structure is disposed between the source and the gate structure, and the drain extended structure is disposed between the drain and the gate structure. Before the source fabrication is completed, P-type ion doping is performed on the source extended structure, and before the drain fabrication is completed, P-type ion doping is performed on the drain extended structure. Ion doping is performed on the source and the drain, and the ion doping concentrations of the source and the source extended structure are different, as are the ion doping concentrations of the drain and the drain extended structure. The P-type ion doping concentration of the source extended structure is higher than that of the source, and the P-type ion doping concentration of the drain extended structure is higher than that of the drain.

6. The method for fabricating a fully enclosed gate field-effect transistor according to claim 5, characterized in that: When fabricating an N-type field-effect transistor, N-type ions are doped into the source and the drain, such that the P-type ion doping concentration of the source extension structure is higher than the N-type ion doping concentration of the source, and the P-type ion doping concentration of the drain extension structure is higher than the N-type ion doping concentration of the drain; when fabricating a P-type field-effect transistor, P-type ions are doped into the source and the drain, such that the P-type ion doping concentration of the source extension structure is higher than the P-type ion doping concentration of the source, and the P-type ion doping concentration of the drain extension structure is higher than the P-type ion doping concentration of the drain.

7. The method for fabricating a fully enclosed gate field-effect transistor according to claim 5, characterized in that: The source extension structure and the drain extension structure are fabricated using an etching process, and ion doping is performed on the source extension structure and the drain extension structure using an ion implantation process.

8. The method for fabricating a fully enclosed gate field-effect transistor according to any one of claims 5-7, characterized in that: The fabrication method for the source extension structure and the drain extension structure includes: S1. Obtain the substrate, and alternately and stack SiGe layers and Si layers on the substrate to form an extended layer; S2. A groove is processed in the middle of the extended layer, and the remaining part of the extended layer forms two fin structures, and a virtual gate is set in the groove; S3. An isolation layer is processed on one end of each fin structure near the virtual gate. Using one isolation layer as a hard mask, the material of the corresponding fin structure away from the virtual gate is removed by an etching process to form the source extension structure. Using the other isolation layer as a hard mask, the material of the corresponding fin structure away from the virtual gate is removed by an etching process to form the drain extension structure.

9. The method for fabricating a fully enclosed gate field-effect transistor according to claim 8, characterized in that: The P-type ion doping method for the source extension structure and the drain extension structure includes: doping the source extension structure or the drain extension structure with P-type ions before processing the isolation layer.

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