Waveguide-coupled photodetector and method of fabrication thereof

Abstract

The application discloses a waveguide-coupled photodetector, which comprises an SOI substrate, a hollow silica template cavity, a Ge 1‑x Sn x absorption region and an electrode; the SOI substrate comprises a silicon substrate layer and a buried oxide layer which are sequentially connected, a strip waveguide, a taper structure and a top silicon layer which are sequentially arranged on the buried oxide layer; the hollow silica template cavity is arranged above the top silicon layer of the SOI substrate, and a bottom silica layer of the hollow silica template cavity is provided with a window so that part of the top silicon layer is exposed; the Ge 1‑x Sn x absorption region is arranged in the hollow silica template cavity; and the electrode is arranged above the hollow silica template cavity and electrically connected with the Ge 1‑x Sn x absorption region. The waveguide-coupled photodetector of the application can reduce the loss and attenuation of the optical signal caused by the Ge / Si interface defects and dislocations, and improve the performance of the device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of optoelectronic materials and devices, and particularly relates to a waveguide-coupled photodetector, and more particularly relates to a preparation method of the waveguide-coupled photodetector. BACKGROUND

[0002] With the continuous improvement of the demand for intelligent applications such as big data, cloud computing, and AI, the rapid development of the new generation of information technology is promoted. As an important development frontier, optical chips replace electrons as information carriers, and exhibit the performance advantages of high speed, high density, low cost, and low power consumption. Due to good electrical characteristics and CMOS process compatibility, silicon-based optoelectronic integration has become the most promising method at present.

[0003] A silicon-based photodetector is one of the important devices of silicon-based optoelectronic integration. Since the energy band structure of silicon cannot well respond to short-wave infrared and mid-infrared wavebands, Ge 1- x Sn x material is introduced, which has excellent photoelectric properties and CMOS process compatibility. 1-x Sn x The photodetector is mainly divided into two device structures, namely, surface incidence and waveguide coupling, according to different light incidence modes. Compared with the surface incidence structure, the photodetector with the waveguide coupling structure is more easily integrated with other optical waveguide devices, and is suitable for on-chip integration applications. At the same time, in the photodetector with the waveguide coupling structure, the incidence direction of light is perpendicular to the transport direction of carriers, which can basically break the mutual restriction between responsivity and bandwidth, and improve the bandwidth while obtaining relatively high device responsivity. However, in the current photodetector related technology, the silicon-based Ge 1-x Sn x photodetector often has performance limitations due to the interface defects generated by the lattice mismatch at the silicon-germanium heterojunction interface, and therefore, it is necessary to improve the structure of the existing waveguide-coupled photodetector. SUMMARY

[0004] The present application is based on the discovery and understanding of the inventors of the following facts and problems: In the related waveguide-coupled Ge 1-x Sn x photodetector, the evanescent wave coupling structure is more common, and the Ge 1-x Sn x absorption layer is above the silicon waveguide. After the light signal from the silicon waveguide reaches the lower side of the absorption layer, the light signal is coupled into the Ge 1-x Sn x absorption layer with a larger refractive index than silicon through evanescent wave coupling, and the absorption of light is realized. The heterojunction of silicon-germanium is the interface through which the evanescent wave is coupled from the silicon waveguide into the Ge 1-xSn x The dislocation and defect at the heterojunction interface will cause non-radiative recombination absorption of photons, reduce the number of effective photo-generated carriers, and further cause high dark current and low responsivity of the detector device.

[0005] The present application aims to at least solve one of the technical problems in the related art. To this end, an embodiment of the present application proposes a waveguide coupled photodetector, which is not directly provided with Ge 1-x Sn x Absorption layer on the SOI substrate, but by setting a hollow silica template cavity on the SOI substrate, and then epitaxially growing a germanium material in the cavity, so that the process of coupling the optical signal into the detector does not pass through the silicon-germanium heterojunction, thereby improving the performance of the device.

[0006] The waveguide coupled photodetector of the embodiment of the present application comprises: an SOI substrate, a hollow silica template cavity, a Ge 1-x Sn x Absorption region and electrode;

[0007] The SOI substrate comprises a silicon substrate layer and a buried oxide layer connected in sequence, a strip waveguide, a taper structure and a top silicon layer connected in sequence are arranged on the buried oxide layer, and the strip waveguide and the taper structure are connected with the Ge 1-x Sn x Absorption region is located at the same center along the light propagation direction;

[0008] The hollow silica template cavity is arranged above the top silicon layer of the SOI substrate, a bottom window is arranged on the bottom silica layer of the silica template cavity to expose part of the top silicon layer of the SOI substrate, and an electrode hole is arranged on the top silica layer of the silica template cavity;

[0009] The Ge 1-x Sn x Absorption region is arranged in the hollow silica template cavity, and the Ge 1-x Sn x Absorption region comprises a germanium buffer layer and a Ge 1-x Sn x Absorption layer, the germanium buffer layer is arranged in the cavity between the bottom window and the top of the hollow silica template cavity along the direction perpendicular to the top silicon layer; and the Ge 1-x Sn x Absorption layer comprises a P-type doped layer, an intrinsic layer and an N-type doped layer connected in sequence, and the P-type doped layer is connected with the germanium buffer layer, wherein 0≤x≤1;

[0010] The electrode is arranged above the hollow silica template cavity, and is connected with the Ge 1-x Sn x The absorption region is electrically connected.

[0011] The waveguide-coupled photodetector has the following advantages and technical effects:

[0012] 1. The waveguide-coupled photodetector is not directly arranged with a Ge 1-x Sn x absorption layer on the SOI substrate, but a hollow silica template cavity is arranged, a window is arranged at the bottom of the silica template cavity to expose the top silicon layer of the SOI substrate, a germanium buffer layer is arranged at the bottom window of the silica template cavity, the area of the silicon-germanium heterojunction interface is reduced, a Ge 1-x Sn x absorption layer is arranged outside the germanium buffer layer, and a transverse PIN photodetector structure is formed in the hollow silica template cavity. 1-x Sn x The waveguide-coupled photodetector structure is coupled into the Ge 1-x Sn x absorption layer through the extremely thin silica layer at the bottom of the silica template cavity in the form of an evanescent wave, without passing through the silicon-germanium heterojunction interface, so that the loss and attenuation of the optical signal caused by the high-density defects and dislocations of the original silicon-germanium interface are effectively reduced, the adverse effects of the interface defects on the carrier transport are significantly weakened, and an effective photo-generated carrier absorption rate of up to 94.5% in the absorption region is achieved, and the optical responsivity at 1310 nm is 1.2 A / W. Compared with the prior art of directly arranging a Ge

[0013] 2. The waveguide-coupled photodetector effectively improves the absorption rate of photo-generated carriers, and under the premise of maintaining the same level of photo-generated carrier absorption efficiency, the device design can be simplified to realize smaller size and area, which not only reduces the demand for raw materials and resource consumption in the production process, but also promotes the development of photoelectric elements to higher integration and finer direction, and lays a solid foundation for the future development of photoelectric integration technology.

[0014] In some embodiments, the thickness of the bottom silica layer of the hollow silica template cavity is 20-100 nm, and is preferably 50 nm.

[0015] In some embodiments, the bottom window of the hollow silica template cavity has a length of 10-12 microns and a width of 2-3 microns.

[0016] The application also discloses a preparation method of the waveguide-coupled photodetector.

[0017] a. Forming a buried oxide layer on a silicon substrate, depositing a silicon layer on the buried oxide layer, processing the silicon layer to obtain a strip waveguide, a taper structure and a top silicon layer, and preparing an SOI substrate;

[0018] b. Preparing a hollow silica template cavity base on the top silicon layer, opening a bottom window on a bottom silica layer of the silica template cavity base to expose part of the top silicon layer, and opening a window at another end of the silica template cavity base away from the bottom window in a horizontal direction of the silica template cavity base;

[0019] c. Depositing a germanium buffer layer at the bottom window in the silica template cavity base, growing the germanium buffer layer in a direction perpendicular to the top silicon layer to the top of the silica template cavity base, and successively growing a P-type doped layer, an intrinsic layer and an N-type doped layer on the germanium buffer layer to form a Ge 1-x Sn x absorption layer, wherein 0≤x≤1, and preparing a Ge 1-x Sn x absorption region in the hollow silica template cavity base;

[0020] d. Depositing a silica layer outside the Ge 1-x Sn x absorption region to close the hollow silica template cavity base and form a hollow silica template cavity;

[0021] e. Preparing an electrode on the top of the hollow silica template cavity and electrically connecting the electrode with the Ge 1-x Sn x absorption region to prepare the waveguide-coupled photodetector.

[0022] The preparation method of the waveguide-coupled photodetector of the embodiment of the application has the following advantages and technical effects:

[0023] 1. The method of the embodiment of the application uses a template-assisted epitaxy method to prepare a Ge 1-x Sn x waveguide-coupled photodetector, and does not directly grow a Ge 1-x Sn x absorption region on the SOI substrate, but first prepares a hollow silica template cavity base, opens a window at the bottom of the silica template cavity base to expose the top silicon layer, and epitaxially grows a germanium buffer layer and a Ge1-x Sn x absorbing layer, to form a transverse PIN photodetector structure; the photodetector prepared by the embodiment of the present application is coupled into Ge by a very thin silicon dioxide layer at the bottom of the silicon dioxide template cavity through the mode of evanescent wave coupling, instead of passing through the germanium-silicon heterojunction interface 1-x Sn x absorbing layer, which effectively reduces the loss and attenuation of the original germanium-silicon interface high-density defects and dislocations on the optical signal, significantly weakens the adverse effects of interface defects on carrier transport, and realizes an effective photo-generated carrier absorption rate of up to 94.5% in the absorbing region;

[0024] 2. Compared with the prior art of directly growing Ge 1-x Sn x absorbing layer, the optical responsivity at 1310 nm is 1.2 A / W, which effectively enhances the optical responsivity of the device and reduces the dark current level of the device, opening up a new way for optimization of photoelectric conversion efficiency;

[0025] 3. The method of the embodiment of the present application can effectively improve the absorption rate of photo-generated carriers, and under the premise of maintaining the same level of photo-generated carrier absorption efficiency, the device design can be simplified, the size and area of the device can be reduced, which not only reduces the demand for raw materials, but also reduces resource consumption in the production process, and promotes the development of photoelectric elements to higher integration and finer.

[0026] In some embodiments, the method for manufacturing the hollow silicon dioxide template cavity base in step b comprises:

[0027] b1, depositing silicon dioxide on the top silicon layer to form a bottom silicon dioxide layer, and processing a bottom window on the bottom silicon dioxide layer to expose part of the top silicon layer;

[0028] b2, depositing a silicon layer on the bottom silicon dioxide layer, processing the silicon layer and depositing silicon dioxide around the silicon layer to form a silicon dioxide cladding layer, so that the silicon layer is surrounded by the silicon dioxide cladding layer;

[0029] b3, a window is opened on the silicon dioxide cladding layer, which is located at both ends of the silicon layer along the horizontal direction with the bottom window, the silicon layer is removed through the window to expose the top silicon layer at the bottom window, and a hollow silicon dioxide template cavity base is prepared.

[0030] In some embodiments, the deposition method of the silicon dioxide in step b1 and / or step b2 comprises thermal oxidation method, normal pressure chemical vapor deposition method, low pressure chemical vapor deposition method or plasma chemical vapor deposition method.

[0031] In some embodiments, in step b2, the silicon layer is made of polycrystalline silicon or amorphous silicon; and / or, the deposition of the silicon layer comprises plasma chemical vapor deposition.

[0032] In some embodiments, in step b3, the removal of the silicon layer comprises etching the silicon layer by wet etching.

[0033] In some embodiments, in step b1, the processing of the bottom window comprises processing the silicon dioxide layer by electron beam exposure or inductively coupled plasma etching.

[0034] In some embodiments, in step b3, the processing of the window on the silicon dioxide cladding layer comprises processing the silicon dioxide cladding layer by electron beam exposure or inductively coupled plasma etching.

[0035] In some embodiments, in step c, the growth of the germanium buffer layer, the P-type doped layer, the intrinsic layer or the N-type doped layer comprises at least one of chemical vapor deposition and high-temperature diffusion.

[0036] In some embodiments, in step e, the preparation of the electrode comprises: preparing an electrode hole on the top of the hollow silicon dioxide template cavity by electron beam exposure or inductively coupled plasma etching, evaporating metal in the electrode hole by electron beam evaporation to obtain the electrode; preferably, the metal comprises at least one of Ni, Cr, Ti and Au. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a structural schematic diagram of a waveguide-coupled photodetector according to an embodiment of the present application, and the direction of light propagation in the waveguide is parallel to the x-axis in the device coordinate axis.

[0038] Figures 2a-2m is a flowchart of a preparation method of a waveguide-coupled photodetector according to an embodiment of the present application;

[0039] a: forming a buried oxide layer on a silicon substrate; b: obtaining an SOI substrate; c: forming a bottom silicon dioxide layer of a hollow silicon dioxide template cavity; d: opening a bottom window on the bottom silicon dioxide layer of the silicon dioxide template cavity; e: depositing a silicon layer on the bottom silicon dioxide layer; f: processing and thinning the silicon layer; g: patterning the silicon layer; h: depositing a silicon dioxide cladding layer outside the silicon layer; i: opening a window on the silicon dioxide cladding layer; j: removing the silicon layer; k: forming a Ge 1-x Sn x absorption region; l: depositing silicon dioxide outside the Ge 1-x Sn x absorption region; m: preparing an electrode.

[0040] Figure 3 is a side light field distribution diagram of a waveguide-coupled photodetector prepared in Example 1 of the present application.

[0041] Figure 4 is a photo-generated carrier absorption power diagram of a waveguide-coupled photodetector prepared in Example 1 of the present application.

[0042] Figure 5 is a light responsivity curve diagram of a waveguide-coupled photodetector prepared in Example 1 of the present application under different bias voltages.

[0043] Figure 6 is a structure schematic diagram of a waveguide-coupled photodetector of Comparative Example 1.

[0044] Figure 7 is a light responsivity curve diagram of a waveguide-coupled photodetector of Comparative Example 1 under different bias voltages.

[0045] The figure legend: SOI substrate 100; silicon substrate layer 110; buried oxide layer 120; top silicon layer 130; strip waveguide 140; taper structure 150; bottom silicon dioxide layer 200; silicon layer 300; silicon dioxide template layer 400; Ge 1-x Sn x absorption region 500; electrode 600. DETAILED DESCRIPTION

[0046] Embodiments of the present application are described in detail below, examples of which are shown in the accompanying drawings. The embodiments described below by reference to the drawings are exemplary and are intended to explain the present application, and cannot be understood as limiting the present application.

[0047] As Figure 1 shown, the waveguide-coupled photodetector of the embodiment of the present application comprises: SOI substrate 100, hollow silicon dioxide template cavity, Ge 1-x Sn x absorption region 500 and electrode 600; the SOI substrate 100 comprises silicon substrate layer 110 and buried oxide layer 120 connected in sequence, and the buried oxide layer 120 is provided with strip waveguide 140, taper structure 150 and top silicon layer 130 connected in sequence. The strip waveguide 140, the taper structure 150 and the Ge 1-x Sn x absorption region 500 are located at the same center along the light propagation direction. The taper structure 150 is used for the transition of the light field width between the strip waveguide 140 and the Ge 1-x Sn x absorption region 500.

[0048] The hollow silica template cavity is composed of a bottom silica layer 200 and a silica template layer 400.

[0049] Ge 1-x Sn x The absorption region 500 is arranged in the hollow silica template cavity, Ge 1-x Sn x The absorption region 500 includes a germanium buffer layer and a Ge 1-x Sn x The absorption layer, the germanium buffer layer is arranged in the cavity between the bottom window of the bottom silica layer 200 of the silica template cavity and the top in the direction perpendicular to the top silicon layer 130; Ge 1-x Sn x The absorption layer includes a P-type doped layer, an intrinsic layer and an N-type doped layer connected in sequence, and the P-type doped layer is connected with the germanium buffer layer, wherein 0≤x≤1.

[0050] The electrode 600 is arranged above the hollow silica template cavity and is connected with the Ge 1-x Sn x The absorption region 500 is electrically connected.

[0051] The waveguide-coupled photodetector of the embodiment of the present application does not directly arrange a Ge 1-x Sn x absorption region on the SOI substrate, but arranges a hollow silica template cavity, a window is arranged at the bottom of the silica template cavity to expose the top silicon layer of the SOI substrate, a germanium buffer layer is arranged at the bottom window of the silica template cavity to reduce the area of the silicon germanium heterojunction, a Ge1-xSnx absorption layer is arranged outside the germanium buffer layer, and a transverse PIN photodetector structure is formed in the hollow silica template cavity. 1-x Sn x The absorption layer, and the light signal does not pass through the germanium-silicon heterojunction, thereby effectively reducing the loss and attenuation of the original germanium-silicon interface high-density defects and dislocations on the light signal, significantly weakening the adverse effects of interface defects on carrier transport, and realizing an effective photo-generated carrier absorption rate of up to 94.5% in the absorption region. 1-x Sn xThe waveguide-coupled photodetector of the embodiment of the present application can effectively enhance the light responsivity of the device and reduce the dark current level of the device, and the light responsivity at 1310nm is 1.2A / W, which opens up a new way for optimization of photoelectric conversion efficiency;

[0052] The waveguide-coupled photodetector of the embodiment of the present application can effectively improve the absorption rate of photo-generated carriers, and can simplify the device design, realize smaller size and area, reduce the demand for raw materials, reduce resource consumption in the production process, promote the development of photoelectric elements to higher integration and finer, and lay a solid foundation for the future development of photoelectric integration technology.

[0053] In some embodiments, the thickness of the bottom silicon dioxide layer 200 of the silicon dioxide template cavity is 20-100nm, preferably 50nm. In the embodiment of the present application, the thickness of the bottom silicon dioxide layer of the silicon dioxide template cavity is preferably selected to enable the light signal to be coupled into Ge 1-x Sn x The absorption layer is advantageous to improve the absorption efficiency of the absorption layer, reduce the dark current level of the device, and enhance the light responsivity of the device.

[0054] In some embodiments, the length of the bottom window of the silicon dioxide template cavity is 10-12um, and the width is 2-3um. In the embodiment of the present application, the top silicon layer of the SOI substrate is exposed at the bottom window of the silicon dioxide template cavity, and a germanium buffer layer is arranged at the window to further realize epitaxial growth of Ge 1-x Sn x The absorption layer. The size of the bottom window is not particularly limited in the embodiment of the present application, as long as the germanium buffer layer can be grown on the exposed top silicon layer at the window.

[0055] The embodiment of the present application also provides a preparation method of a waveguide-coupled photodetector, comprising the following steps:

[0056] a. Forming a buried oxide layer on a silicon substrate, depositing a silicon layer on the buried oxide layer, processing the silicon layer to obtain a strip waveguide, a taper structure and a top silicon layer, and preparing an SOI substrate;

[0057] b. Manufacturing a hollow silicon dioxide template cavity base on the top silicon layer, opening a bottom window on the bottom silicon dioxide layer of the silicon dioxide template cavity base to expose part of the top silicon layer, and opening a window at the other end of the silicon dioxide template cavity base in the horizontal direction and away from the bottom window;

[0058] c. Deposit a germanium buffer layer at the bottom window of the silicon dioxide template cavity substrate, growing the germanium buffer layer to the top of the silicon dioxide template cavity substrate in a direction perpendicular to the top silicon layer. Continue to grow a P-type doped layer, an intrinsic layer, and an N-type doped layer sequentially outside the germanium buffer layer to form a Ge layer. 1-x Sn x An absorption layer, wherein 0 ≤ x ≤ 1, is formed within the hollow silica template cavity matrix to complete the Ge process. 1-x Sn x Preparation of the absorption region;

[0059] d. In the Ge 1-x Sn x A silica layer is deposited outside the absorption region to seal the hollow silica template cavity substrate, forming a hollow silica template cavity;

[0060] e. Fabricate an electrode at the top of the hollow silica template cavity and connect it with the Ge 1-x Sn x The absorption region is electrically connected to fabricate a waveguide-coupled photodetector.

[0061] The method of this invention employs a template-assisted epitaxy method to prepare Ge. 1-x Sn x Waveguide-coupled photodetectors do not directly grow Ge on SOI substrates 1-x Sn x Instead of using an absorption region, a hollow silicon dioxide template cavity substrate is first prepared. A window is opened at the bottom of the template cavity substrate to expose the top silicon layer. An epitaxial germanium buffer layer and Ge are then formed at the bottom window of the silicon dioxide template cavity substrate. 1-x Sn x An absorption layer is used to form a lateral PIN photodetector structure. In the photodetector fabricated in this embodiment, the optical signal is coupled into the Ge-silicon heterojunction via evanescent wave coupling, bypassing the germanium-silicon heterojunction interface, and instead through an extremely thin silicon dioxide layer at the bottom of the silicon dioxide template cavity. 1-x Sn x The absorption layer effectively reduces the loss and attenuation of optical signals caused by the high-density defects and dislocations at the original germanium-silicon interface, significantly weakens the adverse effects of interface defects on carrier transport, and achieves an effective photogenerated carrier absorption rate of up to 94.5% in the absorption region.

[0062] The method of this invention, compared to the prior art of directly growing Ge on SOI substrates, offers advantages over traditional methods. 1-x Sn x The absorption layer effectively enhances the photoresponsivity of the device and reduces the dark current level. The photoresponsivity at 1310nm is 1.2A / W, opening up new avenues for optimizing photoelectric conversion efficiency.

[0063] The method of the embodiment of the present application can effectively improve the absorption rate of photo-generated carriers, can simplify the device design, realize the reduction of the size and area of the device, and promote the development of the photoelectric element to a higher integration and a more fine direction under the premise of maintaining the same level of photo-generated carrier absorption efficiency.

[0064] In some embodiments, the method for manufacturing the hollow silica template cavity substrate in step b comprises:

[0065] b1, depositing silica on the top silicon layer to form a bottom silica layer, and processing a bottom window on the bottom silica layer to expose part of the top silicon layer;

[0066] b2, depositing a silicon layer on the bottom silica layer, processing the silicon layer, and depositing silica around the silicon layer to form a silica cladding layer, so that the silicon layer is surrounded by the silica cladding layer;

[0067] b3, opening a window on the silica cladding layer, the window being located at both ends of the silicon layer along the horizontal direction with the bottom window, removing the silicon layer through the window and exposing the top silicon layer at the bottom window to obtain the hollow silica template cavity substrate.

[0068] The window opened on the silica cladding layer in step b3 of the embodiment of the present application is not particularly limited, as long as the silicon layer can be removed, and the germanium buffer layer, the P-type doped layer, the intrinsic layer or the N-type doped layer can be deposited through the window in the subsequent process to form a Ge 1-x Sn x The absorption region can also be applied to the embodiment of the present application.

[0069] In some embodiments, the deposition method of the silica in step b1 and / or step b2 comprises a thermal oxidation method, an atmospheric pressure chemical vapor deposition method, a low pressure chemical vapor deposition method or a plasma chemical vapor deposition method. The low pressure chemical vapor deposition method (also referred to as LP-CVD) of the embodiment of the present application refers to a chemical vapor deposition method performed under a condition lower than one atmosphere.

[0070] In some embodiments, the silicon layer in step b2 is made of polycrystalline silicon or amorphous silicon.

[0071] In some embodiments, the deposition method of the silicon layer in step b2 comprises a plasma chemical vapor deposition method.

[0072] In some embodiments, the removal method of the silicon layer in step b3 comprises etching the silicon layer by using a wet etching method.

[0073] In some embodiments, in step b1, the processing method of the bottom window comprises processing the silicon dioxide layer by electron beam exposure or inductively coupled plasma etching.

[0074] In some embodiments, in step b3, the processing method of the window on the silicon dioxide cladding layer comprises processing the silicon dioxide cladding layer by electron beam exposure or inductively coupled plasma etching.

[0075] In some embodiments, in step c, the growth method of the germanium buffer layer, the P-type doped layer, the intrinsic layer or the N-type doped layer comprises at least one of chemical vapor deposition and high-temperature diffusion.

[0076] In some embodiments, in step e, the electrode is prepared by the following steps: preparing an electrode hole on the top of the hollow silicon dioxide template cavity by electron beam exposure or inductively coupled plasma etching, evaporating metal in the electrode hole by electron beam evaporation to obtain the electrode; preferably, the metal comprises at least one of Ni, Cr, Ti and Au.

[0077] The preparation method of the waveguide-coupled photodetector is described in detail below with reference to the embodiments and the accompanying drawings.

[0078] Embodiment 1: Preparation method of waveguide-coupled photodetector

[0079] (1) Preparation of SOI substrate

[0080] As shown in FIGS. 1 and 2, a buried oxide layer 120 with a thickness of 3 μm is formed on a silicon substrate 110, a silicon layer with a thickness of 220 nm is deposited on the buried oxide layer 120, a pattern is formed on the silicon layer by electron beam exposure technology, and a strip waveguide 140 and a taper structure 150 are obtained by inductively coupled plasma etching process (see FIG. 3), wherein the width of the strip waveguide 140 is 0.45 μm, the inlet width of the taper structure 150 is 0.45 μm, the outlet width is 2 μm, and the length is 50 μm, thereby obtaining an SOI substrate 100. Figure 2a 2b As shown in FIGS. 1 and 2, a buried oxide layer 120 with a thickness of 3 μm is formed on a silicon substrate 110, a silicon layer with a thickness of 220 nm is deposited on the buried oxide layer 120, a pattern is formed on the silicon layer by electron beam exposure technology, and a strip waveguide 140 and a taper structure 150 are obtained by inductively coupled plasma etching process (see FIG. 3), wherein the width of the strip waveguide 140 is 0.45 μm, the inlet width of the taper structure 150 is 0.45 μm, the outlet width is 2 μm, and the length is 50 μm, thereby obtaining an SOI substrate 100. Figure 1

[0081] (2) Preparation of hollow silicon dioxide template cavity base

[0082] As shown in FIGS. 1 and 2, a buried oxide layer 120 with a thickness of 3 μm is formed on a silicon substrate 110, a silicon layer with a thickness of 220 nm is deposited on the buried oxide layer 120, a pattern is formed on the silicon layer by electron beam exposure technology, and a strip waveguide 140 and a taper structure 150 are obtained by inductively coupled plasma etching process (see FIG. 3), wherein the width of the strip waveguide 140 is 0.45 μm, the inlet width of the taper structure 150 is 0.45 μm, the outlet width is 2 μm, and the length is 50 μm, thereby obtaining an SOI substrate 100. Figure 2c As shown in FIGS. 1 and 2, a buried oxide layer 120 with a thickness of 3 μm is formed on a silicon substrate 110, a silicon layer with a thickness of 220 nm is deposited on the buried oxide layer 120, a pattern is formed on the silicon layer by electron beam exposure technology, and a strip waveguide 140 and a taper structure 150 are obtained by inductively coupled plasma etching process (see FIG. 3), wherein the width of the strip waveguide 140 is 0.45 μm, the inlet width of the taper structure 150 is 0.45 μm, the outlet width is 2 μm, and the length is 50 μm, thereby obtaining an SOI substrate 100.

[0083] Figure 2d ​​​The pattern is formed on the bottom silicon dioxide layer 200 using electron beam lithography, and then a bottom window is formed on the bottom silicon dioxide layer 200 using inductively coupled plasma etching. The bottom window has a length of 10μm and a width of 3μm.

[0084] like Figure 2e A silicon layer 300, made of polycrystalline silicon, is deposited on the bottom silicon dioxide layer 200 using plasma chemical vapor deposition. The thickness of the grown silicon layer 300 should be greater than the height of the PIN structure in the detector to be fabricated.

[0085] like Figure 2f The silicon layer 300 was thinned using chemical mechanical polishing until it reached the thickness required by the detector.

[0086] like Figure 2g The silicon layer 300 is processed using electron beam lithography to meet Ge requirements. 1-x Sn x The size requirements of the absorption region 500. For example, the width of the processed silicon layer 300 along the light propagation direction should be similar to that of the desired Ge layer. 1-x Sn x The absorption region has a uniform width of 500, which can be 10 μm; its length in the direction perpendicular to the light propagation direction should be greater than the desired Ge content. 1-x Sn x The absorption region has a length of 500 μm, with an excess length of approximately 2–3 μm. This length can be set to 22 μm, and the portion exceeding the detector length will be... Figure 2d The window corresponds to the processed silicon dioxide layer 200. The processed silicon layer 300 has a thickness of 0.5 μm.

[0087] like Figure 2h A silicon dioxide coating layer is formed by depositing silicon dioxide around the silicon layer 300 using plasma chemical vapor deposition.

[0088] like Figure 2i Electron beam lithography was used to... Figure 2h A silicon dioxide coating layer is formed in the middle for processing, and a window is opened to expose the silicon coating layer 300. The opened window is in line with... Figure 2c The bottom windows of the bottom silicon dioxide layer 200 are located at both ends of the silicon layer 300 along the horizontal direction, which are the two ends of the detector to be fabricated.

[0089] like Figure 2j ,pass Figure 2i The window in the middle silica coating layer is completely etched by wet etching until the top silicon layer 130 below the bottom window in the bottom silica layer 200 is exposed, forming a hollow silica template cavity substrate.

[0090] (3) Preparation of Ge 1-x Sn x absorption region

[0091] As Figure 2k , a Ge buffer layer is first grown at the bottom window of the bottom silicon dioxide layer 200 by using an ultra-high vacuum chemical vapor deposition method (UHV / CVD) performed at a pressure lower than 10 -6 Pa), and then a P-type doped layer, an intrinsic layer, and an N-type doped layer of Ge 1-x Sn x are sequentially prepared on the Ge buffer layer by using a high-temperature diffusion method, to finally form a Ge 1-x Sn x absorption region 500.

[0092] (5) Preparation of a hollow silicon dioxide template cavity

[0093] As Figure 2l , a silicon dioxide layer is deposited on the above-formed PIN structure, i.e., the Ge 1-x Sn x absorption region 500 by using a chemical vapor deposition technique, a passivation treatment is performed, a silicon dioxide template cavity substrate is closed, and a silicon dioxide template layer 400 is formed, which, together with the bottom silicon dioxide layer 200, forms a hollow silicon dioxide template cavity, the cavity of which encapsulates the Ge 1-x Sn x absorption region 500.

[0094] (5) Preparation of an electrode

[0095] As Figure 2l , an electrode pattern is formed on the top of the silicon dioxide template cavity by using electron beam exposure, and the top silicon dioxide layer of the silicon dioxide template cavity is etched to form an electrode hole by using an inductively coupled plasma etching technique.

[0096] As Figure 2m , metal Ni is evaporated in the electrode hole by using an electron beam evaporation technique, to form a metal electrode 600 electrically connected with the Ge 1- x Sn x absorption region 500, to obtain a waveguide-coupled photodetector.

[0097] The waveguide-coupled photodetector prepared in this embodiment is subjected to performance testing, and the test results are shown in Figures 3-5 .

[0098] Test conditions: The waveguide-coupled photodetector is tested under a 1310 nm single-mode light source.

[0099] Figure 3This is a side view of the optical field distribution of the waveguide-coupled photodetector prepared in Example 1. The values ​​represent electric field strength; the larger the value, the stronger the electric field, and consequently, the stronger the optical field at that location. Figure 3 As shown, light propagates along the strip waveguide 140 and the taper structure 150 to the device, and is coupled upwards to the GeGen structure via an evanescent wave. 1-x Sn x Absorption region 500. Ge 1-x Sn x The light field intensity is greatest at the front end of the absorption region, gradually attenuating along the x-direction as light propagates, and decreasing to a very small value at the end of the device.

[0100] Figure 4 The image shows the photogenerated carrier absorption power of the waveguide-coupled photodetector prepared in Example 1. The waveguide-coupled photodetector prepared in Example 1 effectively reduces the influence of defects at the germanium-silicon heterojunction interface on carriers, resulting in an effective photogenerated carrier absorption rate of 94.5% in the absorption region.

[0101] Figure 5 The image shows the optical responsivity curves of the waveguide-coupled photodetector prepared in Example 1 under different bias voltages. Figure 5 As shown, under a reverse bias voltage of -1V, the waveguide-coupled photodetector has a photoresponsivity of 1.2A / W at 1310nm, which can achieve a high photoresponsivity.

[0102] Comparative Example 1

[0103] Comparative Example 1 shows a waveguide-coupled photodetector used in existing technology, with the structure as follows: Figure 6 As shown, it includes an SOI substrate and a Ge substrate. 1-x Sn x Absorption region and electrode; SOI substrate includes a silicon substrate layer and a buried oxide layer connected in sequence, and a strip waveguide (not shown in the figure), a taper structure (not shown in the figure) and a top silicon layer are disposed on the buried oxide layer connected in sequence.

[0104] The main difference from Example 1 is that in Comparative Example 1, a germanium buffer layer and a Ge layer are deposited sequentially on the top silicon layer. 1- x Sn x Ge absorption layer formation 1-x Sn x Absorption region, Ge 1-x Sn x The size of the absorption region is the same as that of the photodetector in Example 1.

[0105] The performance of the waveguide-coupled photodetector in this comparative example was tested, and the test results are shown below. Figure 7 .

[0106] Figure 7The figure of the light responsivity curve of the waveguide-coupled photodetector of Comparative Example 1 under different bias voltages. As shown in the figure, the light responsivity of the photodetector at 1310 nm is only 0.96 A / W under a reverse bias voltage of -1 V. Figure 7

[0107] The photodetector of Comparative Example 1 has a clear silicon-germanium heterojunction in structure, in which the high-density defects and dislocations will cause loss and attenuation of the optical signal, and adversely affect the light responsivity of the device, resulting in the light responsivity of the photodetector at 1310 nm being only 0.96 A / W. The photodetector of the embodiment of the present application is not directly grown with Ge 1-x Sn x absorption region, but a hollow silica template cavity is provided, and a germanium buffer layer and a Ge 1-x Sn x absorption layer are sequentially deposited on the top silicon layer exposed by the window at the bottom of the silica template cavity, forming a lateral PIN photodetector structure in the silica template cavity. The optical signal is coupled into the Ge 1-x Sn x absorption layer through evanescent wave coupling, without passing through the silicon-germanium heterojunction, but through the extremely thin silica layer at the bottom of the silica template cavity, which significantly weakens the adverse effects of interface defects, and the light responsivity is significantly improved.

[0108] In the present application, the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the different embodiments or examples described in the present specification and the features of the different embodiments or examples can be combined and combined by those skilled in the art without contradiction.

[0109] Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.​

Claims

1. A waveguide-coupled photodetector, comprising: Comprising: SOI substrate, hollow silica template cavity, Ge 1-x Sn x Absorption region and electrodes The SOI substrate comprises a silicon substrate layer and a buried oxide layer connected in sequence, a strip waveguide, a taper structure and a top silicon layer are arranged on the buried oxide layer in sequence, the strip waveguide and the taper structure are connected with the Ge 1-x Sn x The absorption regions are located at the same center along the light propagation direction; The hollow silica template cavity is arranged above the top silicon layer of the SOI substrate, the bottom silica layer of the hollow silica template cavity is arranged with a bottom window to expose part of the top silicon layer of the SOI substrate, and the top silica layer of the hollow silica template cavity is arranged with an electrode hole. The Ge 1-x Sn x The absorption region is arranged in the hollow silica template cavity, and the Ge 1-x Sn x The absorption region comprises a germanium buffer layer and a Ge 1-x Sn x The absorption layer, the germanium buffer layer is arranged in the cavity between the bottom window and the top of the hollow silica template cavity in the direction perpendicular to the top silicon layer; the Ge 1-x Sn x The absorption layer comprises a P-type doped layer, an intrinsic layer and an N-type doped layer connected in sequence, the P-type doped layer is connected with the germanium buffer layer, and 0≤x<1. The electrode is arranged above the hollow silica template cavity, and is connected with the Ge 1-x Sn x The absorption region is electrically connected.

2. The waveguide-coupled photodetector of claim 1, wherein, The thickness of the bottom silica layer of the hollow silica template cavity is 20 nm-100 nm.

3. The waveguide-coupled photodetector of claim 2, wherein, The thickness of the bottom silica layer of the hollow silica template cavity is 50 nm.

4. The waveguide-coupled photodetector of claim 1, wherein, The length of the bottom window of the hollow silica template cavity is 10-12 μm, and the width is 2-3 μm.

5. A method of fabricating a waveguide-coupled photodetector, comprising: Comprising the following steps: a. Forming a buried oxide layer on a silicon substrate, depositing a silicon layer on the buried oxide layer, processing the silicon layer to obtain a strip waveguide, a taper structure and a top silicon layer, and preparing an SOI substrate; b. Preparing a hollow silica template cavity base on the top silicon layer, the bottom silica layer of the hollow silica template cavity base is arranged with a bottom window to expose part of the top silicon layer, and a window is arranged at the other end of the hollow silica template cavity base away from the bottom window in the horizontal direction; c. depositing a germanium buffer layer at a bottom window in the silica template cavity base, growing the germanium buffer layer in a direction perpendicular to the top silicon layer to the top of the silica template cavity base, and continuing to grow, in order, a P-type doped layer, an intrinsic layer, and an N-type doped layer to form Ge 1-x Sn x absorbing layer, where 0≤x<1, completing Ge 1-x Sn x absorbing region d. depositing a layer of silicon dioxide outside the Ge 1-x Sn x depositing a layer of silicon dioxide outside the absorption region to enclose the hollow silicon dioxide template cavity e. Fabricating electrodes on top of the hollow silica template cavities and connecting them to the Ge 1-x Sn x Absorption region is electrically connected, and a waveguide-coupled photodetector is prepared.

6. The method of claim 5, wherein the method further comprises: The method for preparing the hollow silica template cavity base in step b comprises: b1. Depositing silica on the top silicon layer to form a bottom silica layer, and processing the bottom silica layer to form a bottom window to expose part of the top silicon layer; b2. Depositing a silicon layer on the bottom silica layer, processing the silicon layer and depositing silica around the silicon layer to form a silica cladding layer, so that the silicon layer is surrounded by the silica cladding layer; b3. Opening a window on the silica cladding layer, the window is arranged at both ends of the silicon layer in the horizontal direction together with the bottom window, and the silicon layer is removed through the window to expose the top silicon layer at the bottom window, thereby preparing a hollow silica template cavity base.

7. The method of claim 6, wherein the method further comprises: The deposition method of the silica in step b1 and / or step b2 comprises a thermal oxidation method, an atmospheric pressure chemical vapor deposition method, a low pressure chemical vapor deposition method or a plasma chemical vapor deposition method.

8. The method of claim 6, wherein the method further comprises: The silicon layer in step b2 is made of polycrystalline silicon or amorphous silicon, and / or the deposition method of the silicon layer comprises a plasma chemical vapor deposition method; The removal method of the silicon layer in step b3 comprises etching the silicon layer by using a wet etching method.

9. The method of claim 6, wherein the method further comprises: The processing method of the bottom window in step b1 comprises processing the silica layer by using an electron beam exposure or an inductively coupled plasma etching method; And / or, the processing method of the window on the silica cladding layer in step b3 comprises processing the silica cladding layer by using an electron beam exposure or an inductively coupled plasma etching method.

10. The method of claim 5, wherein the method further comprises: The growth method of the germanium buffer layer, the P-type doped layer, the intrinsic layer or the N-type doped layer in step c comprises at least one of a chemical vapor deposition method and a high temperature diffusion method.

11. The method of claim 5, wherein the method further comprises: In the step e, the electrode preparation includes: preparing an electrode hole on the top of the hollow silica template cavity by electron beam exposure or inductively coupled plasma etching, evaporating metal in the electrode hole by electron beam evaporation, and obtaining the electrode.

12. The method of claim 11, wherein the method further comprises: The metal includes at least one of Ni, Cr, Ti and Au.

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