A clock network circuit for eliminating the influence of power supply noise

Abstract

The present invention discloses a clock network circuit for eliminating the influence of power supply noise, and relates to the field of signal delay control technology, including: a power supply module and a delay module; the first input end of the power supply module is connected to the power supply voltage, the second input end of the power supply module is connected to the output clock signal, the output end of the power supply module is connected to the control end of the delay module, the input end of the delay module is connected to the input clock signal, and the output end of the delay module is connected to the output clock signal; the power supply module is used to adjust the power supply voltage according to the power supply voltage and the output clock signal voltage; the delay module is used to adjust the delay of the input clock signal according to the power supply voltage. The present invention samples the power supply voltage and the output clock signal voltage by setting the power supply module, compares the difference between the two voltages to adjust the power supply voltage, and the power supply voltage controls the delay module to delay the clock signal, thereby offsetting the delay caused by the power supply noise on the clock signal and eliminating the influence of the power supply noise on the clock signal.

Description

Technical Field

[0001] The invention relates to the technical field of signal delay control, and in particular to a clock network circuit for eliminating the influence of power supply noise. Background Art

[0002] The clock network circuit is a circuit system used to synchronize clock signals in electronic devices. The main task of the clock network circuit is to synchronize the clock signal to the target device to ensure that the various parts of the system can work together accurately. During this whole process, the clock signal is crucial for synchronous operation. Therefore, designing an efficient and low-jitter clock network is a core part of any high-performance electronic design.

[0003] With the continuous development of electronic devices, the amount and accuracy of data processing are constantly improving. There is an increasing demand for low-power and low-interference circuits, and the performance requirements for the clock circuits therein are also getting higher and higher. For clock network circuits, power supply noise will affect the clock signal. When power supply noise is applied to the clock network circuit, the clock signal will jitter, causing the clock signal to have a larger or smaller delay. The specific manifestation of this delay is that when the power supply voltage is high under the influence of noise, the jitter edge of the clock signal will be advanced, and when the power supply voltage is low under the influence of noise, the jitter edge of the clock signal will lag behind. The delay of the clock signal will affect the overall performance of the circuit. Therefore, it is necessary to design a circuit that eliminates the influence of power supply noise on the clock signal. Summary of the invention

[0004] The purpose of the present invention is to provide a clock network circuit that eliminates the influence of power supply noise. The present invention sets a power supply module 100 to sample the power supply voltage and the voltage of the output clock signal, compares the difference between the two voltages to adjust the power supply voltage, and the power supply voltage controls the delay module 200 to delay the clock signal, thereby offsetting the delay caused by the power supply noise on the clock signal and eliminating the influence of the power supply noise on the clock signal.

[0005] The purpose of the present invention is achieved by the following technical means:

[0006] The present invention provides a clock network circuit for eliminating the influence of power supply noise, comprising: a power supply module (100) and a delay module (200);

[0007] The first input end of the power supply module (100) is connected to a power supply voltage, the second input end of the power supply module (100) is connected to an output clock signal, the output end of the power supply module (100) is connected to a control end of the delay module (200), the input end of the delay module (200) is connected to an input clock signal, and the output end of the delay module (200) is connected to an output clock signal;

[0008] The power supply module (100) is used to adjust the power supply voltage according to the power supply voltage and the output clock signal voltage;

[0009] The delay module (200) is used to adjust the delay of the input clock signal according to the power supply voltage.

[0010] Preferably, the power supply module (100) comprises: a first amplifying unit (110), a second amplifying unit (120), a filtering unit (130) and a voltage dividing unit (140);

[0011] The first input end of the first amplifying unit (110) is connected to a power supply voltage, the second input end of the first amplifying unit (110) is connected to an output end of the voltage dividing unit (140), and the output end of the first amplifying unit (110) is connected to an input end of the second amplifying unit (120);

[0012] The output end of the second amplifying unit (120) is connected to the control end of the delay module (200);

[0013] The input end of the filtering unit (130) is connected to the output end of the second amplifying unit (120), and the output end of the filtering unit (130) is grounded;

[0014] The input end of the voltage dividing unit (140) is connected to the output end of the delay module (200);

[0015] The first amplifying unit (110) is used to amplify the difference between the power supply voltage and the output clock signal voltage;

[0016] The second amplifying unit (120) is used to adjust the supply voltage;

[0017] The filtering unit (130) is used to smooth the supply voltage;

[0018] The voltage dividing unit (140) is used to adjust the input voltage of the second input end of the first amplifying unit (110).

[0019] Preferably, the power supply module (100) further comprises: a feedforward unit (150);

[0020] The input end of the feedforward unit (150) is connected to the output end of the delay module (200), and the output end of the feedforward unit (150) is connected to the output end of the first amplification unit (110);

[0021] The feedforward unit (150) is used to adjust the response of the first amplification unit (110);

[0022] The feedforward unit (150) comprises: a first capacitor (C1) and a second capacitor (C2);

[0023] A first end of the first capacitor (C1) is connected to an output end of the delay module (200), and a second end of the first capacitor (C1) is connected to a second input end of the first amplification unit (110);

[0024] A first end of the second capacitor (C2) is connected to an output end of the delay module (200), and a second end of the second capacitor (C2) is connected to an output end of the first amplification unit (110).

[0025] Preferably, the second amplifying unit (120) comprises: a first transistor (M1), a second transistor (M2) and a first resistor (R1);

[0026] The gate of the first transistor (M1) is connected to the output end of the first amplifying unit (110), the source of the first transistor (M1) is connected to the power supply voltage, and the drain of the first transistor (M1) is grounded;

[0027] The gate and source of the second transistor (M2) are connected to a power supply voltage, and the drain of the second transistor (M2) is grounded;

[0028] A first end of the first resistor (R1) is connected to a power supply voltage, and a second end of the first resistor (R1) is grounded.

[0029] Preferably, the filtering unit (130) comprises: a second resistor (R2) and a third capacitor (C3);

[0030] The first end of the second resistor (R2) is connected to the output end of the second amplifying unit (120), the second end of the second resistor (R2) is connected to the first end of the third capacitor (C3); and the second end of the third capacitor (C3) is grounded.

[0031] Preferably, the voltage dividing unit (140) comprises a third resistor (R3) and a fourth resistor (R4);

[0032] A first end of the third resistor (R3) is connected to the output end of the delay module (200), and a second end of the third resistor (R3) is connected to the second input end of the first amplification unit (110);

[0033] A first end of the fourth resistor (R4) is connected to a second end of the third resistor (R3), and a second end of the fourth resistor (R4) is grounded.

[0034] Preferably, the delay module (200) comprises: a bias generating unit (210) and a delay control unit (220);

[0035] The input end of the bias generating unit (210) is connected to the output end of the power supply module (100), and the output end of the bias generating unit (210) is connected to the control of the delay control unit (220);

[0036] The input end of the delay control unit (220) is connected to the input clock signal, and the output end of the delay control unit (220) is connected to the output clock signal;

[0037] The bias voltage generating unit (210) is used to generate a bias voltage according to a power supply voltage;

[0038] The delay control unit (220) is used to adjust the delay of the input clock signal according to the bias voltage.

[0039] Preferably, the delay control unit (220) comprises: a voltage-controlled delay line;

[0040] The voltage-controlled delay line comprises: a plurality of delay devices connected in series;

[0041] The control end of each of the delay devices is connected to the output end of the bias voltage generating unit (210), and the output end of each of the delay devices is respectively connected to the output clock signal.

[0042] Preferably, it also includes: a filtering module (300);

[0043] The input end of the filter module (300) is connected to the power supply voltage, and the output end of the filter module (300) is connected to the first input end of the power supply module (100);

[0044] The filtering module (300) is used to smooth the power supply voltage;

[0045] The filtering module (300) comprises: a fourth capacitor (C4);

[0046] A first end of the fourth capacitor (C4) is connected to a power supply voltage, and a second end of the fourth capacitor (C4) is connected to a first input end of the power supply module (100).

[0047] Preferably, it also includes: a decoupling module (400);

[0048] The input end of the decoupling module (400) is connected to the first input end of the power supply module (100), and the output end of the decoupling module (400) is grounded;

[0049] The decoupling module (400) is used to remove noise from the power supply voltage;

[0050] The decoupling module (400) comprises: a fifth capacitor (C5);

[0051] A first end of the fifth capacitor (C5) is connected to a first input end of the power supply module (100), and a second end of the fifth capacitor (C5) is grounded.

[0052] Compared with the prior art, the present invention has the following beneficial effects:

[0053] The present invention sets a power supply module 100 to sample the power supply voltage and the voltage of the output clock signal, compares the difference between the two voltages to adjust the power supply voltage, and the power supply voltage controls the delay module 200 to delay the clock signal, thereby offsetting the delay caused by power supply noise on the clock signal and eliminating the influence of power supply noise on the clock signal.

[0054] The present invention provides a two-stage amplification unit to amplify the difference between the power supply voltage and the voltage of the output clock signal, thereby increasing the error amplification multiple and thus improving the linearity of the power supply module 100 .

[0055] The present invention sets a bias generating unit 210 and a delay control unit 220, inputs the supply voltage as a control voltage into the bias generating unit 210 to generate a bias voltage, and the delay control unit 220 adjusts the delay size according to the bias voltage, thereby providing low module power consumption and small module area.

[0056] The present invention arranges a filter module 300 and a decoupling module 400 between the power supply voltage and the power supply module 100, and processes the power supply voltage noise before delay synchronization, thereby reducing the influence of the power supply noise on the clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0058] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0059] Figure 1 A schematic diagram of the structure of a clock network circuit for eliminating the influence of power supply noise provided by this embodiment;

[0060] Figure 2 A schematic diagram of the structure of another clock network circuit for eliminating the influence of power supply noise provided by this embodiment;

[0061] Figure 3 A circuit structure diagram of a clock network circuit for eliminating the influence of power supply noise, including a feed-forward unit, provided in this embodiment;

[0062] Figure 4 A circuit structure diagram of a second amplifying unit of a clock network circuit for eliminating the influence of power supply noise provided by this embodiment;

[0063] Figure 5 A circuit structure diagram of a clock network circuit for eliminating the influence of power supply noise, including a filtering unit, provided in this embodiment;

[0064] Figure 6 A circuit structure diagram of a clock network circuit for eliminating the influence of power supply noise, including a voltage dividing unit, provided in this embodiment;

[0065] Figure 7 A schematic diagram of the structure of another clock network circuit for eliminating the influence of power supply noise provided by this embodiment;

[0066] Figure 8 A circuit structure diagram of a clock network circuit for eliminating the influence of power supply noise, including a delay control unit provided in this embodiment;

[0067] Fig. 9 A circuit structure diagram of a clock network circuit for eliminating the influence of power supply noise, including a filtering module, provided in this embodiment;

[0068] Fig.10 A circuit structure diagram of a clock network circuit for eliminating the influence of power supply noise, including a decoupling module, provided in this embodiment. DETAILED DESCRIPTION

[0069] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0070] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0071] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0072] The clock network circuit is a circuit system used to synchronize clock signals in electronic devices. The main task of the clock network circuit is to synchronize the clock signal to the target device to ensure that the various parts of the system can work together accurately. During this whole process, the clock signal is crucial to the synchronous operation. Therefore, designing an efficient and low-jitter clock network is the core part of any high-performance electronic design. With the continuous development of electronic devices, the amount and accuracy of data processing are constantly improving, and there is an increasing demand for low-power and low-interference circuits, and the performance requirements for the clock circuits therein are also getting higher and higher. For the clock network circuit, power supply noise will affect the clock signal. When power supply noise is applied to the clock network circuit, the clock signal will jitter, resulting in a larger or smaller delay in the clock signal. The specific manifestation of this delay is that when the power supply voltage is high under the influence of noise, the jitter edge of the clock signal will be advanced, and when the power supply voltage is low under the influence of noise, the jitter edge of the clock signal will lag behind, and the delay of the clock signal will affect the overall performance of the circuit. Therefore, it is necessary to design a circuit that eliminates the influence of power supply noise on the clock signal.

[0073] The present invention sets a power supply module 100 to sample the power supply voltage and the voltage of the output clock signal, compares the difference between the two voltages to adjust the power supply voltage, and the power supply voltage controls the delay module 200 to delay the clock signal, thereby offsetting the delay caused by power supply noise on the clock signal and eliminating the influence of power supply noise on the clock signal.

[0074] Example 1

[0075] A clock network circuit that eliminates the effects of power supply noise, such as Figure 1 As shown, it includes: a power supply module 100 and a delay module 200;

[0076] The first input terminal of the power supply module 100 is connected to the power supply voltage, the second input terminal of the power supply module 100 is connected to the output clock signal, the output terminal of the power supply module 100 is connected to the control terminal of the delay module 200, the input terminal of the delay module 200 is connected to the input clock signal, and the output terminal of the delay module 200 is connected to the output clock signal;

[0077] The power supply module 100 is used to adjust the power supply voltage according to the power supply voltage and the output clock signal voltage;

[0078] The delay module 200 is used to adjust the delay of the input clock signal according to the supply voltage.

[0079] It should be noted that power supply noise refers to the voltage fluctuation on the power supply voltage that changes over time. Under the influence of power supply noise, the power supply voltage will be higher or lower than the normal power supply voltage. Different voltages will produce different delays on the same clock path. When the power supply voltage is high, it will cause the rising edge or falling edge of the clock signal to advance, and when the power supply voltage is low, it will cause the rising edge or falling edge of the clock signal to lag, resulting in a delay between the clock signal and the standard clock signal.

[0080] In this embodiment, the power supply module 100 is set to sample the power supply voltage and the voltage of the output clock signal, and the difference between the two voltages is compared to adjust the power supply voltage. The power supply voltage controls the delay module 200 to delay the clock signal, thereby offsetting the delay caused by the power supply noise on the clock signal and eliminating the influence of the power supply noise on the clock signal.

[0081] In some embodiments, Figure 2 As shown, the power supply module 100 includes: a first amplifying unit 110, a second amplifying unit 120, a filtering unit 130 and a voltage dividing unit 140;

[0082] The first input terminal of the first amplifying unit 110 is connected to the power supply voltage, the second input terminal of the first amplifying unit 110 is connected to the output terminal of the voltage dividing unit 140, and the output terminal of the first amplifying unit 110 is connected to the input terminal of the second amplifying unit 120;

[0083] The output end of the second amplifying unit 120 is connected to the control end of the delay module 200;

[0084] The input end of the filter unit 130 is connected to the output end of the second amplifying unit 120, and the output end of the filter unit 130 is grounded;

[0085] The input end of the voltage dividing unit 140 is connected to the output end of the delay module 200;

[0086] The first amplifying unit 110 is used to amplify the difference between the power supply voltage and the output clock signal voltage;

[0087] The second amplifying unit 120 is used to adjust the supply voltage;

[0088] The filter unit 130 is used to smooth the supply voltage;

[0089] The voltage dividing unit 140 is used to adjust the input voltage of the second input terminal of the first amplifying unit 110 .

[0090] Specifically, the first amplifier unit 110 receives a power supply voltage and an output clock signal voltage at two input terminals, samples the voltages of the two, and outputs a first amplified voltage according to the voltage difference between the two. The first amplifier unit 110 may be a conventional current mirror error amplifier.

[0091] The second amplifying unit 120 inputs the first amplified voltage, amplifies the first amplified voltage based on the first amplifying unit 110, and outputs a second amplified voltage. The second amplified voltage is used as a power supply voltage to power and control the delay module 200.

[0092] The filter unit 130 is disposed between the output end of the second amplifying unit 120 and the delay module 200 to filter out the noise of the power supply voltage applied to the two-stage amplifying unit, thereby reducing the power supply noise and providing a stable power supply voltage to control the operation of the delay module 200 .

[0093] The voltage dividing unit 140 divides the voltage of the output clock signal and inputs the divided voltage into the second input terminal of the first amplifying unit 110 to ensure the normal delay operation of the entire circuit.

[0094] The smaller the linearity of the power supply module 100, the smaller the impact of the change of the input voltage on the output voltage, and the better the performance of the power supply module 100. In this embodiment, by providing a two-stage amplification unit to amplify the difference between the power supply voltage and the voltage of the output clock signal, the error amplification factor is increased, thereby improving the linearity of the power supply module 100.

[0095] In some embodiments, Figure 3 As shown, the power supply module 100 further includes: a feedforward unit 150;

[0096] The input end of the feedforward unit 150 is connected to the output end of the delay module 200 , and the output end of the feedforward unit 150 is connected to the output end of the first amplification unit 110 ;

[0097] A feed-forward unit 150, configured to adjust the response of the first amplifying unit 110;

[0098] The feedforward unit 150 includes: a first capacitor C1 and a second capacitor C2;

[0099] A first end of the first capacitor C1 is connected to the output end of the delay module 200 , and a second end of the first capacitor C1 is connected to the second input end of the first amplifying unit 110 ;

[0100] A first end of the second capacitor C2 is connected to the output end of the delay module 200 , and a second end of the second capacitor C2 is connected to the output end of the first amplifying unit 110 .

[0101] In this embodiment, the feedforward unit 150 is set at the output end of the delay module 200 and the output end of the first amplifying unit 110, and zero points and poles are introduced into the loop of the first amplifying unit 110, so as to improve the transient response of the first amplifying unit 110 and reduce the voltage ringing generated by the first amplifying unit 110, thereby reducing the voltage fluctuation caused by the voltage ringing, thereby affecting the normal operation of the delay module 200.

[0102] In some embodiments, Figure 4 , the second amplifying unit 120 includes: a first transistor M1, a second transistor M2 and a first resistor R1;

[0103] The gate of the first transistor M1 is connected to the output terminal of the first amplifying unit 110, the source of the first transistor M1 is connected to the power supply voltage, and the drain of the first transistor M1 is grounded;

[0104] The gate and source of the second transistor M2 are connected to the power supply voltage, and the drain of the second transistor M2 is grounded;

[0105] A first end of the first resistor R1 is connected to a power supply voltage, and a second end of the first resistor R1 is grounded.

[0106] In some embodiments, Figure 5 As shown, the filtering unit 130 includes: a second resistor R2 and a third capacitor C3;

[0107] A first end of the second resistor R2 is connected to the output end of the second amplifying unit 120 , a second end of the second resistor R2 is connected to a first end of the third capacitor C3 ; and a second end of the third capacitor C3 is grounded.

[0108] In some embodiments, Figure 6 As shown, the voltage dividing unit 140 includes a third resistor R3 and a fourth resistor R4;

[0109] A first end of the third resistor R3 is connected to the output end of the delay module 200 , and a second end of the third resistor R3 is connected to the second input end of the first amplifying unit 110 ;

[0110] A first end of the fourth resistor R4 is connected to the second end of the third resistor R3 , and a second end of the fourth resistor R4 is grounded.

[0111] In some embodiments, Figure 7As shown, the delay module 200 includes: a bias generating unit 210 and a delay control unit 220;

[0112] The input end of the bias generating unit 210 is connected to the output end of the power supply module 100, and the output end of the bias generating unit 210 is connected to the control end of the delay control unit 220;

[0113] An input end of the delay control unit 220 is connected to an input clock signal, and an output end of the delay control unit 220 is connected to an output clock signal;

[0114] A bias voltage generating unit 210, configured to generate a bias voltage according to a supply voltage;

[0115] The delay control unit 220 is used to adjust the delay of the input clock signal according to the bias voltage.

[0116] It should be noted that the bias generating unit 210 can be a conventional bias generating circuit. Under the control of the power supply voltage, the bias generating unit 210 will output two voltages Vcp and Vcn. Under the control of the voltages Vcp and Vcn, the delay control unit 220 outputs a clock signal with a certain delay compared to the standard clock signal. In this embodiment, it is not necessary to set up a monitoring and phase detection device to obtain the phase of the voltage signal on the signal chain one by one and compare and analyze the phase of the standard clock signal. By setting the bias generating unit 210 and the delay control unit 220, the power supply voltage is input as a control voltage to the bias generating unit 210 to generate a bias voltage, and the delay control unit 220 adjusts the delay according to the bias voltage, thereby providing low module power consumption and small module area.

[0117] In some embodiments, Figure 8 As shown, the delay control unit 220 includes: a voltage-controlled delay line;

[0118] The voltage controlled delay line comprises: a plurality of delay devices connected in series;

[0119] The control end of each delayer is connected to the output end of the bias generating unit 210 , and the output end of each delayer is connected to the output clock signal respectively.

[0120] Specifically, the voltage-controlled delay line is used to provide clock signals with different phase delays, which mainly delay the clock signal through a delayer. The delayer has a clock signal input terminal, a clock signal output terminal, and two control voltage input terminals, and the two control voltage input terminals are respectively connected to the output terminals of the voltages Vcp and Vcn generated by the bias generating unit 210. When the clock signal is input into the delayer, the delayer outputs a clock signal with a certain delay according to the control of the voltages Vcp and Vcn. After the input clock signal passes through multiple delayers connected in series, a clock signal that has been subjected to power supply noise elimination and delay synchronization can be obtained.

[0121] It should be noted that when the power supply voltage is normal, the input clock signal will also be delayed through the control of Vbp, and an output clock signal delayed by a reference value will be provided. After the circuit is configured, the output clock signal delayed by a reference value can be synchronized with the standard clock signal.

[0122] In some embodiments, Fig. 9 As shown, it also includes: a filtering module 300;

[0123] The input end of the filter module 300 is connected to the power supply voltage, and the output end of the filter module 300 is connected to the first input end of the power supply module 100;

[0124] A filter module 300, used for smoothing the power supply voltage;

[0125] The filter module 300 includes: a fourth capacitor C4;

[0126] A first end of the fourth capacitor C4 is connected to the power supply voltage, and a second end of the fourth capacitor C4 is connected to the first input end of the power supply module 100 .

[0127] In this embodiment, by providing the filter module 300 between the power supply voltage and the power supply module 100, the noise of the power supply voltage is processed before delay synchronization is performed, thereby reducing the influence of the power supply noise on the clock signal.

[0128] In some embodiments, Fig.10 As shown, it also includes: a decoupling module 400;

[0129] The input end of the decoupling module 400 is connected to the first input end of the power supply module 100, and the output end of the decoupling module 400 is grounded;

[0130] A decoupling module 400, used to remove noise from the power supply voltage;

[0131] The decoupling module 400 includes: a fifth capacitor C5;

[0132] A first end of the fifth capacitor C5 is connected to the first input end of the power supply module 100 , and a second end of the fifth capacitor C5 is grounded.

[0133] In this embodiment, by providing a decoupling module 400 on the bypass of the power supply voltage, the noise of the power supply voltage is processed before delay synchronization is performed, thereby reducing the influence of the power supply noise on the clock signal.

[0134] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A clock network circuit for eliminating the influence of power supply noise, characterized in that: include: A power supply module (100) and a delay module (200); The first input end of the power supply module (100) is connected to a power supply voltage, the second input end of the power supply module (100) is connected to an output clock signal, the output end of the power supply module (100) is connected to a control end of the delay module (200), the input end of the delay module (200) is connected to an input clock signal, and the output end of the delay module (200) is connected to an output clock signal; The power supply module (100) is used to adjust the power supply voltage according to the difference between the power supply voltage and the output clock signal voltage; The delay module (200) is used to adjust the delay of the input clock signal according to the power supply voltage; The power supply module (100) comprises: a first amplifying unit (110), a second amplifying unit (120), a filtering unit (130) and a voltage dividing unit (140); The first input end of the first amplifying unit (110) is connected to a power supply voltage, the second input end of the first amplifying unit (110) is connected to an output end of the voltage dividing unit (140), and the output end of the first amplifying unit (110) is connected to an input end of the second amplifying unit (120); The output end of the second amplifying unit (120) is connected to the control end of the delay module (200); The input end of the filtering unit (130) is connected to the output end of the second amplifying unit (120), and the output end of the filtering unit (130) is grounded; The input end of the voltage dividing unit (140) is connected to the output end of the delay module (200); The first amplifying unit (110) is used to amplify the difference between the power supply voltage and the output clock signal voltage; The second amplifying unit (120) is used to adjust the supply voltage; The filtering unit (130) is used to smooth the supply voltage; The voltage dividing unit (140) is used to adjust the input voltage of the second input end of the first amplifying unit (110); Wherein, the power supply module (100) further comprises: a feedforward unit (150); The input end of the feedforward unit (150) is connected to the output end of the delay module (200), and the output end of the feedforward unit (150) is connected to the output end of the first amplification unit (110); The feedforward unit (150) is used to adjust the response of the first amplification unit (110); The feedforward unit (150) comprises: a first capacitor (C1) and a second capacitor (C2); A first end of the first capacitor (C1) is connected to an output end of the delay module (200), and a second end of the first capacitor (C1) is connected to a second input end of the first amplification unit (110); A first end of the second capacitor (C2) is connected to an output end of the delay module (200), and a second end of the second capacitor (C2) is connected to an output end of the first amplification unit (110); The delay module (200) comprises: a bias generating unit (210) and a delay control unit (220); The input end of the bias generating unit (210) is connected to the output end of the power supply module (100), and the output end of the bias generating unit (210) is connected to the control of the delay control unit (220); The input end of the delay control unit (220) is connected to the input clock signal, and the output end of the delay control unit (220) is connected to the output clock signal; The bias voltage generating unit (210) is used to generate a bias voltage according to a power supply voltage; The delay control unit (220) is used to adjust the delay of the input clock signal according to the bias voltage; The clock network circuit further comprises: a filtering module (300) and a decoupling module (400); The input end of the filter module (300) is connected to the power supply voltage, and the output end of the filter module (300) is connected to the first input end of the power supply module (100); The filtering module (300) is used to smooth the power supply voltage; The filtering module (300) comprises: a fourth capacitor (C4); A first end of the fourth capacitor (C4) is connected to a power supply voltage, and a second end of the fourth capacitor (C4) is connected to a first input end of the power supply module (100); The input end of the decoupling module (400) is connected to the first input end of the power supply module (100), and the output end of the decoupling module (400) is grounded; The decoupling module (400) is used to remove noise from the power supply voltage; The decoupling module (400) comprises: a fifth capacitor (C5); A first end of the fifth capacitor (C5) is connected to a first input end of the power supply module (100), and a second end of the fifth capacitor (C5) is grounded.

2. A clock network circuit for eliminating the influence of power supply noise according to claim 1, characterized in that: The second amplifying unit (120) comprises: a first transistor (M1), a second transistor (M2) and a first resistor (R1); The gate of the first transistor (M1) is connected to the output end of the first amplifying unit (110), the source of the first transistor (M1) is connected to the power supply voltage, and the drain of the first transistor (M1) is grounded; The gate and source of the second transistor (M2) are connected to a power supply voltage, and the drain of the second transistor (M2) is grounded; A first end of the first resistor (R1) is connected to a power supply voltage, and a second end of the first resistor (R1) is grounded.

3. A clock network circuit for eliminating the influence of power supply noise according to claim 1, characterized in that: The filtering unit (130) comprises: a second resistor (R2) and a third capacitor (C3); The first end of the second resistor (R2) is connected to the output end of the second amplifying unit (120), the second end of the second resistor (R2) is connected to the first end of the third capacitor (C3); and the second end of the third capacitor (C3) is grounded.

4. The clock network circuit for eliminating the influence of power supply noise according to claim 1, characterized in that: The voltage dividing unit (140) comprises a third resistor (R3) and a fourth resistor (R4); A first end of the third resistor (R3) is connected to the output end of the delay module (200), and a second end of the third resistor (R3) is connected to the second input end of the first amplification unit (110); A first end of the fourth resistor (R4) is connected to a second end of the third resistor (R3), and a second end of the fourth resistor (R4) is grounded.

5. The clock network circuit for eliminating the influence of power supply noise according to claim 1, characterized in that: The delay control unit (220) comprises: a voltage-controlled delay line; The voltage-controlled delay line comprises: a plurality of delay devices connected in series; The control end of each of the delay devices is connected to the output end of the bias voltage generating unit (210), and the output end of each of the delay devices is respectively connected to the output clock signal.

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