Multi-rate incremental high-precision low-delay analog-to-digital converter and implementation method thereof

Abstract

The present invention discloses a multi-rate incremental high-precision low-delay analog-to-digital converter and its implementation method, including: a first analog-to-digital converter, for receiving an input signal and converting the input signal into a first digital code; a second analog-to-digital converter, the input end of the second analog-to-digital converter is electrically connected to the output end of the first analog-to-digital converter, for receiving the input signal and the first digital code, and converting the input signal and the first digital code into a residual voltage; an incremental noise shaping analog-to-digital converter, the input end of the incremental noise shaping analog-to-digital converter is electrically connected to the output end of the second analog-to-digital converter, for receiving the residual voltage, and converting the residual voltage into a second digital code; an encoder, the input end of the encoder is electrically connected to the output end of the first analog-to-digital converter and the output end of the incremental noise shaping analog-to-digital converter, respectively, and the first digital code and the second digital code are encoded to obtain a code value. The present invention can solve the problem of bandwidth limitation due to oversampling of the entire channel.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a multi-rate incremental high-precision low-delay analog-to-digital converter and an implementation method thereof. Background Art

[0002] Traditional noise-shaping analog-to-digital converters (ADCs) usually rely on increasing the oversampling rate, filter order, or successive approximation register (SAR) quantization bit number to improve the system's signal-to-quantization noise ratio (SQNR). Too high a sampling rate means greater power consumption, limited system bandwidth, and circuit speed cannot be increased; the order of the loop filter is related to the stability of the entire system, and the maximum amplitude of the input signal is limited by high-order feedback; when increasing the SAR quantization bit number, the capacitor array mismatch error will deteriorate the system's linearity, and a larger capacitor array will consume more area and power.

[0003] Compared with the noise shaping ADC, the traditional incremental ADC performs a reset operation before each quantization to eliminate the information of the previous quantization state. It can maintain the same quantization accuracy in each input amplitude range and has high linearity, but the design complexity and power consumption of its filter are still high. In addition, when the filter of the traditional incremental ADC is reset, the switching thermal noise will be injected into the internal part along the signal transmission path, limiting the further improvement of the signal-to-noise-distortion ratio (SNDR).

[0004] Therefore, there is an urgent need to provide an analog-to-digital converter to improve the above defects. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a multi-rate incremental high-precision low-delay analog-to-digital converter and an implementation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] In a first aspect, the present invention provides a multi-rate incremental high-precision low-delay analog-to-digital converter, comprising:

[0007] A first analog-to-digital converter, configured to receive an input signal and convert the input signal into a first digital code;

[0008] A second analog-to-digital converter, wherein an input terminal of the second analog-to-digital converter is electrically connected to an output terminal of the first analog-to-digital converter, and is used to receive an input signal and a first digital code, and convert the input signal and the first digital code into a residual voltage;

[0009] An incremental noise shaping analog-to-digital converter, wherein the input end of the incremental noise shaping analog-to-digital converter is electrically connected to the output end of the second analog-to-digital converter, and is used to receive the residual voltage and convert the residual voltage into a second digital code;

[0010] The encoder has an input terminal electrically connected to an output terminal of the first analog-to-digital converter and an output terminal of the incremental noise shaping analog-to-digital converter, and is used to receive a first digital code and a second digital code, encode the first digital code and the second digital code, and obtain a code value.

[0011] In a second aspect, the present invention further provides a method for implementing a multi-rate incremental high-precision low-latency analog-to-digital converter, which is used to drive the multi-rate incremental high-precision low-latency analog-to-digital converter provided by the present invention, comprising:

[0012] During the first stage conversion, the first analog-to-digital converter receives an input signal and converts the input signal once to obtain a first digital code;

[0013] In the second stage conversion, the second analog-to-digital converter receives the input signal and the first digital code, and converts the input signal and the first digital code into a residual voltage; the incremental noise shaping analog-to-digital converter receives the residual voltage, and converts the residual voltage at least twice to obtain a second digital code;

[0014] The encoder encodes the first digital code obtained during the first-stage conversion and the second digital code obtained during the second-stage conversion to obtain a code value.

[0015] Beneficial effects of the present invention:

[0016] The present invention provides a multi-rate incremental high-precision low-delay analog-to-digital converter and an implementation method thereof. A multi-stage analog-to-digital converter is used. In the first-stage conversion, the first analog-to-digital converter converts an input signal into a first digital code. In the second-stage conversion, first, the second analog-to-digital converter converts the input signal and the first digital code into a residual voltage. Then, an incremental noise shaping analog-to-digital converter converts the residual voltage into a second digital code. An encoder encodes the first digital code and the second digital code to obtain a final required code value. In the first-stage conversion, a Nyquist conversion is performed at a frequency of Fs. In the second-stage conversion, N incremental noise shaping conversions are performed at a frequency of N·Fs. After each conversion is completed, a loop filter is reset. Compared with a traditional noise shaping analog-to-digital converter, the present invention is based on a multi-rate mode and adopts local oversampling to achieve high precision, which can solve the problem of bandwidth limitation due to oversampling of the entire channel.

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 1 is a schematic diagram of a multi-rate incremental high-precision low-delay analog-to-digital converter provided by an embodiment of the present invention;

[0019] Figure 2is another schematic diagram of a multi-rate incremental high-precision low-delay analog-to-digital converter provided by an embodiment of the present invention;

[0020] Figure 3 is another schematic diagram of a multi-rate incremental high-precision low-delay analog-to-digital converter provided by an embodiment of the present invention;

[0021] Figure 4 It is a schematic diagram of the results of Simulink simulation of different filter types provided by an embodiment of the present invention;

[0022] Figure 5 It is a timing diagram for realizing a cycle of 14-bit high-precision low-latency analog-to-digital conversion provided by an embodiment of the present invention;

[0023] Figure 6 is a spectrum diagram of an 8-bit SAR ADC provided by an embodiment of the present invention;

[0024] Figure 7 This is a spectrum diagram of the output code value when implementing 14-bit high-precision and low-latency analog-to-digital conversion provided by an embodiment of the present invention;

[0025] Figure 8 It is a timing diagram for realizing a cycle of 24-bit high-precision low-latency analog-to-digital conversion provided by an embodiment of the present invention;

[0026] Fig. 9 This is a spectrum diagram of the output code value when implementing 24-bit high-precision and low-latency analog-to-digital conversion provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0028] See also Figure 1 , Figure 1 1 is a schematic diagram of a multi-rate incremental high-precision low-latency analog-to-digital converter provided by an embodiment of the present invention. The multi-rate incremental high-precision low-latency analog-to-digital converter provided by the present invention includes:

[0029] A first analog-to-digital converter ADC1, used for receiving an input signal and converting the input signal into a first digital code;

[0030] A second analog-to-digital converter ADC2, wherein an input terminal of the second analog-to-digital converter ADC2 is electrically connected to an output terminal of the first analog-to-digital converter ADC1, and is used to receive an input signal and a first digital code, and convert the input signal and the first digital code into a residual voltage;

[0031] An incremental noise shaping analog-to-digital converter IADC, wherein an input end of the incremental noise shaping analog-to-digital converter IADC is electrically connected to an output end of the second analog-to-digital converter ADC2, and is used to receive a residual voltage and convert the residual voltage into a second digital code;

[0032] The encoder has an input terminal electrically connected to an output terminal of the first analog-to-digital converter ADC1 and an output terminal of the incremental noise shaping analog-to-digital converter IADC, and is used to receive a first digital code and a second digital code, encode the first digital code and the second digital code, and obtain a code value.

[0033] For more details, please see Figure 1 The embodiment provides a multi-rate incremental high-precision low-delay analog-to-digital converter, which uses a multi-stage analog-to-digital converter. In the first stage conversion, the first analog-to-digital converter ADC1 converts the input signal into a first digital code. In the second stage conversion, first, the second analog-to-digital converter ADC2 converts the input signal and the first digital code into a residual voltage. Then, the incremental noise shaping analog-to-digital converter IADC converts the residual voltage into a second digital code. The encoder encodes the first digital code and the second digital code to obtain the final required code value. In the first stage conversion, Nyquist conversion is performed at a frequency of Fs, and in the second stage conversion, N incremental noise shaping conversions are performed at a frequency of N·Fs. After each conversion, the loop filter is reset. Compared with the traditional noise shaping analog-to-digital converter, the embodiment is based on a multi-rate mode and uses local oversampling to achieve high precision, which can solve the problem of bandwidth limitation due to oversampling of the entire channel.

[0034] It should be noted that Figure 1 The illustrated embodiment only schematically shows the schematic electrical connection relationship of each device and does not represent their actual positional relationship. The electrical connection is represented by a straight line with an arrow, which also indicates the signal transmission direction. Among them, the input signals VIP and VIN of the first analog-to-digital converter ADC1 are the same as the input signals VIP and VIN of the second analog-to-digital converter ADC2, DOUT1 is the first digital code, DOUT2 is the second digital code, and DOUT is the output after processing of the entire device.

[0035] In an optional embodiment of the present invention, the signal transfer function STF of the incremental noise shaping analog-to-digital converter IADC=1.

[0036] Specifically, in this embodiment, the second-stage conversion performs N incremental noise shaping conversions at a frequency of N·Fs, and the loop filter is reset after each conversion is completed. Between each reset operation, the input signal input to the incremental noise shaping analog-to-digital converter IADC is a fixed DC value. Therefore, the transfer function STF of the input signal is 1, and there is no signal-to-noise distortion ratio (SNDR) caused by the attenuation of the signal amplitude with the frequency.

[0037] In an optional embodiment of the present invention, see Figure 2 , Figure 2 It is another schematic diagram of a multi-rate incremental high-precision low-delay analog-to-digital converter provided by an embodiment of the present invention. The incremental noise shaping analog-to-digital converter IADC includes a third analog-to-digital converter ADC3, a filter, an amplifier, a comparator and an extraction filter. The input end of the third analog-to-digital converter ADC3 is electrically connected to the output end of the second analog-to-digital converter ADC2, the input end of the filter is electrically connected to the output end of the third analog-to-digital converter ADC3, the input end of the comparator is electrically connected to the output end of the filter, the output end of the comparator is electrically connected to the input end of the third analog-to-digital converter ADC3, the output end of the comparator is also electrically connected to the input end of the extraction filter, the output end of the extraction filter is used to output a second digital code, the input end of the amplifier is electrically connected to the output end of the filter, and the output end of the amplifier is electrically connected to the input end of the filter to feed back the amplified voltage.

[0038] In an optional embodiment of the present invention, please continue to refer to Figure 2 The first analog-to-digital converter ADC1 includes a plurality of capacitors arranged in parallel, each capacitor corresponds to a switch, and the conduction of the switch is used to transmit a signal to the plate of the capacitor. The first analog-to-digital converter ADC1 also includes a comparator, and the output end of the comparator is electrically connected to the input end of the second analog-to-digital converter ADC2. At the same time, the output end of the comparator is used to output a first digital code.

[0039] In an optional embodiment of the present invention, please continue to refer to Figure 2 The second analog-to-digital converter ADC2 includes a plurality of capacitors arranged in parallel, each capacitor corresponds to a switch, the conduction of the switch is used to transmit a signal to the plate of the capacitor, the output end of the second analog-to-digital converter ADC2 is electrically connected to the input end of the third analog-to-digital converter ADC3, and is used to provide a residual voltage to the second analog-to-digital converter ADC2.

[0040] In an optional embodiment of the present invention, please continue to refer to Figure 2 The third analog-to-digital converter ADC3 includes a plurality of capacitors arranged in parallel, each capacitor is provided with a corresponding switch, and the conduction of the switch is used to transmit a signal to the plate of the capacitor.

[0041] Please note that, see Figure 3 , Figure 3 It is another schematic diagram of the multi-rate incremental high-precision low-latency analog-to-digital converter provided in an embodiment of the present invention. The second analog-to-digital converter ADC2 can be replaced by a digital-to-analog converter. The input end of the digital-to-analog converter is electrically connected to the output end of the first analog-to-digital converter ADC1. The output signal of the digital-to-analog converter is subtracted from the signal input to the first analog-to-digital converter ADC1 to obtain a residual voltage. The residual signal is input to the third analog-to-digital converter ADC3 for subsequent processing.

[0042] In an optional embodiment of the present invention, please continue to refer to Figure 2 The filter includes a first capacitor C1, a second capacitor C2, a first switch K1, a second switch group K2 and a third switch group K3. The second switch group K2 includes a switch K2-1, a switch K2-2, a switch K2-3 and a switch K2-4. The third switch group K3 includes a switch K3-1, a switch K3-2, a switch K3-3 and a switch K3-4. Wherein,

[0043] One end of the first switch K1 is electrically connected to the first node N1, the other end of the first switch K1 is electrically connected to the second node N2, the output end of the third analog-to-digital converter ADC3 is electrically connected to the first node N1, and the input end of the comparator is electrically connected to the second node N2;

[0044] One end of the switch K2-1 is electrically connected to the first node N1, the other end of the switch K2-1 is electrically connected to the third node N3, the first plate of the first capacitor C1 is electrically connected to the third node N3, the second plate of the first capacitor C1 is electrically connected to the fourth node N4, one end of the switch K2-2 is electrically connected to the fourth node N4, and the other end of the switch K2-2 is electrically connected to the second node N2;

[0045] One end of the switch K3-1 is electrically connected to the first node N1, the other end of the switch K3-1 is electrically connected to the fifth node N5, the first plate of the second capacitor C2 is electrically connected to the fifth node N5, the second plate of the second capacitor C2 is electrically connected to the sixth node N6, one end of the switch K3-2 is electrically connected to the sixth node N6, and the other end of the switch K3-2 is electrically connected to the second node N2;

[0046] One end of the switch K2-3 is electrically connected to the common voltage terminal, the other end of the switch K2-3 is electrically connected to the fifth node N5, one end of the switch K2-4 is electrically connected to the sixth node N6, and the other end of the switch K2-4 is electrically connected to the output terminal of the amplifier;

[0047] One end of the switch K3-3 is electrically connected to the common voltage end, the other end of the switch K3-3 is electrically connected to the third node N3, one end of the switch K3-4 is electrically connected to the fourth node N4, and the other end of the switch K3-4 is electrically connected to the output end of the amplifier.

[0048] It should be noted that the on-state voltage φ of the first switch d When the potential is high, the first switch is turned on, and the on-state voltage of the first switch is φ e When the potential is high, the second switch group is turned on, and the turn-on voltage of the first switch is φ f When the potential is high, the second switch group is turned on, and the voltage φ input to the comparator c When the voltage is high, the comparator works and the voltage φ input to the amplifier amp When it is high, the amplifier is working.

[0049] It should be noted that Figure 1 In the embodiment shown, the signals processed in the IADC are all differential signals. Figure 2 The illustrated embodiment merely schematically illustrates the transmission direction of the signal and does not represent the number of signals.

[0050] Based on the same inventive concept, the present invention also provides a method for implementing a multi-rate incremental high-precision low-latency analog-to-digital converter, which is used to drive the multi-rate incremental high-precision low-latency analog-to-digital converter provided by the above embodiment of the present invention. The embodiment of the analog-to-digital converter is referred to above and will not be described in detail here; the implementation method includes:

[0051] In the first stage conversion, the first analog-to-digital converter ADC1 receives an input signal, converts the input signal once, and obtains a first digital code;

[0052] In the second stage conversion, the second analog-to-digital converter ADC2 receives the input signal and the first digital code, and converts the input signal and the first digital code into a residual voltage; the incremental noise shaping analog-to-digital converter IADC receives the residual voltage, and converts the residual voltage at least twice to obtain a second digital code;

[0053] The encoder encodes the first digital code obtained during the first-stage conversion and the second digital code obtained during the second-stage conversion to obtain a code value.

[0054] For more details, please see Figure 1The present embodiment provides a method for implementing a multi-rate incremental high-precision low-delay analog-to-digital converter, which performs conversion in two stages. In the first stage conversion, the first analog-to-digital converter ADC1 converts the input signal into a first digital code. In the first stage conversion, the conversion is performed only once. In the second stage conversion, first, the second analog-to-digital converter ADC2 converts the input signal and the first digital code into a residual voltage. Secondly, the incremental noise shaping analog-to-digital converter IADC converts the residual voltage into a second digital code. In the second stage conversion, the conversion is performed at least twice. The encoder encodes the first digital code and the second digital code to obtain the final required code value. In the first stage conversion, the Nyquist conversion is performed at a frequency of Fs, and in the second stage conversion, N incremental noise shaping conversions are performed at a frequency of N·Fs. After each conversion, the loop filter is reset. Compared with the traditional noise shaping analog-to-digital converter, the present embodiment is based on a multi-rate mode and uses local oversampling to achieve high precision, which can solve the problem of bandwidth limitation due to oversampling of the entire channel.

[0055] In an optional embodiment of the present invention, the incremental noise shaping analog-to-digital converter IADC receives the residual voltage, converts the residual voltage at least twice, and obtains a second digital code, including:

[0056] During the first conversion, the third analog-to-digital converter ADC3 transmits the received residual voltage to the comparator, and the comparator converts the residual voltage to obtain the residual value after the first conversion;

[0057] During the second conversion, the third analog-to-digital converter transmits the received residual voltage to the filter, and the residual value after the first conversion is transmitted to the amplifier for amplification and then stored in the filter. The filter superimposes the residual voltage with the amplified residual value after the first conversion, and then transmits it to the comparator for conversion to obtain a second digital code signal.

[0058] In an optional embodiment of the present invention, during the second stage conversion, when the incremental noise shaping analog-to-digital converter performs the first conversion, the comparator directly compares the residual voltage, and the filter is not reset and does not work.

[0059] Specifically, in this embodiment, during the second stage conversion, that is, the first incremental noise shaping analog-to-digital conversion, the filter in the incremental noise shaping analog-to-digital converter IADC does not work and is not reset, which can reduce the injection of switching thermal noise in the filter and thereby improve the signal-to-noise distortion ratio.

[0060] It should be noted that in order to achieve an SQNR of 81dB and a sampling rate of 100M / S, the filter type is modeled and simulated. The simulation results are as follows: Figure 4As shown, the SQNR value obtained by the exponential filter is much higher than the SQNR values ​​obtained by the first-order and second-order filters, so the filter is selected as 3*Z -1 , and select the decimation filter as 1 / (1-3*Z -1 ).

[0061] In an optional embodiment of the present invention, during the second stage conversion, the first capacitor C1 and the second capacitor C2 work alternately to achieve multiple conversions of the incremental noise shaping analog-to-digital converter.

[0062] In an optional embodiment of the present invention, the residual value after the first conversion is transmitted to the amplifier for amplification and then stored in the filter. The filter superimposes the residual voltage with the residual value after the first conversion, and then transmits it to the comparator for conversion to obtain a second digital code signal, including:

[0063] The third switch group K3 is turned on, and the residual value after the first conversion is transmitted to the input end of the amplifier. The amplifier amplifies the residual value after the first conversion and stores it in the second plate of the first capacitor C1; the first switch K1 is turned off, the second switch group K2 is turned on, and the residual voltage is transmitted to the first plate of the first capacitor C1. The first capacitor C1 superimposes the residual voltage and the amplified residual value after the first conversion on the second plate of the first capacitor C1, and then converts it through the comparator to obtain a second digital code signal; or,

[0064] The second switch group K2 is turned on, and the residual value after the first conversion is transmitted to the input end of the amplifier. The amplifier amplifies the residual value after the first conversion and stores it in the second plate of the second capacitor C2; the first switch K1 is turned off, and the third switch group K3 is turned on, and the residual voltage is transmitted to the first plate of the second capacitor C2. The second capacitor C2 superimposes the residual voltage and the amplified residual value after the first conversion on the second plate of the second capacitor C2, and after conversion by the comparator, a second digital code signal is obtained.

[0065] In an optional embodiment of the present invention, the expression of the second digital code is:

[0066]

[0067] Where VRES represents the residual voltage, m represents the number of second-stage conversions, Q2(m) represents the quantization noise introduced after each conversion, i represents the index of the second-stage conversion, i∈(0,m), V n (i) represents the noise introduced by the filter and amplifier during the i-th conversion.

[0068] In an optional embodiment of the present invention, see Figure 5 , Figure 5This is a timing diagram of a cycle of 14-bit high-precision low-latency analog-to-digital conversion provided by an embodiment of the present invention. Taking the implementation of 14-bit high-precision low-latency analog-to-digital conversion as an example, the circuit principle and working process are explained. In one sampling cycle, the first stage converts once, and the first analog-to-digital converter ADC1 converts 7 bits each time, and the second stage converts 4 times, and each conversion quantizes 3 bits (including two redundancies). Figure 6 and Figure 7 As shown, the final overall architecture achieves an SNDR of 81dB. In this example, an 8-bit precision SAR is used to achieve a 14-bit precision resolution, and the setup time and setup error of the SAR ADC capacitor plate only need to meet 8-bit precision. Compared with the SARADC with the same SQNR, the number of capacitor array bits is reduced by 4 bits. And the first analog-to-digital converter ADC1 can be a SAR ADC, flash ADC, etc., for the first conversion, the second analog-to-digital converter ADC2 is used to generate a high-precision residual voltage, and the third analog-to-digital converter ADC3 is used as a quantizer in the incremental noise shaping analog-to-digital converter IADC.

[0069] Assume that the capacitor sampling thermal noise of the first analog-to-digital converter ADC1 is VN1, and the capacitor sampling thermal noise of the second analog-to-digital converter ADC2 is VN2; the error caused by the sampling mismatch of the capacitor of the first analog-to-digital converter ADC1 is VS1, and the error caused by the sampling mismatch of the capacitor of the second analog-to-digital converter ADC2 is VS2; the error caused by the capacitor mismatch of the first analog-to-digital converter ADC1 is VM1, and the error caused by the capacitor mismatch of the second analog-to-digital converter ADC2 is VM2; the quantization residual of the first analog-to-digital converter ADC1 is Q1, and the quantization residual of the second analog-to-digital converter ADC2 is Q2. Then the following formula can be obtained:

[0070] Dout1=VIN1+VN1+VS1+VM1+Q1;

[0071] Wherein, Dout1 represents the first digital code.

[0072] For the second analog-to-digital converter ADC2 and the third analog-to-digital converter ADC3, after the second analog-to-digital converter ADC2 performs the copying operation, the residual on the capacitor plate is transmitted to the incremental noise shaping analog-to-digital converter IADC, and the output of the incremental noise shaping analog-to-digital converter IADC can be obtained:

[0073] Dout2=VIN2+VN2+VS2+VM2+Q2-Dout1;

[0074] Wherein, Dout2 represents the second digital code.

[0075] For the entire analog-to-digital conversion, the output is:

[0076] Dout=Dout1+Dout2=VIN2+VN2+VS2+VM2+Q2;

[0077] It can be seen that the sampling thermal noise of the first analog-to-digital converter ADC1, the mismatch between capacitors, and the sampling error do not affect the accuracy of the final analog-to-digital converter. Therefore, under the premise of ensuring that the redundant bits of the third analog-to-digital converter ADC3 are sufficient to cover all errors, the unit capacitance of the capacitor array in the first analog-to-digital converter ADC1 can be as small as possible, thereby speeding up the conversion speed.

[0078] In this embodiment, in the second level conversion, there are four conversions in total, specifically:

[0079] The input of the third analog-to-digital converter ADC3 is:

[0080] VRES=-(VN2+VS2+VM2+Q2);

[0081] Between each reset, the residual voltage VRES is a constant value, and in this type of feedback path, the transfer function of the input signal is 1, and there is no attenuation. When the first analog-to-digital converter ADC1 quantizes 7 bits, the second analog-to-digital converter ADC2 synchronously generates a high-precision residual voltage and stores the residual value on the upper plate of the capacitor set in the third analog-to-digital converter ADC3. During the first conversion, the first switch K1 is closed, and the comparator directly quantizes the residual voltage to obtain the digital code Dout2 (1) output during the first conversion; the third switch group K3 is closed, and the residual value after the first conversion is transferred to the input end of the amplifier for amplification and storage on the second plate of the first capacitor C1. After the amplification is completed, the first switch K1 is turned off, and the second switch group K2 is closed, and the voltage of the upper plate of the capacitor set in the third analog-to-digital converter ADC3 and the amplified voltage are superimposed on the second plate of the first capacitor C1. The comparator compares the voltage of the second plate of the first capacitor C1 three times to obtain the digital code Dout2 (2) output during the second conversion; then the amplifier enters the amplification state again, amplifies the residual value after the second conversion, and stores it. After the amplification is completed, the second switch group K2 is turned off and the third switch group K3 is closed, and the voltage of the upper plate of the capacitor set in the third analog-to-digital converter ADC3 and the amplified voltage are superimposed on the second plate of the second capacitor C2. The comparator compares the voltage of the second plate of the second capacitor C2 three times to obtain the digital code Dout2 (3) output during the third conversion; then the amplifier enters the amplification state again, amplifies the residual value after the third conversion and stores it on the second plate of the first capacitor C1. After the amplification is completed, the third switch group K3 is turned off and the second switch group K2 is closed, and the voltage of the upper plate of the capacitor set in the third analog-to-digital converter ADC3 and the amplified voltage are superimposed on the second plate of the first capacitor C1. The comparator compares the voltage of the second plate of the first capacitor C1 three times to obtain the digital code Dout2 (4) output during the fourth conversion; starting from the second conversion, the second switch group K2 and the third work in a ping-pong timing sequence. During the first conversion, the filter does not work, which can reduce the injection of filter switch thermal noise and thus improve SNDR. The second-stage incremental noise-shaping ADC performs four conversions in total. During each conversion, the high-level rising edge of the signal input to the amplifier arrives three times, which means three bits of quantization.

[0082] Assume that the quantization noise introduced after each conversion is Q2(i), i = 1, 2, 3, 4; at the same time, the noise introduced by the filter and amplifier is V n (i), i=1, 2, 3, 4.

[0083] The digital code Dout2(1) output at the first conversion is expressed as:

[0084] Dout2(1)=VRES+Q2(1);

[0085] The digital code Dout2(2) output during the second conversion is expressed as:

[0086] Dout2(2)=VRES+Q2(2)-3Q2(1)+V n (2);

[0087] At the same time, the digital codes Dout2(3) and Dout2(4) output by the third and fourth conversions are expressed as:

[0088]

[0089] Consider eliminating Q2(1), Q2(2), and Q2(3), and summing Dout2(i) with weight 3. The final output code value is expressed as:

[0090] Dout2=(Dout2(4)+3*Dout2(3)+9*Dout2(2)+27*Dout2(1)) / 40;

[0091] Substitute into:

[0092] Dout2=VRES+Q2(4) / 40+(V n (4) +3V n (3) +9V n (2)) / 40;

[0093] The filters of the traditional incremental ADC and the noise shaping ADC will introduce noise during the first conversion. The digital code Dout2(1)' of the first output corresponding to the traditional incremental ADC is expressed as:

[0094] Dout2(1)'=VRES+Q2(1)+V n (1);

[0095] The final output code is:

[0096] Dout2'=VRES+Q2(4) / 40+(V n (4) +3V n (3) +9V n (2) +27V n (1)) / 40;

[0097] From a noise power perspective, the noise introduced by traditional incremental ADCs and noise-shaping ADCs during the first conversion is eight times the overall noise introduced by this design architecture.

[0098] In an optional embodiment of the present invention, see Figure 8 and Fig. 9 , and can also achieve 24-bit precision low-latency analog-to-digital conversion, increasing the number of conversions of the incremental noise shaping analog-to-digital converter IADC to 11 times. The working timing is as follows Figure 8 As shown, the second switch group K2 and the third switch group K3 work in a ping-pong timing sequence, and their respective high-level rising edges arrive 5 times, and the spectrum of the output code is obtained as shown in Fig. 9 As shown. Based on the SAR ADC with 8-bit resolution, the SNDR is 148.810dB, which is 24-bit resolution. When IADC converts 11 times, the output code value of this level is:

[0099]

[0100] The traditional incremental ADC and the noise shaping ADC will introduce noise in the first conversion. If 11 conversions are performed, the obtained Dout2' is expressed as:

[0101]

[0102] From the perspective of noise power, the noise introduced by the traditional incremental ADC and noise shaping ADC during the first conversion is also 8 times the overall noise introduced by this design architecture, which means that this architecture can improve the SQNR by 9dB compared with the traditional incremental ADC and noise shaping ADC. It can also be understood that using low-bit precision SAR to achieve a higher-precision signal-to-noise ratio reduces the requirements for the capacitor plate settling time and settling error, and can achieve 24-bit high-precision low-latency analog-to-digital conversion.

[0103] In summary, the multi-rate incremental high-precision, low-latency analog-to-digital converter provided by the present invention, compared with the traditional incremental ADC, avoids the injection of switching thermal noise when the filter is reset for the first time, thereby improving the accuracy; and can achieve reconfiguration of accuracy and speed by changing the number of conversions in the second stage and the number of quantization bits for each conversion, and can achieve 24-bit high-precision, low-latency analog-to-digital conversion; it can also further introduce multi-channel interleaving to achieve higher conversion speeds, without the need to use oversampling technology, and can achieve a wide bandwidth input signal range.

[0104] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0105] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0106] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A multi-rate incremental high-precision low-delay analog-to-digital converter, characterized in that: include: A first analog-to-digital converter, configured to receive an input signal and convert the input signal into a first digital code; a second analog-to-digital converter, wherein an input terminal of the second analog-to-digital converter is electrically connected to an output terminal of the first analog-to-digital converter, and is used to receive the input signal and the first digital code, and convert the input signal and the first digital code into a residual voltage; an incremental noise shaping analog-to-digital converter, wherein the input end of the incremental noise shaping analog-to-digital converter is electrically connected to the output end of the second analog-to-digital converter, and is used to receive the residual voltage and convert the residual voltage into a second digital code; the incremental noise shaping analog-to-digital converter comprises a third analog-to-digital converter, a filter, an amplifier, a comparator and a decimation filter, wherein the input end of the third analog-to-digital converter is electrically connected to the output end of the second analog-to-digital converter, the input end of the filter is electrically connected to the output end of the third analog-to-digital converter, the input end of the comparator is electrically connected to the output end of the filter, the output end of the comparator is electrically connected to the input end of the third analog-to-digital converter, the output end of the comparator is also electrically connected to the input end of the decimation filter, the output end of the decimation filter is used to output the second digital code, the input end of the amplifier is electrically connected to the output end of the filter, and the output end of the amplifier is electrically connected to the input end of the filter to feed back the amplified voltage; An encoder, wherein the input end of the encoder is electrically connected to the output end of the first analog-to-digital converter and the output end of the incremental noise shaping analog-to-digital converter, respectively, and is used to receive the first digital code and the second digital code, encode the first digital code and the second digital code, and obtain code values.

2. The multi-rate incremental high-precision low-delay analog-to-digital converter according to claim 1, characterized in that: The signal transfer function STF of the incremental noise shaping analog-to-digital converter is STF=1.

3. The multi-rate incremental high-precision low-delay analog-to-digital converter according to claim 1, characterized in that: The filter includes a first capacitor, a second capacitor, a first switch, a second switch group and a third switch group, the second switch group includes switch 1, switch 2, switch 3 and switch 4, the third switch group includes switch 5, switch 6, switch 7 and switch 8; wherein, One end of the first switch is electrically connected to the first node, the other end of the first switch is electrically connected to the second node, the output end of the third analog-to-digital converter is electrically connected to the first node, and the input end of the comparator is electrically connected to the second node; One end of the switch 1 is electrically connected to the first node, the other end of the switch 1 is electrically connected to the third node, the first plate of the first capacitor is electrically connected to the third node, the second plate of the first capacitor is electrically connected to the fourth node, one end of the switch 2 is electrically connected to the fourth node, and the other end of the switch 2 is electrically connected to the second node; One end of the switch five is electrically connected to the first node, the other end of the switch five is electrically connected to the fifth node, the first plate of the second capacitor is electrically connected to the fifth node, the second plate of the second capacitor is electrically connected to the sixth node, one end of the switch six is ​​electrically connected to the sixth node, and the other end of the switch six is ​​electrically connected to the second node; One end of the switch three is electrically connected to the common voltage end, the other end of the switch three is electrically connected to the fifth node, one end of the switch four is electrically connected to the sixth node, and the other end of the switch four is electrically connected to the output end of the amplifier; One end of the switch seven is electrically connected to the common voltage end, the other end of the switch seven is electrically connected to the third node, one end of the switch eight is electrically connected to the fourth node, and the other end of the switch eight is electrically connected to the output end of the amplifier.

4. A method for implementing a multi-rate incremental high-precision low-latency analog-to-digital converter, used to drive the multi-rate incremental high-precision low-latency analog-to-digital converter as claimed in any one of claims 1 to 3, characterized in that: include: During the first stage conversion, the first analog-to-digital converter receives an input signal and converts the input signal once to obtain a first digital code; During the second-stage conversion, the second analog-to-digital converter receives the input signal and the first digital code, and converts the input signal and the first digital code into a residual voltage; the incremental noise shaping analog-to-digital converter receives the residual voltage, and converts the residual voltage at least twice to obtain a second digital code; wherein, during the first conversion, the third analog-to-digital converter transmits the received residual voltage to the comparator, and the comparator converts the residual voltage to obtain a residual value after the first conversion; during the second conversion, the third analog-to-digital converter transmits the received residual voltage to the filter, and the residual value after the first conversion is transmitted to the amplifier for amplification and then stored in the filter, and the filter superimposes the residual voltage and the amplified residual value after the first conversion, and then transmits it to the comparator for conversion to obtain the second digital code signal; The encoder encodes the first digital code obtained during the first-stage conversion and the second digital code obtained during the second-stage conversion to obtain a code value.

5. The method for implementing a multi-rate incremental high-precision low-delay analog-to-digital converter according to claim 4, characterized in that: During the second-stage conversion, when the incremental noise shaping analog-to-digital converter performs the first conversion, the comparator directly compares the residual voltage, and the filter is not reset and does not work.

6. The method for implementing a multi-rate incremental high-precision low-delay analog-to-digital converter according to claim 4, characterized in that: During the second stage conversion, the first capacitor and the second capacitor work alternately to achieve multiple conversions of the incremental noise shaping analog-to-digital converter.

7. The method for implementing a multi-rate incremental high-precision low-delay analog-to-digital converter according to claim 6, characterized in that: The residual value after the first conversion is transmitted to the amplifier for amplification and then stored in the filter. The filter superimposes the residual voltage with the amplified residual value after the first conversion, and then transmits it to the comparator for conversion to obtain a second digital code signal, including: The third switch group is turned on, and the residual value after the first conversion is transmitted to the input end of the amplifier. The amplifier amplifies the residual value after the first conversion and stores it in the second plate of the first capacitor; the first switch is turned off, and the second switch group is turned on, and the residual voltage is transmitted to the first plate of the first capacitor. The first capacitor superimposes the residual voltage and the amplified residual value after the first conversion on the second plate of the first capacitor, and then converts it through the comparator to obtain the second digital code signal; or, The second switch group is turned on, and the residual value after the first conversion is transmitted to the input end of the amplifier. The amplifier amplifies the residual value after the first conversion and stores it in the second plate of the second capacitor; the first switch is turned off, and the third switch group is turned on, and the residual voltage is transmitted to the first plate of the second capacitor. The second capacitor superimposes the residual voltage and the amplified residual value after the first conversion on the second plate of the second capacitor, and then after conversion by the comparator, the second digital code signal is obtained.

8. The method for implementing a multi-rate incremental high-precision low-delay analog-to-digital converter according to claim 4, characterized in that: The expression of the second digital code is: Where VRES represents the residual voltage, m represents the number of second-stage conversions, Q2(m) represents the quantization noise introduced after each conversion, i represents the index of the second-stage conversion, i∈(0,m), V n (i) represents the noise introduced by the filter and amplifier during the i-th conversion.

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