A method and device for real-time simulation of software-hardware clock synchronization between multiple nodes

Abstract

The present invention relates to the technical field of big data simulation and discloses a method and device for synchronizing software-hardware clocks between multiple nodes in real-time simulation. The method synchronizes the clock signals of the calculation steps of the hardware connected to each node in the simulation software, thereby ensuring the consistency of the simulation system clock signal. By verifying the calculation steps between the hardware and software of each node, the consistency of the software-hardware time steps is ensured, eliminating the clock synchronization mechanism between software, reducing the difficulty of synchronizing the simulation system clock, and avoiding the accumulation of system clock errors, thereby improving the joint real-time simulation performance between multiple nodes.

Description

Technical Field

[0001] The present invention relates to the technical field of big data simulation, and in particular to a method and device for real-time simulation of software-hardware clock synchronization between multiple nodes. Background Art

[0002] Real-time simulation of power systems is an effective means of understanding their characteristics, supporting their research, planning, operation, production, and equipment manufacturing, and ensuring their safe and reliable operation. With the rapid development of new power systems, the massive grid-connected renewable energy generators and power electronic devices have dramatically expanded, necessitating large-scale node parallel simulation. Clock synchronization methods between multiple nodes are a key factor influencing parallel simulation. Existing clock synchronization methods correct each node's clock within a fixed period, causing clock errors between different nodes to accumulate within the correction period, impacting the performance of joint real-time simulations across multiple nodes.

[0003] Currently, in real-time simulation, clock synchronization between multiple nodes is difficult. Clock errors are difficult to synchronize accurately, which easily leads to clock error accumulation, thus greatly reducing the joint real-time simulation performance between multiple nodes. Summary of the Invention

[0004] The present invention provides a method and apparatus for synchronizing software and hardware clocks between multiple nodes in real-time simulation. This method reduces the difficulty of clock synchronization between multiple nodes in real-time simulation. Accurate clock error synchronization prevents system clock error accumulation, thereby improving the performance of joint real-time simulation between multiple nodes.

[0005] In view of this, a first aspect of the present invention provides a method for real-time simulation of software-hardware clock synchronization between multiple nodes, comprising:

[0006] In response to a clock synchronization request for a real-time simulation task, the clock signals of each calculation step of the hardware connected to each node in the simulation software are synchronized;

[0007] For each node in the simulation software, comparing the number of calculation steps of the first node with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node to determine whether the number of calculation steps is synchronized;

[0008] When the calculation step number of the first node is compared to the calculation step number corresponding to the clock signal of the hardware connected to the first node and is synchronized, the first node continues to execute the next calculation task, and updates the current calculation step number of the first node by 1, and goes to the step of comparing the calculation step number of the first node to see whether the calculation step number corresponding to the clock signal of the hardware connected to the first node is synchronized, until the calculation tasks of all calculation steps of the first node are completed.

[0009] Preferably, the step of synchronizing the clock signals of the calculation steps of the hardware to which each node in the simulation software is respectively connected comprises:

[0010] Based on the timing server, a reference clock signal is distributed to each calculation step of the hardware connected to each node in the simulation software;

[0011] The clock signals of the calculation steps of the hardware connected to each node are clock-calibrated according to each reference clock signal, so that the clock signals of the calculation steps of the hardware are synchronized with the reference clock signals allocated to the calculation steps of the hardware.

[0012] Preferably, the step of comparing, for each node in the simulation software, the number of calculation steps of a first node and the number of calculation steps corresponding to the clock signal of the hardware connected to the first node to determine whether they are synchronized comprises:

[0013] When the first node completes the current computing task, transmitting computing task data to the hardware connected to the first node, wherein the computing task data includes the number of computing steps corresponding to the current computing task;

[0014] comparing the number of calculation steps corresponding to the first node completing the current calculation task and the number of calculation steps corresponding to the current clock signal received by the hardware to determine whether they are consistent;

[0015] When the number of calculation steps corresponding to the first node completing the current calculation task received by the hardware is compared with the number of calculation steps corresponding to the current clock signal, the hardware executes the next calculation task and transmits the next calculation task data back to the simulation software running on the first node;

[0016] Comparing whether the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node is consistent with the number of calculation steps when the first node executes the next calculation task;

[0017] When the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node is compared with the number of calculation steps when the first node completes the next calculation task, it is determined that the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node.

[0018] Preferably, after the step of comparing whether the number of calculation steps corresponding to the current calculation task received by the hardware is consistent with the number of calculation steps corresponding to the current clock signal, the method further includes:

[0019] When the number of calculation steps corresponding to the first node completing the current calculation task received by the hardware is compared and the number of calculation steps corresponding to the current clock signal are inconsistent, the simulation program run by the simulation software is terminated.

[0020] Preferably, after the step of comparing, for each node in the simulation software, the number of calculation steps of the first node and the number of calculation steps corresponding to the clock signal of the hardware connected to the first node to determine whether the first node is synchronized, the method further comprises:

[0021] When the number of calculation steps of the first node is compared to the number of calculation steps corresponding to the clock signal of the hardware connected to the first node and is found to be out of synchronization, the simulation program run by the simulation software is terminated.

[0022] Preferably, the method further comprises:

[0023] When the first node completes the current computing task, transmitting computing task data to a second node connected to the first node, wherein the computing task data includes the number of computing steps corresponding to the current computing task;

[0024] periodically comparing, according to a preset verification period, whether the number of computation steps corresponding to the completion of the current computation task by the first node and received by the second node is consistent with the number of computation steps corresponding to the completion of the current computation task by the second node;

[0025] When comparing the number of computing steps corresponding to the first node completing the current computing task received by the second node and the number of computing steps corresponding to the second node completing the current computing task, if they are consistent, the second node executes the next computing task;

[0026] When the number of calculation steps corresponding to the first node completing the current calculation task received by the second node is compared and the number of calculation steps corresponding to the second node completing the current calculation task are inconsistent, the simulation program run by the simulation software is terminated.

[0027] In a second aspect, the present invention further provides a real-time simulation multi-node software-hardware clock synchronization device, comprising:

[0028] A timing synchronization module is used to synchronize the clock signals of the calculation steps of the hardware connected to each node in the simulation software in response to a clock synchronization request for the real-time simulation task;

[0029] A verification synchronization module is used to compare, for each node in the simulation software, whether the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node;

[0030] The verification execution module is used to compare whether the calculation step number of the first node is synchronized with the calculation step number corresponding to the clock signal of the hardware connected to the first node, then the first node continues to execute the next calculation task, and updates the current calculation step number of the first node by 1, and executes the comparison of whether the calculation step number of the first node is synchronized with the calculation step number corresponding to the clock signal of the hardware connected to the first node, until the calculation tasks of all calculation steps of the first node are completed.

[0031] In a third aspect, the present invention also provides an electronic device comprising a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the processor executes the steps of the real-time simulation multi-node software-hardware clock synchronization method as described in the first aspect.

[0032] In a fourth aspect, the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed, implements the steps of the real-time simulation multi-node software-hardware clock synchronization method as described in the first aspect.

[0033] In a fifth aspect, the present invention also provides a computer program product, comprising a computer program stored on a non-transitory computer-readable storage medium, wherein the computer program comprises program instructions, wherein when the program instructions are executed by a computer, the computer is caused to execute the steps of the real-time simulation multi-node software-hardware clock synchronization method as described in the first aspect.

[0034] It can be seen from the above technical solutions that the present invention has the following advantages:

[0035] The present invention ensures the consistency of the simulation system clock signal by synchronizing the clock signals of the calculation steps of the hardware connected to each node in the simulation software. By verifying the calculation steps between the hardware and software of each node, the time step consistency of the software and the hardware is ensured, the clock synchronization mechanism between software is eliminated, the difficulty of simulation system clock synchronization is reduced, and the accumulation of system clock errors is avoided, thereby improving the joint real-time simulation performance between multiple nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of the structure of an electromagnetic transient simulation system provided by an embodiment of the present invention;

[0037] Figure 2 A flowchart of a method for real-time simulation of software-hardware clock synchronization between multiple nodes provided by an embodiment of the present invention;

[0038] Figure 3A schematic diagram of the structure of a real-time simulation multi-node software-hardware clock synchronization device provided by an embodiment of the present invention;

[0039] Figure 4 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0041] The real-time simulation multi-node software-hardware clock synchronization method provided in the embodiment of the present application can be applied to Figure 1 The electromagnetic transient simulation system is shown in the application environment. The electromagnetic transient simulation system includes a timing server 101, a signal amplifier 102, an FPGA timing card 103, hardware 104 and simulation software 105. The timing server 101 can be a Beidou timing server, which receives Beidou satellite signals to generate a reference clock signal, and sends the reference clock signal to the signal amplifier through a communication channel according to the 1PPS and TOD protocols. i It is the reference clock signal for the xth calculation step. The signal amplifier 102 receives the reference clock signal sent by the timing server, and then amplifies and processes the reference clock signal to ensure that the reference clock signal is not interfered with and remains stable during transmission, and distributes the reference clock signal for each calculation step to the FPGA timing card 103 of different nodes to meet the requirement of smaller clock error of each node. There are multiple FPGA timing cards 103, and the multiple FPGA timing cards are respectively interconnected with the hardware of multiple different nodes. The timing card receives the amplified reference clock signal sent by the signal amplifier 102, and then parses and processes the amplified reference clock signal. The FPGA timing card 103 will calibrate its own clock according to the received amplified reference clock signal to ensure that the clock signal on the timing card is synchronized with the clock of the timing server 101, so as to ensure that each hardware 104 in the network can obtain accurate authorized clock information, thereby maintaining the time uniformity and synchronization of the entire network system. Among them, the clock signal of the xth calculation step of the FPGA timing card 103 of the jth node is recorded as t jx , (x, j=1,2,…).

[0042] A node is the smallest independent unit of simulation calculations within the simulation software, including the CPU, FPGA, and corresponding peripheral interfaces. In an electromagnetic transient simulation system, the nodes within the simulation software 105 are connected to corresponding hardware 104, such as various control and protection devices, rectifier / inverter equipment for new energy sources, and protection devices.

[0043] Based on this, Figure 2 As shown, an embodiment of the present invention provides a real-time simulation method for software-hardware clock synchronization between multiple nodes. The method provided by the embodiment of the present invention can be executed by a real-time simulation device for software-hardware clock synchronization between multiple nodes. The real-time simulation device for software-hardware clock synchronization between multiple nodes can be implemented in the form of hardware and / or software. The real-time simulation device for software-hardware clock synchronization between multiple nodes can be configured in a computer device.

[0044] The embodiment of the present invention provides a method for real-time simulation of software-hardware clock synchronization between multiple nodes, including steps S1 to S3.

[0045] Step S1: In response to a clock synchronization request for a real-time simulation task, the clock signals of the calculation steps of the hardware to which each node in the simulation software is respectively connected are synchronized.

[0046] Among them, based on the application environment of the aforementioned electromagnetic transient simulation system, the FPGA timing card 103 is used to synchronize the clock signals of each calculation step of the hardware connected to each node in the simulation software. The clock signals of each calculation step of the hardware of each node can be synchronized with the clock between the Beidou timing server. At the same time, the timing synchronization of the clock signals of each calculation step of the hardware of each node can be completed before simulation, ensuring the consistency of the clock signal of the simulation system.

[0047] Since software synchronization involves more complex links and requires execution instruction set synchronization, there are too many interference factors (such as various operations and scheduling performed by the operating system), which makes it extremely difficult to implement. Therefore, the embodiment of the present invention first synchronizes the clock signals of each calculation step of the hardware of each node, thereby reducing the difficulty of simulation system clock synchronization.

[0048] Specifically, the process of performing timing synchronization on the clock signals of the calculation steps of the hardware to which each node in the simulation software is respectively connected in step S1 includes steps S101 to S102.

[0049] Step S101: allocating a reference clock signal to each calculation step of the hardware to which each node in the simulation software is connected based on the timing server.

[0050] Step S102: perform clock calibration on the clock signals of the calculation steps of the hardware connected to each node according to each reference clock signal, so that the clock signals of the calculation steps of the hardware are synchronized with the reference clock signals allocated to the calculation steps of the hardware.

[0051] Step S2: for each node in the simulation software, compare the number of calculation steps of the first node with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node to see whether they are synchronized.

[0052] The first node may be any node in the simulation software.

[0053] During the real-time simulation process, multiple nodes in the simulation software perform joint simulation operation. At the same time, based on the simulation real-time synchronization relationship, the calculation steps of the first node should be synchronized with the calculation steps corresponding to the clock signal of the hardware connected to the first node.

[0054] If the calculation steps of the two are not synchronized, it means that the steps of the two simulation programs are not consistent. It is necessary to force the program to stop and not proceed to the next step. An error will be reported directly.

[0055] For example, when the number of calculation steps of the first node is compared and is not synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node, the simulation program run by the simulation software is terminated, thereby reporting an error to avoid the accumulation of system clock errors, thereby improving the electromagnetic transient joint real-time simulation performance between multiple nodes.

[0056] Exemplarily, the process of comparing the number of calculation steps of the first node and the number of calculation steps corresponding to the clock signal of the hardware connected to the first node in step S2 to see whether they are synchronized includes steps S201 to S205.

[0057] Step S201: When the first node completes the current computing task, the computing task data is transmitted to the hardware connected to the first node, wherein the computing task data includes the number of computing steps corresponding to the current computing task.

[0058] Among them, the calculation task is the simulation task when the first node runs at the current calculation step, such as various primary and secondary calculation tasks in electromagnetic transient simulation, four arithmetic operations of various data, and matrix inversion.

[0059] When the first node completes the current computing task, it outputs the computing task data to the hardware connected to the first node. In addition to the task calculation result of the first node completing the current computing task, the computing task data should also include the number of calculation steps corresponding to the current computing task to facilitate subsequent hardware verification.

[0060] Step S202: Compare the number of calculation steps corresponding to the first node completing the current calculation task received by the hardware with the number of calculation steps corresponding to the current clock signal to see whether they are consistent.

[0061] Step S203: When the number of calculation steps corresponding to the current calculation task completed by the first node received by the comparison hardware is consistent with the number of calculation steps corresponding to the current clock signal, the hardware executes the next calculation task and returns the next calculation task data to the simulation software running on the first node.

[0062] Similarly, when the number of calculation steps corresponding to the current calculation task completed by the first node received by the comparison hardware is inconsistent with the number of calculation steps corresponding to the current clock signal, the simulation program run by the simulation software is terminated and an error is reported, and the next step is not performed to avoid the accumulation of system clock errors, thereby improving the performance of electromagnetic transient joint real-time simulation among multiple nodes.

[0063] When the number of calculation steps corresponding to the current calculation task completed by the first node received by the comparison hardware is consistent with the number of calculation steps corresponding to the current clock signal, in order to make the software and hardware a benchmark for each other, the embodiment of the present invention iteratively verifies the number of calculation steps, that is, the hardware executes the next step of the calculation task data back to the simulation software running on the first node, so that the simulation software can further verify the calculation steps relative to the hardware, wherein the calculation task data returned by the hardware to the simulation software should include the number of calculation steps.

[0064] Step S204: Compare the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node with the number of calculation steps when the first node executes the next calculation task to see if they are consistent.

[0065] Step S205: When the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node is compared and is consistent with the number of calculation steps when the first node completes the next calculation task, it is determined that the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node.

[0066] When the hardware executes the next step of the calculation task data, the simulation software on the first node connected to the hardware should also execute the calculation task data with the same number of calculation steps as the hardware.

[0067] When the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node is inconsistent with the number of calculation steps when the first node completes the next calculation task, it is determined that the calculation steps of the first node are not synchronized with the calculation steps corresponding to the clock signal of the hardware connected to the first node. The simulation program run by the simulation software is terminated to report an error and the next operation is not performed to avoid the accumulation of system clock errors, thereby improving the electromagnetic transient joint real-time simulation performance between multiple nodes.

[0068] Step S3: When the calculation step number of the first node is compared to the calculation step number corresponding to the clock signal of the hardware connected to the first node and is synchronized, the first node continues to execute the next calculation task, and updates the current calculation step number of the first node plus 1, and goes to step S2 until the calculation tasks of all calculation steps of the first node are completed.

[0069] Among them, in order to complete the software-hardware clock synchronization between all nodes in the simulation system, after completing the clock synchronization of all calculation steps of each node, it is necessary to synchronize the clocks of all calculation steps of the next node until the calculation tasks of all calculation steps of all nodes in the simulation system are completed and the clocks are synchronized.

[0070] The above can complete the software-hardware clock synchronization between all nodes in the simulation system. In real-time multi-node joint simulation, the clocks of the software between multiple nodes should also be synchronized.

[0071] To this end, in some embodiments, the method further includes steps S401 to S404.

[0072] Step S401: When the first node completes the current computing task, the computing task data is transmitted to the second node connected to the first node, wherein the computing task data includes the number of computing steps corresponding to the current computing task.

[0073] Step S402: according to a preset verification period, periodically compare the number of calculation steps corresponding to the first node completing the current calculation task and received by the second node with the number of calculation steps corresponding to the second node completing the current calculation task to see whether they are consistent.

[0074] It should be noted that during multi-node joint simulation, the clock signal of each node's calculation step number has a time delay, and verification is performed at each step, which also affects simulation efficiency. Therefore, the calculation step number between two nodes can be verified every certain number of calculation steps. Therefore, it is necessary to periodically verify the calculation step number between two nodes according to a preset verification period. The verification period can be 100 steps, 1000 steps, etc., without limitation.

[0075] The check period can be calculated based on the crystal oscillator frequency f in the host of the first node. j To determine, that is, the verification period n=f j / 100.

[0076] Step S403: When the number of calculation steps corresponding to the first node completing the current calculation task and received by the second node is compared and the number of calculation steps corresponding to the second node completing the current calculation task are consistent, the second node executes the next calculation task.

[0077] Step S404: When the number of calculation steps corresponding to the first node completing the current calculation task and received by the second node is compared and the number of calculation steps corresponding to the second node completing the current calculation task are inconsistent, the simulation program run by the simulation software is terminated.

[0078] The following is a calculation example of the real-time simulation multi-node software-hardware clock synchronization method provided by an embodiment of the present invention. The calculation example includes:

[0079] 1) Determine the signal T received by the Beidou timing server x The reference clock signal for the xth calculation step is calculated by x After amplification, the reference clock signal T of the xth calculation step is x FPGA timing cards assigned to different nodes, where the x-step clock signal of the FPGA timing card of the j-th node is t jx (x, j = 1, 2, ...).

[0080] 2) FPGA timing card receives reference clock signal T x , and calibrate its own clock signal, it can achieve time synchronization with the timing server.

[0081] 3) After starting the multi-node joint simulation task, the simulation software completes the mth step of the calculation task on the jth node and transmits the calculation results to the external hardware device and other nodes connected to the node j. The transmitted data is recorded as D ojm (m, j=1,2,…).

[0082] 4) The external hardware device connected to the jth node receives data D ojm After that, with its own clock signal t jx Compare, if the number of calculation steps x = the number of calculation steps m, then the hardware device performs the next calculation task and uses the sampling device to collect the calculation task data D of the hardware device ijx+1 Transmitted to the simulation software running on the jth node; if x≠m, the simulation program is terminated.

[0083] 5) The simulation software on the jth node receives the computing task data D transmitted by the hardware device connected to the node j ijx+1 After that, the data D executed by this node j ojm If x+1=m+1, the simulation software will continue the next calculation task on the jth node and pass the calculation results to the external hardware devices and other nodes connected to this node. The transmitted data is recorded as D ojm+1 ; If x+1≠m+1, terminate the simulation program. If the program is terminated, it will terminate without continuing the operation.

[0084] 6) Perform software step comparison and verification every 1000 steps: After the simulation software completes the yth step calculation task on the jth node, the transmitted data D oky To the kth node. The kth node receives the data D oky The transmission data D after the simulation software completes the m-1 step calculation task at this node k ojm-1 Compare, if y-1=m-1, the simulation software will continue with the next calculation task on the kth node; if y-1≠m-1, the simulation program will be terminated.

[0085] It should be noted that the present invention ensures the consistency of the simulation system clock signal by synchronizing the clock signals of each calculation step of the hardware connected to each node in the simulation software. By verifying the calculation steps between the hardware and software of each node, the time step consistency of the software and hardware is ensured, the clock synchronization mechanism between software is eliminated, the difficulty of simulation system clock synchronization is reduced, and the accumulation of system clock errors is avoided, thereby improving the joint real-time simulation performance between multiple nodes.

[0086] Based on the same inventive concept, an embodiment of the present application also provides a real-time simulation multi-node software-hardware clock synchronization device for implementing the above-mentioned real-time simulation multi-node software-hardware clock synchronization method.

[0087] The implementation solution provided by the device to solve the problem is similar to the implementation solution described in the above method. Therefore, the specific limitations in the embodiments of one or more real-time simulation multi-node software-hardware clock synchronization devices provided below can be found in the above limitations on the real-time simulation multi-node software-hardware clock synchronization method, and will not be repeated here.

[0088] like Figure 3 As shown, an embodiment of the present invention further provides a real-time simulation multi-node software-hardware clock synchronization device, comprising:

[0089] The timing synchronization module 100 is used to synchronize the clock signals of the calculation steps of the hardware connected to each node in the simulation software in response to the clock synchronization request for the real-time simulation task;

[0090] A verification synchronization module 200 is used to compare, for each node in the simulation software, whether the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node;

[0091] The verification execution module 300 is used to compare whether the calculation step number of the first node is synchronized with the calculation step number corresponding to the clock signal of the hardware connected to the first node. When the calculation step number of the first node is compared and synchronized with the calculation step number corresponding to the clock signal of the hardware connected to the first node, the first node continues to execute the next calculation task, and updates the current calculation step number of the first node by 1, and executes the comparison of whether the calculation step number of the first node is synchronized with the calculation step number corresponding to the clock signal of the hardware connected to the first node, until the calculation tasks of all calculation steps of the first node are completed.

[0092] In some embodiments, the timing synchronization module 100 is used to allocate a reference clock signal to each calculation step of the hardware connected to each node in the simulation software based on the timing server; and perform clock calibration on the clock signal of each calculation step of the hardware connected to each node according to each reference clock signal, so that the clock signal of each calculation step of the hardware is synchronized with the reference clock signal allocated to each calculation step of the hardware.

[0093] In some embodiments, the verification synchronization module 200 is used to transmit the computing task data to the hardware connected to the first node when the first node completes the current computing task, wherein the computing task data includes the number of computing steps corresponding to the current computing task; compare whether the number of computing steps corresponding to the first node completing the current computing task received by the hardware is consistent with the number of computing steps corresponding to the current clock signal; when the number of computing steps corresponding to the first node completing the current computing task received by the hardware is consistent with the number of computing steps corresponding to the current clock signal, the hardware executes the next computing task and transmits the next computing task data back to the simulation software running on the first node; compare whether the number of computing steps corresponding to the next computing task data received by the simulation software on the first node is consistent with the number of computing steps when the first node executes the next computing task; when the number of computing steps corresponding to the next computing task data received by the simulation software on the first node is consistent with the number of computing steps when the first node completes the next computing task, it is determined that the computing steps of the first node are synchronized with the number of computing steps corresponding to the clock signal of the hardware connected to the first node.

[0094] In some embodiments, the verification synchronization module 200 is further used to terminate the simulation program run by the simulation software when the number of calculation steps corresponding to the first node completing the current calculation task received by the comparison hardware is inconsistent with the number of calculation steps corresponding to the current clock signal.

[0095] In some embodiments, the verification synchronization module 200 is further configured to terminate the simulation program run by the simulation software when the number of calculation steps of the first node is compared to the number of calculation steps corresponding to the clock signal of the hardware connected to the first node and is out of synchronization.

[0096] In some embodiments, the apparatus further comprises:

[0097] The data transmission module is used to transmit the computing task data to the second node connected to the first node when the first node completes the current computing task, wherein the computing task data includes the number of computing steps corresponding to the current computing task.

[0098] The node verification module is used to periodically compare the number of calculation steps corresponding to the first node completing the current calculation task received by the second node with the number of calculation steps corresponding to the second node completing the current calculation task according to a preset verification period to see whether they are consistent.

[0099] The first execution module is used to compare the number of calculation steps corresponding to the first node completing the current calculation task received by the second node and the number of calculation steps corresponding to the second node completing the current calculation task, and when the comparison is consistent, the second node executes the next calculation task.

[0100] The second execution module is used to terminate the simulation program run by the simulation software when comparing the number of calculation steps corresponding to the first node completing the current calculation task received by the second node and the number of calculation steps corresponding to the second node completing the current calculation task are inconsistent.

[0101] like Figure 4 As shown, an embodiment of the present invention also provides an electronic device, the electronic device 10 includes a memory 20 and a processor 30, the memory 20 stores a computer program, and when the computer program is executed by the processor 30, the processor 30 executes the steps of the real-time simulation multi-node software-hardware clock synchronization method as in any of the above embodiments.

[0102] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed, the steps of the real-time simulation method for synchronizing software and hardware clocks between multiple nodes in any of the above embodiments are implemented.

[0103] An embodiment of the present invention also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions, wherein when the program instructions are executed by a computer, the computer executes the steps of the real-time simulation multi-node software-hardware clock synchronization method in any of the above embodiments.

[0104] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, electronic devices, computer storage media, and computer program products can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0105] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0106] In several embodiments provided by the present invention, it is understood that each box in the flow chart or block diagram can represent a module, program segment or part of the code, and the module, program segment or part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved.

[0107] In the several embodiments provided by the present invention, it should be understood that the disclosed systems, electronic devices, computer storage media, computer program products and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0108] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0109] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0110] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for executing all or part of the steps of the method described in each embodiment of the present invention via a computer device (which can be a personal computer, server, or network device, etc.). The aforementioned storage medium includes various media that can store program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0111] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for real-time simulation of software-hardware clock synchronization between multiple nodes, characterized in that: include: In response to a clock synchronization request for a real-time simulation task, the clock signals of each calculation step of the hardware connected to each node in the simulation software are synchronized; For each node in the simulation software, comparing the number of calculation steps of the first node with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node to determine whether the number of calculation steps is synchronized, including: When the first node completes the current computing task, transmitting computing task data to the hardware connected to the first node, wherein the computing task data includes the number of computing steps corresponding to the current computing task; comparing the number of calculation steps corresponding to the first node completing the current calculation task and the number of calculation steps corresponding to the current clock signal received by the hardware to determine whether they are consistent; When the number of calculation steps corresponding to the first node completing the current calculation task received by the hardware is compared with the number of calculation steps corresponding to the current clock signal, the hardware executes the next calculation task and transmits the next calculation task data back to the simulation software running on the first node; Comparing whether the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node is consistent with the number of calculation steps when the first node executes the next calculation task; When comparing the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node and the number of calculation steps when the first node completes the next calculation task, it is determined that the calculation step number of the first node is synchronized with the calculation step number corresponding to the clock signal of the hardware connected to the first node; When the calculation step number of the first node is compared to the calculation step number corresponding to the clock signal of the hardware connected to the first node and is synchronized, the first node continues to execute the next calculation task, and updates the current calculation step number of the first node by 1, and goes to the step of comparing the calculation step number of the first node to see whether the calculation step number corresponding to the clock signal of the hardware connected to the first node is synchronized, until the calculation tasks of all calculation steps of the first node are completed.

2. The method for real-time simulation multi-node software-hardware clock synchronization according to claim 1, wherein: The step of synchronizing the clock signals of the calculation steps of the hardware to which the nodes in the simulation software are respectively connected comprises: Based on the timing server, a reference clock signal is distributed to each calculation step of the hardware connected to each node in the simulation software; The clock signals of the calculation steps of the hardware connected to each node are clock-calibrated according to each reference clock signal, so that the clock signals of the calculation steps of the hardware are synchronized with the reference clock signals allocated to the calculation steps of the hardware.

3. The real-time simulation multi-node software-hardware clock synchronization method according to claim 1, characterized in that: After the step of comparing the number of calculation steps corresponding to the first node completing the current calculation task received by the hardware with the number of calculation steps corresponding to the current clock signal to see whether they are consistent, the method further includes: When the number of calculation steps corresponding to the first node completing the current calculation task received by the hardware is compared and the number of calculation steps corresponding to the current clock signal are inconsistent, the simulation program run by the simulation software is terminated.

4. The method for real-time simulation multi-node software-hardware clock synchronization according to claim 1, wherein: After the step of comparing, for each node in the simulation software, the number of calculation steps of the first node and the number of calculation steps corresponding to the clock signal of the hardware connected to the first node to determine whether the first node is synchronized, the method further includes: When the number of calculation steps of the first node is compared to the number of calculation steps corresponding to the clock signal of the hardware connected to the first node and is found to be out of synchronization, the simulation program run by the simulation software is terminated.

5. The method for real-time simulation multi-node software-hardware clock synchronization according to claim 1, wherein: The method further comprises: When the first node completes the current computing task, transmitting computing task data to a second node connected to the first node, wherein the computing task data includes the number of computing steps corresponding to the current computing task; periodically comparing, according to a preset verification period, whether the number of computation steps corresponding to the completion of the current computation task by the first node and received by the second node is consistent with the number of computation steps corresponding to the completion of the current computation task by the second node; When comparing the number of computing steps corresponding to the first node completing the current computing task received by the second node and the number of computing steps corresponding to the second node completing the current computing task, if they are consistent, the second node executes the next computing task; When the number of calculation steps corresponding to the first node completing the current calculation task received by the second node is compared and the number of calculation steps corresponding to the second node completing the current calculation task are inconsistent, the simulation program run by the simulation software is terminated.

6. A real-time simulation multi-node software-hardware clock synchronization device, characterized in that: include: A timing synchronization module is used to synchronize the clock signals of the calculation steps of the hardware connected to each node in the simulation software in response to a clock synchronization request for the real-time simulation task; A verification synchronization module is used to compare, for each node in the simulation software, whether the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node; For each node in the simulation software, comparing the number of calculation steps of the first node with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node to determine whether the number of calculation steps is synchronized, including: When the first node completes the current computing task, transmitting computing task data to the hardware connected to the first node, wherein the computing task data includes the number of computing steps corresponding to the current computing task; comparing the number of calculation steps corresponding to the first node completing the current calculation task and the number of calculation steps corresponding to the current clock signal received by the hardware to determine whether they are consistent; When the number of calculation steps corresponding to the first node completing the current calculation task received by the hardware is compared with the number of calculation steps corresponding to the current clock signal, the hardware executes the next calculation task and transmits the next calculation task data back to the simulation software running on the first node; Comparing whether the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node is consistent with the number of calculation steps when the first node executes the next calculation task; When comparing the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node and the number of calculation steps when the first node completes the next calculation task, it is determined that the calculation step number of the first node is synchronized with the calculation step number corresponding to the clock signal of the hardware connected to the first node; The verification execution module is used to compare whether the calculation step number of the first node is synchronized with the calculation step number corresponding to the clock signal of the hardware connected to the first node, then the first node continues to execute the next calculation task, and updates the current calculation step number of the first node by 1, and executes the comparison of whether the calculation step number of the first node is synchronized with the calculation step number corresponding to the clock signal of the hardware connected to the first node, until the calculation tasks of all calculation steps of the first node are completed.

7. An electronic device, characterized in that: The electronic device includes a memory and a processor, wherein a computer program is stored in the memory. When the computer program is executed by the processor, the processor executes the steps of the real-time simulation multi-node software-hardware clock synchronization method as described in any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed, the steps of the real-time simulation multi-node software-hardware clock synchronization method according to any one of claims 1 to 5 are implemented.

9. A computer program product, characterized in that The computer program product includes a computer program stored on a non-transitory computer-readable storage medium, wherein the computer program includes program instructions, wherein when the program instructions are executed by a computer, the computer is caused to perform the steps of the real-time simulation multi-node software-hardware clock synchronization method as described in any one of claims 1 to 5.

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