Measurement system and measurement method for determining clock synchronization accuracy

Abstract

The present disclosure provides a measurement system, method, device and medium for determining clock synchronization accuracy, characterized in that it comprises: a signal acquisition module configured to simultaneously acquire signals from at least one device and convert the acquired signals into logic level signals; a signal processing module configured to receive the logic level signals from the signal acquisition module and perform "logical and" and "logical or" operations on the logic level signals respectively to output processed signals; a recording module configured to record time data corresponding to the periodic signals output by the signal processing module in each period; and a data analysis module configured to receive the time data from the recording module and compare the time data with corresponding master clock time data, thereby determining the clock synchronization accuracy of the at least one device.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology in industrial automation, and in particular to a measurement system and method for determining clock synchronization accuracy. Background Technology

[0002] In the field of industrial automation, such as Figure 1 As shown, when multiple devices 1 to 6 are interconnected using a certain connection method (e.g., via an EPA communication protocol network), in order for all connected devices to be uniformly scheduled and operated to jointly complete the measurement and control work in the system, all connected devices need to use the time of one of the devices (e.g., device 1) as a reference, and the other devices (e.g., devices 2 to 6) synchronize with the device providing the time reference. Device 1, which provides the clock reference, is called the master clock device, and devices 2 to 6, which synchronize with the master clock device, are called slave clock devices.

[0003] Traditional methods for measuring master-slave clock synchronization accuracy rely primarily on specialized equipment such as oscilloscopes, which are typically expensive. With technological advancements, some systems have begun employing software-based monitoring methods, analyzing communication data to assess clock synchronization accuracy. However, software-based monitoring methods are susceptible to network latency and packet loss. Additionally, there are solutions using centralized synchronization systems that broadcast time signals from a master clock to synchronize multiple devices; however, these methods suffer from high dependency and the risk of single points of failure.

[0004] In contrast, using an oscilloscope for clock synchronization accuracy measurements offers advantages such as high reliability, high-precision time resolution, and intuitive waveform display, making it easier for engineers to analyze synchronization signals. While oscilloscopes can provide a high-precision time reference, using them for clock synchronization accuracy measurements has limitations such as operational complexity, high cost, and low time efficiency. Furthermore, each measurement can only be applied to a small number of nodes, making it unsuitable for multi-node clock synchronization measurement scenarios. Summary of the Invention

[0005] To address the aforementioned issues, this disclosure provides a measurement system and testing method for determining clock synchronization accuracy. Through a signal acquisition module, a logic processing module, and a data analysis module, it can not only simultaneously acquire and select multiple signals, but also monitor and record changes in the synchronization signal in real time and intuitively output the clock synchronization accuracy measurement results. This avoids complex operations, significantly improves operational convenience and measurement efficiency, and solves the above problems.

[0006] According to a first aspect of the present disclosure, a measurement system for determining clock synchronization accuracy is provided, comprising: a signal acquisition module configured to simultaneously acquire signals from at least one device and convert the acquired signals into logic level signals; a signal processing module configured to receive the logic level signals from the signal acquisition module and perform "logical AND" and "logical OR" operations on the logic level signals respectively to output processed signals; a recording module configured to record time data corresponding to the periodic signals output by the signal processing module in each cycle; and a data analysis module configured to receive the time data from the recording module and compare the time data with corresponding master clock time data to determine the clock synchronization accuracy of the at least one device.

[0007] In one embodiment, the signal acquisition module further comprises a channel selection unit configured to be communicatively connected with the recording module, and after the signal acquisition module acquires signals and completes conversion, selectively perform processing on at least part of the logic level signals based on the channel types corresponding to the acquired signals.

[0008] In one embodiment, the channel selection unit is further configured to selectively shield at least part of the logic level signals based on the channel types corresponding to the acquired signals, or transmit at least part of the logic level signals to the recording module.

[0009] In one embodiment, the recording module is further configured to record the time of the logic level signals received from the channel selection unit in each cycle and perform time compensation on the time.

[0010] In one embodiment, the recording module is further configured to record the input time of the logic level signals into the signal processing module and the output time from the signal processing module, so as to obtain a compensation time for time compensation by calculating the difference between the input time and the output time.

[0011] In one embodiment, the recording module is further configured to record the time of the periodic signals output by the signal processing module after "logical OR" processing in each cycle as a left deviation time; and

[0012] record the time of the periodic signals output by the signal processing module after "logical AND" processing as a right deviation time.

[0013] In one embodiment, the data analysis module is further configured to: calculate the maximum left skew time and the maximum right skew time among all cycles based on the left skew time and the right skew time in each cycle recorded by the recording module; and determine the jitter range of the clock synchronization precision based on the maximum left skew time and the maximum right skew time.

[0014] In one embodiment, the data analysis module is configured to: calculate the left skew time difference between the maximum left skew time and the minimum left skew time, and the right skew time difference between the maximum right skew time and the minimum right skew time in each cycle based on the plurality of left skew times and the plurality of right skew times in each cycle recorded by the recording module; and calculate the maximum value among the left skew time difference and the right skew time difference in all cycles, thereby determining the jitter range of the clock synchronization precision based on the maximum value.

[0015] In one embodiment, the data analysis module is configured to: calculate the average value of the left skew time and the right skew time in each cycle based on the left skew time and the right skew time in each cycle recorded by the recording module; calculate the total average value of the average values in all cycles, and the difference between the total average value and the corresponding master clock time data; and determine the skew of the clock synchronization precision based on the difference between the total average value and the corresponding master clock time data.

[0016] In one embodiment, the data analysis module is configured to: calculate the left difference value of the left skew time and the corresponding master clock time, and the right difference value of the right skew time and the corresponding master clock time in each cycle based on the plurality of left skew times and the plurality of right skew times in each cycle recorded by the recording module; perform comparison on the left difference value and the right difference value to obtain the maximum value among the left difference value and the right difference value in each cycle; and calculate the average value of the maximum values for all cycles, thereby determining the skew of the clock synchronization precision based on the average value.

[0017] According to a second aspect of the present disclosure, a measurement method is provided, comprising: connecting a signal acquisition module of the measurement system with at least one communication device; acquiring signals by the signal acquisition module and converting the acquired signals into logic level signals; performing logic processing on the logic level signals by the signal processing module and outputting to a recording module; recording the time when the signal processing module outputs periodic signals by the recording module; comparing the time data with the master clock time data by the data analysis module, thereby determining the clock synchronization precision.

[0018] According to a third aspect of the present disclosure, there is provided a computing device for determining clock synchronization accuracy, comprising one or more processors; and memory storing computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to perform the measurement method according to the second aspect of the present disclosure.

[0019] According to a fourth aspect of the present disclosure, there is provided a non-transitory storage medium having stored thereon computer-executable instructions that, when executed by a computer, cause the computer to perform the measurement method according to the second aspect or the third aspect of the present disclosure.

[0020] It should be understood that nothing in this section is intended to limit the scope of the embodiments of the present disclosure. Other aspects of the present disclosure will become apparent from the following description, which is given by way of example only. BRIEF DESCRIPTION OF DRAWINGS

[0021] The above and other features, aspects and advantages of certain embodiments of the present disclosure will become more apparent from the following description of the disclosure when taken in conjunction with the accompanying drawings. In the drawings, like reference numerals refer to like elements.

[0022] Figure 1 A schematic diagram of a plurality of devices in a connected state according to embodiments of the present disclosure is shown.

[0023] Figure 2 A schematic diagram of a measurement system for determining clock synchronization accuracy according to embodiments of the present disclosure is shown.

[0024] Figure 3 A flowchart of a measurement method using a measurement system for determining clock synchronization accuracy according to embodiments of the present disclosure is shown.

[0025] Figure 4 A schematic block diagram of an electronic device for implementing a measurement method for determining clock synchronization accuracy according to embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0026] Exemplary embodiments of the present disclosure are described herein with reference to the accompanying drawings, in which various details are set forth to facilitate an understanding of the embodiments of the present disclosure. However, it will be apparent to those of ordinary skill in the art that various changes in the details can be made without departing from the scope and spirit of the present disclosure. Like reference numerals in the drawings and the description below mean the same or similar elements.

[0027] The term "includes" and its variants are meant to cover non-exclusive inclusions, i.e., that the listed items are among a list of items, but not excluding others. Unless specifically stated, the term "or" means "and / or". The terms "one example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional example embodiment". Other explicit or implicit definitions can also be included below.

[0028] As described above, in industrial automation systems, the prior art generally measures the clock synchronization accuracy of oscilloscope measuring devices, such as the clock synchronization accuracy of multiple slave devices complying with the EPA (Ethernet for Plant Automation) communication protocol. However, when measuring the clock synchronization accuracy using the prior art, there are generally disadvantages such as high cost, complex operation, low efficiency, insufficient real-time and scalability, and difficulty in integration.

[0029] Specifically, conventional clock synchronization accuracy measurement methods rely on high-precision professional measuring devices such as oscilloscopes, which are generally expensive and increase the cost burden of enterprises. Moreover, it often requires professional knowledge and skills to operate these professional measuring devices, which limits the popularity and convenience of the measurement process. In addition, when using professional measuring devices such as oscilloscopes for synchronization measurement, it is usually necessary to operate node by node, which not only takes time but also has extremely low measurement efficiency in the face of a large number of node measurement scenarios. At the same time, the characteristics of single-point measurement result in limitations of the prior art in real-time monitoring of clock synchronization accuracy, making it difficult to meet the demand for rapid response in a dynamically changing production environment, and even more difficult to flexibly adapt to changes in system size as the industrial automation system expands, thereby lacking good scalability. Moreover, integrating the oscilloscope in the prior art into the existing industrial automation system requires a lot of changes and adaptations, which significantly increases the difficulty of technology upgrade.

[0030] Therefore, the present disclosure provides an improved measurement system and test method for determining clock synchronization accuracy, which can not only realize the collection and signal selection of multiple signals at the same time through the signal collection module, logic processing module and data analysis module, but also can monitor and record the changes of the synchronization signal in real time and intuitively output the clock synchronization accuracy measurement results, thereby avoiding complex operations and significantly improving the operation convenience and measurement efficiency, solving the above problems. The measurement system for determining clock synchronization accuracy according to various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that there can be other components in the actual measurement system, but in order not to obscure the focus of the present disclosure, the present disclosure does not discuss and the accompanying drawings do not show these other components.

[0031] Figure 2 A measurement system for determining clock synchronization accuracy according to some embodiments of the present disclosure is shown. As shown in FIG. 1, the measurement system for determining clock synchronization accuracy according to some embodiments of the present disclosure includes a signal collection module 100, a logic processing module 200 and a data analysis module 300.Figure 2 As shown, the measurement system for determining clock synchronization accuracy comprises a signal acquisition module, a signal processing module, a recording module and a data analysis module connected in sequence, the signal acquisition module is configured to simultaneously acquire signals from at least one communication device, and convert the acquired signals into logic level signals respectively; the signal processing module is configured to receive the logic level signals from the signal acquisition module, and perform logical AND and logical OR processing on the logic level signals respectively to output the processed signals; the recording module is configured to record the time when the signal processing module outputs the periodic signals in each cycle; and the data analysis module is configured to receive the time data from the recording module, and compare the time data with the corresponding master clock time data to determine the clock synchronization accuracy.

[0032] The above measurement system adopts a modular implementation manner, is easy to integrate with existing systems, does not need a complex adaptation process, and reduces the difficulty of technical upgrading. Moreover, the measurement system adopts a low-cost circuit design to replace expensive professional measurement equipment, which significantly reduces the cost.

[0033] The above at least one device can be an EPA slave clock device, which is connected with an EPA master clock device through an EPA communication system, and the above signals can include any one of an Ethernet trigger signal, a periodic signal and a second pulse signal.

[0034] The signal acquisition module can further comprise a channel selection unit, and the channel selection unit is configured to selectively shield at least part of the logic level signals in the plurality of logic level signals according to the channel type corresponding to each acquired signal when the signal acquisition module acquires a plurality of signals. The channel selection unit can also be connected with the recording module, and is configured to selectively transmit at least part of the logic level signals in the plurality of logic level signals to the recording module according to the channel type corresponding to each acquired signal.

[0035] Through the signal acquisition module, the measurement system can be connected with multiple EPA slave clock devices at the same time and acquire multiple signals at the same time, thereby facilitating the measurement system to process multiple signal channels in parallel, thereby greatly shortening the measurement time and improving the measurement efficiency, and being especially suitable for clock synchronization accuracy measurement scenarios of large-scale nodes. Moreover, the signal shielding function of the channel selection unit in the signal acquisition module provides great flexibility, allowing users to selectively shield the signals of specific channels according to test requirements, thereby improving the pertinence and efficiency of the test.

[0036] The signal processing module is configured to perform logical AND and logical OR processing on the logic level signals through AND gates and OR gates or lines or and lines. The signal processing module processes multiple signals in parallel, simplifying the measurement process, reducing the dependence on professional operation skills, making the measurement process more convenient and easy to popularize. At the same time, the logical processing of multiple signals enables the measurement system to respond to the measurement needs of multiple devices in actual use, reduces subsequent operations, and thus ensures real-time monitoring of clock synchronization accuracy, thereby meeting the demand for rapid response in a dynamically changing production environment.

[0037] The recording module can be configured to record the time when the signal processing module outputs the periodic signal after logical OR processing in each cycle as the left deviation time, and record the time when the signal processing module outputs the periodic signal after logical AND processing as the right deviation time. The recording module can also be configured to record the time when the logic level signal from the channel selection unit is received in each cycle, and to perform time compensation on the time. Specifically, the recording module is configured to record the time when the logic level signal enters the signal processing module and the time when the logic level signal is output from the signal processing module, so as to obtain the compensation time for time compensation by calculating the difference between the input and output times.

[0038] It should be understood that the recording module can not only record the time when the output of the signal processing module and the channel selection unit changes from "0" to "1" (i.e., the time when the logic level signal changes from low to high), but also can record the time when the output of the signal processing module and the channel selection unit changes from "1" to "0" (i.e., the time when the logic level signal changes from high to low). Whether the foregoing output signal changes from high to low or from low to high depends on the specific measurement scene requirements.

[0039] Through the above signal processing module and recording module, the measurement system provided by the present disclosure can monitor and record the changes of the synchronization signal in real time, quickly respond to the measurement needs of the clock synchronization accuracy, thereby meeting the demand for rapid response in a dynamically changing production environment.

[0040] In the analysis of clock synchronization accuracy, jitter range and deviation are two important parameters. Therefore, the data analysis module in the measurement system provided by the present disclosure can be at least configured to calculate the jitter range and deviation parameters in the clock synchronization accuracy according to the time data recorded by the recording module.

[0041] Specifically, the data analysis module is configured to calculate the maximum left deviation time and the maximum right deviation time in all cycles according to the left deviation time and the right deviation time in each cycle recorded by the recording module, and determine the jitter range of the clock synchronization accuracy based on the maximum left deviation time and the maximum right deviation time.

[0042] When the signal acquisition module acquires multiple signals, the data analysis module is configured to calculate the left deviation time difference between the maximum and minimum left deviation time and the right deviation time difference between the maximum and minimum right deviation time in each cycle based on the multiple left deviation times and multiple right deviation times recorded by the recording module in each cycle. The jitter range of the clock synchronization accuracy is determined based on the maximum value of the left deviation time difference and right deviation time difference in all cycles.

[0043] For deviation data in clock synchronization accuracy measurement, the data analysis module can also be configured to calculate the average value of the left and right deviation times in each cycle based on the left and right deviation times recorded by the recording module, and calculate the total average value of the average value in all cycles, as well as the difference between the total average value and the corresponding master clock time data, thereby determining the deviation of clock synchronization accuracy based on the difference.

[0044] Similar to the jitter range analysis in clock synchronization accuracy when acquiring multiple signals, when the signal acquisition module acquires multiple signals, the data analysis module can also be configured to calculate the left difference between the left deviation time and the corresponding master clock time and the right difference between the right deviation time and the corresponding master clock time in each cycle based on the multiple left deviation times and multiple right deviation times recorded by the recording module in each cycle. The maximum value of the left and right difference values ​​in each cycle is obtained by comparison, and the average value of the maximum value in all cycles is calculated. The deviation of clock synchronization accuracy is then determined based on the average value.

[0045] Optionally, the data analysis module can also be configured to calculate the average left deviation time and the average right deviation time across all cycles, based on the left deviation time and right deviation time recorded by the recording module for each cycle.

[0046] Furthermore, based on the jitter range data and deviation data output by the data analysis module, users can clearly obtain the clock synchronization accuracy of the device.

[0047] like Figure 3 As shown, the measurement method using the aforementioned measurement system for determining clock synchronization accuracy includes connecting the signal acquisition module of the measurement system to at least one communication device; converting the acquired signal into a logic level signal through the signal acquisition module, performing logic processing on the logic level signal through the signal processing module and outputting it to the recording module, recording the time when the signal processing module outputs a periodic signal through the recording module, and comparing the time data with the master clock time data through the data analysis module, thereby determining the clock synchronization accuracy of the device.

[0048] The measurement system and the measurement method according to the present disclosure are cost-effective, easy to operate, efficient, real-time, and flexible, and have the advantages of customization, scalability, and easy system integration. Specifically, the present disclosure adopts a low-cost circuit design, replacing expensive professional measurement equipment, thereby reducing the cost burden of enterprises in terms of clock synchronization accuracy measurement. Moreover, the measurement system can simultaneously collect signals from multiple devices and dynamically shield the signals of specific channels according to user configuration, which is highly flexible. By logically processing multiple signals, the amount of data is effectively reduced, thereby realizing real-time monitoring of clock synchronization accuracy and timely feedback of measurement results, which is crucial for stable operation of the system.

[0049] In terms of clock synchronization accuracy analysis, the measurement system provided by the present disclosure can not only calculate the average synchronization time, but also determine the maximum and minimum time deviation, which is beneficial for deviation analysis, thereby providing comprehensive evaluation of clock synchronization accuracy. Moreover, the entire measurement system adopts a modular design, each module has a clear function and interface, and is easy to integrate into an existing industrial automation system.

[0050] The present disclosure also provides a computing device for determining clock synchronization accuracy, which comprises one or more processors and a memory storing computer-executable instructions, the computer-executable instructions, when executed by the one or more processors, causing the one or more processors to perform the measurement method according to any one of the preceding embodiments of the present disclosure.

[0051] The present disclosure also provides a non-transitory storage medium having computer-executable instructions stored thereon, the computer-executable instructions, when executed by a computer, causing the computer to perform the measurement method according to any one of the preceding embodiments of the present disclosure.

[0052] Figure 4 A schematic block diagram of an example device 700 that can be used to implement embodiments of the present disclosure is shown. For example, the master clock device 1 and the slave clock devices 2 to 6 as shown in Figure 1 The measurement system as shown in Figure 2 may be implemented by the device 700. As shown in Figure 4 The device 700 includes a central processing unit (CPU) 701, which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 702 or computer program instructions loaded from a storage unit 708 into a random access memory (RAM) 703. In the random access memory 703, various programs and data required for operation of the device 700 can also be stored. The central processing unit 701, the read-only memory 702, and the random access memory 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0053] A number of the components in device 700 are connected to the input / output interface 705, including: an input unit 706, such as a keyboard, mouse, microphone, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a disk, optical disk, etc.; and a communication unit 709, such as a network card, modem, wireless communication transceiver, etc. The communication unit 709 allows device 700 to exchange information / data with other devices over a computer network, such as the Internet, and / or various telecommunication networks.

[0054] The various processes and processes described above, such as the methods, can be performed by the central processing unit 701. For example, in some embodiments, the methods shown can be implemented as a computer software program tangibly embodied in a machine readable medium, such as the storage unit 708. In some embodiments, part or all of the computer program can be loaded onto and / or installed on device 700 via the read only memory 702 and / or the communication unit 709. One or more actions of the methods described above can be performed when the computer program is loaded into the random access memory 703 and executed by the central processing unit 701. Figure 3

[0055] The present disclosure relates to methods, apparatus, systems, electronic devices, computer readable storage media, and / or computer program products. A computer program product can include computer readable program instructions for executing various aspects of the present disclosure. The computer readable storage media can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage media can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage media include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch cards or punched tape, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0056] ​Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0057] Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computing device, partly on the user's computing device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device or entirely on the remote computing device or server. In the latter scenario, the remote computing device can be connected to the user's computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computing device, for example, through the Internet using an Internet Service Provider. In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0058] The computer readable program instructions can also be loaded onto a computing / processing device, other programmable data processing apparatus, or other device to cause a series of operations to be performed on the computing / processing device, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computing / processing device, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0059] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include a non-transitory computer readable storage medium that can be a computer- readable storage medium having no data, programs, program modules, e.g., instructions for operation, or digital content stored thereon or therein for a short time or not at all. The computer readable storage medium can also have other meanings inhered thereby, which are known to those skilled in the relevant art.

[0060] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0061] The flow diagrams and the block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams and the block diagrams can represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical functions (‘instruction(s)’). In some alternative implementations, the functions noted in the block can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and

[0062] It will be appreciated by those of ordinary skill in the art that the present disclosure is not limited to the above-described embodiments, and the present disclosure can be implemented in many other forms without departing from the spirit and scope of the present disclosure. Therefore, the examples and embodiments presented are to be considered illustrative rather than restrictive, and the present disclosure is capable of covering various modifications and alternative forms without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A measurement system for determining clock synchronization accuracy, characterized by, The application comprises: a signal acquisition module configured to simultaneously acquire signals from at least one device and convert the acquired signals into logic level signals; a signal processing module configured to receive the logic level signals from the signal acquisition module and perform "logical AND" and "logical OR" operations on the logic level signals respectively to output processed signals, wherein the time when the signal processing module outputs periodic signals after "logical OR" processing in each cycle is recorded as left deviation time, and the time when the signal processing module outputs periodic signals after "logical AND" processing is recorded as right deviation time; a recording module configured to record time data corresponding to the periodic signals output by the signal processing module in each cycle; and a data analysis module configured to receive the time data from the recording module and compare the time data with corresponding master clock time data to determine the clock synchronization accuracy of the at least one device, wherein the left deviation time and the right deviation time in each cycle recorded by the recording module are used to calculate the left difference value between the left deviation time and the corresponding master clock time and the right difference value between the right deviation time and the corresponding master clock time in each cycle respectively, the left difference value and the right difference value are compared, the maximum value of the left difference value and the right difference value in each cycle is obtained, the average value of the maximum values for all cycles is calculated, and the deviation of the clock synchronization accuracy is determined based on the average value, and the jitter range of the clock synchronization accuracy is determined based on the maximum left deviation time and the maximum right deviation time, wherein the average value of the left deviation time and the right deviation time in each cycle recorded by the recording module is calculated to obtain the average value of the left deviation time and the right deviation time in each cycle, the total average value of the average values for all cycles is calculated, and the difference between the total average value and the corresponding master clock time data is used to determine the deviation of the clock synchronization accuracy.

2. The measurement system of claim 1, wherein, The signal acquisition module further comprises: a channel selection unit configured to be in communication connection with the recording module, and after the signal acquisition module acquires signals and completes conversion, selectively performs processing on at least part of the logic level signals based on the channel types corresponding to the acquired signals.

3. The measurement system of claim 2, wherein, The channel selection unit is further configured to: selectively mask at least part of the logic level signals based on the channel types corresponding to the acquired signals, or transmit at least part of the logic level signals to the recording module.

4. The measurement system of claim 3, wherein, The recording module is further configured to: record the time of the logic level signals received from the channel selection unit in each cycle and perform time compensation on the time.

5. The measurement system of claim 4, wherein, The recording module is further configured to: record the input time of the logic level signals into the signal processing module and the output time from the signal processing module, so as to obtain the compensation time for time compensation by calculating the difference between the input time and the output time.

6. The measurement system of claim 1, wherein, The data analysis module is configured to: Based on the left deviation times and the right deviation times recorded by the recording module in each period, a left deviation time difference between a maximum left deviation time and a minimum left deviation time in each period is calculated, and a right deviation time difference between a maximum right deviation time and a minimum right deviation time is calculated; and The maximum value of the left deviation time difference and the right deviation time difference in all periods is calculated, so as to determine the jitter range in the clock synchronization precision based on the maximum value.

7. A measurement method using the measurement system for determining the precision of clock synchronization according to any one of claims 1 to 6, characterized in that, The measurement method comprises: connecting a signal acquisition module of the measurement system with at least one communication device; acquiring signals by the signal acquisition module and converting the acquired signals into logic level signals; performing logic processing on the logic level signals by the signal processing module and outputting to a recording module; recording, by the recording module, time when the signal processing module outputs periodic signals; comparing, by the data analysis module, the time data with the master clock time data, so as to determine the clock synchronization precision.

8. A computing device for determining clock synchronization accuracy, the computing device comprising: The computing device comprises: one or more processors; and a memory storing computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to perform the measurement method according to claim 7.

9. A non-transitory storage medium having stored thereon computer- executable instructions that, when executed by a processor of a device, cause the device to perform: The computer-executable instructions, when executed by a computer, cause the computer to perform the measurement method according to claim 7.

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