A network model inference fault processing method and system of an MCU

Abstract

The application relates to the field of edge computing and fault processing, and particularly provides a network model inference fault processing method and system of MCU, wherein a main core for model inference under normal conditions is arranged in the MCU, an auxiliary core for model inference when the main core is faulty is also arranged, and the main core and the auxiliary core share a set of storage resources; a fault detection device is also integrated in the MCU, the fault detection device judges whether the main core is faulty and wakes up the auxiliary core. Compared with the prior art, the application can realize the effect that even if the main core is faulty, subsequent inference tasks can still be normally performed.

Description

Technical Field

[0001] This invention relates to the fields of edge computing and fault handling, specifically providing a method and system for handling network model inference faults in an MCU. Background Technology

[0002] Edge computing, as an emerging computing architecture, aims to bring data processing and storage as close as possible to the data source and end user to reduce latency, improve response speed, and reduce the demand for network bandwidth.

[0003] Edge computing places computing resources closest to the data source, significantly reducing data transmission latency and enabling faster data processing and response, which is particularly important for applications requiring real-time feedback (such as industrial automation and intelligent transportation). To accommodate the limited computing and storage capabilities of edge computing devices, researchers have conducted extensive research on reducing model parameters, computational complexity, and memory consumption, resulting in models such as MobileNet and EfficientNet.

[0004] In real life, many edge computing scenarios place high demands on the stability of model inference, such as industrial automation and control systems, intelligent transportation systems, and medical and health monitoring. Therefore, how to improve the stability of edge computing systems has become an urgent problem to be solved. Summary of the Invention

[0005] This invention addresses the shortcomings of the prior art by providing a highly practical method for handling network model inference faults in MCUs.

[0006] A further technical objective of this invention is to provide a reasonably designed, safe, and applicable network model inference fault handling system for MCUs.

[0007] The technical solution adopted by this invention to solve its technical problem is:

[0008] A method for handling network model inference faults in an MCU, wherein the MCU has a main core for model inference under normal conditions and an auxiliary core for model inference when the main core fails, and the main core and the auxiliary core share a set of storage resources;

[0009] The MCU also integrates a fault detection device, which determines whether the main core has malfunctioned and wakes up the auxiliary cores.

[0010] Furthermore, when the main core is running normally, the auxiliary core is in a dormant state. When the main core is performing inference, it saves the first address of the output data of the layer to the intermediate data first address register after completing the calculation task of each layer, and copies the address of the first instruction of the next layer's calculation program from the PC register to the program counter backup register.

[0011] Furthermore, the intermediate data base address register is either the Intermediate Data Base Address Register or the IDBAR.

[0012] The program counter backup register is either the Program Counter Backup Register or the PCBR.

[0013] Furthermore, if the fault detection device detects a fault in the main core during inference, it will wake up the auxiliary core. The auxiliary core first locates the starting address and length of the input data of the incomplete inference layer of the main core in RAM based on the values ​​in IDBAR and IDLR, and then copies the value of PCBR into the PC pointer register to continue the inference that the main core has not completed.

[0014] A network model inference fault handling system for an MCU includes a main core for model inference under normal conditions and an auxiliary core for model inference when the main core fails. The main core and the auxiliary core share a set of storage resources.

[0015] The MCU also integrates a fault detection device, which determines whether the main core has malfunctioned and wakes up the auxiliary cores.

[0016] Furthermore, when the main core is running normally, the auxiliary core is in a dormant state. When the main core is performing inference, it saves the first address of the output data of the layer to the intermediate data first address register after completing the calculation task of each layer, and copies the address of the first instruction of the next layer's calculation program from the PC register to the program counter backup register.

[0017] Furthermore, the intermediate data base address register is either the Intermediate Data Base Address Register or the IDBAR.

[0018] The program counter backup register is either the Program Counter Backup Register or the PCBR.

[0019] Furthermore, if the fault detection device detects a fault in the main core during inference, it will wake up the auxiliary core. The auxiliary core first locates the starting address and length of the input data of the incomplete inference layer of the main core in RAM based on the values ​​in IDBAR and IDLR, and then copies the value of PCBR into the PC pointer register to continue the inference that the main core has not completed.

[0020] Compared with existing technologies, the network model inference fault handling method and system for MCUs of the present invention have the following outstanding advantages:

[0021] This invention enables subsequent inference tasks to continue normally even if the main core fails. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Appendix Figure 1 This is a schematic diagram of the framework for a network model inference fault handling method for MCUs;

[0024] Appendix Figure 2 This is a flowchart illustrating a network model inference fault handling method for an MCU. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] The following is a preferred embodiment:

[0027] like Figure 1-2 As shown in this embodiment, a network model inference fault handling method for an MCU is provided. In the MCU, a main core for model inference under normal conditions is set up, and an auxiliary core for model inference when the main core fails is also set up. The main core and the auxiliary core share a set of storage resources.

[0028] The MCU also integrates a fault detection device, which determines whether the main core has malfunctioned and wakes up the auxiliary cores.

[0029] To conserve energy, auxiliary cores are in sleep mode while the main core is running normally. When the main core is performing inference, after completing the computation task of a layer, the starting address of the output data of that layer (which is also the input data of the next layer) is saved to the Intermediate Data Base Address Register (IDBAR), the data length is saved to the Intermediate Data Length Register (IDLR), and the address of the first instruction of the next layer's computation program is copied from the PC register to the Program Counter Backup Register (PCBR).

[0030] If the fault detection device detects a fault in the main core during inference, such as program crash or core damage, the fault detection device will wake up the auxiliary core. The auxiliary core first locates the starting address and length of the input data of the incomplete inference layer of the main core in RAM based on the values ​​in IDBAR and IDLR, and then copies the value of PCBR into the PC pointer register to continue the inference that the main core has not completed.

[0031] By using the above methods, it is possible to ensure that even if the main core fails, the current and subsequent inference tasks can still proceed normally.

[0032] Based on the above method, this embodiment provides a network model inference fault handling system for an MCU. The MCU has a main core for model inference under normal conditions and an auxiliary core for model inference when the main core fails. The main core and the auxiliary core share a set of storage resources.

[0033] The MCU also integrates a fault detection device, which determines whether the main core has malfunctioned and wakes up the auxiliary cores.

[0034] When the main core is running normally, the auxiliary core is in a dormant state. When the main core is performing inference, it saves the starting address of the output data of the layer to the intermediate data starting address register after completing the calculation task of each layer, and copies the address of the first instruction of the next layer's calculation program from the PC register to the program counter backup register.

[0035] The intermediate data base address register is either the Intermediate Data Base Address Register or the IDBAR.

[0036] The program counter backup register is either the Program Counter Backup Register or the PCBR.

[0037] If the fault detection device detects a fault in the main core during inference, it will wake up the auxiliary core. The auxiliary core first locates the starting address and length of the input data of the incomplete inference layer of the main core in RAM based on the values ​​in IDBAR and IDLR, and then copies the value of PCBR into the PC pointer register to continue the inference that the main core has not completed.

[0038] The paper describes the fault handling process based on inference from a MobileNet V1 network model.

[0039] Assuming the types and parameters of each layer of the MobileNet V1 network model are as shown in Table 1, and assuming that the main core crashes during the inference calculation of layer 8 for some reason, the execution flow is as follows:

[0040] S1. The system is powered on, and both the main core and auxiliary cores are in hibernation mode.

[0041] S2. Inference begins. The main core is awakened and performs inference calculations for layers 1 to 7 according to the network structure. After each layer is completed, the first address and length of the output data are saved to IDBAR and IDLR respectively, and the address of the first instruction of the next layer calculation program is saved to PCBR.

[0042] S3. During the execution of layer 8, the program crashes. The fault monitoring device detects this fault and wakes up the auxiliary core. At this time, the values ​​in IDBAR and IDLR are the starting address and length of the output data of layer 7, respectively, and the value in PCBR is the address of the first instruction of the calculation program of layer 8.

[0043] S4. The auxiliary core copies the value of PCBR, i.e. the address of the first instruction of the 8th layer calculation program, to the PC register, locates the output data of the 7th layer, i.e. the input data of the 8th layer, according to the values ​​of IDBAR and IDLR, and then continues the calculation of the 8th layer.

[0044] S5. After the calculation of layer 8 is completed, the auxiliary core continues to complete the calculation of layers 9 to 30 until the reasoning is completed.

[0045] Table 1. Types and parameters of each layer in the MobileNet V1 network model.

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[0049] The specific embodiments described above are merely specific examples of the present invention. The patent protection scope of the present invention includes, but is not limited to, the specific embodiments described above. Any technical solution that conforms to the technical claims of the present invention and any appropriate changes or substitutions made by a person skilled in the art should fall within the patent protection scope of the present invention.

[0050] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for handling network model inference faults in an MCU, characterized in that, The MCU is configured with a main core for model inference under normal conditions and an auxiliary core for model inference when the main core fails. The main core and the auxiliary core share a set of storage resources. The MCU also integrates a fault detection device, which determines whether the main core has malfunctioned and wakes up the auxiliary cores. When the main core is running normally, the auxiliary core is in a dormant state. When the main core is performing inference, each time the calculation task of a layer is completed, the first address of the output data of that layer is saved to the intermediate data first address register, and the address of the first instruction of the next layer calculation program is copied from the PC register to the program counter backup register. The intermediate data base address register is either the Intermediate Data Base Address Register or IDBAR. The program counter backup register is either a Program Counter Backup Register or a PCBR. If the fault detection device detects a fault in the main core during inference, it will wake up the auxiliary core. The auxiliary core first locates the starting address and length of the input data of the incomplete inference layer of the main core in RAM based on the values ​​in IDBAR and IDLR, and then copies the value of PCBR into the PC pointer register to continue the inference that the main core has not completed.

2. A network model inference fault handling system for an MCU, characterized in that, The MCU is configured with a main core for model inference under normal conditions and an auxiliary core for model inference when the main core fails. The main core and the auxiliary core share a set of storage resources. The MCU also integrates a fault detection device, which determines whether the main core has malfunctioned and wakes up the auxiliary cores. When the main core is running normally, the auxiliary core is in a dormant state. When the main core is performing inference, each time the calculation task of a layer is completed, the first address of the output data of that layer is saved to the intermediate data first address register, and the address of the first instruction of the next layer calculation program is copied from the PC register to the program counter backup register. The intermediate data base address register is either the Intermediate Data Base Address Register or IDBAR. The program counter backup register is either a Program Counter Backup Register or a PCBR. If the fault detection device detects a fault in the main core during inference, it will wake up the auxiliary core. The auxiliary core first locates the starting address and length of the input data of the incomplete inference layer of the main core in RAM based on the values ​​in IDBAR and IDLR, and then copies the value of PCBR into the PC pointer register to continue the inference that the main core has not completed.

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