Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display. In the display panel, a pixel circuit and a first signal trace are connected through a first connection position, a second signal trace is connected through a second connection position, and a pixel electrode is connected through a third connection position. Moreover, the orthographic projection of a first opening area in a common electrode on a substrate covers the orthographic projection of each connection position on the substrate, so that the coupling capacitance of the conductive film layer at the common electrode and each connection position can be avoided, and the abnormal increase of the coupling capacitance at each connection position can be avoided. Therefore, the display panel can be prevented from generating a heating phenomenon, and the yield of the display panel can be ensured.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Liquid crystal display (LCD) panels are widely used in large-size display devices due to their low power consumption.

[0003] In related technologies, a liquid crystal display panel includes a substrate, a common electrode, pixel electrodes, and a liquid crystal layer located on the substrate. Furthermore, the liquid crystal display panel also includes a common electrode driving circuit located in the peripheral region of the substrate and a pixel electrode driving circuit located in the display area of ​​the substrate. The common electrode driving circuit is connected to the common electrode and provides a common electrode driving signal to the common electrode; the pixel circuit is connected to the pixel electrode and provides a pixel electrode driving signal to the pixel electrode. The common electrode driving signal and the pixel electrode driving signal together drive the liquid crystal molecules in the liquid crystal layer to deflect, thereby enabling the liquid crystal display panel to transmit light.

[0004] However, the large coupling capacitance in the LCD panel leads to high power consumption and heat generation, which in turn affects the yield rate of the LCD panel. Summary of the Invention

[0005] This application provides a display panel and a display device, which can solve the problem of low yield rate of display panels in related technologies. The technical solution is as follows:

[0006] On one hand, a display panel is provided, the display panel comprising:

[0007] Substrate;

[0008] Multiple first signal traces are located on the substrate, arranged along a first direction and extending along a second direction, wherein the second direction intersects the first direction;

[0009] Multiple second signal traces located on the substrate, arranged along the second direction and extending along the first direction;

[0010] Multiple pixel circuits are arranged in an array, each pixel circuit and a first signal trace are connected through a first connection position, and each pixel circuit and a second signal trace are connected through a second connection position;

[0011] Multiple pixel electrodes corresponding to the multiple pixel circuits, each pixel electrode and the corresponding pixel circuit are connected through a third connection position, and each pixel circuit transmits a drive signal from the second signal line to the corresponding pixel electrode under the control of the first signal line;

[0012] A common electrode having a plurality of first opening regions corresponding to the plurality of pixel circuits, wherein the orthographic projection of each first opening region on the substrate covers the orthographic projection of the corresponding first connection position, the second connection position and the third connection position on the substrate.

[0013] And a black matrix layer, the orthogonal projection of which on the substrate covers the orthogonal projection of the first opening region on the substrate.

[0014] Optionally, the common electrode also has a plurality of second opening regions, wherein the orthographic projection of the second opening regions on the substrate is located within the orthographic projection of the black matrix layer on the substrate;

[0015] Each second opening region's orthographic projection on the substrate covers a portion of the orthographic projection of a second signal trace on the substrate. Each second opening region is located between two adjacent first opening regions along the first direction, and each second opening region and the adjacent first opening region have a gap in the first direction.

[0016] Optionally, the first opening region includes a connected first region and a second region;

[0017] The orthographic projection of the first region on the substrate partially overlaps with the overlapping areas of the first signal trace and the second signal trace, and the orthographic projection of the second region on the substrate at least covers the orthographic projection of the third connection position on the substrate.

[0018] The length of the second region along the first direction is different from the length of the first region along the first direction.

[0019] Optionally, the display panel further includes: a plurality of third signal traces arranged along the first direction and extending along the second direction;

[0020] Each of the third signal traces is connected to the common electrode.

[0021] Optionally, the display panel includes a gate layer, a first insulating layer, an active layer, a source / drain layer, a second insulating layer, a common electrode layer, a third insulating layer, and a pixel electrode layer, which are sequentially stacked along a direction away from the substrate.

[0022] The gate layer includes the plurality of first signal traces and the plurality of third signal traces; the active layer includes the plurality of active patterns; the source-drain layer includes the second signal traces arranged along the second direction and having gaps, a first connection portion and a second connection portion; the common electrode layer includes the common electrode; and the pixel electrode layer includes the pixel electrode and a third connection portion.

[0023] The target portion of the second signal trace is connected to the active pattern, one end of the first connection portion is connected to the active pattern, the other end of the first connection portion is connected to the pixel electrode, the second connection portion and the common electrode are connected through the third connection portion, and the second connection portion is connected to the third signal trace.

[0024] Optionally, the orthographic projection of the third connecting portion on the substrate includes a first projection area and a second projection area;

[0025] The orthographic projections of the first projection area and the first opening area on the substrate overlap, and the orthographic projections of the second projection area and the common electrode on the substrate overlap.

[0026] The portion of the third connection located in the first projection area is connected to the second connection, and the portion of the third connection located in the second projection area is connected to the common electrode.

[0027] Optionally, the orthographic projection of the first opening region onto the substrate covers the target overlapping region;

[0028] The target overlapping region is the overlapping region of the orthographic projection of the third signal trace on the substrate and the orthographic projection of the second signal trace on the substrate.

[0029] Optionally, the display panel further includes: a plurality of fourth signal traces arranged along the second direction and extending along the first direction, wherein each of the fourth signal traces is connected to the common electrode;

[0030] The common electrode also has a plurality of third opening regions, each of which has a projection on the substrate that overlaps with a projection of a fourth signal trace on the substrate. Each of the third opening regions is located between two adjacent first opening regions along the first direction, and each of the third opening regions and the adjacent first opening region has a gap in the first direction.

[0031] Optionally, the orthographic projection of the first opening region on the substrate overlaps with the orthographic projection of the first signal trace on the substrate.

[0032] The orthographic projection of the third opening region on the substrate is outside the orthographic projection of the black matrix layer on the substrate.

[0033] Optionally, the display panel includes a gate layer, a first insulating layer, an active layer, a source / drain layer, a second insulating layer, a common electrode layer, a third insulating layer, and a pixel electrode layer, which are sequentially stacked along a direction away from the substrate.

[0034] Wherein, the gate layer includes the first signal trace, the active layer includes a plurality of active patterns, the source-drain layer includes the second signal trace, the fourth signal trace and the first connection portion, the common electrode layer includes the common electrode, and the pixel electrode layer includes the pixel electrode;

[0035] The target portion of the second signal trace is connected to the active pattern, one end of the first connection portion is connected to the active pattern, and the other end of the first connection portion is connected to the pixel electrode.

[0036] Optionally, the pixel circuit includes a switching transistor; the switching transistor includes a gate, a source, and a drain.

[0037] The first signal trace includes an integral signal trace body and a signal trace pattern, wherein the signal trace pattern serves as the gate of the switching transistor.

[0038] The orthographic projection of the active pattern on the substrate includes a source region, a drain region, and a channel region located between the source region and the drain region. The portion of the first connection portion that overlaps and connects with the drain region serves as the drain of the switching transistor. The target portion of the second signal trace serves as the source of the switching transistor. The channel region is the area where the signal trace pattern overlaps with the active pattern but does not overlap with either the first connection portion or the second signal trace.

[0039] Optionally, the orthographic projection of the source region on the substrate lies within the orthographic projection of the signal trace pattern on the substrate;

[0040] The orthographic projection of the drain region on the substrate includes: a third projection region located within the orthographic projection of the signal trace pattern on the substrate, and a fourth projection region located outside the orthographic projection of the signal trace pattern on the substrate.

[0041] Optionally, the active pattern has a first active boundary and a second active boundary extending along the first direction and opposite to each other, wherein the first active boundary is the boundary of the drain region away from the source region, and the second active boundary is the boundary of the source region away from the drain region.

[0042] The signal trace pattern has a first pattern boundary extending along the first direction, and the first connection portion has a connection portion boundary extending along the first direction.

[0043] The orthographic projection of the first pattern boundary on the substrate is located between the orthographic projection of the first active boundary on the substrate and the orthographic projection of the connecting portion boundary on the substrate.

[0044] Wherein, the distance between the first pattern boundary and the connecting portion boundary along the second direction is less than 3 micrometers.

[0045] Optionally, the signal trace pattern has a second pattern boundary extending along the second direction and away from the signal trace body; the active pattern has a third active boundary and a fourth active boundary extending along the second direction and opposite to each other, wherein the third active boundary is closer to the second pattern boundary than the fourth active boundary.

[0046] The distance between the second pattern boundary and the third active boundary along the first direction is less than or equal to 3 micrometers.

[0047] Optionally, the overlapping area of ​​the orthographic projection of the second signal trace on the substrate and the orthographic projection of the signal trace pattern on the substrate includes: a first overlapping area and a second overlapping area.

[0048] Wherein, the length of the first overlapping region along the first direction is less than or equal to the distance between the second pattern boundary and the third active boundary along the first direction, and the length of the second overlapping region along the first direction is the length of the third active boundary and the fourth active boundary along the first direction.

[0049] Optionally, the second signal trace has a first trace boundary and a second trace boundary extending along the first direction, wherein at least a portion of the orthographic projection of the first trace boundary on the substrate and at least a portion of the orthographic projection of the second trace boundary on the substrate are both located within the orthographic projection of the signal trace pattern on the substrate.

[0050] Wherein, the distance between the first trace boundary and the second trace boundary along the second direction is less than or equal to 3 micrometers.

[0051] Optionally, the display panel includes: an array substrate and a color filter substrate disposed opposite each other, and a liquid crystal layer located between the array substrate and the color filter substrate;

[0052] The array substrate includes the plurality of first signal lines, the plurality of second signal lines, the plurality of pixel circuits, the plurality of pixel electrodes, and the common electrode; the color filter substrate includes the black matrix layer.

[0053] On the other hand, a display device is provided, the display device including a power supply component and a display panel as described above;

[0054] The power supply component is used to supply power to the display panel.

[0055] The beneficial effects of the technical solution provided in this application include at least the following:

[0056] This application provides a display panel and a display device. In the display panel, pixel circuits and first signal lines are connected through a first connection location, second signal lines are connected through a second connection location, and pixel electrodes are connected through a third connection location. Furthermore, the orthographic projection of the first opening area in the common electrode onto the substrate covers the orthographic projection of each connection location onto the substrate. Therefore, coupling capacitance between the common electrode and the conductive film layers at each connection location can be avoided, thereby preventing abnormal increases in coupling capacitance at each connection location. This prevents overheating of the display panel and ensures high yield. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a partial structural diagram of a display panel provided in an embodiment of this application;

[0059] Figure 2 This is a partial structural diagram of another display panel provided in an embodiment of this application;

[0060] Figure 3 yes Figure 1 A schematic diagram of the common electrode in the display panel shown;

[0061] Figure 4 yes Figure 2 A schematic diagram of the common electrode in the display panel shown;

[0062] Figure 5 This is a partial structural schematic diagram of another display panel provided in an embodiment of this application;

[0063] Figure 6 yes Figure 5 A schematic diagram of the common electrode in the display panel shown;

[0064] Figure 7 This is a top view of a substrate provided in an embodiment of this application;

[0065] Figure 8 This is a schematic diagram of the connection relationship of a pixel circuit provided in an embodiment of this application;

[0066] Figure 9 This is a partial cross-sectional view of the display panel provided in an embodiment of this application;

[0067] Figure 10 This is a partial top view of a gate layer provided in an embodiment of this application;

[0068] Figure 11 This is a partial top view of a first insulating layer provided in an embodiment of this application;

[0069] Figure 12 This is a partial top view of an active layer provided in an embodiment of this application;

[0070] Figure 13 This is a partial superposition diagram of a gate layer, a first insulating layer, and an active layer provided in an embodiment of this application;

[0071] Figure 14 This is a partial top view of a source / drain layer provided in an embodiment of this application;

[0072] Figure 15 This is a partial superimposed schematic diagram of a gate layer, a first insulating layer, an active layer, and a source / drain layer provided in an embodiment of this application;

[0073] Figure 16 This is a schematic diagram of a planarization layer provided in an embodiment of this application;

[0074] Figure 17 This is a partial superimposed schematic diagram of a gate layer, a first insulating layer, an active layer, a source-drain layer, and a planarization layer provided in an embodiment of this application.

[0075] Figure 18 yes Figure 17 Cross-sectional view along the AA direction;

[0076] Figure 19 This is a partial superimposed schematic diagram of a gate layer, a first insulating layer, an active layer, a source-drain layer, a planarization layer, and a common electrode layer provided in an embodiment of this application.

[0077] Figure 20 yes Figure 19 Cross-sectional view along the BB direction;

[0078] Figure 21 This is a partial top view of a third insulating layer provided in an embodiment of this application;

[0079] Figure 22 This is a partial superimposed schematic diagram of a gate layer, a first insulating layer, an active layer, a source-drain layer, a planarization layer, a common electrode layer, and a third insulating layer provided in an embodiment of this application.

[0080] Figure 23 yes Figure 22 Cross-sectional view along the CC direction;

[0081] Figure 24 This is a partial top view of a pixel electrode layer provided in an embodiment of this application;

[0082] Figure 25 This is a schematic diagram of a gate layer, a first insulating layer, an active layer, a source-drain layer, a planarization layer, a common electrode layer, a third insulating layer, and a pixel electrode layer provided in an embodiment of this application.

[0083] Figure 26 yes Figure 25 Cross-sectional view along the DD direction;

[0084] Figure 27 yes Figure 1 The diagram shows a planar view of the black matrix layer in the display panel.

[0085] Figure 28 This is a partial superimposed schematic diagram of another gate layer, first insulating layer, active layer, source and drain layers, planarization layer and common electrode layer provided in an embodiment of this application.

[0086] Figure 29 This is a partial superimposed schematic diagram of another gate layer, first insulating layer, active layer, source-drain layer, planarization layer, common electrode layer and third insulating layer provided in an embodiment of this application.

[0087] Figure 30 This is a schematic diagram of another gate layer, first insulating layer, active layer, source-drain layer, planarization layer, common electrode layer, third insulating layer and pixel electrode layer provided in the embodiments of this application.

[0088] Figure 31 This is a partial top view of another gate layer provided in an embodiment of this application;

[0089] Figure 32 This is a partial top view of another active layer provided in an embodiment of this application;

[0090] Figure 33 This is a partial superposition diagram of another gate layer, first insulating layer and active layer provided in an embodiment of this application;

[0091] Figure 34 This is a partial top view of another source / drain layer provided in an embodiment of this application;

[0092] Figure 35 This is a partial superimposed schematic diagram of another gate layer, first insulating layer, active layer and source / drain layer provided in an embodiment of this application;

[0093] Figure 36 This is a partial top view of another flat layer provided in an embodiment of this application;

[0094] Figure 37 This is a partial superimposed schematic diagram of another gate layer, first insulating layer, active layer, source-drain layer and planarization layer provided in an embodiment of this application;

[0095] Figure 38 This is a partial superimposed schematic diagram of another gate layer, first insulating layer, active layer, source-drain layer, planarization layer, and common electrode layer provided in the embodiments of this application.

[0096] Figure 39 This is a partial top view of another third insulating layer provided in the embodiments of this application;

[0097] Figure 40 This is a partial superimposed schematic diagram of another gate layer, first insulating layer, active layer, source-drain layer, planarization layer, common electrode layer and third insulating layer provided in the embodiments of this application.

[0098] Figure 41 This is a partial top view of another pixel electrode layer provided in an embodiment of this application;

[0099] Figure 42 This is a schematic diagram of another gate layer, first insulating layer, active layer, source-drain layer, second insulating layer, common electrode layer, third insulating layer and pixel electrode layer provided in the embodiments of this application;

[0100] Figure 43 yes Figure 5 The diagram shows a black matrix layer in the display panel.

[0101] Figure 44 This is a partial schematic diagram of a gate layer, an active layer, and a source / drain layer provided in an embodiment of this application;

[0102] Figure 45 This is a partial schematic diagram of another gate layer, active layer, and source / drain layer provided in an embodiment of this application;

[0103] Figure 46 This is a schematic diagram of light leakage simulation provided in an embodiment of this application;

[0104] Figure 47This is a partial schematic diagram of the gate layer, active layer, and source / drain layer in related technologies;

[0105] Figure 48 yes Figure 1 A partially enlarged schematic diagram of the display panel shown;

[0106] Figure 49 yes Figure 5 A partially enlarged schematic diagram of the display panel shown;

[0107] Figure 50 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0108] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0109] LCD display panels are widely used in the display field. With increasing competition in the panel industry, the quality requirements for a-Si and oxide products are becoming increasingly similar to those for low-temperature polysilicon (LTPS) products. Specifically, a-Si products refer to display panels using amorphous silicon thin-film transistors (TFTs), oxide products refer to display panels using oxide TFTs, and LTPS products refer to display panels using LTPS TFTs.

[0110] LTPS, being low-temperature polycrystalline silicon, boasts extremely high mobility and charge rate. Therefore, at the same resolution and refresh rate, LTPS can achieve the target charge rate using thin-film transistors with smaller channels. This results in lower overall voltage drop (loading) and power consumption for LTPS, significantly less than, for example, Oxide products. As the application frequency of Oxide products gradually increases, Oxide LCD products now need to support refresh rates of 600Hz. Due to the increased refresh rate requirements, the number of charge-discharge cycles of the driving circuit also increases proportionally, leading to a significant increase in power consumption and highlighting the heat generation issue of the driving circuit.

[0111] Figure 1 This is a partial structural schematic diagram of a display panel provided in an embodiment of this application. (Reference) Figure 1 The display panel 1 includes: a substrate 101, multiple first signal lines 102, multiple second signal lines 103, multiple pixel circuits 104, multiple pixel electrodes 105, a common electrode 106, and a black matrix (BM) layer 107.

[0112] Multiple first signal traces 102 are located on the substrate 101, arranged along a first direction X and extending along a second direction Y. Multiple second signal traces 103 are located on the substrate 101, arranged along the second direction Y and extending along the first direction X. The second direction Y and the first direction X intersect. The multiple first signal traces 102 extending along the second direction Y can mean that the general direction of the multiple first signal traces 102 is the second direction Y, and the multiple second signal traces 103 extending along the first direction X can mean that the general direction of the multiple second signal traces 103 is the first direction X. The first direction X can be the pixel column direction of the display panel 1, and the second direction Y can be the pixel row direction of the display panel 1.

[0113] Multiple pixel circuits 104 are arranged in an array. Each pixel circuit 104 is connected to a first signal line 102 through a first connection position m1, and each pixel circuit 104 is connected to a second signal line 103 through a second connection position m2. Multiple pixel electrodes 105 correspond one-to-one with multiple pixel circuits 104, and each pixel electrode 105 is connected to its corresponding pixel circuit 104 through a third connection position m3. That is, each pixel circuit 104 is connected to a first signal line 102, a second signal line 103, and its corresponding pixel electrode 105.

[0114] Each first signal line 102 can be used to control the on / off state of the pixel circuit 104 connected to it. When the first signal line 102 controls the pixel circuit 104 connected to it to be in the on / off state, the pixel circuit 104 can receive and transmit the drive signal from the second signal line 103 to the corresponding pixel electrode 105. That is, each pixel circuit 104 transmits the drive signal from the second signal line 103 to the corresponding pixel electrode 105 under the control of the first signal line 102.

[0115] refer to Figure 1 The common electrode 106 has a plurality of first opening regions 106a corresponding to the plurality of pixel circuits 104. The orthographic projection of each first opening region 106a on the substrate 101 covers the orthographic projection of each of the corresponding first connection positions m1, second connection positions m2 and third connection positions m3 on the substrate 101. That is, the orthographic projection of the common electrode 106 on the substrate 101 and the orthographic projection of each connection position on the substrate 101 do not overlap.

[0116] Typically, the first signal trace 102, the second signal trace 103, and the pixel electrode 105 are all disposed on a different layer from the pixel circuit 104. Therefore, the connection points of the first signal trace 102, the second signal trace 103, and the pixel electrode 105 with the pixel circuit 104 usually include at least two conductive film layers. That is, the coupling capacitance at each connection point is relatively large compared to other locations. Therefore, by ensuring that the orthographic projection of the first opening region 106a in the common electrode 106 onto the substrate 101 covers the orthographic projections of each connection point onto the substrate 101, coupling capacitance between the common electrode 106 and the conductive film layers at each connection point can be avoided, thereby preventing abnormal increases in coupling capacitance at each connection point. This prevents overheating of the display panel 1 and ensures the yield rate of the display panel 1.

[0117] Furthermore, in related technologies, uncontrollable electric fields may be generated between various signal traces and pixel electrodes. The common electrode, located between the signal traces and pixel electrodes, can shield these uncontrollable electric fields, thereby preventing light leakage problems in the display panel.

[0118] In this embodiment, the first opening region 106a of the common electrode 106 is a hollow area without the material of the common electrode 106, and therefore cannot serve as a shield for the electric field. However, the orthogonal projection of the black matrix layer 107 onto the substrate 101 covers the orthogonal projection of the first opening region 106a onto the substrate 101. Therefore, the light from the first opening region 106a can be covered by the black matrix layer 107, preventing light leakage from the portion of the display panel 1 located in the first opening region 106a and ensuring the display effect of the display panel 1.

[0119] In summary, this application provides a display panel in which pixel circuits and first signal traces are connected through a first connection location, second signal traces are connected through a second connection location, and pixel electrodes are connected through a third connection location. Furthermore, the orthographic projection of the first opening area in the common electrode onto the substrate covers the orthographic projection of each connection location onto the substrate, thus preventing coupling capacitance between the common electrode and the conductive film layers at each connection location, thereby preventing abnormal increases in coupling capacitance at each connection location. This avoids overheating in the display panel and ensures high yield.

[0120] In this embodiment, the display panel 1 includes an array substrate and a color filter substrate disposed opposite each other, and a liquid crystal layer located between the array substrate and the color filter substrate. The array substrate includes multiple first signal lines 102, multiple second signal lines 103, multiple pixel circuits 104, multiple pixel electrodes 105, and a common electrode 106. The color filter substrate includes a black matrix layer 107.

[0121] That is, multiple first signal lines 102, multiple second signal lines 103, multiple pixel circuits 104, multiple pixel electrodes 105, and a common electrode 106 can be integrated on the array substrate. The black matrix layer 107 is integrated on the color filter substrate.

[0122] Optionally, the substrate 101 included in the display panel 1 can be a substrate used to set various structures in the array substrate, while the black matrix layer 107 is integrated into the color filter substrate. Figure 1 The pattern shown as 107 can be used to represent the orthographic projection of the black matrix layer 107 onto the substrate 101.

[0123] Optionally, the pixel electrode 105 and the common electrode 106 can be made of transparent materials, such as indium tin oxide (ITO). The first signal trace 102 can be a gate signal line, used to provide a gate signal to the pixel circuit 104. The second signal trace 103 can be a data drive signal line, used to provide a data drive signal to the pixel circuit 104.

[0124] In this embodiment, the area in the display panel 1 with multiple pixel electrodes 105 can be multiple light-transmitting areas of the display panel 1. To avoid crosstalk between the light transmitted through the multiple light-transmitting areas in the display panel 1, the black matrix layer 107 can typically be located between adjacent light-transmitting areas. Specifically, adjacent light-transmitting areas in the multiple light-transmitting areas arranged along the first direction X are separated by multiple first signal lines 102, and adjacent light-transmitting areas in the multiple light-transmitting areas arranged along the second direction Y are separated by multiple second signal lines 103. Thus, the orthographic projection of the black matrix layer 107 onto the substrate 101 covers the orthographic projection of the first signal lines 102 onto the substrate 101, and also covers the orthographic projection of the second signal lines 103 onto the substrate 101.

[0125] Figure 2 This is a partial structural diagram of another display panel provided in an embodiment of this application. (Reference) Figure 2 The common electrode 106 also has a plurality of second opening regions 106b. Furthermore, the orthographic projection of each second opening region 106b on the substrate 101 covers the orthographic projection of a second signal trace 103 on the substrate 101.

[0126] Optionally, each second signal trace 103 extending along the first direction X can be divided into multiple first signal segments 1031 by multiple first signal traces 102 extending along the first direction X. The orthographic projection of each second opening region 106b on the substrate 101 covers the orthographic projection of one first signal segment 1031 on the substrate 101. That is, for the multiple second opening regions 106b designed for the area of ​​the common electrode 106 on a second signal trace 103, the multiple second opening regions 106b can be arranged along the extension direction X of the second signal trace 103, and there is a gap between adjacent second opening regions 106b.

[0127] Since the orthographic projection of the common electrode 106 on the substrate 101 and the orthographic projections of each first signal segment 1031 of the second signal trace 103 on the substrate 101 do not overlap, the overlap area of ​​the common electrode 106 and the second signal trace 103 can be reduced. Furthermore, the coupling capacitance of the common electrode 106 and the second signal trace 103 can be reduced, thereby reducing the overall coupling capacitance of the display panel 1, further preventing overheating of the display panel 1, and ensuring the yield rate of the display panel 1.

[0128] Furthermore, since the orthographic projection of the second opening region 106b on the substrate 101 is located within the orthographic projection of the black matrix layer 107 on the substrate 101, the light emitted from the second opening region 106b can be covered by the black matrix layer 107, thus preventing light leakage from the part of the display panel 1 located in the second opening region 106b and ensuring the display effect of the display panel 1.

[0129] Typically, the first connection position m1, the second connection position m2, and the third connection position m3 are roughly located in the overlapping area of ​​the first signal trace 102 and the second signal trace 103. Therefore, refer to... Figure 1 and Figure 2 Multiple first opening regions 106a in the common electrode 106 can be arranged in the overlapping area of ​​the first signal trace 102 and the second signal trace 103.

[0130] Furthermore, refer to Figure 2 When the common electrode 106 is designed with multiple second opening regions 106b, each second opening region 106b can be located between two adjacent first opening regions 106a along the first direction X, and each second opening region 106b and the adjacent first opening region 106a have a gap in the first direction X. That is, a row of multiple first opening regions 106a and a row of multiple second opening regions 106b arranged in the first direction X are staggered and have gaps between them. This not only reduces the coupling capacitance, but also ensures that the common electrode 106 is in a connected state at the gap between the first opening region 106a and the second opening region 106b, which facilitates the overall signal conduction of the common electrode 106.

[0131] refer to Figure 3 and Figure 4 The first opening region 106a includes a first region 106a1 and a second region 106a2 that are connected. The orthographic projection of the first region 106a1 onto the substrate 101 overlaps with the overlapping regions of the first signal trace 102 and the second signal trace 103. This avoids coupling capacitance between the portion of the common electrode 106 located in the first region 106a1 and the first signal trace 102 or the second signal trace 103. The orthographic projection of the second region 106a2 onto the substrate 101 at least covers the orthographic projection of the third connection location m3 onto the substrate 101. Therefore, by having the second region 106a2 cover the third connection location m3, coupling capacitance between the common electrode 106 and the conductive film layer at the third connection location m3 can be avoided.

[0132] Optional, combined Figures 1 to 4 The second region 106a2 can be located among multiple light-transmitting regions arranged along the first direction X, and is arranged along the second direction Y with the connected first region 106a1. Figure 2 and Figure 4 The first opening region 106a and the second opening region 106b in the common electrode 106, which are used to cover the same second signal trace 103, are arranged along the first direction X.

[0133] refer to Figure 3 and Figure 4 The length of the second region 106a2 along the first direction X is different from the length of the first region 106a1 along the first direction X. Therefore, embodiments of this application can adjust the lengths of the first region 106a1 and the second region 106a2 along the first direction X based on the actual layout design in the display panel 1. For example, Figure 3 and Figure 4 In the first region 106a1, the length along the first direction X is greater than the length along the first direction X of the second region 106a2. Alternatively, Figure 5 This is a partial structural schematic diagram of another display panel provided in the embodiments of this application. Figure 6 yes Figure 5 A schematic diagram of a portion of the common electrode structure in the display panel is shown. (Reference) Figure 6 In the first region 106a2, the length along the first direction X is greater than the length along the first direction X of the first region 106a1.

[0134] Optional, see reference Figure 7The substrate 101 has a display area 101a and a peripheral area 101b surrounding the display area 101a. The display panel 1 also includes a common driving power supply circuit (not shown) located in the peripheral area 101b, which can be connected to a common electrode 106 to provide a common signal to the common electrode 106. Furthermore, the portion of the common electrode 106 located in the peripheral area 101b can be connected to the common driving power supply circuit.

[0135] refer to Figure 1 and Figure 2 The display panel 1 further includes multiple third signal traces 108 arranged along a first direction X and extending along a second direction Y. Each third signal trace 108 is connected to a common electrode 106. Furthermore, each third signal trace 108 is also connected to a common driving power supply circuit. Thus, in addition to the portion of the common electrode 106 directly connected to the common driving power supply circuit, it can also be indirectly connected via the third signal traces 108, thereby reducing the voltage drop (loading) of the common signal in different areas of the common electrode 106, improving the uniformity of the common signal transmitted in different areas of the common electrode 106, and ensuring the display uniformity of the display panel 1.

[0136] refer to Figure 1 and Figure 2 It can be seen that the orthographic projection of the first opening region 106a onto the substrate 101 covers the target overlapping region n. This target overlapping region n is the overlapping region of the orthographic projection of the third signal trace 108 onto the substrate 101 and the orthographic projection of the second signal trace 103 onto the substrate 101.

[0137] By ensuring that the orthographic projection of the first opening region 106a onto the substrate 101 covers the target overlapping region n, coupling capacitance between the common electrode 106 and the second signal trace 103 and the third signal trace 108 of the target overlapping region n can be avoided, thus preventing the coupling capacitance of the target overlapping region n from becoming too large. This prevents the display panel 1 from overheating and ensures the yield rate of the display panel 1.

[0138] refer to Figure 5 The display panel 1 further includes multiple fourth signal traces 109 arranged along the second direction Y and extending along the first direction X. Each fourth signal trace 109 is connected to a common electrode 106. Figure 5 The connection relationship between the fourth signal trace 109 and the common electrode 106 is not shown in the diagram.

[0139] Optionally, each fourth signal trace 109 extending along the first direction X can be divided into multiple second signal segments 1091 by multiple first signal traces 102 extending along the first direction X. The common electrode 106 can have multiple third opening regions 106c, and the orthographic projection of each third opening region 106c on the substrate 101 covers the orthographic projection of a second signal segment 1091 on the substrate 101. That is, for the multiple third opening regions 106c designed for the area of ​​the common electrode 106 on a fourth signal trace 109, the multiple third opening regions 106c can be arranged along the extension direction X of the fourth signal trace 109, and there is a gap between adjacent third opening regions 106c.

[0140] refer to Figure 6 When the common electrode 106 is designed with multiple third opening regions 106c, each third opening region 106c is located between two adjacent first opening regions 106a along the first direction X, and each third opening region 106c and the adjacent first opening region 106a have a gap in the first direction X. That is, a row of multiple first opening regions 106a and a row of multiple third opening regions 106c arranged in the first direction X are staggered and have gaps between them. This not only reduces the coupling capacitance, but also ensures that the common electrode 106 is in a connected state at the gap between the first opening region 106a and the third opening region 106c, facilitating the overall signal conduction of the common electrode 106.

[0141] Since the orthographic projection of the common electrode 106 on the substrate 101 and the orthographic projections of each signal segment of the fourth signal trace 109 on the substrate 101 do not overlap, the overlap area between the common electrode 106 and the fourth signal trace 109 can be reduced, thereby reducing the coupling capacitance between the common electrode 106 and the fourth signal trace 109. This reduces the overall coupling capacitance of the display panel 1, further preventing overheating and ensuring the yield rate of the display panel 1.

[0142] refer to Figure 5 The orthographic projection of the second signal segment 1091 of the fourth signal trace 109 onto the substrate 101 overlaps with the orthographic projection of the light-transmitting region onto the substrate 101. Therefore, the orthographic projection of the third opening region 106c designed in the common electrode 106 onto the substrate 101 overlaps with the orthographic projection of the light-transmitting region onto the substrate 101. Furthermore, since the light-transmitting region needs to achieve a light-transmitting effect, the orthographic projection of the black matrix layer 107 onto the substrate 101 will not cover the light-transmitting region. Thus, the orthographic projection of the third opening region 106c onto the substrate 101 is located outside the orthographic projection of the black matrix layer 107 onto the substrate 101.

[0143] Typically, the fourth signal trace 109 can be a touch trace included in the touch structure of the display panel 1. Touch traces are generally not affected by the uncontrollable electric field generated between the various signal traces and the pixel electrode 105. Therefore, even if the third opening area 106c is not covered by the black matrix layer 107, thus failing to achieve light shielding, and the third opening area 106c of the common electrode 106 is a hollow area without the material of the common electrode 106, thus failing to shield the electric field, the area of ​​the display panel 1 located in the third opening area 106c will not experience light leakage due to the uncontrollable electric field.

[0144] exist Figure 5 In the implementation shown, the orthographic projection of the first opening region 106a in the common electrode 106 onto the substrate 101 not only covers each connection location but also partially overlaps with the orthographic projection of the first signal trace 102 onto the substrate 101. This reduces the overlap area between the common electrode 106 and the first signal trace 102, thereby reducing the coupling capacitance between them.

[0145] Optional, Figure 5 In the first opening region 106a arranged along the second direction Y, a portion of the first signal trace 102 is exposed. Furthermore, there is a gap between adjacent first opening regions 106a arranged along the second direction Y to ensure signal conduction of the common electrode 106 as a whole.

[0146] Figure 8 This is a schematic diagram illustrating the connection relationship of a pixel circuit according to an embodiment of this application. (Reference) Figure 8 The pixel circuit 104 may include a switching transistor T, which includes a gate, a source, and a drain. The gate of the switching transistor T is connected to a first signal line 102, and the switching transistor T is turned on or off under the control of a gate signal provided by the first signal line 102. The source of the switching transistor T is connected to a second signal line 103, and the drain of the switching transistor T is connected to the pixel electrode 105. When the switching transistor T is in the on state, the second signal line 103 transmits a data driving signal to the pixel electrode 105 through the on switching transistor T, thereby changing the electric field between the pixel electrode 105 and the common electrode 106, which in turn drives the liquid crystal molecules in the liquid crystal layer to deflect, achieving light transmission.

[0147] Figure 9 This is a partial cross-sectional view of the display panel provided in an embodiment of this application. (Reference) Figure 9 The display panel 1 includes a gate layer a, a first insulating layer b, an active layer c, a source-drain layer d, a second insulating layer e, a common electrode layer f, a third insulating layer g, and a pixel electrode layer h, which are stacked sequentially in a direction away from the substrate 101.

[0148] As a first alternative implementation, in the case where the common electrode 106 includes multiple first opening regions 106a, and the display panel 1 includes multiple third signal traces 108 (i.e. Figure 1 (The scheme is as follows). To make it easier to clearly represent each membrane layer, the following is a brief introduction to each membrane layer in terms of individual single layers and progressive stacking.

[0149] Figure 10 This is a partial top view of a gate layer provided in an embodiment of this application. (Reference) Figure 10 The gate layer a includes multiple first signal traces 102 and multiple third signal traces 108. Furthermore, the multiple first signal traces 102 and multiple third signal traces 108 are arranged alternately in the first direction X.

[0150] Each of the multiple first signal traces 102 includes an integral signal trace body 1021 and a signal trace pattern 1022. The first signal trace 102 extending along the second direction Y can mean that the signal trace body 1021 extends along the second direction Y, and the signal trace pattern 1022 is a raised pattern formed on the side of the signal trace body 1021. This signal trace pattern 1022 can serve as the gate of a switching transistor T.

[0151] A first insulating layer b may be formed on the aforementioned gate layer a to insulate the gate layer a from the subsequently formed active layer c. This first insulating layer b may be a gate insulator (GI). Furthermore, refer to... Figure 11 The first insulating layer b has a first via b1, which can be used to connect the third signal trace 108 and the common electrode 106. For clarity, the various first vias b1 of the first insulating layer b are shown below. Figure 11 The first via b1 is represented by a filled pattern. Other areas without filled patterns are used to represent areas where the first insulating layer b has solid material.

[0152] Figure 12 This is a partial top view of an active layer provided in an embodiment of this application. Figure 13 This is a partial superposition diagram of a gate layer, a first insulating layer, and an active layer provided in an embodiment of this application. (Reference) Figure 12 and Figure 13 The active layer c includes multiple active patterns c1, and each switching transistor T includes one active pattern c1.

[0153] Each active pattern c1, projected onto the substrate 101, includes a channel region and a doped region (source region and drain region). The source and drain regions can be conductiveized through doping to achieve electrical connections between the structures. The channel region is located between the source and drain regions, and is the area where the signal trace pattern 1022 overlaps with the active pattern c1 but does not overlap with either the source or drain regions.

[0154] The active layer c can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source and drain regions mentioned above can be regions doped with n-type or p-type impurities.

[0155] Figure 14 This is a partial top view of a source / drain layer provided in an embodiment of this application. Figure 15 This is a partial superimposed schematic diagram of a gate layer, a first insulating layer, an active layer, and a source / drain layer provided in an embodiment of this application. (Reference) Figure 14 and Figure 15 The source-drain layer d includes a second signal trace 103 arranged along the second direction Y and having a gap, a first connection portion d1 and a second connection portion d2.

[0156] In this configuration, the target portion of the second signal trace 103 is connected to the active pattern c1, and each second signal trace 103 may have multiple target portions, each target portion being connected to a corresponding active pattern c1. One end of the first connection portion d1 is connected to the active pattern c1. The target portion of the second signal trace 103 serves as the source of the switching transistor T, and the portion of the first connection portion d1 that overlaps and connects with the drain region serves as the drain of the switching transistor T.

[0157] Furthermore, the orthographic projection of the second connection portion d2 on the substrate 101 and the orthographic projection of the third signal trace 108 on the substrate 101 overlap. The first via b1 in the first insulating layer b is located in the overlapping area of ​​the second connection portion d2 and the third signal trace 108, and the second connection portion d2 and the third signal trace 108 are electrically connected through the first via b1 in the first insulating layer b.

[0158] A second insulating layer e may be formed on the aforementioned source / drain layer d to insulate the source / drain layer d from the subsequently formed common electrode 106. The second insulating layer e may include a first passivation layer (PVX) e1 and a planarization layer (PLN) e2 stacked along a direction away from the substrate 101. The planarization layer e2 may be made of an organic material, such as resin.

[0159] The first passivation layer e1 may have a second via e11 and a third via e12. The orthographic projection of the second via e11 on the substrate 101 does not overlap with the orthographic projection of the common electrode 106 on the substrate 101. The second via e11 is used to connect the pixel electrode 105 in the subsequently formed pixel electrode layer h and the first connection portion d1 in the source-drain layer d. The orthographic projection of the third via e12 on the substrate 101 does not overlap with the orthographic projection of the common electrode 106 on the substrate 101, but partially overlaps with the orthographic projection of the second connection portion d2 in the source-drain layer d on the substrate 101. The third via e12 is used to connect the third connection portion h1 in the subsequently formed pixel electrode layer h and the second connection portion d2 in the source-drain layer d.

[0160] Figure 16 This is a schematic diagram of a flat layer structure provided in an embodiment of this application. Figure 17 This is a partial superimposed schematic diagram of a gate layer, a first insulating layer, an active layer, a source / drain layer, and a planarization layer provided in an embodiment of this application. (Reference) Figure 16 and Figure 17 The planarization layer e2 may have a fourth via e21 and a fifth via e22.

[0161] Figure 18 yes Figure 17 Cross-sectional view along the AA direction. (Combined with...) Figures 16 to 18 The orthographic projection of the fourth via e21 in the planarization layer e2 onto the substrate 101 partially overlaps with the orthographic projection of the second via e11 in the first passivation layer e1 onto the substrate 101, serving as a connection point for the subsequently formed pixel electrode 105 and the first connection portion d1. The orthographic projection of the fifth via e22 in the planarization layer e2 onto the substrate 101 partially overlaps with the orthographic projection of the third via e12 in the passivation layer e1, and the fifth via e22 also has a region that does not overlap with the third via e12 in the first passivation layer e1. That is, the orthographic projection of the fifth via e22 onto the substrate 101 covers the orthographic projection of the third via e12 onto the substrate 101, and the fifth via e22 covers the third via e12.

[0162] To facilitate the illustration of the fourth vias e21 and the fifth via e22 of the planarization layer e2, Figures 16 to 17 The vias are represented by fill patterns. Other areas without fill patterns are used to represent areas where the planarization layer e2 has solid material.

[0163] Figure 19 This is a partial superimposed schematic diagram of a gate layer, a first insulating layer, an active layer, a source / drain layer, a planarization layer, and a common electrode layer provided in an embodiment of this application. Figure 19 The common electrode layer in the superimposed schematic diagram shown includes the following common electrodes: Figure 3 The common electrode shown. Figure 20 yes Figure 19 Cross-sectional view along the BB direction.

[0164] refer to Figure 3 , Figure 19 and Figure 20 The orthographic projection of the common electrode 106 on the substrate 101 and the orthographic projection of the fifth via e22 in the planarization layer e2 on the substrate 101 partially overlap. Furthermore, the orthographic projection of the first opening region 106a in the common electrode 106 on the substrate 101 and the orthographic projection of the third via e12 in the first passivation layer e1 on the substrate 101 overlap.

[0165] That is, a common electrode 106 is designed in the planarization layer e2 in the region where the fifth via e22 and the third via e12 do not overlap. Furthermore, a first opening region 106a of the common electrode 106 is designed in the region where the fifth via e22 and the third via e12 overlap.

[0166] Figure 21 This is a partial top view of a third insulating layer provided in an embodiment of this application. Figure 22 This is a partial superimposed schematic diagram of a gate layer, a first insulating layer, an active layer, a source-drain layer, a planarization layer, a common electrode layer, and a third insulating layer provided in an embodiment of this application. Figure 23 yes Figure 22 Cross-sectional view along the CC direction. (Combined with...) Figures 21 to 22 The third insulating layer g can be the second passivation layer, and the third insulating layer g includes a sixth via g1 and a seventh via g2.

[0167] The orthographic projection of the sixth via g1 onto the substrate 101 overlaps with the orthographic projection of the first connection portion d1 onto the substrate. This sixth via g1 is used to connect the pixel electrode 105 in the subsequently formed pixel electrode layer h to the first connection portion d1 in the source / drain layer d. That is, the pixel electrode 105 and the first connection portion d1 are connected through the second via e11 in the passivation layer, the fourth via e21 in the planarization layer e2, and the sixth via g1 in the third insulating layer g.

[0168] The orthographic projection of the seventh via g2 on the substrate 101 partially overlaps with the orthographic projection of the first opening region 106a on the substrate 101, and also overlaps with the orthographic projection of the common electrode 106 on the substrate 101. That is, a portion of the seventh via g2 can expose a portion of the second connection portion d2 located in the source-drain layer d, and another portion of the seventh via g2 can expose a portion of the common electrode 106.

[0169] To facilitate the illustration of the sixth via g1 and the seventh via g2 of the third insulating layer g, Figures 21 to 22 Vias are represented by filled patterns. Other areas without filled patterns are used to represent areas where the third insulating layer g has solid material.

[0170] Figure 24 This is a partial top view of a pixel electrode layer provided in an embodiment of this application. Figure 25 This is a schematic diagram of a gate layer, a first insulating layer, an active layer, a source-drain layer, a planarization layer, a common electrode layer, a third insulating layer, and a pixel electrode layer provided in an embodiment of this application. Figure 26 yes Figure 25 Cross-sectional view along the DD direction.

[0171] Combination Figures 24 to 26 The pixel electrode layer h includes a pixel electrode 105 and a third connection portion h1. The orthographic projection of the pixel electrode 105 on the substrate 101 and the orthographic projection of the first connection portion h1 on the substrate 101 partially overlap, and the pixel electrode 105 and the first connection portion h1 are electrically connected. This allows the second signal trace 103 to transmit a data drive signal to the pixel electrode 105 through the pixel circuit 104.

[0172] The orthographic projection of the third connection portion h1 on the substrate 101 includes a first projection area h11 and a second projection area h12. The orthographic projections of the first projection area h11 and the first opening area 106a on the substrate 101 overlap, and the orthographic projections of the second projection area h12 and the common electrode 106 on the substrate 101 overlap. The portion of the third connection portion h1 located in the first projection area h11 is connected to the second connection portion d2, and the portion of the third connection portion h1 located in the second projection area h12 is connected to the common electrode 106. This enables the third signal trace 108 to be connected through the second connection portion d2, the third connection portion h1, and the common electrode 106.

[0173] Figure 27 yes Figure 1 A schematic diagram of the black matrix layer in the display panel shown. (Combined with...) Figure 1 and Figure 27 As can be seen, the black matrix layer 107 can cover the first opening area 106a of the common electrode 106, and also covers the second signal trace 103. Therefore, the light emitted from the location of the first opening area 106a or the second signal trace 103 can be covered by the black matrix layer 107, avoiding light leakage in the part of the display panel 1 located in the first opening area 106a or the second signal trace 103, and ensuring the display effect of the display panel 1.

[0174] As a second optional implementation, in the case where the common electrode 106 includes multiple first opening regions 106a and multiple second opening regions 106b, and the display panel 1 includes multiple third signal traces 108 (i.e. Figure 2 (The scheme is as follows). To make it easier to clearly represent each membrane layer, the following is a brief introduction to each membrane layer in terms of individual single layers and progressive stacking.

[0175] In this embodiment, the design of the gate layer a, the first insulating layer b, the active layer c, and the second insulating layer e can be referred to the description of the first embodiment above, and will not be repeated here.

[0176] Figure 28 This is a partial superimposed schematic diagram of another gate layer, first insulating layer, active layer, source-drain layer, planarization layer and common electrode layer provided in an embodiment of this application. Figure 28 The common electrode layer f shown in the superimposed schematic diagram includes the common electrode 106. Figure 4 The common electrode is shown. (Reference) Figure 4 and Figure 28 In addition to a plurality of first opening regions 106a, the common electrode 106 also includes a plurality of second opening regions 106b.

[0177] The orthographic projection of each second opening region 106b on the substrate 101 covers a portion of the orthographic projection of a second signal trace 103 on the substrate 101.

[0178] Figure 29 This is a partial superimposed schematic diagram of another gate layer, first insulating layer, active layer, source-drain layer, planarization layer, common electrode layer and third insulating layer provided in an embodiment of this application. Figure 30 This is a schematic diagram illustrating a gate layer, a first insulating layer, an active layer, a source / drain layer, a planarization layer, a common electrode layer, a third insulating layer, and a pixel electrode layer provided in an embodiment of this application. (Reference) Figure 29 and Figure 30 The design of the third insulating layer g and the pixel electrode layer h can be the same as in the first implementation.

[0179] In the second implementation, the structure of the black matrix layer 107 can be the same as that of the black matrix layer 107 in the first implementation, for example... Figure 27 The black matrix layer 107 is shown. Since the black matrix layer 107 can cover the second signal trace 103, even if the common electrode 106 is designed with a second opening area 106b at the location of the second signal trace 103, the light emitted from the second opening area 106b can be covered by the black matrix layer 107, avoiding light leakage in the part of the display panel 1 located in the second opening area 106b, and ensuring the display effect of the display panel 1.

[0180] As a third alternative implementation, in the case where the common electrode 106 includes multiple first opening regions 106a and multiple third opening regions 106c, and the display panel 1 includes multiple fourth signal traces 109 (i.e. Figure 5 (The scheme is as follows). To make it easier to clearly represent each membrane layer, the following is a brief introduction to each membrane layer in terms of individual single layers and progressive stacking.

[0181] Figure 31 This is a partial top view of another gate layer provided in an embodiment of this application. (Reference) Figure 31 The gate layer a includes multiple first signal traces 102. The multiple first signal traces 102 are arranged along a first direction X and extend along a second direction Y.

[0182] Each of the multiple first signal traces 102 includes an integral signal trace body 1021 and a signal trace pattern 1022. The first signal trace 102 extending along the second direction Y can mean that the signal trace body 1021 extends along the second direction Y, and the signal trace pattern 1022 is a raised pattern formed on the side of the signal trace body 1021. This signal trace pattern 1022 can serve as the gate of a switching transistor T.

[0183] A first insulating layer b may be formed on the aforementioned gate layer a to insulate the gate layer a from the subsequently formed active layer c. This first insulating layer b can be a gate insulating layer. Since the first insulating layer b can be an entire layer of insulating material, it is not illustrated in the accompanying drawings.

[0184] Figure 32 This is a partial top view of another active layer provided in the embodiments of this application. Figure 33 This is a partial superposition diagram of another gate layer, first insulating layer, and active layer provided in an embodiment of this application. (See reference) Figure 32 and Figure 33 The active layer c includes multiple active patterns c1, and each switching transistor T includes one active pattern c1.

[0185] Each active pattern c1, projected onto the substrate 101, includes a channel region and a doped region (source region and drain region). The source and drain regions can be conductiveized through doping to achieve electrical connections between the structures. The channel region is located between the source and drain regions, and is the area where the signal trace pattern 1022 overlaps with the active pattern c1 but does not overlap with either the source or drain regions.

[0186] The active layer c can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source and drain regions mentioned above can be regions doped with n-type or p-type impurities.

[0187] Figure 34 This is a partial top view of another source / drain layer provided in an embodiment of this application. Figure 35 This is a partial superimposed schematic diagram of another gate layer, first insulating layer, active layer, and source / drain layer provided in an embodiment of this application. (See reference) Figure 34 and Figure 35 The source-drain layer d includes a second signal trace 103 arranged along the second direction Y and having a gap, a fourth signal trace 109, and a first connection portion d1.

[0188] In this configuration, the target portion of the second signal trace 103 is connected to the active pattern c1, and each second signal trace 103 may have multiple target portions, each target portion being connected to a corresponding active pattern c1. One end of the first connection portion d1 is connected to the active pattern c1. The target portion of the second signal trace 103 serves as the source of the switching transistor T, and the portion of the first connection portion d1 that overlaps with and connects to the drain region serves as the drain of the switching transistor T.

[0189] In addition, the fourth signal trace 109 can be used to connect to the common electrode 106 in the subsequently formed common electrode layer f, so as to provide a common signal for the common electrode 106.

[0190] A second insulating layer e may be formed on the aforementioned source / drain layer d to insulate the source / drain layer d from the subsequently formed common electrode 106. The second insulating layer e may include a first passivation layer e1 and a planarization layer e2 stacked in a direction away from the substrate 101. Furthermore, in this implementation, the vias in the first passivation layer e1 and the planarization layer e2 are designed identically.

[0191] Taking planarization layer e2 as an example Figure 36 and Figure 37 An eighth via e23 may be present in the first passivation layer e1 and the planarization layer e2. The orthographic projection of the eighth via e23 on the substrate 101 partially overlaps with the orthographic projection of the first connection portion d1 on the substrate 101. The eighth via e23 is used to connect the pixel electrode 105 in the subsequently formed pixel electrode layer h and the first connection portion d1 in the source-drain layer d.

[0192] To facilitate the illustration of the eighth vias e23 of the first passivation layer e1 and the planarization layer e2, Figures 36 to 37 Vias are represented by a fill pattern. Other areas without fill patterns are used to represent areas where the planarization layer e2 has solid material.

[0193] Figure 38 This is a partial superimposed schematic diagram of a gate layer, a first insulating layer, an active layer, a source-drain layer, a planarization layer, and a common electrode layer provided in an embodiment of this application. Figure 38The common electrode 106 in the common electrode layer f shown in the superimposed schematic diagram is... Figure 6 The common electrode is shown. (Reference) Figure 6 and Figure 38 The common electrode 106 has multiple first opening regions 106a and multiple third opening regions 106c.

[0194] In this configuration, the orthographic projection of the first opening region 106a onto the substrate 101 overlaps with the orthographic projection of the eighth via e23 onto the substrate 101. This allows the subsequently formed pixel electrode 105 to connect to the first connection portion d1 through the eighth via e23 exposed by the first opening region 106a. Furthermore, the orthographic projection of the third opening region 106c onto the substrate 101 partially overlaps with the orthographic projection of the fourth signal trace 109 onto the substrate 101. This reduces the overlap area between the common electrode 106 and the fourth signal trace 109, thereby reducing the coupling capacitance between the common electrode 106 and the fourth signal trace 109 and lowering the likelihood of overheating issues in the display panel 1.

[0195] Figure 39 This is a partial top view of another third insulating layer provided in the embodiments of this application. Figure 40 This is a partial superimposed schematic diagram of another gate layer, first insulating layer, active layer, source / drain layer, planarization layer, common electrode layer, and third insulating layer provided in an embodiment of this application. (Reference) Figure 39 and Figure 40 The third insulating layer g includes a ninth via g1.

[0196] The ninth via g1 is used to connect the pixel electrode 105 in the subsequently formed pixel electrode layer h and the first connection portion d1 in the source-drain layer d. That is, the pixel electrode 105 and the first connection portion d1 are connected through the eighth via e23 in the second insulating layer e and the ninth via g1 in the third insulating layer g.

[0197] To facilitate the illustration of each of the ninth vias g1 in the third insulating layer g, Figures 39 to 40 Vias are represented by filled patterns. Other areas without filled patterns are used to represent areas where the third insulating layer g has solid material.

[0198] Figure 41 This is a partial top view of another pixel electrode layer provided in the embodiments of this application. Figure 42 This is a schematic diagram of another gate layer, first insulating layer, active layer, source / drain layer, second insulating layer, common electrode layer, third insulating layer, and pixel electrode layer provided in an embodiment of this application. (Reference) Figure 41 and Figure 42 The pixel electrode layer h includes pixel electrodes 105.

[0199] The orthographic projection of the pixel electrode 105 on the substrate 101 and the orthographic projection of the first connection portion d1 on the substrate 101 partially overlap, and the pixel electrode 105 and the first connection portion d1 are electrically connected. This allows the second signal trace 103 to transmit a data drive signal to the pixel electrode 105 through the pixel circuit 104.

[0200] Figure 43 yes Figure 5 A schematic diagram of the black matrix layer in the display panel shown. (Combined with...) Figure 5 and Figure 43 As can be seen, the black matrix layer 107 can cover the first opening area 106a of the common electrode 106. Therefore, the light emitted from the first opening area 106a can be covered by the black matrix layer 107, avoiding light leakage problems in the parts of the display panel 1 located in the first opening area 106a or the second signal trace 103, and ensuring the display effect of the display panel 1.

[0201] Furthermore, the black matrix layer 107 does not cover the third opening area 106c of the common electrode 106. A fourth signal trace 109 is designed at the location of the third opening area 106, which can be a touch trace included in the touch structure of the display panel 1. Since touch traces are generally not affected by the uncontrollable electric field generated between the various signal traces and the pixel electrode 105, even if the third opening area 106c is not covered by the black matrix layer 107, thus failing to achieve light shielding, and the third opening area 106c of the common electrode 106 is a hollow area without the material of the common electrode 106, thus failing to shield the electric field, the area of ​​the display panel 1 located in the third opening area 106c will not experience light leakage due to the uncontrollable electric field.

[0202] In all three implementations described above, the fabrication process of each film layer includes: forming a thin film and patterning the thin film using a photomask. The patterning process includes: photoresist coating, exposure using a photomask, development, etching, and photoresist removal. For example, the fabrication process of the active pattern c1 in the active layer c includes: forming an active thin film and patterning the active thin film using a photomask of the active layer.

[0203] It should be noted that the gate layer, the first insulating layer (Scheme 1 and Scheme 2 perform patterning processing on the first insulating layer, while Scheme 3 does not require patterning processing on the first insulating layer), the active layer, the source-drain layer, the first passivation layer PVX1, the planarization layer, the common electrode, the second passivation layer PVX2, and the pixel electrode of the display panel need to be patterned using a mask.

[0204] In the patterning process, the first passivation layer PVX1 and the second passivation layer PVX use the same mask. Furthermore, the masks used in the fabrication process are, in sequence: gate layer mask, active layer mask, first insulating layer mask (Scheme 1 and Scheme 2), source / drain layer mask, planarization layer mask, common electrode mask, passivation layer (PVX1 and PVX2) mask, and pixel electrode mask.

[0205] As a fourth optional implementation method, Figure 44 This is a partial schematic diagram of a gate layer, active layer, and source / drain layer provided in an embodiment of this application. (Reference) Figure 44 The orthographic projection of the source region c11 onto the substrate 101 lies within the orthographic projection of the signal trace pattern 1022 onto the substrate 101. Specifically, the source region c11 refers to the overlapping region of the orthographic projection of the active pattern c1 onto the substrate 101 and the orthographic projection of the second signal trace 103 onto the substrate 101. In other words, the overlapping region of the second signal trace 103 and the active pattern c1 lies within the orthographic projection of the signal trace pattern 1022 onto the substrate 101.

[0206] Furthermore, the orthographic projection of the drain region c12 onto the substrate 101 includes a third projection region c12a located within the orthographic projection of the signal trace pattern 1022 onto the substrate 101, and a fourth projection region c12b located outside the orthographic projection of the signal trace pattern 1022 onto the substrate 101. Here, the drain region c12 refers to the overlapping area of ​​the orthographic projection of the active pattern c1 onto the substrate 101 and the orthographic projection of the first connection portion d1 onto the substrate 101. That is, a portion of the overlapping area of ​​the active pattern c1 and the first connection portion d1 is located within the signal trace pattern 1022, and another portion is located outside the signal trace pattern 1022.

[0207] With the active pattern c1 having a fixed size, the first pattern boundary 1022a of the signal trace pattern 1022 can be reduced inward, decreasing the area of ​​the orthographic projection of the signal trace pattern 1022 onto the substrate 101. Furthermore, the overlap area between the signal trace pattern 1022 and the first connection portion d1 can be reduced, lowering the coupling capacitance between the pixel electrode 105 connected to the signal trace pattern 1022 and the first connection portion d1. The first pattern boundary 1022a extends along the first direction X and is closer to the drain region c12 than the source region c11.

[0208] refer to Figure 44The active pattern c1 has a first active boundary c1a and a second active boundary c1b extending along a first direction X and opposite to each other. The first active boundary c1a is the boundary of the drain region c12 away from the source region c11, and the second active boundary c1b is the boundary of the source region c11 away from the drain region c12. The first connection portion d1 has a connection portion boundary d1a extending along the first direction X.

[0209] The orthographic projection of the first pattern boundary 1022a onto the substrate 101 lies between the orthographic projection of the first active boundary c1a onto the substrate 101 and the orthographic projection of the connection boundary d1a onto the substrate 101. This allows a portion of the active pattern c1 to lie outside the signal trace pattern 1022, thereby reducing the area of ​​the signal trace pattern 1022.

[0210] Optionally, the distance between the first pattern boundary 1022a and the connection boundary d1a along the second direction Y is less than 3 μm. For example, the distance w1 between the first pattern boundary 1022a and the connection boundary d1a along the second direction Y is 2.5 μm. This implementation reduces the overlap area between the orthographic projection of the signal trace pattern 1022 on the substrate 101 and the orthographic projection of the first connection d1 on the substrate 101, thereby reducing the coupling capacitance between the first signal trace 102 and the pixel electrode 105.

[0211] refer to Figure 44 The signal trace pattern 1022 has a second pattern boundary 1022b extending along the second direction Y and located away from the signal trace body 1021. The active pattern c1 has a third active boundary c1c and a fourth active boundary c1d extending along the second direction Y and located opposite each other. The third active boundary c1c is closer to the second pattern boundary 1022b than the fourth active boundary c1d.

[0212] Optionally, the distance w2 between the second pattern boundary 1022b and the third active boundary c1c along the first direction X is less than or equal to 3 μm. That is, the smaller distance between the second pattern boundary 1022b and the third active boundary c1c along the first direction X allows the second pattern boundary 1022b of the signal trace pattern 1022 to be recessed, reducing the area of ​​the orthographic projection of the signal trace pattern 1022 onto the substrate 101. Furthermore, this can reduce the overlap area between the second signal trace 103 and the signal trace pattern 1022, and reduce the coupling capacitance between the second signal trace 103 and the first signal trace 102.

[0213] For example, the distance between the second pattern boundary 1022b and the third active boundary c1c along the first direction X is 2μm.

[0214] In this embodiment, the overlapping area of ​​the orthographic projection of the second signal trace 103 on the substrate 101 and the orthographic projection of the signal trace pattern 1022 on the substrate 101 includes: a first overlapping area p1 and a second overlapping area p2.

[0215] Wherein, the length of the first overlapping region p1 along the first direction X is less than or equal to the distance between the second pattern boundary 1022b and the third active boundary c1c along the first direction X. The length of the second overlapping region p2 along the first direction X is the length of the third active boundary c1c and the fourth active boundary c1d along the first direction X.

[0216] Normally, since the second overlapping region p2 is the overlapping area of ​​the active pattern c1 and the second signal trace 103, and the size of the active pattern c1 affects the size of the channel region c13 of the switching transistor T, the size of the active pattern c1 is usually not adjusted, making it difficult to adjust the area of ​​the second overlapping region p2. Furthermore, in order to reduce the overlap area between the second signal trace 103 and the signal trace pattern 1022, the area of ​​the first overlapping region p1 can be reduced.

[0217] Optionally, the distance w2 between the second pattern boundary 1022b and the third active boundary c1c along the first direction X is small (less than 3 μm). Therefore, the length of the first overlapping region p1 along the first direction X is less than or equal to the distance w1 between the second pattern boundary 1022b and the third active boundary c1c along the first direction X. Furthermore, the area of ​​the first overlapping region p1 can be made smaller, thereby reducing the coupling capacitance between the second signal trace 103 and the first signal trace 102.

[0218] Example, reference Figure 44 The length of the first overlapping region p1 along the first direction X is equal to the distance w1 between the second pattern boundary 1022b and the third active boundary c1c along the first direction X. Alternatively, refer to... Figure 45 The length of the first overlapping region p1 along the first direction X is less than the distance w1 between the second pattern boundary 1022b and the third active boundary c1c along the first direction X.

[0219] In the embodiments of this application, reference is made to Figure 44 The second signal trace 103 has a first trace boundary 103a and a second trace boundary 103b extending along a first direction X. The first trace boundary 103a is further away from the drain region c2 relative to the second trace boundary 103b, and at least a portion of the orthographic projection of the first trace boundary 103a onto the substrate 101 and at least a portion of the orthographic projection of the second trace boundary 103b onto the substrate 101 are located within the orthographic projection of the signal trace pattern 1022 onto the substrate 101.

[0220] Therefore, the overlap area between the second signal trace 103 and the signal trace pattern 1022 can depend on the distance between the first trace boundary 103a and the second trace boundary 103b in the second signal trace 103 along the second direction Y (i.e., the trace width w3 + w4 of the overlapping portion of the second signal trace 103 and the signal trace pattern 1022). The width of the overlapping portion of the second signal trace 103 and the signal trace pattern 1022 is the width of the second signal trace 103 along the second direction Y. That is, the width of the second signal trace 103 along the second direction Y can be equal to the sum of the distance w3 between the first trace boundary 103a and the second active boundary c1b along the second direction Y, and the distance w4 between the second active boundary c1b and the first trace boundary 102a along the second direction Y.

[0221] Optionally, the distance (w3+w4) between the first trace boundary 103a and the second trace boundary 103b along the second direction Y is less than or equal to 3μm. That is, the smaller distance between the first trace boundary 103a and the second trace boundary 103b can reduce the overlap area between the second signal trace 103 and the signal trace pattern 1022, and reduce the coupling capacitance between the second signal trace 103 and the first signal trace 102.

[0222] refer to Figure 44 and Figure 45 The orthographic projection of the second active boundary c1b on the substrate 101 lies between the orthographic projection of the first trace boundary 103a on the substrate 101 and the orthographic projection of the second trace boundary 103b on the substrate 101. That is, the orthographic projection of the second signal trace 103 on the substrate 101 covers the orthographic projection of the second active boundary c1b of the active pattern c1 on the substrate 101.

[0223] Optional, with Figure 44Taking the structure shown as an example, the distance w1 between the first pattern boundary 1022a and the connecting boundary d1a along the second direction Y is 2.5 μm. The distance w2 between the third active boundary c1c and the second pattern boundary 1022b along the first direction X is 3 μm. The distance w3 between the second trace boundary 103b and the second active boundary c1b along the second direction Y is 2.5 μm. The distance w4 between the second active boundary c1b and the first trace boundary 103a along the second direction Y is 0.5 μm. The distance w5 between the first active boundary c1a and the first pattern boundary 1022a along the second direction Y is 1.5 μm. The width w6 of the channel region c13 along the second direction Y is 5 μm, and the width w7 of the channel region c13 along the first direction X is 5 μm. The distance w8 between the fourth active boundary c1d and the boundary of the signal trace body 1021 away from the channel region c13 is 3 μm. The distance w9 between the boundary of the first connection d1 away from the signal line body 1021 and the third active boundary c1c is 0.25μm. The distance between the first trace boundary 102a and the third pattern boundary 1022c of the signal trace pattern 1022 along the second direction Y is 2.5μm.

[0224] by Figure 45 Taking the structure shown as an example, the distance w1 between the first pattern boundary 1022a and the connecting boundary d1a along the second direction Y is 2.5 μm. The distance w2 between the third active boundary c1c and the second pattern boundary 1022b along the first direction X is 2 μm. The length of the first overlapping region p1 along the first direction X is less than the distance w2, for example, the distance w11 is 1.5 μm. The distance w3 between the second trace boundary 103b and the second active boundary c1b along the second direction Y is 2.5 μm. The distance w4 between the second active boundary c1b and the first trace boundary 103a along the second direction Y is 0.5 μm. The distance w5 between the first active boundary c1a and the first pattern boundary 1022a along the second direction Y is 1.5 μm. The width w6 of the channel region c13 along the second direction Y is 5 μm, and the width w7 of the channel region c13 along the first direction X is 5 μm. The distance w8 between the fourth active boundary c1d and the boundary of the signal trace body 1021 away from the channel region c13 is 1.5 μm. The distance w9 between the boundary of the first connection portion d1 away from the signal trace body 1021 and the third active boundary c1c is 0.25 μm. The distance between the first trace boundary 102a and the third pattern boundary 1022c of the signal trace pattern 1022 along the second direction Y is 2.5 μm.

[0225] In this embodiment, the display panel further includes a liquid crystal layer. The liquid crystal molecules in the liquid crystal layer are deflected under the combined drive of the pixel electrode 105 and the common electrode 106, thereby enabling the display panel to transmit light.

[0226] Among them, reference Figure 8A liquid crystal capacitor Clc and a storage capacitor Cst are formed between the pixel electrode 105 and the common electrode 106. These two capacitors are the required capacitors in the display panel 1. The coupling capacitances caused by the overlap of the conductive film layers include: the coupling capacitance Cgd between the gate layer a and the source / drain layer d, the coupling capacitance Cgp between the gate layer a and the pixel electrode 105, the coupling capacitance Cgc between the gate layer a and the common electrode 106, and the coupling capacitance Cdc between the source / drain layer d and the common electrode 106. Therefore, in order to reduce the overall coupling capacitance of the display panel 1, this embodiment of the application can consider reducing the above four types of coupling capacitances.

[0227] It should be noted that, referring to Table 1, the loading of display panel 1 mainly consists of two parts, namely the loading of the array substrate row driver (GOA) circuit and the loading of the source driver circuit.

[0228] Table 1

[0229]

[0230] The loading of the GOA circuit is typically related to the coupling capacitance of the gate layer a and other conductive layers. For example, the loading of the GOA circuit includes: the coupling capacitance Cgd between the gate layer a and the source / drain layer d, the coupling capacitance Cgp between the gate layer a and the pixel electrode 105, and the coupling capacitance Cgc between the gate layer a and the common electrode 106. Similarly, the loading of the source circuit is typically related to the coupling capacitance of the source / drain layer d and other conductive layers. For example, the loading of the source circuit includes: the coupling capacitance Cgd between the gate layer a and the source / drain layer d, and the coupling capacitance Cdc between the drain layer d and the common electrode 106.

[0231] Based on the above analysis, it can be seen that in order to reduce the loading of the display panel, one can usually start by reducing the coupling capacitors Cgd, Cgp, Cgc, and Cdc.

[0232] In the first optional implementation described above, the common electrode 106 has multiple first opening regions 106a, and the first opening regions 106a cover each connection location, the film layer at the connection location including the source and drain layers. Therefore, by designing multiple first opening regions 106a on the common electrode 106, the coupling capacitance Cdc between the common electrode 106 and the source and drain layers d can be reduced.

[0233] Specifically, by detecting the coupling capacitance Cdc, the coupling capacitance Cdc in the solution of this application embodiment is reduced by approximately 22% compared to the coupling capacitance Cdc in the prior art. The loading of the source-drain layer d is reduced by approximately 6%. This is equivalent to a reduction of approximately 6% in the loading of the overall source circuit.

[0234] Furthermore, since the common electrode 106 features a perforated design with a first opening area 106a, it is necessary to ensure that the display panel is free of light leakage. (Reference) Figure 4 The light leakage area of ​​display panel 1 is located near the gate edge of the switching transistor T. Since this area is shielded by the black matrix layer 107, display panel 1 actually has no risk of light leakage.

[0235] For the second optional implementation described above, since the orthogonal projection of the black matrix layer 107 on the substrate 101 can cover the orthogonal projection of the second signal trace 103 on the substrate 101, multiple second opening regions 106b can be designed in the common electrode 106.

[0236] The black matrix layer 107 covers the centerline of the portion of the second signal trace 103 and may overlap with the centerline of the second signal trace 103. For example, assuming the width of the second signal trace 103 along the second direction Y is 3μm, and the width of the portion of the black matrix layer 107 covering the second signal trace 103 along the second direction Y is 6μm, then the width of the black matrix layer 107 extending beyond the second signal trace 103 on both sides is 1.5μm.

[0237] For display panels, light leakage refers to the phenomenon where, when the display panel shows a black image, the black matrix layer 107 fails to effectively block the light leakage area, resulting in a black image that is not truly black or visually less black. For a normally black LCD display panel, when the display panel shows a black image, the voltage magnitudes of the signals transmitted by the source / drain layers d to the pixel electrode 107 and the common electrode are the same. In this case, there is no electric field between the pixel electrode 107 and the common electrode 106, thus preventing the liquid crystal molecules in the liquid crystal layer from deflecting and allowing light to pass through, resulting in light leakage. Furthermore, in this case, there is no need for the black matrix layer 107 to block the light, and therefore no light leakage occurs.

[0238] For high-resolution tablet PCs (TPCs), the second insulating layer e between the source / drain layer d and the common electrode 106 is a relatively thick organic film layer. This organic film layer is approximately 2 μm thick. Since an electric field of at least 2500 Å thickness is required to drive liquid crystal molecule deflection in the third insulating layer g between the common electrode 106 and the pixel electrode 107, the thickness of the third insulating layer g between the common electrode 106 and the pixel electrode 107 is typically 2500 Å. However, the thicknesses between the source / drain layer and the upper electrode (common electrode) are both greater than 24000 Å, resulting in a very small electric field and consequently, very small deflection of the liquid crystal molecules. Furthermore, because the second signal trace 103 is shielded by the black matrix layer 107, light leakage is very small. Simultaneously, based on... Figure 46 The simulation results show that there is no light leakage region near the second signal line 103. Therefore, the second implementation method described above can not only reduce the coupling capacitance Cdc but also avoid light leakage.

[0239] In the third optional implementation described above, the common electrode 106 has multiple first opening regions 106a and multiple third opening regions 106c, with the first opening regions 106a covering each of the first connection traces 102. Therefore, by designing multiple first opening regions 106a in the common electrode 106, the coupling capacitance Cgc between the common electrode 106 and the gate layer a can be reduced.

[0240] For high pixel density (pixels per inch, PPI) products, since the black matrix layer 107 on the first signal trace 102 generally provides significant obstruction, designing the first opening region 106a on the common electrode 106 does not affect light leakage. Testing revealed that the coupling capacitance Cgc decreased by approximately 60%, and the loading of the gate layer a decreased by approximately 8%. This is equivalent to an overall GOA loading reduction of approximately 8%.

[0241] It should be noted that this solution is particularly suitable for high PPI products where the black matrix layer 107 on the first signal trace 102 has a wide coverage area, such as the portion of the black matrix layer 107 covering the first signal trace 102 with a width greater than 25μm along the first direction X.

[0242] Figure 47 This is a partial schematic diagram of a gate layer, active layer, and source / drain layer in a related technology. The coupling capacitance Cgd between the gate layer and the source / drain layer is mainly positively correlated with the overlap area between the gate layer and the source / drain layer. (Reference) Figure 47 The overlap area between the gate layer and the source / drain layer is mainly located in the region of the switching transistor T. Among them, the active pattern... Compared to the gate layer shrinkage (i.e., active patterning) The orthographic projection on the substrate lies within the orthographic projection of the gate layer on the substrate, and the active pattern... With the first signal trace in the gate layer Active pattern with a distance greater than 5μm along the first direction X. and the first connecting part The overlap region has a length of 3 μm along the second direction Y. Second signal trace. The width is 3μm. Among them, Figure 47 All dimensions shown are in μm.

[0243] Regarding the fourth optional implementation method mentioned above Figure 44 In this design, the active pattern c1 in the switching transistor T is designed to extend outward relative to the signal trace pattern 1022, and the overlap distance w1 between the active pattern c1 and the first connection portion d1 is reduced from 3μm to 2.5μm. The distance w2 between the third active boundary c1c of the active pattern c1 and the second pattern boundary of the signal trace pattern 1022 is reduced from 5μm to 3μm.

[0244] Through the above design, the overlap area between the signal trace pattern 1022 in the gate layer and the first connection portion d1 in the source-drain layer d is reduced. Furthermore, since the first connection portion d1 is connected to the pixel electrode 107, the reduction in the overlap area between the signal trace pattern 1022 and the first connection portion d1 reduces the coupling capacitance Cgp between the gate layer and the pixel electrode 107. Measurements show that the coupling capacitance Cgp decreases by approximately 30%.

[0245] Simultaneously, since the overlap area between the gate layer and the second signal trace 103 is also reduced, the coupling capacitance Cgd between the gate layer and the second signal trace 103 (source-drain layer) can be reduced. Measurements show that the coupling capacitance Cgp decreases by approximately 25%.

[0246] After adopting this optimization scheme, the overall gate layer loading is reduced by about 15%, which is equivalent to a 15% reduction in the loading and power consumption of the GOA circuit. The overall source-drain layer loading is reduced by about 10%, which is equivalent to a 10% reduction in the loading and power consumption of the overall source circuit.

[0247] When the display panel 1 is lit, illumination increases the number of carriers in the active pattern c1, significantly affecting the on-state current Ion and off-state current Ioff of the switching transistor T, especially the off-state current Ioff. An increase in the off-state current Ioff is equivalent to an increase in the leakage current of the switching transistor T. This increase in leakage current causes the potential of the pixel electrode 107 to be unstable, leading to crosstalk, image retention, and other display problems. Therefore, in LCD display panels of related technologies, if the switching transistors in the display panel are low-temperature polycrystalline oxide (LTPO) thin-film transistors, the distance by which the signal trace pattern 1022 extends outward from the active pattern c1 along the first direction X is generally quite large. Figure 47 The distance shown is 5 μm.

[0248] But for Figure 44 The scheme shown has a portion of the active pattern c1 exposed outside the signal trace pattern 1022, but testing revealed that the scheme does not have any display problems related to it.

[0249] Regarding the fourth optional implementation method mentioned above Figure 45 To further reduce the power consumption and capacitance of the second signal trace 103, a solution is proposed to further reduce the coupling capacitance Cgd, which means further compressing the length w10 of the first overlapping region p1 along the first direction X. For example, the active pattern c1 in the switching transistor T is designed to extend outward relative to the signal trace pattern 1022, and the overlap distance w1 between the active pattern c1 and the first connection portion d1 is reduced from 3 μm to 2.5 μm. The distance w2 between the third active boundary c1c of the active pattern c1 and the second pattern boundary of the signal trace pattern 1022 is reduced from 5 μm to 2 μm, and the length w10 of the first overlapping region p1 along the first direction X is 1.5 μm.

[0250] To illustrate the embodiments of this application Figure 44 and Figure 45 The proposed solution will not significantly affect the on-state current Ion, off-state current Ioff, threshold voltage Vth, and electron mobility (Mob) of the switching transistor T. The embodiments of this application... Figure 44 and Figure 45 The test element group (TEG) of the scheme shown is used to detect different detection positions under both illumination and no-light conditions.

[0251] Taking the aspect ratio W / L=5 / 5=1 of the channel region c13 as an example, positions 1, 2, and 3 of the display panel are detected. Referring to Table 2, it can be seen that... Figure 44 and Figure 45 In the scheme shown, the on-state current Ion, off-state current Ioff, threshold voltage Vth, and mobility Mob of the switching transistor T are relative to... Figure 48 The difference is not significant compared to the conventional schemes shown. Therefore, it is determined that the distance in the above scheme has little impact on the characteristics of the switching transistor T and can be practically applied.

[0252] Table 2

[0253]

[0254] Figure 48 yes Figure 1 A partially enlarged schematic diagram of the display panel shown. (Reference) Figure 48 The length L1 of the first region 106a1 of the first opening region 106a in the common electrode 106 along the first direction X ranges from 28 μm to 33 μm, for example, 31 μm. The length L2 of the first region 106a1 along the second direction Y ranges from 12 μm to 18 μm, for example, 15 μm. The length L3 of the second region 106a2 along the first direction X ranges from 27 μm to 33 μm, for example, 30 μm. The length L4 of the second region 106a2 along the second direction Y ranges from 6 μm to 10 μm, for example, 8 μm.

[0255] Figure 49 yes Figure 5 A partially enlarged schematic diagram of the display panel shown. (Reference) Figure 49 The length L1 of the first region 106a1 of the first opening region 106a along the first direction X ranges from 10 μm to 15 μm, for example, 13.4 μm. The length L3 of the second region 106a2 along the first direction X ranges from 20 μm to 25 μm, for example, 23.8 μm. The sum of the length L2 of the first region 106a1 along the second direction Y and the length L4 of the second region 106a2 along the second direction Y (L2+L4) ranges from 28 to 35 μm, for example, 31 μm.

[0256] In summary, this application provides a display panel in which pixel circuits and first signal traces are connected through a first connection location, second signal traces are connected through a second connection location, and pixel electrodes are connected through a third connection location. Furthermore, the orthographic projection of the first opening area in the common electrode onto the substrate covers the orthographic projection of each connection location onto the substrate, thus preventing coupling capacitance between the common electrode and the conductive film layers at each connection location, thereby preventing abnormal increases in coupling capacitance at each connection location. This avoids overheating in the display panel and ensures high yield.

[0257] Figure 50 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. (Reference) Figure 50 The display device includes a power supply component 2 and a display panel 1 as described in the above embodiment. The power supply component 2 is used to supply power to the display panel 1.

[0258] Optionally, the display device can be an LCD display device. The display device can be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-books, as well as any product or component with display functionality.

[0259] Since the display device can have essentially the same technical effects as the display panel described in the previous embodiments, for the sake of brevity, the technical effects of the display device will not be described again here.

[0260] The terminology used in the embodiments section of this application is for explaining the embodiments of this application only and is not intended to limit this application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0261] The terminology used in the embodiments section of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," "third," and similar terms used in the patent application specification and claims of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising" or "including," and similar terms mean that the elements or objects preceding "comprising" or "including" encompass the elements or objects listed following "comprising" or "including" and their equivalents, and do not exclude other elements or objects. The terms "connected," "linked," and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0262] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized by, The display panel (1) comprises: a substrate (101); a plurality of first signal lines (102) arranged along a first direction (X) and extending along a second direction (Y) on the substrate (101), the second direction (Y) intersecting the first direction (X); a plurality of second signal lines (103) arranged along the second direction (Y) and extending along the first direction (X) on the substrate (101); a plurality of pixel circuits (104) arranged in an array, each of the pixel circuits (104) being connected to one of the first signal lines (102) through a first connection position (m1), and each of the pixel circuits (104) being connected to one of the second signal lines (103) through a second connection position (m2); a plurality of pixel electrodes (105) corresponding to the plurality of pixel circuits (104), each of the pixel electrodes (105) being connected to the corresponding pixel circuit (104) through a third connection position (m3), and each of the pixel circuits (104) transmitting a driving signal from the second signal line (103) to the corresponding pixel electrode (105) under the control of the first signal line (102); a common electrode (106) having a plurality of first opening regions (106a) corresponding to the plurality of pixel circuits (104), a footprint of each of the first opening regions (106a) on the substrate (101) covering a footprint of each of the first connection position (m1), the second connection position (m2) and the third connection position (m3) on the substrate (101); and a black matrix layer (107), a footprint of the black matrix layer (107) on the substrate (101) covering a footprint of the first opening region (106a) on the substrate (101).

2. The display panel of claim 1, wherein, The common electrode (106) further has a plurality of second opening regions (106b), a footprint of each of the second opening regions (106b) on the substrate (101) being located within a footprint of the black matrix layer (107) on the substrate (101); a footprint of each of the second opening regions (106b) on the substrate (101) covering a part of a footprint of one of the second signal lines (103) on the substrate (101), each of the second opening regions (106b) being located between two of the first opening regions (106a) adjacent in the first direction (X), and each of the second opening regions (106b) and the adjacent first opening regions (106a) having a gap in the first direction (X).

3. The display panel of claim 1, wherein, The first opening region (106a) comprises a first area (106a1) and a second area (106a2) which are connected; A first region (106a1) is partially overlapped with an overlapping region of the first signal line (102) and the second signal line (103) in a projection of the substrate (101) on a plane, and a second region (106a2) covers at least a projection of the third connection position (m3) on the substrate (101). The length of the second region (106a2) along the first direction (X) is different from the length of the first region (106a1) along the first direction (X).

4. The display panel of any of claims 1 to 3, wherein, The display panel (1) further comprises a plurality of third signal lines (108) arranged along the first direction (X) and extending along the second direction (Y). Each of the third signal lines (108) is connected to the common electrode (106).

5. The display panel of claim 4, wherein, The display panel (1) comprises, in a direction away from the substrate (101), a gate layer (a), a first insulating layer (b), an active layer (c), a source-drain layer (d), a second insulating layer (e), a common electrode layer (f), a third insulating layer (g), and a pixel electrode layer (h). The gate layer (a) comprises the plurality of first signal lines (102) and the plurality of third signal lines (108), the active layer (c) comprises a plurality of active patterns (c1), the source-drain layer (d) comprises the second signal line (103) arranged along the second direction (Y) and having a gap, a first connection part (d1), and a second connection part (d2), the common electrode layer (f) comprises the common electrode (106), and the pixel electrode layer (h) comprises the pixel electrode (105) and a third connection part (h1). A target part of the second signal line (103) is connected to the active pattern (c1), one end of the first connection part (d1) is connected to the active pattern (c1), the other end of the first connection part (d1) is connected to the pixel electrode (105), the second connection part (d2) is connected to the common electrode (106) through the third connection part (h1), and the second connection part (d2) is connected to the third signal line (108).

6. The display panel of claim 5, wherein, A projection of the third connection part (h1) on the substrate (101) comprises a first projection area (h11) and a second projection area (h12). A projection of the first projection area (h11) and the first opening area (106a) on the substrate (101) is overlapped, and a projection of the second projection area (h12) and the common electrode (106) on the substrate (101) is overlapped. The third connection part (h1) located in the first projection area (h11) is connected to the second connection part (d2), and the third connection part (h1) located in the second projection area (h12) is connected to the common electrode (106).

7. The display panel of claim 4, wherein, A projection of the first opening area (106a) on the substrate (101) covers a target overlapping region (n). The target overlapping region (n) is an overlapping region of a normal projection of the third signal trace (108) on the substrate (101) and a normal projection of the second signal trace (103) on the substrate (101).

8. The display panel of any of claims 1 to 3, wherein, The display panel (1) further comprises a plurality of fourth signal traces (109) arranged along the second direction (Y) and extending along the first direction (X), wherein each fourth signal trace (109) is connected with the common electrode (106). The common electrode (106) further comprises a plurality of third opening regions (106c), a normal projection of each third opening region (106c) on the substrate (101) partially overlaps with a normal projection of one fourth signal trace (109) on the substrate (101), each third opening region (106c) is located between two adjacent first opening regions (106a) along the first direction (X), and each third opening region (106c) and the adjacent first opening region (106a) have a gap along the first direction (X).

9. The display panel of claim 8, wherein, A normal projection of the first opening region (106a) on the substrate (101) partially overlaps with a normal projection of the first signal trace (102) on the substrate (101). A normal projection of the third opening region (106c) on the substrate (101) is located outside a normal projection of the black matrix layer (107) on the substrate (101).

10. The display panel of claim 8, wherein, The display panel (1) comprises a gate layer (a), a first insulating layer (b), an active layer (c), a source-drain layer (d), a second insulating layer (e), a common electrode layer (f), a third insulating layer (g), and a pixel electrode layer (h) stacked in sequence away from the substrate (101); The gate layer (a) comprises the first signal trace (102), the active layer (c) comprises a plurality of active patterns (c1), the source-drain layer (d) comprises the second signal trace (103), the fourth signal trace (109), and a first connecting part (d1), the common electrode layer (f) comprises the common electrode (106), and the pixel electrode layer (h) comprises the pixel electrode (105). A target part of the second signal trace (103) is connected with the active pattern (c1), one end of the first connecting part (d1) is connected with the active pattern (c1), and the other end of the first connecting part (d1) is connected with the pixel electrode (105).

11. The display panel of claim 5 or 10, wherein, The pixel circuit (104) comprises a switching transistor (T), and the switching transistor (T) comprises a gate, a source, and a drain. The first signal trace (102) comprises a signal trace main body (1021) and a signal trace pattern (1022) in an integrated structure, and the signal trace pattern (1022) serves as the gate of the switching transistor (T). A positive projection of the active pattern (c1) on the substrate (101) includes a source region, a drain region, and a channel region between the source region and the drain region, a part of the first connection portion (d1) and the drain region overlap and connect as a drain of the switching transistor (T), a target part of the second signal line (103) as a source of the switching transistor (T), and the channel region is a region where the signal line pattern (1022) and the active pattern (c1) overlap and neither the first connection portion (d1) nor the second signal line (103) overlaps.

12. The display panel of claim 11, wherein, A positive projection of the source region on the substrate (101) is located within a positive projection of the signal line pattern (1022) on the substrate (101). A positive projection of the drain region on the substrate (101) includes a third projection region (c12a) located within a positive projection of the signal line pattern (1022) on the substrate (101), and a fourth projection region (c12b) located outside the positive projection of the signal line pattern (1022) on the substrate (101).

13. The display panel of claim 12, wherein, The active pattern (c1) has a first active boundary (c1a) and a second active boundary (c1b) extending along the first direction (X) and opposite to each other, the first active boundary (c1a) is a boundary of the drain region away from the source region, and the second active boundary (c1b) is a boundary of the source region away from the drain region. The signal line pattern (1022) has a first pattern boundary (1022a) extending along the first direction (X), and the first connection portion (d1) has a connection portion boundary (d1a) extending along the first direction (X). A positive projection of the first pattern boundary (1022a) on the substrate (101) is located between a positive projection of the first active boundary (c1a) on the substrate (101) and a positive projection of the connection portion boundary (d1a) on the substrate (101). The distance between the first pattern boundary (1022a) and the connection portion boundary (d1a) along the second direction (Y) is less than 3 microns.

14. The display panel of claim 13, wherein, The signal line pattern (1022) has a second pattern boundary (1022b) extending along the second direction (Y) and away from one side of the signal line body (1021), and the active pattern (c1) has a third active boundary (c1c) and a fourth active boundary (c1d) extending along the second direction (Y) and opposite to each other, the third active boundary (c1c) is closer to the second pattern boundary (1022b) than the fourth active boundary (c1d). The distance between the second pattern boundary (1022b) and the third active boundary (c1c) along the first direction (X) is less than or equal to 3 microns.

15. The display panel of claim 14, wherein, A projection of the second signal wire (103) on the substrate (101) and a projection of the signal wire pattern (1022) on the substrate (101) overlap in a first overlapping area (p1) and a second overlapping area (p2); Wherein, a length of the first overlapping area (p1) along the first direction (X) is less than or equal to a distance between the second pattern boundary (1022b) and the third active boundary (c1c) along the first direction (X), and a length of the second overlapping area (p2) along the first direction (X) is a length of the third active boundary (c1c) and the fourth active boundary (c1d) along the first direction (X).

16. The display panel of claim 15, wherein, The second signal wire (103) has a first wire boundary (103a) and a second wire boundary (103b) extending along the first direction (X), at least part of a projection of the first wire boundary (103a) on the substrate (101) and at least part of a projection of the second wire boundary (103b) on the substrate (101) are located within a projection of the signal wire pattern (1022) on the substrate (101); Wherein, a distance between the first wire boundary (103a) and the second wire boundary (103b) along the second direction (Y) is less than or equal to 3 microns.

17. The display panel of any one of claims 1 to 3, wherein, The display panel (1) comprises: an array substrate and a color film substrate arranged in a cell, and a liquid crystal layer between the array substrate and the color film substrate; Wherein, the array substrate comprises the plurality of first signal wires (102), the plurality of second signal wires (103), the plurality of pixel circuits (104), the plurality of pixel electrodes (105) and the common electrode (106); the color film substrate comprises the black matrix layer (107).

18. A display device comprising: The display device comprises a power supply component (2) and the display panel (1) as claimed in any one of claims 1 to 17; Wherein, the power supply component (2) is configured to supply power to the display panel (1).

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