Remapping method, apparatus, device, and storage medium

Abstract

The application provides a remapping method, device, equipment and storage medium. The method is applied to an electronic device including a processor, a read-only first memory and a random access second memory. The method includes: obtaining a data modification request, the data modification request being used for requesting to modify data at a first address in the first memory into target data; determining a first data block where the first address is located in the first memory, and judging whether the first data block exists in the second memory; if yes, updating the first data block in the second memory according to the first address and the target data, so that the processor reads the target data in the second memory; and if not, storing the first data block to the second memory, and updating the first data block in the second memory according to the first address and the target data, so that the processor reads the target data in the second memory. The method expands the range of modifiable data and can be applied to more complex use scenarios.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a remapping method and device, equipment and storage medium. BACKGROUND

[0002] The read-only memory on the chip is often used to store various fixed programs and data, especially the startup program. After the chip is packaged, the data in the internal read-only memory cannot be modified and will not be lost, but the programs and data therein may be wrong or missing, or the programs or data in the read-only memory need to be modified to meet the changing market demand.

[0003] In order to reduce the cost and avoid reflow, in the prior art, a read control module and less circuit logic are added in the channel between the processor and the read-only memory to modify a small amount of data in the read-only memory of the chip. However, this method can only set the replacement address and replacement data to the system register through the DEBUG module, and can only replace the single instruction sentence, and cannot cope with the complex scenario of processor burst transmission or continuous transmission (burst access). Another way is to realize through software pre-embedding points, which can only modify the register value at the fixed embedding point position, and cannot modify the non-register code error. SUMMARY

[0004] The present application provides a remapping method, device, equipment and storage medium to solve the problems that the complex scenario of processor burst transmission or continuous transmission (burst access) cannot be coped with when modifying the data in the first memory, and the non-register code error cannot be modified.

[0005] In a first aspect, the present application provides a remapping method, comprising:

[0006] Obtaining a data modification request, the data modification request being used to request to modify the data at a first address in the first memory into target data;

[0007] Determining a first data block where the first address is located in the first memory, and judging whether the first data block exists in the second memory;

[0008] If yes, updating the first data block in the second memory according to the first address and the target data, so that the processor reads the target data in the second memory;

[0009] If no, storing the first data block to the second memory, and updating the first data block in the second memory according to the first address and the target data, so that the processor reads the target data in the second memory.

[0010] In a possible implementation, the updating the first data block in the second memory according to the first address and the target data comprises:

[0011] determining a first start address of the first data block in the first memory and a second start address of the first data block in the second memory;

[0012] determining a second address corresponding to the first address in the second memory according to the first address, the first start address and the second start address;

[0013] updating data at the second address in the second memory to the target data.

[0014] In a possible implementation, the determining the second address corresponding to the first address in the second memory according to the first address, the first start address and the second start address comprises:

[0015] determining a target offset of the first address relative to the first start address;

[0016] determining the second address according to the second start address and the target offset, wherein an offset between the second address and the second start address is the target offset.

[0017] In a possible implementation, the data modification request further comprises a target address corresponding to the first address and an enable signal corresponding to the first address, the target address being an address in the second memory; and the storing the first data block to the second memory comprises:

[0018] receiving a first data access request sent by the processor, the first data access request comprising a first access address;

[0019] determining whether the enable signal is a preset value when the first access address is the same as the first address;

[0020] if yes, obtaining the target address in the data modification request and storing the first data block to the second memory according to the target address.

[0021] In a possible implementation, the method further comprises:

[0022] obtaining the target data according to the first data access request;

[0023] sending the target data to the processor.

[0024] In a possible implementation, after storing the first data block to the second memory and updating the first data block in the second memory according to the first address and the target data, the method further includes:

[0025] sending the target address of the target data in the second memory to the processor, so that the processor creates a mapping relationship between the first address and the target address.

[0026] In a possible implementation, the method further includes:

[0027] determining, by the processor, a third address to be accessed in the first memory;

[0028] obtaining a mapping relationship table, the mapping relationship table including at least one address in the first memory and a mapping address of each address in the second memory;

[0029] determining whether the mapping relationship table includes a mapping address corresponding to the third address;

[0030] if yes, performing data access on the second memory according to the mapping address corresponding to the third address;

[0031] if no, performing data access on the first memory according to the third address.

[0032] In a possible implementation, the processor is provided with a control component on a data bus of the first memory; and performing data access on the first memory according to the third address includes:

[0033] generating, by the processor, a second data access request according to the third address, the second data access request including the third address;

[0034] sending, by the processor, the second data access request to the control component;

[0035] obtaining, by the control component, to-be-modified information, the to-be-modified information including a to-be-modified address, an enable signal corresponding to the to-be-modified address, a target modification address corresponding to the to-be-modified address, and to-be-modified data corresponding to the to-be-modified address;

[0036] determining, by the control component, whether the to-be-modified information includes the third address;

[0037] If yes, the processor is sent the third address corresponding to the data to be modified, and the control component performs address remapping processing according to the third address, the third address corresponding to the enable signal, the third address corresponding to the target modification address, and the third address corresponding to the data to be modified.

[0038] If no, the control component queries the third address corresponding data in the first processor, and sends the third address corresponding data to the processor.

[0039] In a possible implementation, the control component performs address remapping processing according to the third address, the third address corresponding to the enable signal, the third address corresponding to the target modification address, and the third address corresponding to the data to be modified, including:

[0040] It is judged whether the third address corresponding to the enable signal is equal to a preset value.

[0041] If yes, the third data block corresponding to the third address is determined in the first memory.

[0042] According to the third address corresponding to the target modification address, the third data block is stored in the second memory.

[0043] According to the third address and the third address corresponding to the data to be modified, the third data block in the second memory is updated.

[0044] In a possible implementation, after the control component performs address remapping processing according to the third address and the third address corresponding to the data to be modified, the method further includes:

[0045] The third address and the third address corresponding to the data to be modified are deleted in the data to be modified.

[0046] In a second aspect, the embodiments of the present application provide a remapping device, the device includes a first acquisition module, a first judgment module and an update module, wherein,

[0047] The first acquisition module is used to acquire a data modification request, and the data modification request is used to request modifying data on a first address in the first memory to target data.

[0048] The first judgment module is used to determine a first data block where the first address is located in the first memory, and judge whether the first data block exists in the second memory.

[0049] If yes, the updating module is configured to update the first data block in the second memory according to the first address and the target data, so that the processor reads the target data in the second memory;

[0050] If no, the updating module is configured to store the first data block to the second memory, and update the first data block in the second memory according to the first address and the target data, so that the processor reads the target data in the second memory.

[0051] In a possible implementation, the updating module is specifically configured to:

[0052] determine a first start address of the first data block in the first memory and a second start address of the first data block in the second memory;

[0053] determine a second address corresponding to the first address in the second memory according to the first address, the first start address and the second start address;

[0054] update data on the second address to the target data in the second memory.

[0055] In a possible implementation, the updating module is specifically configured to:

[0056] determine a target offset of the first address relative to the first start address;

[0057] determine the second address according to the second start address and the target offset, wherein an offset between the second address and the second start address is the target offset.

[0058] In a possible implementation, the updating module is specifically configured to:

[0059] receive a first data access request sent by the processor, wherein the first data access request includes a first access address;

[0060] when the first access address is the same as the first address, determine whether the enabling signal is a preset value;

[0061] If yes, the target address is acquired in the data modification request, and the first data block is stored to the second memory according to the target address.

[0062] In a possible implementation, the updating module is specifically configured to:

[0063] acquire the target data according to the first data access request;

[0064] sending the target data to the processor.

[0065] In a possible implementation, the updating module is specifically configured to:

[0066] The sending of the target data to the processor is at a target address of the target data in the second memory, so that the processor creates a mapping relationship between the first address and the target address.

[0067] In a possible implementation, the remapping apparatus further includes a determining module, a second obtaining module, a second judging module, and a data accessing module, wherein,

[0068] The determining module is configured to determine, by the processor, a third address to be accessed in the first memory.

[0069] The second obtaining module is configured to obtain a mapping relationship table, the mapping relationship table including at least one address in the first memory and a mapping address of each address in the second memory.

[0070] The second judging module is configured to judge whether the mapping address corresponding to the third address exists in the mapping relationship table.

[0071] If yes, the data accessing module is configured to perform data access on the second memory according to the mapping address corresponding to the third address.

[0072] If no, the data accessing module is configured to perform data access on the first memory according to the third address.

[0073] In a possible implementation, the data accessing module is specifically configured to:

[0074] Generate, by the processor, a second data access request according to the third address, the second data access request including the third address;

[0075] Send, by the processor, the second data access request to the control component;

[0076] Obtain, by the control component, to-be-modified information, the to-be-modified information including a to-be-modified address, an enabling signal corresponding to the to-be-modified address, a target modification address corresponding to the to-be-modified address, and to-be-modified data corresponding to the to-be-modified address;

[0077] Judge, by the control component, whether the third address is included in the to-be-modified information.

[0078] If yes, the data to be modified corresponding to the third address is sent to the processor, and the control component is used to perform address remapping according to the third address, the enable signal corresponding to the third address, the target modification address corresponding to the third address, and the data to be modified corresponding to the third address.

[0079] If no, the data corresponding to the third address is queried in the first processor through the control component, and the data corresponding to the third address is sent to the processor.

[0080] In a possible implementation, the data access module is specifically configured to:

[0081] determine whether the enable signal corresponding to the third address is equal to a preset value;

[0082] If yes, the third data block corresponding to the third address is determined in the first memory;

[0083] the third data block is stored into the second memory according to the target modification address corresponding to the third address;

[0084] the third data block in the second memory is updated according to the third address and the data to be modified corresponding to the third address.

[0085] In a possible implementation, the data access module is specifically configured to:

[0086] the third address and the data to be modified corresponding to the third address are deleted from the information to be modified.

[0087] In a third aspect, an embodiment of the present application provides a terminal device, the terminal device comprising a memory and a processor;

[0088] The memory and the processor are coupled;

[0089] The memory is configured to store program instructions;

[0090] The processor is configured to invoke the program instructions, so that the terminal device performs the remapping method in the first aspect and any possible implementation.

[0091] In a fourth aspect, an embodiment of the present application provides a non-transitory computer readable storage medium storing computer instructions, the computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by the terminal device to implement the remapping method in the first aspect and any possible implementation.

[0092] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising a computer program, which, when executed by a terminal device, is used to implement the remapping method according to the first aspect and any possible implementation manner.

[0093] The remapping method, device, equipment and storage medium provided by the present application can map the data block in which the data in the read-only memory is located to the random access memory when the data in the read-only memory needs to be modified, and modify the data in the data block in the random access memory. In this way, the data modification of the data at any address in the read-only memory can be flexibly performed, the flexibility of the data modification of the read-only memory is improved, the range of the modifiable data is expanded, and the complex scenarios of processor burst transmission or continuous transmission (burst access) can be applied. BRIEF DESCRIPTION OF DRAWINGS

[0094] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0095] Figure 1 The system architecture schematic diagram provided by the embodiment of the present application;

[0096] Figure 2 The flowchart of the remapping method provided by the embodiment of the present application;

[0097] Figure 3 The remapping process schematic diagram provided by the embodiment of the present application;

[0098] Figure 4 The flowchart of the data access of the first memory provided by the embodiment of the present application;

[0099] Figure 5 The structure schematic diagram of the control component provided by the embodiment of the present application;

[0100] Figure 6 The structure schematic diagram of the remapping device provided by the embodiment of the present application;

[0101] Figure 7 The structure schematic diagram of another remapping device provided by the embodiment of the present application;

[0102] Figure 8 The structure schematic diagram of the terminal device provided by the embodiment of the present application.

[0103] The specific embodiments of the application have been shown and described in the above drawings and text, and will be described in more detail below. These drawings and text are not intended to limit the scope of the concept of the application in any way, but to illustrate the concept of the application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0104] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The following description is made with reference to the accompanying drawings in which like reference numerals refer to like elements, and the description which follows is made by way of non-limiting examples with reference to the drawings and is not intended to limit the scope of the application as expressed by the appended claims.

[0105] In the technical solution of the present application, the collection, storage, use, processing, transmission, provision and disclosure of financial data or user data and other information comply with relevant laws and regulations and do not violate public order and good customs.

[0106] It should be noted that in the embodiments of the present application, some existing software, components, models and other industry solutions may be mentioned, which should be considered as exemplary, and the purpose is only to illustrate the feasibility of the implementation of the technical solution of the present application, but it does not mean that the applicant has or will necessarily use the solution.

[0107] For ease of understanding, the following will be combined with Figure 1 The system architecture to which the embodiments of the present application are applicable is described.

[0108] Figure 1 The system architecture provided by the embodiments of the present application is shown in the following Figure 1 , which includes a processor, a first memory and a second memory. The processor can interact with the first memory and the second memory, respectively. The processor can be a central processing unit (CPU) of a chip, the first memory can be a read-only memory (ROM) in the chip, and the second memory can be a random access memory (RAM) in the chip.

[0109] In actual application, the data in the first memory and the second memory can be used for storing data. Since the first memory is a read-only memory, the data in the first memory cannot be directly modified. If the data in the first memory needs to be modified, the data block in which the data is located in the first memory can be mapped to the second memory, and the modification of the data in the second memory is completed. When the processor reads the data at the address, the corresponding data in the second memory can be directly read.

[0110] For example, assuming that there is a processor 1, a first memory 1 and a second memory 1, data 1 in the first memory 1 is at an address 1, and the address 1 is located in a data block 1. If the data 1 in the first memory 1 needs to be modified to data 3, the data block 1 can be remapped to the second memory 1, and the data 1 in the second memory 1 is modified to data 3. When the processor 1 reads the data at the address 1, the data block 1 in the second memory 1 can be read, that is, the data read by the processor is data 3.

[0111] It should be noted that, Figure 1 The system architecture diagram is only used as an example and is not limited to the system architecture diagram.

[0112] In the related art, a small amount of data in the read-only memory of the chip is modified by adding a read control module and a small amount of circuit logic in the channel between the processor and the read-only memory. However, this method can only set the replacement address and the replacement data to the system register through the DEBUG module, and can only replace the single instruction statement, and cannot cope with the complex scenario of processor burst transmission or continuous transmission (burst access). Another way is to realize through software pre-embedding points, which can only modify the register values at fixed embedding points, and cannot modify non-register code errors.

[0113] In the embodiment of the present application, when the data in the read-only memory needs to be modified, the data block in which the data is located in the read-only memory can be mapped to the random access memory, and the data in the data block is modified in the random access memory. In this way, the data in the read-only memory at any address can be flexibly modified, the flexibility of modifying the data in the read-only memory is improved, the range of data that can be modified is expanded, and the data is mapped in the second memory in the form of a data block, which can be applied to the complex scenario of processor burst transmission or continuous transmission (burst access).

[0114] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described again in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0115] Figure 2 is a flowchart of a remapping method provided by an embodiment of the present application. Please refer to Figure 2 The method can include the following steps:

[0116] S201, obtaining a data modification request.

[0117] The data modification request can include a first address and target data. The first address can be the address of the data to be modified in the first memory, and the target data can be used to replace the original data corresponding to the first address. The data modification request is used to request to modify the data at the first address in the first memory to the target data.

[0118] The execution subject of the embodiment of the present application can be a remapping device, or a remapping apparatus provided in the remapping device. The remapping apparatus can be implemented by software, or by a combination of software and hardware.

[0119] S202, determining a first data block in which the first address is located in the first memory, and determining whether the first data block exists in the second memory.

[0120] If yes, S203 is performed.

[0121] If no, S204 is performed.

[0122] The first data block can be a data block in which the data at the first address in the first memory is located. The first data block can include a plurality of data, and the addresses of the plurality of data in the first memory are continuous. The plurality of continuous addresses corresponding to the plurality of data can be determined by the maximum transmission data amount in the interaction process between the processor and the first memory and the first address. The maximum transmission data amount is to ensure that the data corresponding to the plurality of modification addresses in the burst transmission or continuous transmission (burst access) complex scenario is in the same data block. In this way, even in the burst transmission or continuous transmission (burst access) complex scenario, the modification of the data can be realized.

[0123] For example, assuming that the first address is 0x21000032, the maximum amount of data transferred in the interaction between the processor and the first memory is 64 bytes, it is determined that the first data block can contain 64 data, and the starting address of the plurality of continuous addresses is 0x21000000, it can be determined that the plurality of continuous addresses corresponding to the plurality of data in the first data block can be 0x21000000 to 0x21000064.

[0124] If there is a modification request for a certain data in the first data block in the first memory before the current time, the data in the first data block has been stored in the second memory before the current time, and at this time, the first data block already exists in the second memory. That is, if the first data block exists in the second memory, it means that the first data block has completed the remapping process in the second memory, at this time, the storage address of the data at the first address in the second memory is determined, and the data modification is completed according to the target data at the address. If the first data block does not exist in the second memory, it means that the first data block has not been remapped before the current time, and the first data block needs to be remapped first, and then the data modification is performed according to the target data at the storage address of the data at the first address in the second memory.

[0125] S203, updating the first data block in the second memory according to the first address and the target data, so that the processor reads the target data in the second memory.

[0126] There are two ways to update the first data block in the second memory according to the first address and the target data:

[0127] Method one: determining a first starting address of the first data block in the first memory and a second starting address of the first data block in the second memory; determining a second address corresponding to the first address in the second memory according to the first address, the first starting address and the second starting address; updating the data on the second address to the target data in the second memory.

[0128] The first starting address can be the address of the first data in the first data block in the first memory, the second starting address can be the address of the first data in the first data block in the second memory, and the second address can be the address of the data corresponding to the first address in the second memory.

[0129] The way of determining the second starting address corresponding to the first address in the second memory is as follows: determining a target offset of the first address relative to the first starting address; determining the second address according to the second starting address and the target offset, wherein the offset between the second address and the second starting address is the target offset.

[0130] The target offset can be an offset between the first address and the first start address. Any two of the target offset, the first address and the first start address can be used to obtain the other one.

[0131] For example, if the first address is 0x21000024 and the first start address is 0x21000000, the target offset can be obtained as 24. If the target offset is 36 and the first start address is 0x21000000, the first address can be obtained as 0x21000036. If the target offset is 10 and the first address is 0x21000010, the first start address can be obtained as 0x21000000.

[0132] For example, if there are a first memory 1 and a second memory 1, the first address is 0x21000014, and the target data is X, the addresses of the plurality of data contained in the first data block corresponding to the first address in the first memory 1 are 0x21000000 to 0x21000064, and the addresses of the plurality of data contained in the first data block in the second memory 1 are 0x00000000 to 0x00000064. The first start address of the first data block in the first memory 1 is determined as 0x21000000, and the second start address of the first data block in the second memory 1 is determined as 0x00000000. The target offset can be determined as 14 according to the first address 0x21000014 and the first start address 0x21000000, and the second address can be determined as 0x00000014 according to the second start address 0x00000000 and the target offset 14. The data at the second address 0x00000014 is updated to the target data X.

[0133] Method 2: The data modification request further includes a target address corresponding to the first address. The target address can be a storage address of the first data block in the second memory. When the first data block does not exist in the second memory, the target address corresponding to the first address is obtained. After the first data block is stored in the second memory, the data at the target address in the second memory is updated to the target data according to the target data.

[0134] S204, storing the first data block into the second memory, and updating the first data block in the second memory according to the first address and the target data, so that the processor reads the target data in the second memory.

[0135] The first data block can be stored into the second memory by the following manner: the data modification request further comprises a target address corresponding to the first address, an enable signal corresponding to the first address, the first data access request sent by the receiving processor, and the first data access request comprises the first access address; when the first access address is the same as the first address, it is judged whether the enable signal is a preset value; if yes, the target address is obtained from the data modification request, and the first data block is stored into the second memory according to the target address.

[0136] The target address can be an address in the second memory, which is used to determine which address in the second memory the plurality of data in the first data block is stored in. Assuming that the plurality of data in the first data block is in a plurality of continuous addresses 0x21000000 to 0x21000064 in the first memory, and the target address is 0x00000014, the plurality of data in the first data block is stored in addresses 0x00000000 to 0x00000064 in the second memory.

[0137] The enable signal can be used to determine whether the data at the first address is subjected to the remapping processing. Whether the first address corresponding to the enable signal is subjected to the remapping processing is determined by judging whether the enable signal is a preset value. The preset value can be 0 or other preset value set in advance. Assuming that the preset value is 0, the enable signal corresponding to the first address 1 is 0, and the enable signal corresponding to the first address 2 is 1, the first address 1 is subjected to the remapping processing, and the first address 2 is not subjected to the remapping processing.

[0138] The first access request can be used for the processor to request to access the data in the first memory, and the first access address can be the address of the data in the first memory requested to be accessed by the processor.

[0139] For example, assuming that there are a processor 1, a first memory 1 and a second memory 1, the preset value is 0, the first address in the data modification request is 0x21000014, the enable signal is 0, the target address is 0x21000014, and the target data is X, it is determined that the plurality of data in the first data block corresponding to the first address is in addresses 0x21000000 to 0x21000064 in the first memory. When the first data access request 1 sent by the processor 1 is received, the first access address is obtained as 0x21000014. The first access address 0x21000014 is the same as the first address 0x21000014, it is judged that the enable signal is a preset value, the target address is obtained as 0x00000014 from the data modification request, and according to the target address, it is determined that the plurality of data in the first data block is in addresses 0x00000000 to 0x00000064 in the second memory, and the first data block is stored in the second memory.

[0140] After storing the first data block to the second memory and updating the first data block in the second memory according to the first address and the target data, the target address of the target data in the second memory is sent to the processor, so that the processor creates a mapping relationship between the first address and the target address.

[0141] Meanwhile, to ensure that the access efficiency of the processor when accessing data is not affected during the data modification process, the target data can be obtained according to the first data access request, and the target data can be sent to the processor.

[0142] In Figure 2 In the embodiment shown in the figure, when it is needed to modify the data at the first address in the first memory (read-only memory) to target data, the first data block where the first address is located can be determined, if the first data block exists in the second memory (random access memory), the address of the data at the first address in the second memory is determined, and the data at the address is modified according to the target data; if not, the first data block is stored into the second memory according to the target address, and the data at the target address in the second memory is modified according to the target data, after the data modification is completed, the target address is sent to the processor, so that the processor creates a mapping relationship between the first address and the target address, in this way, when the processor accesses the data at the first address next time, the target address can be directly accessed, the problem that only the data at part of the addresses is modified when the first memory is modified is avoided, the data at any address in the first memory can be modified, the flexibility of data modification is improved, the range of data modification is expanded, and in the mapping process, the data is mapped in the form of data block, the problem that data modification cannot be realized in complex scenarios such as burst access of the processor is solved.

[0143] In Figure 2 On the basis of the embodiment shown in the figure, the following will be described in combination with Figure 3 The remapping process is described through specific embodiments.

[0144] Figure 3 A remapping process diagram provided by the embodiment of the present application is shown in the figure. Figure 3 The data modification request of the input control component is shown in Table 1.

[0145] Table 1

[0146]

[0147]

[0148] The preset value is 0, the maximum transmission data amount in the interaction process of the processor and the first memory is 64 bytes, the first data block 1 corresponding to the first address 0x21000001 in the first memory respectively contains data in the address range of 0x21000000 to 0x21000064, the first data block 2 corresponding to the first address 0x15000011 contains data in the address range of 0x15000000 to 0x15000064, and the first data block 3 corresponding to the first address 0x36000052 contains data in the address range of 0x36000000 to 0x36000064.

[0149] When it is judged that the first data block 1 and the first data block 2 do not exist in the second memory, if the first access address included in the first data access request sent by the processor is 0x21000001, the first access address is the same as the first address 0x21000001, it is judged that the enable signal corresponding to the first address 0x21000001 is the preset value, the target address corresponding to the first address 0x21000001 in the data modification request is 0x00000001, and the storage address of the plurality of data in the first data block 1 in the second memory is determined to be 0x00000000 to 0x00000064 according to the target address 0x00000001. According to the target address 0x00000001 of the target data A in the second memory, data modification is performed, and after the data modification is completed, the target address of the target data in the second memory is sent to the processor, so that the processor creates a mapping relationship between the first address 0x21000001 and the target address 0x00000001.

[0150] If the first access address included in the first data access request sent by the processor is 0x15000011, the first access address is the same as the first address 0x15000011, it is judged that the enable signal corresponding to the first address 0x15000011 is different from the preset value, and then the first address 0x15000011 is not subjected to remapping processing.

[0151] It is judged that the first data block 3 exists in the second memory, and the storage address of the plurality of data in the first data block 3 in the second memory is determined to be 0x02000000 to 0x02000064.

[0152] The first data block 3 has a first start address 0x36000000 in the first memory and a second start address 0x02000000 in the second memory. According to the first start address 0x36000000 and the first address 0x36000052, a target offset is 52. According to the target offset 52 and the second start address 0x02000000, a second address is 0x02000052. The data corresponding to the second address 0x02000052 in the second memory is modified to the target data C corresponding to the first address 0x36000052.

[0153] In Figure 3 In the embodiment shown, if data modification processing is needed for data at an address in the first memory, it can be determined whether a data block corresponding to the address exists in the second memory. If the data block exists, a storage address of the data at the address in the second memory is determined, and data modification is performed at the storage address according to target data. If the data block does not exist, remapping processing is performed for the address, and data modification is performed at a target address corresponding to the address according to target data. After the modification is completed, the target address is sent to the processor, and the processor creates a mapping relationship between the address and the target address, so that when the processor accesses data at the address later, data access can be directly performed at the target address. The maximum transmission data amount is used to determine a data block in which the modified data is located, and the data block is mapped to the second memory, so that data modification for multiple continuous modification addresses can be completed at the same time, and the method is suitable for complex scenarios such as burst transmission or continuous transmission (burst access) of the processor, and the transmission of multiple continuous modification addresses.

[0154] On the basis of any of the above embodiments, the following describes Figure 4 The process of data access to the first memory is described.

[0155] Figure 4 The flowchart of data access to the first memory provided by the embodiments of the present application is shown.

[0156] Please refer to Figure 4 The method can include the following steps.

[0157] S401, determining, by a processor, a third address to be accessed in a first memory.

[0158] The third address can be an address to be accessed in the first memory by the processor.

[0159] S402, obtaining a mapping relationship table.

[0160] The mapping relationship table includes at least one address in the first memory and a mapping address of each address in the second memory. For any address in the first memory which has completed remapping, the mapping address can be the corresponding address of the address in the second memory.

[0161] For example, assuming that the addresses 0x21000011, 0x20000001 and 0x11000010 in the first memory have completed remapping, and the mapping addresses in the second memory are addresses 0x00000011, 0x01000001 and 0x01000010 respectively. The mapping relationship table about the addresses 0x21000011, 0x20000001 and 0x11000010 is shown in Table 2:

[0162] Table 2

[0163] Address in first memory Mapped address in second memory 0x21000011 0x00000011 0x20000001 0x01000001 0x11000010 0x01000010

[0164] S403, judging whether the mapping address corresponding to the third address exists in the mapping relationship table.

[0165] If yes, step S404 is executed;

[0166] If no, step S405 is executed.

[0167] If the third address exists in the mapping relationship table, it means that the remapping processing of the third address has been completed in the second memory before the current time. At this time, if the processor accesses the data at the third address, the data access can be directly performed at the mapping address corresponding to the third address in the second memory. If the third address does not exist in the mapping relationship table, it means that the remapping processing of the third address has not been performed. When the processor accesses the data at the third address, the data access is still performed at the third address in the first memory.

[0168] S404, performing data access to the second memory according to the mapping address corresponding to the third address.

[0169] For example, assuming that the third address is 0x21000011, the mapping address corresponding to the third address is 0x00000011 in the mapping relationship table, and the processor directly performs data access at the mapping address 0x00000011 in the second memory.

[0170] S405, performing data access to the first memory according to the third address.

[0171] The data access to the first memory is performed in the following manner: a second data access request is generated by the processor according to the third address, the second data access request including the third address; the second data access request is sent by the processor to the control component; the to-be-modified information is obtained by the control component, the to-be-modified information including the to-be-modified address, the enable signal corresponding to the to-be-modified address, the target modified address corresponding to the to-be-modified address, and the to-be-modified data corresponding to the to-be-modified address; it is determined by the control component whether the third address is included in the to-be-modified information; if yes, the to-be-modified data corresponding to the third address is sent to the processor, and the address remapping processing is performed by the control component according to the third address, the enable signal corresponding to the third address, the target modified address corresponding to the third address, and the to-be-modified data corresponding to the third address; if not, the data corresponding to the third address is queried in the first processor by the control component, and the data corresponding to the third address is sent to the processor.

[0172] The second data access request can be a request of the processor for data access to the first memory, the processor being provided with the control component on a data bus of the first memory, the control component being configured to determine whether the third address needs to be modified and to complete the address remapping processing. The to-be-modified information includes at least one to-be-modified address, an enable signal corresponding to each to-be-modified address, a target modified address corresponding to each to-be-modified address, and to-be-modified data corresponding to each to-be-modified address, wherein the to-be-modified address can be an address of data to be modified in the first memory, the enable signal can be used to determine whether the data at the to-be-modified address needs to be remapped, the target modified address can be a storage address of the data at the to-be-modified address in the second memory, and the to-be-modified data can be data used to replace the original data at the to-be-modified address.

[0173] Suppose that the data in the first memory needs to be modified, the to-be-modified addresses are 0x21000001, 0x15000011, 0x04000020, and 0x21000011, the enable signals corresponding to the to-be-modified addresses are 0, 1, 0, and 0 respectively, the target modified addresses corresponding to the to-be-modified addresses are 0x00000001, 0x01000011, 0x11000020, and 0x10000011 respectively, and the to-be-modified data corresponding to the to-be-modified addresses are A, B, C, and D respectively, the to-be-modified information can be as shown in Table 3.

[0174] Table 3

[0175] Address to be modified Enable signal Target modified address Data to be modified 0x21000001 0 0x00000001 A 0x15000011 1 0x01000011 B 0x04000020 0 0x11000020 C 0x21000011 0 0x10000011 D

[0176] The address remapping process using the control component is as follows: determine whether the enable signal corresponding to the third address is equal to a preset value; if so, determine the third data block corresponding to the third address in the first memory; store the third data block in the second memory according to the target modification address corresponding to the third address; update the third data block in the second memory according to the third address and the data to be modified corresponding to the third address.

[0177] The third data block can be the data block containing the data at the third address in the first memory.

[0178] Please refer to step S204 for the process of address remapping through the control component; it will not be repeated here.

[0179] After address remapping is performed by the control component and the data modification is completed in the second memory, the third address and the data to be modified corresponding to the third address are deleted from the information to be modified.

[0180] exist Figure 4 In the illustrated embodiment, when the processor needs to access a third address in the first memory, it determines whether the third address has been remapped before the current time based on the mapping table. If so, the processor accesses the data at the mapped address corresponding to the third address in the second memory. If not, it determines whether the information to be modified includes the third address. If the information includes the third address, the data to be modified corresponding to the third address is returned to the processor, and the third address is remapped. If the information does not include the third address, the data at the third address in the first memory is accessed. In this way, the data block containing the modified data in the first memory is mapped to the second memory. When the processor reads the data in the first memory, it can directly read the modified data in the second memory. This method enables data modification at any address in the read-only memory, improving the flexibility of data modification in the read-only memory, expanding the range of modifiable data, and ensuring that the access efficiency of the system during data access is not affected during the data modification process.

[0181] Based on any of the above embodiments, the control components in the embodiments of this application will be described in detail below.

[0182] Figure 5 This is a schematic diagram of the structure of a control component provided in an embodiment of this application. Figure 5As shown, the control component 12 is located between the processor 11 and the first memory 13, and is connected to the processor 11 and the first memory 13 respectively via a data bus 15. When it is not necessary to modify the data in the first memory 13, the control component 12 will not process the data access request sent by the processor 11. At this time, the function of the control component 12 is the same as that of the data bus 15, which is only used as a data transmission channel to transmit data information when the processor 11 and the first memory 13 interact.

[0183] When data in the first memory 13 needs to be modified, the control component 12 is activated, and the information to be modified is input into the control component 12. The information to be modified may include at least one address to be modified, an enable signal corresponding to each address to be modified, a target modification address corresponding to each address to be modified, and data to be modified corresponding to each address to be modified. When the control component 12 receives a data access request sent by the processor 11, it obtains the access address in the data access request and determines whether the address to be modified contains an access address, that is, whether there is an address to be modified that matches the access address among the multiple addresses to be modified in the information to be modified. If an access address is contained, the data to be modified corresponding to the access address is returned to the processor 11, and address remapping is performed according to the address to be modified, the enable signal, the target modification address, and the data to be modified. If the information to be modified does not contain an access address, the data corresponding to the access address is read from the first memory 13 according to the access address, the access data is obtained, and the access data is sent to the processor 11.

[0184] The information input to the control component 12 may include data access requests, information to be modified, and startup information. The data access requests are sent by the processor 11 and input to the control component 12 via the data bus 15. The information to be modified and the startup information are input by the user. When it is necessary to modify the data in the first memory 13, the user inputs the startup information and the information to be modified into the control component 12. The startup information is used to start the control component 12.

[0185] exist Figure 5 In the embodiment shown, the control component 12 is located between the processor 11 and the first memory 13. It is mainly designed inside the chip and no external programs or modules are involved. When the data in the first memory 13 is modified, it will not pose a security risk to the data in the first memory 13.

[0186] Figure 6 This is a schematic diagram of a remapping device provided in an embodiment of this application. Please refer to... Figure 6 The remapping device 20 may include: a first acquisition module 21, a first judgment module 22, and an update module 23, wherein,

[0187] The first obtaining module 21 is configured to obtain a data modification request, the data modification request being used to request modification of data at a first address in a first memory into target data.

[0188] The first determining module 22 is configured to determine a first data block in which the first address is located in the first memory, and determine whether the first data block exists in a second memory.

[0189] If yes, the updating module 23 is configured to update the first data block in the second memory according to the first address and the target data, so that the processor reads the target data in the second memory.

[0190] If no, the updating module 23 is further configured to store the first data block to the second memory, and update the first data block in the second memory according to the first address and the target data, so that the processor reads the target data in the second memory.

[0191] The remapping apparatus provided in the embodiment can be used to execute the remapping method shown in the method embodiments, and has similar implementation principles and technical effects, which will not be described here in detail.

[0192] In a possible implementation, the updating module 23 is specifically configured to:

[0193] determine a first start address of the first data block in the first memory and a second start address of the first data block in the second memory;

[0194] determine, according to the first address, the first start address and the second start address, a second address corresponding to the first address in the second memory;

[0195] update data at the second address in the second memory to the target data.

[0196] In a possible implementation, the updating module 23 is specifically configured to:

[0197] determine a target offset of the first address relative to the first start address;

[0198] determine the second address according to the second start address and the target offset, wherein an offset between the second address and the second start address is the target offset.

[0199] In a possible implementation, the updating module 23 is specifically configured to:

[0200] receive a first data access request sent by the processor, the first data access request including a first access address;

[0201] when the first access address is the same as the first address, determine whether the enable signal is a preset value;

[0202] If yes, the target address is acquired in the data modification request, and the first data block is stored to the second memory according to the target address.

[0203] In a possible implementation, the updating module 23 is specifically configured to:

[0204] acquire target data according to the first data access request;

[0205] send the target data to the processor.

[0206] In a possible implementation, the updating module 23 is specifically configured to:

[0207] send the target address of the target data in the second memory to the processor, so that the processor creates a mapping relationship between the first address and the target address.

[0208] The remapping apparatus provided in this embodiment can be used to execute the remapping method shown in the method embodiments, and has similar implementation principles and technical effects, which will not be described here in detail.

[0209] Figure 7 Another structure diagram of a remapping apparatus provided in this embodiment is shown in FIG. 30. Figure 7 The remapping apparatus 30 can further include a determining module 34, a second acquiring module 35, a second judging module 36, and a data access module 37, wherein,

[0210] The determining module 34 is configured to determine, by the processor, a third address to be accessed in the first memory.

[0211] The second acquiring module 35 is configured to acquire a mapping relationship table, the mapping relationship table including at least one address in the first memory and a mapping address of each address in the second memory.

[0212] The second judging module 36 is configured to judge whether the mapping address corresponding to the third address exists in the mapping relationship table.

[0213] If yes, the data access module 37 is configured to perform data access on the second memory according to the mapping address corresponding to the third address.

[0214] If no, the data access module 37 is configured to perform data access on the first memory according to the third address.

[0215] In a possible implementation, the data access module 37 is specifically configured to:

[0216] generate, by the processor, a second data access request according to the third address, the second data access request including the third address;

[0217] send, by the processor, the second data access request to the control component.

[0218] The control component obtains to-be-modified information, and the to-be-modified information includes a to-be-modified address, an enable signal corresponding to the to-be-modified address, a target modification address corresponding to the to-be-modified address, and to-be-modified data corresponding to the to-be-modified address;

[0219] The control component determines whether the to-be-modified information includes a third address;

[0220] If yes, the control component sends to-be-modified data corresponding to the third address to the processor, and performs address remapping processing on the third address, the enable signal corresponding to the third address, the target modification address corresponding to the third address, and the to-be-modified data corresponding to the third address.

[0221] If no, the control component queries data corresponding to the third address in the first processor, and sends the data corresponding to the third address to the processor.

[0222] In a possible implementation, the data access module 37 is specifically configured to:

[0223] The control component determines whether the enable signal corresponding to the third address is equal to a preset value.

[0224] If yes, the control component determines a third data block corresponding to the third address in the first memory.

[0225] The control component stores the third data block into the second memory according to the target modification address corresponding to the third address.

[0226] The control component updates the third data block in the second memory according to the third address and the to-be-modified data corresponding to the third address.

[0227] In a possible implementation, the data access module 37 is specifically configured to:

[0228] The control component deletes the third address and the to-be-modified data corresponding to the third address in the to-be-modified information.

[0229] The remapping apparatus provided in this embodiment can be used to execute the remapping method shown in the method embodiments, and has similar implementation principles and technical effects, which are not described herein again.

[0230] Figure 8 A structural schematic diagram of a terminal device is provided in this embodiment. As shown in the figure, Figure 8 The terminal device 40 can include a memory 41 and a processor 42.

[0231] The memory 41 and the processor 42 are coupled and can communicate with each other. For example, the memory 41 and the processor 42 communicate with each other through the communication bus 43. The memory 41 is configured to store computer-executable instructions. The processor 42 is configured to invoke the program instructions to enable the terminal device to perform the remapping method according to the first aspect and any possible implementation.

[0232] Optionally, the terminal device can be the same as the computing device, or the terminal device can perform any one of the methods in the embodiments of the present application, and the computing device can also perform any one of the methods in the embodiments of the present application.

[0233] Optionally, the processor can be a central processing unit (CPU), a graphics processing unit (GPU), another general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or the like. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of the present application can be directly embodied as hardware processor execution or a combination of hardware and software modules in the processor.

[0234] The embodiments of the present application provide a non-transitory computer-readable storage medium storing computer instructions. The computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are executed by a first computing device, the computer-executable instructions are configured to implement the remapping method according to the first aspect and any possible implementation.

[0235] The embodiments of the present application provide a computer program product, which includes a computer program. When the computer program is executed by a terminal device, the computer program is configured to implement the remapping method according to the first aspect and any possible implementation.

[0236] All or part of the steps of the above-mentioned method embodiments can be completed by program instruction-related hardware. The foregoing program can be stored in a readable memory. When the program is executed, the steps of the foregoing method embodiments are executed. The foregoing memory (storage medium) includes a read-only memory (English: read-only memory, abbreviation: ROM), a RAM, a flash memory, a hard disk, a solid state disk, a magnetic tape, a floppy disk (English: floppy disk), an optical disc, and any combination thereof.

[0237] The embodiments of the present application are described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as a combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor or other programmable processing unit to produce a machine, so that the instructions executed by the computer or other programmable processing unit generate a device that implements the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that implements the functions specified in the flowchart and / or block diagram block or blocks.

[0238] These computer program instructions can also be stored in a computer-readable memory that can direct the computer or other programmable processing unit to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including instruction apparatus, which implements the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that implements the functions specified in the flowchart and / or block diagram block or blocks.

[0239] These computer program instructions can also be loaded into a computer or other programmable processing unit, so that a series of operation steps are performed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide a process for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that implements the functions specified in the flowchart and / or block diagram block or blocks.

[0240] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the embodiments of the present application also intend to include these modifications and variations.

[0241] In the embodiments of the present application, the terms "comprising", "containing" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, the element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element. The term "or" and its variants can refer to "and / or". In the embodiments of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. In the embodiments of the present application, "a plurality of" means two or more. "And / or", which describes the relationship between the associated objects, means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects.

[0242] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the embodiments of the present application cover any and all variations of the present application that lie within the scope of the general inventive concepts herein, along with all of the alterations and further modifications of the embodiments of the present application that are disclosed and that can fall out by the usual practice of the art to which the embodiments of the present application pertains.

Claims

1. A remapping method, characterized by, The application is applied to an electronic device, the electronic device comprises a processor, a read-only first memory and a random access second memory, and comprises: obtaining a data modification request, the data modification request is used for requesting to modify data at a first address in the first memory into target data; determining a first data block where the first address is located in the first memory, and judging whether the first data block exists in the second memory; if yes, updating the first data block in the second memory according to the first address and the target data, so that the processor reads the target data in the second memory; if no, storing the first data block to the second memory, and updating the first data block in the second memory according to the first address and the target data, so that the processor reads the target data in the second memory; the remapping method further comprises: determining a third address to be accessed in the first memory by the processor; obtaining a mapping relationship table, the mapping relationship table comprises at least one address in the first memory and a mapping address of each address in the second memory; judging whether the mapping address corresponding to the third address exists in the mapping relationship table; if yes, performing data access on the second memory according to the mapping address corresponding to the third address; if no, performing data access on the first memory according to the third address; the processor and the data bus of the first memory are provided with a control component; performing data access on the first memory according to the third address comprises: generating a second data access request by the processor according to the third address, the second data access request comprises the third address; sending the second data access request to the control component by the processor; obtaining to-be-modified information by the control component, the to-be-modified information comprises a to-be-modified address, an enable signal corresponding to the to-be-modified address, a target modification address corresponding to the to-be-modified address, and to-be-modified data corresponding to the to-be-modified address; judging whether the third address exists in the to-be-modified information by the control component; if yes, sending the to-be-modified data corresponding to the third address to the processor, and performing address remapping processing by the control component according to the third address, the enable signal corresponding to the third address, the target modification address corresponding to the third address, and the to-be-modified data corresponding to the third address; if no, querying the data corresponding to the third address in the first memory by the control component, and sending the data corresponding to the third address to the processor.

2. The method of claim 1, wherein, updating the first data block in the second memory according to the first address and the target data comprises: determining a first start address of the first data block in the first memory and a second start address of the first data block in the second memory; determining, according to the first address, the first start address and the second start address, a second address corresponding to the first address in the second memory; updating data at the second address in the second memory to the target data.

3. The method of claim 2, wherein, determining, according to the first address, the first start address and the second start address, a second address corresponding to the first address in the second memory, comprises: determining a target offset of the first address relative to the first start address; determining the second address according to the second start address and the target offset, wherein an offset between the second address and the second start address is the target offset.

4. The method according to any one of claims 1 to 3, characterized in that, The data modification request further comprises a target address corresponding to the first address and an enable signal corresponding to the first address, the target address being an address in the second memory; storing the first data block to the second memory, comprises: receiving a first data access request sent by the processor, the first data access request comprising a first access address; when the first access address is the same as the first address, determining whether the enable signal is a preset value; if yes, obtaining the target address in the data modification request, and storing the first data block to the second memory according to the target address.

5. The method of claim 4, wherein, The method further comprises: obtaining the target data according to the first data access request; sending the target data to the processor.

6. The method of claim 1, wherein, After storing the first data block to the second memory and updating the first data block in the second memory according to the first address and the target data, the method further comprises: sending a target address of the target data in the second memory to the processor, so that the processor creates a mapping relationship between the first address and the target address.

7. The method of claim 1, wherein, According to the third address, an enable signal corresponding to the third address, a target modification address corresponding to the third address, and to-be-modified data corresponding to the third address, performing address remapping processing by the control component, comprises: determining whether the enable signal corresponding to the third address is equal to a preset value; if yes, determining a third data block corresponding to the third address in the first memory; storing the third data block to the second memory according to the target modification address corresponding to the third address; updating the third data block in the second memory according to the third address and the to-be-modified data corresponding to the third address.

8. The method of claim 1, wherein, After performing address remapping processing by the control component according to the third address and to-be-modified data corresponding to the third address, the method further comprises: deleting the third address and the to-be-modified data corresponding to the third address in the to-be-modified information.

9. A remapping device, characterized by The device is applied to an electronic device, and the electronic device comprises a processor, a read-only first memory and a random access second memory, and the device comprises: a first obtaining module configured to obtain a data modification request, the data modification request being used to request modifying data at a first address in the first memory to target data; The first judging module is configured to determine a first data block in which the first address is located in the first memory, and judge whether the first data block exists in the second memory. If yes, the updating module is configured to update the first data block in the second memory according to the first address and the target data, so that the processor reads the target data in the second memory. If no, the updating module is configured to store the first data block into the second memory, and update the first data block in the second memory according to the first address and the target data, so that the processor reads the target data in the second memory. The remapping device further comprises: The determining module is configured to determine, by the processor, a third address to be accessed in the first memory. The second obtaining module is configured to obtain a mapping relationship table, the mapping relationship table comprising at least one address in the first memory and a mapping address of each address in the second memory. The second judging module is configured to judge whether the mapping address corresponding to the third address exists in the mapping relationship table. If yes, the data accessing module is configured to perform data access on the second memory according to the mapping address corresponding to the third address. If no, the data accessing module is configured to perform data access on the first memory according to the third address. The data bus between the processor and the first memory is provided with a control component; and the data accessing module is specifically configured to: generate, by the processor, a second data access request according to the third address, the second data access request comprising the third address; send, by the processor, the second data access request to the control component; obtain, by the control component, to-be-modified information, the to-be-modified information comprising a to-be-modified address, an enable signal corresponding to the to-be-modified address, a target modification address corresponding to the to-be-modified address, and to-be-modified data corresponding to the to-be-modified address; judge, by the control component, whether the third address is included in the to-be-modified information; if yes, send, to the processor, the to-be-modified data corresponding to the third address, and perform address remapping processing by the control component according to the third address, the enable signal corresponding to the third address, the target modification address corresponding to the third address, and the to-be-modified data corresponding to the third address; if no, query, by the control component, the data corresponding to the third address in the first memory, and send, to the processor, the data corresponding to the third address.

10. A terminal device, comprising: The memory and the processor are coupled. The memory is configured to store program instructions. The processor is configured to invoke the program instructions, so that the terminal device executes the method in any one of claims 1 to 8. The computer instructions are configured to enable the computer to execute the method in any one of claims 1 to 8.

11. A non-transitory computer readable storage medium having stored thereon computer instructions, wherein: The computer program is executed by the processor to implement the method in any one of claims 1 to 8. ​ 12. A computer program product comprising a computer program, characterized in that, ​

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