System and method for generating quality metrics for optimization tasks in topology synthesis of networks

Abstract

Qualifying network properties can be used for network topology generation, such as network-on-chip (NoC). Systems and methods are disclosed for generating quality metrics for optimization tasks in the topology generation of a network. The systems and methods can be used for topology synthesis of a network such as a network-on-chip (NoC). According to various embodiments and aspects of the present invention, quality metrics are generated, analyzed and used to determine a quantitative quality value set for a given generated solution for a network. The disclosed methods allow a network designer or an automated network generation process to determine whether the resulting solution is a good, average or bad solution. An advantage of the present invention is that the design process and the work of the designer is simplified by using quality metrics. Various quality metrics are generated using a network definition. These quality metrics provide a quality evaluation and quality assessment of the optimization process for the generated (optimized) network. The quality metrics include analyzing the latency through the network and analyzing the bus cable length used by the network.

Description

[0001] This application is a divisional application of the Chinese Invention Patent Application No. 202111464959.7, with the title of “System and method for generating quality metric of optimization task in topology synthesis of network”, filed on December 3, 2021. TECHNICAL FIELD

[0002] The present invention is in the field of network design and more specifically, relates to generating and using quality metrics in topology synthesis of a network-on-chip (NoC). BACKGROUND

[0003] Multi-processor systems have been implemented in a system-on-chip (SoC) that communicates through a network-on-chip (NoC). The SoC includes instances of master (initiator) intellectual property (IP) and slave (target) IP. Transactions are sent from a master to one or more slaves in the form of packets using an industry standard protocol. A master connected to the NoC uses an address to select a slave, sending a request transaction to the slave. The NoC decodes the address and transfers the request from the master to the slave. The slave processes the transaction and sends a response transaction that is transported by the NoC back to the master.

[0004] Creating an optimal NoC that meets all the requirements in terms of performance, such as connectivity and latency between sources and destinations, frequency of various elements, maximum area available to the NoC logic, minimum throughput between sources and destinations, location of elements connected to the NoC on the floorplan, with a minimum number of logic and cables is a complex task. This is typically the job of a chip architect or a chip designer to create an optimal NoC, which is a difficult and time consuming task. In addition to this being a difficult task, the design of the NoC is modified every time there is a change in requirements, such as modifying the chip floorplan or modifying the expected performance. Therefore, this task needs to be redone frequently during the design time of the chip. This process is time consuming, leading to production delays.

[0005] As mentioned earlier, creating an optimal NoC that meets all the requirements in terms of performance and minimizes the number of logic and cables used is a complex task. This is a difficult and time consuming task. Also, the design of the NoC is modified every time there is a change in requirements. Therefore, the optimization of the NoC is redone frequently during the design time. When given a set of constraints, an optimal NoC is created automatically considering various processes. Regardless of the process used to create the NoC automatically, there is a need to evaluate the result produced by the automatic process to determine the quality of the result or output. Therefore, what is needed is a system and method to analyze the NoC and generate a quality metric for the given generated solution for that NoC. SUMMARY

[0006] In accordance with various embodiments and aspects of the present invention, systems and methods are disclosed that analyze a network-on-chip (NoC) and produce a quality metric for a given solution of the NoC. The disclosed systems and methods include a process that implements optimization strategies to maximize the quality of the result, which allows the designer to understand whether the resulting solution is a good, average, or bad solution. Advantages of the present invention include simplifying the design process and the work of the designer by using the quality metric generated for the network. Various quality metrics are determined. These quality metrics provide a method for quality evaluation. The quality metrics can determine the quality of optimization of the generated network. The quality metrics include analyzing the paths and edges in the network. BRIEF DESCRIPTION OF DRAWINGS

[0007] For a more complete understanding of the present invention, reference is now made to the following descriptions taken in connection with the accompanying drawings in which:

[0008] Figure 1A A logical view of a network-on-chip (NoC) is shown, including various elements that create the NoC.

[0009] Figure 1B A NoC is shown that includes elements placed on a layout plan of the network.

[0010] Figure 2 A process for determining the actual versus optimal distance between a source (R) and sink (S) pair of endpoints in accordance with aspects and embodiments of the present invention is shown.

[0011] Figure 3A A block diagram of a layout plan with fly paths and shortest paths in accordance with aspects and embodiments of the present invention is shown.

[0012] Figure 3B A block diagram of a layout plan with actual paths and fly paths in accordance with aspects and embodiments of the present invention is shown.

[0013] Figure 4 A process for clustering or merging edges in a NoC in accordance with various aspects and embodiments of the present invention is shown.

[0014] Figure 5A A block diagram of pre-clustering of edges in a NoC in accordance with various aspects and embodiments of the present invention is shown.

[0015] Figure 5B A block diagram of clustered edges in a NoC in accordance with various aspects and embodiments of the present invention is shown.

[0016] Figure 6 A layout plan including connection mapping is shown in accordance with various aspects and embodiments of the present application.

[0017] Figure 7 A layout plan including logical edges and switches is shown in accordance with various aspects and embodiments of the present application. Figure 6

[0018] Figure 8 A layout plan including segmented paths is shown in accordance with various aspects and embodiments of the present application. Figure 7

[0019] Figure 9 A layout plan including optimal paths and actual paths is shown in accordance with various aspects and embodiments of the present application. Figure 8 DETAILED DESCRIPTION

[0020] Various examples of the present technology illustrative of various aspects and embodiments of the present application are described below. In general, the examples can use the described aspects in any combination. All statements herein reciting principles, aspects, and embodiments of the present application, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

[0021] It is noted that, as used herein, the singular articles "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. The terms "one aspect," "an aspect," "certain aspects," "some aspects," "various aspects," or the like mean at least one aspect, feature, structure, or characteristic described in connection with any embodiment.

[0022] In this specification, the occurrence of the phrase "in one embodiment," "in at least one embodiment," "in an embodiment," "in certain embodiments," and similar language means that a particular aspect, feature, structure, or characteristic described in connection with any embodiment is included in at least one embodiment of the present application. The appearances of the phrase "in one embodiment," "in at least one embodiment," "in an embodiment," "in certain embodiments," and similar language in various places in the specification are not necessarily all referring to the same embodiment or to one or more particular embodiments. Furthermore, the described aspects and embodiments of the present application are merely illustrative and are not to be construed as limiting the scope or spirit of the present application as understood by one of ordinary skill in the art. Effective manufacture or use of the disclosed application is achieved in any embodiment that includes any novel aspect described herein. All statements herein reciting principles, aspects, and embodiments of the present application, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. It is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future.

[0023] ​​​As used herein, "source," "host," and "initiator" refer to intellectual property (IP) blocks, units, or modules. The terms "source," "host," and "initiator" are used interchangeably in the scope and embodiments of the present invention. As used herein, "sink," "destination," "slave," and "target" refer to IP blocks; these terms are used interchangeably in the scope and embodiments of the present invention. As used herein, "transaction" is a request transaction or a response transaction. Examples of request transactions include write requests and read requests.

[0024] Transactions are passed from a source to a destination through a route or communication path that traverses a network-on-chip (NoC) that includes various links and switches (a type of node). The terms "path" and "route" are used interchangeably herein. A path includes and is composed of any combination of nodes and edges (also referred to as links herein) along which data is transmitted from a source to a destination. According to various aspects and embodiments of the present invention, edge clustering minimizes long edges. Many long edges that traverse narrow corridors between two or more forbidden zones (blocking zones) cause cable jams. Minimizing long edges helps reduce congestion. According to various aspects and embodiments of the present invention, the length of an edge (link) is measured as the length of the routing cable between the endpoints of the edge.

[0025] As used herein, a node is defined as a point of distribution or communication endpoint that is capable of creating, receiving, and / or transmitting information on a communication path or channel. A node can refer to any of the following: a switch, a splitter, a merger, a buffer, and an adapter. As used herein, a splitter and a merger are switches; not all switches are splitters or mergers. As used herein and according to various aspects and embodiments of the present invention, the term "splitter" describes a switch that has a single ingress port and multiple egress ports. As used herein and according to various aspects and embodiments of the present invention, the term "merger" describes a switch that has a single egress port and multiple ingress ports.

[0026] Referring now to Figure 1A , a network-on-chip (NoC) 100 according to various aspects and embodiments of the present invention is shown. A NoC is a special type of network (or interconnect) used to handle communication between units of a system-on-chip (SoC). As described below, switches route communication flows between sources and destinations and perform arbitration. Adapters handle various conversions between data widths, clocks, and power domains. Buffers are used to insert pipeline elements to span long distances, or to store packets to handle rate adaptation between fast senders and slow receivers, and vice versa. The number and precise functionality of each network element depends on the network-on-chip technology employed. NoC elements are implemented on-chip using digital logic as logical functions.

[0027] NoC 100 is one example of a network. According to various aspects and embodiments of the present application, a network comprises a set of nodes and a set of edges, each of which has a model and can be used at the core of a topology synthesis process to perform and implement transformations on the network and converge to an optimal solution that fits the specified requirements. NoC 100 comprises nodes and endpoints and uses assembled basic network functions such as: network interface units (NIUs) 102, 104, 106, 108, 110, 112, 130, 132, and 134; nodes / switches 114, 116, 118, 120, and 122; buffers such as buffer 124; and adapters such as adapter 126. The basic functions of the NoC (represented by the components that implement them) communicate with each other using an internal NoC transport protocol based on packetized transport. The NIUs convert the protocol used by the attached SoC units (IP bloc) to the transport protocol used internally by the NoC. The NoC basic network functions communicate with each other using an internal transport protocol specific to NoC 100, typically based on packetized transport. The NIUs convert the protocol used by the attached System on Chip (SoC) units (not shown) to the transport protocol used internally by NoC 100. The switches route the communication flow between sources and destinations. The buffers 124 are used to insert pipeline elements to span long distances, or to store packets to handle rate adaptation between fast senders and slow receivers, or vice versa. The adapters 126 handle various conversions between data width, clock, and power domains.

[0028] Reference is now made to Figure 1B NoC 150 is shown in a floorplan with various elements such as NIUs, switches, and blocking regions. NoC 150 comprises various connecting elements through various switches. According to one aspect of the present application, a set of constraints is used as input to a tool, which is discussed in more detail below. According to some aspects of the present application, the tool performs a set of sub-steps and produces a resulting NoC, such as NoC 150, and a description of its configured elements and the location of each element on the floorplan (topology synthesis). The generated description is used to actually implement the NoC hardware, using the generated physical information to guide the back-end implementation flow.

[0029] Reference is now made to Figure 2This invention discloses a process for determining a NoC quality metric (quantitative network quality metric) according to various aspects and embodiments of the invention. In step 210, a network description and constraints for the network (e.g., NoC) are loaded into memory. The NoC description can be loaded from any source, such as a disk, or transmitted from a remote location. The format in which the data is encoded can be any format, and the scope of the invention is not limited thereto. In step 212, the process selects a source and destination pair (R, S). In step 214, routing information between (R, S) is retrieved for analysis. The routing information includes a sequence of switches traversed by the route. In step 216, the shortest path (or cable length) of the optimal path is determined or calculated. The length of the shortest path for the pair (R, S) is determined as L0. In step 218, the actual path or cable length for the pair (R, S) is calculated when traveling from the source to the destination or destination via the NoC. This is determined by summing all consecutive paths along the route between consecutive nodes traversed. The total actual cable length or path length is determined and designated as L1. (The last sentence appears to be incomplete and may be a fragment from a different context.) Figure 3A and Figure 3B This was discussed in more detail.

[0030] Therefore, for each source (connected to the example network, NoC) communicating with the destination, a minimum distance (shortest path) is calculated. According to one aspect of the invention, the minimum distance algorithm for determining the distance from the source to the destination considers congested areas where logical and cable layout planning is not feasible. The minimum distance algorithm can use any well-known routing algorithm such as Djikstra, A*, etc., and the scope of the invention is not limited thereto. Once a minimum distance is determined, it is used as a reference.

[0031] According to some aspects and embodiments of the invention, L0 and L1 are stored in memory. In step 220, the difference between the actual path (L1) and the ideal path (L0) is determined to generate a deviation in the routing of the pair (R, S). The deviation is stored in memory and mapped for the pair (R, S). In step 230, the process determines whether all possible pairs (R, S) have been processed. If not, in step 232, another pair (R1, S1) is selected, and processing returns to step 214. This is repeated until all pairs (R1, S1) have been processed. n S n In other words, the path length from the source to the destination is calculated (via NoC). Additionally, the minimum distance between the same pair of (source, destination) points is calculated. The actual path length is compared to the minimum distance to determine the difference between the pair of (source, destination) points. This difference represents the difference path metric. This is performed on all pairs of (source, destination) and produces a set of differences. Once all pairs have been processed, as determined in step 230, then in step 240, the process uses all pairs (R...n , S n ) to generate a histogram representation of the computed differences and to compute the average difference value.

[0032] According to one aspect of the present application, the set of differences is used to generate a report using the average difference. Further, according to various aspects and embodiments of the present application, the set of differences can be reported as a list of differences shown as a ranked list or a histogram. The results of the differences are also used to generate an average value of the differences. This results in a type of quality metric.

[0033] The quality metric is a representation of the average difference between the theoretical minimum distance on the layout plan and the actual distance of a signal traveling through the NoC or network from a source to a destination. The quality metric is an indication of how good (or bad) the latency is through the NoC. The latency through the NoC measures the time required for a message to traverse or cross the NoC from a source to a destination. The latency is impacting the performance of components connected to the NoC, such as CPUs. Thus, the smaller the difference between the actual distance and the minimum distance, the better the performance of the NoC; in other words, the lower the latency.

[0034] Reference is now made to Figure 3A and Figure 3B According to one aspect and embodiment of the present application, the layout plan 300 of the network is shown to have a blocked region 310, a source or initiator 320 (R) that communicates with a destination or target 330 (S) through a route that traverses switches 322 in the network or NoC. This route is represented by a flight path 340 (dashed line). The flight path 340 is a visual representation of the connection between the initiator 320 and the target 300. The flight path 340 is represented by a minimum distance path 350. The minimum distance path 350 is compared to an actual path 352 and determined by a minimum distance finding algorithm (A* in this non-limiting example). According to some aspects and embodiments of the present application, this algorithm is a combination of such minimum distance algorithms and other heuristics, such as heuristics used to create the routing graph.

[0035] According to one aspect and embodiment of the present application, the actual path 352 includes four segments of lengths lo, li, l2, and l3 connected via switches 322. The actual total path length is LI, which is determined as follows:

[0036] LI = lo + li + l2, + l3

[0037] The segments of lengths lo, li, l2, and l3 are Manhattan paths, which route using vertical and horizontal segments. The difference between the length LI (actual path 352) and the minimum distance path Lo (minimum or optimal path 350) is the difference between the aggregate length of the segments of the actual path and the aggregate length of the optimal network path. This process uses the path length calculations in Figure 2 the process of

[0038] Reference is now made to Figure 4 , which shows a process for determining another NoC quality metric or quantitative network quality metric, in accordance with various aspects and embodiments of the present application. At step 410, segments, also referred to as edges, of a NoC or network are stored in memory along with NoC constraints. The format in which the NoC description is encoded does not limit the scope of the present application. As shown herein, at step 410, a set of segments (for a pair of source, sink (R, S)) is stored in memory. The stored set of segments is examined to cluster links or edges.

[0039] In accordance with one aspect and embodiment of the present application, at step 420, merging of edges (segments) or clustering of edges is performed. The purpose of edge clustering is to minimize resources and improve performance goals by appropriate algorithms and techniques. In accordance with some aspects of the present application, edge clustering is applied in conjunction and in synergy with node clustering. Edge clustering and node clustering can be used in combination by mixing, simultaneous application, or sequential application. The advantage and goal is to expand the spectrum of topology synthesis, spanning a larger solution space for the network.

[0040] The clustering process takes advantage of the proximity and direction of the flows of transmitted packets: when two segments (edges) are close enough and carry packets in the same direction, one is deleted, leaving the other. If two segments SI and S2 are close in the same direction and differ greatly in length, the longest segment (e.g., S2) is split into two or three sub-segments (e.g., S2.1, S2.2, S2.3) so that one of the sub-segments (e.g., S2.2) has the same length as the other segment (e.g., SI) to be attempted to merge. Clustering is then attempted. The clustering is based on assimilation schemes (merging) between horizontal or vertical edge sets and transmit packets in the same direction, e.g., from left to right, from right to left, from top to bottom, or from bottom to top.

[0041] In accordance with one embodiment and aspect of the present application, the clustering algorithm takes into account other requirements, such as performance or avoiding deadlocks, to decide when to assimilate two segments and cluster the segments. The clustering algorithm attempts to pair as many segments as possible. The clustering mechanism continues until there are no more segments that are close to another segment.

[0042] At step 430, the difference between the actual path length and the consolidated path length is computed. The aggregate length of the set of segments left after clustering represents the "minimal" network in terms of wires; thus, it gives a notion of the number of wires used by the NoC compared to the theoretical minimum. More wires result in more logic gates and more area required. Thus, the closer the minimal network uses to the theoretical minimum, the better the NoC.

[0043] At step 440, according to an aspect and embodiment of the present application, the average difference (difference between the actual network aggregate length and the theoretical minimum network aggregate length) is computed and presented. This information is used to generate a report based on the average difference. Further, according to various aspects and embodiments of the present application, this set of differences can be reported as a list of differences shown as a ranked list or a histogram. The result is an average value representing the difference in quality metric based on the length of the wires derived from the consolidated edges.

[0044] Reference is now made to Figure 5A and Figure 5B , which show a block diagram of a layout plan 500 for implementing the process of determining a quality metric according to various aspects and embodiments of the present application. The layout plan 500 includes a blocked area 510. Two sources 520 communicate with two targets 530 using edges 550 and 540. The process consolidates edge 540 to produce edge 542. The process consolidates edge 550 to produce edge 552.

[0045] Reference is now made to Figures 6 to 9 , which shows the process for consolidating or folding edges in various stages according to various aspects and embodiments of the present application. The initiator communicates with multiple targets, as shown. The flight paths are shown in dashed lines, and are not labeled for clarity. Specifically, an example of a routing or communication path between one initiator (INIT1) and a target (TARG3) is shown, and the connection map is shown in Figure 6 , using only the flight paths or routes. Figure 7 The logical edges of the network are shown (shown as flight paths with dashed lines) as well as the switches connecting the edges. As shown, INIT1 uses a direct flight path as one option to communicate with TARG3. Also shown, INIT1 uses a logical route to communicate with TARG3, which goes through three segments connected by two switches. Consider any number of paths and switches for connecting INIT1 and TARG3, all of which are within the scope of various aspects and embodiments of the present application. Figure 8 Detailed segments are shown representing possible edges connecting INIT1 and TARG3. Figure 9The optimal path P13 connecting INIT1 and TARG3 is shown. P13 represents the length of the cable of the optimal conflict-free path directly connecting INIT1 and TARG3. In addition to the optimal conflict-free path, there is also a route p1-p2-p3 from INIT1 to TARG3 that goes through switches swl and SW2. This route is the actual route through the NoC. The sum of the lengths of the cables of route p1-p2-p3 is the sum of the lengths of the cables of all conflict-free paths along the route from INIT1 to swl to sw2 to TARG3. The route implements the connection. According to aspects of the invention, a route is an ordered list of network elements, one for each pair (initiator, target), one for each pair (target, initiator). The route indicates how and through which elements the traffic between the two pairs will flow.

[0046] Thus, the total bus cable length from INIT1 to TARG3 is represented as follows:

[0047] WL(INIT1, TARG3) = WL(p1) + WL(p2) + WL(p3)

[0048] The total optimal WL from INIT1 to TARG3 is represented as follows:

[0049] Optimal WL = WL(P13)

[0050] According to various aspects and embodiments of the invention, the same process is applied to all initiator-target pairs represented by connections in the connection map to determine the quality metric.

[0051] Certain methods according to various aspects of the invention can be performed by instructions stored on a non-transitory computer readable medium. The non-transitory computer readable medium stores code including instructions that, if executed by one or more processors, will cause a system or computer to perform the steps of the methods described herein. Non-transitory computer readable media include: rotating magnetic disks, rotating optical disks, flash random access memory (RAM) chips, and other mechanical moving or solid state storage media. Any type of computer readable media suitable for storing code including instructions according to various examples is suitable for use with the present invention.

[0052] Certain examples have been described herein and it will be noted that different combinations of different components from different examples are possible. In order to better explain the examples, salient features are presented; however, it will be apparent that certain features can be added, modified, and / or omitted without modifying functional aspects of the described examples.

[0053] Various examples are methods of the acts of using any machine or combination of machines. The method examples are complete with respect to the steps presented in the world, anywhere. For example, according to various aspects and embodiments of the present disclosure, an IP element or unit includes a processor (e.g., a CPU or GPU), a random access memory (RAM - e.g., off-chip dynamic RAM or DRAM), a network interface for wired or wireless connectivity, such as Ethernet, WiFi, 3G, 4G Long Term Evolution (LTE), 5G, and other wireless interface standards radios. The IP can also include various I / O interface devices as needed for different peripherals, such as touch screen sensors, geo-positioning receivers, microphones, speakers, Bluetooth peripherals, and USB devices such as keyboards and mice, etc. By executing instructions stored in the RAM device, the processor performs the steps of the methods as described herein.

[0054] Some examples are one or more non-transitory computer-readable media arranged to store such instructions for the methods described herein. Any machine holding a non-transitory computer-readable medium including any necessary code can implement an example. Some examples can be implemented as physical devices, such as semiconductor chips; hardware description language representations of the logic or functional behavior of such devices; and one or more non-transitory computer-readable media arranged to store such hardware description language representations. Descriptions of principles, aspects, and embodiments recited herein include structural and functional equivalents. Elements described herein as being coupled or in communication with each other can be directly coupled or in communication with each other via one or more intervening elements.

[0055] Those skilled in the art will recognize many modifications and variations. Such modifications and variations are intended to be within the scope of the described features. Descriptions of principles, aspects and embodiments recited herein include structural and functional equivalents. Elements described herein as being “coupled” or “communicably coupled” with each other can be directly coupled or communicably coupled with each other using one or more intervening elements. Embodiments described herein as “in communication” or “in communication with” another device, module, or element include any form of communication or link, and include an effective relationship. For example, a communication link can be established using a wired connection, a wireless protocol, a near field protocol, or RFID.

[0056] Whenever a term is used in the detailed description and claims, such term is intended to be inclusive of the meaning of the term “includes” or “comprising.”

[0057] Accordingly, it is not intended that the scope of the application be limited to the examples shown and described herein. Rather, the scope and spirit of the application is embodied by the appended claims.

Claims

1. A method for calculating a quantitative network quality metric using at least one bus cable length quality metric, the method comprising: receiving, at a tool, network information for a network, the network connecting a plurality of initiators and a plurality of targets using a plurality of routes, wherein the network is a network-on-chip (NoC) and includes a plurality of edges such that each initiator-target pair is connected by one or more edges of the plurality of edges along a route; determining an actual path length for each initiator-target pair based on the edges in a route that connects the initiator of each of the initiator-target pairs to the target; merging the plurality of edges, each edge of the plurality of edges being part of a different route for a different initiator-target pair, the plurality of edges being clustered based on proximity and direction to generate a plurality of merged edges, the plurality of merged edges making up a plurality of merged routes; determining a difference between each of the plurality of routes and a corresponding merged route of the plurality of merged routes; and generating a visual representation of the difference, wherein the visual representation is at least one bus cable length quality metric of a design of the network.

2. The method of claim 1, wherein the network information includes segment information.

3. The method of claim 1, wherein the step of merging includes conditionally clustering any edge based on performance requirements.

4. The method of claim 1, wherein the step of merging comprises: If the resulting merged route produces a deadlock, avoid clustering.

5. The method of claim 1, wherein a bus cable length of all remaining edges of the plurality of merged edges is a minimum network bus cable length.

6. A system comprising a non-transitory computer readable medium for storing code such that when executed by one or more processors to calculate a quantitative network quality metric including at least one bus cable length quality metric, the system is caused to: receive network information for a network, the network connecting a plurality of initiators and a plurality of targets using a plurality of routes, wherein the network is a network-on-chip (NoC) and includes a plurality of edges such that each initiator-target pair is connected by one or more edges of the plurality of edges along a route; determine an actual path length for each initiator-target pair based on the edges in a route that connects the initiator of each of the initiator-target pairs to the target; merge the plurality of edges, each edge of the plurality of edges being part of a different route for a different initiator-target pair, the plurality of edges being merged based on proximity and direction to generate a plurality of merged edges, the plurality of merged edges making up a plurality of merged routes; determine a difference between each of the plurality of routes and a corresponding merged route of the plurality of merged routes; and generate a visual representation of the difference, wherein the visual representation is at least one bus cable length quality metric of a design of the network.

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