A Modeling Method for Integrated Circuit IC Based on Graph Theory

Abstract

The present invention relates to the technical field of integrated circuit modeling, and in particular to an integrated circuit IC modeling method based on graph theory, ICL file data preprocessing: by reading the ICL file and using predefined regular expressions to match and extract data elements of different levels and types, these data elements are stored in a structured dictionary ICL Database according to type and hierarchical relationship, and graph theory modeling: using a directed graph model to express the structure and function of the integrated circuit, creating nodes and edges to reflect the components in the circuit and their connection relationship. Automatically identifying the connection relationship in the circuit helps to reduce design errors and improve the reliability of the design; through the graph search algorithm, the shortest or optimal path from input to output or between specific components is automatically found, thereby optimizing the test coverage and efficiency; the scalability of the graph model makes it easy to add new components or modify the existing structure during the design process without destroying the integrity of the overall design.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit modeling, and in particular to an integrated circuit IC modeling method based on graph theory. Background Art

[0002] In the field of integrated circuit (IC) design and testing, as the integration level increases and the design complexity increases, the description and analysis methods of circuits have also evolved. ICL (Instrument Connectivity Language) is a format for describing modules and their connection relationships in integrated circuits. Traditionally, using ICL files to generate circuit test and verification solutions requires a lot of manual analysis and design modifications, which becomes particularly cumbersome and error-prone when dealing with large-scale or complex IC designs.

[0003] Existing technologies usually rely on manual parsing of ICL files and manual writing or updating of PDL. Its disadvantages include the following:

[0004] 1. Inefficiency of manual processing: The manual process lacks automation support, resulting in inefficiency in updating PDL when the hardware architecture changes.

[0005] 2. High error rate: Due to reliance on manual operations, the possibility of errors increases, especially when dealing with complex IC designs. These errors may lead to inaccurate test results and add additional debugging and verification workload.

[0006] 3. Lack of flexibility and scalability: As the complexity of IC design increases, existing manual methods are difficult to adapt to rapidly changing design requirements. The lack of effective tools to automatically adapt to design changes limits the flexibility and scalability of the test process.

[0007] 4. Insufficient data utilization: Existing technologies fail to fully utilize detailed information in ICL files, such as the connection relationship and hierarchical structure between modules, which limits the depth and comprehensiveness of test design. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, the present invention provides an integrated circuit IC modeling method based on graph theory, which can effectively solve the problems of inefficiency, high error rate, lack of flexibility and scalability, and insufficient data utilization of manual processing in the prior art.

[0009] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0010] The present invention provides an integrated circuit IC modeling method based on graph theory, characterized in that it comprises the following steps:

[0011] S100: ICL file data preprocessing: by reading the ICL file and using predefined regular expressions to match and extract data elements of different levels and types, these data elements are stored in a structured dictionary ICL Database according to type and level relationship;

[0012] S200: Graph Modeling: Based on the ICL Database, a directed graph model is used to express the structure and function of integrated circuits, and nodes and edges are created to reflect the components in the circuit and their connection relationships.

[0013] Furthermore, step S100 also includes a construction method for converting the complex hierarchical data in the ICL file into a dictionary format; the construction method includes the following steps:

[0014] S111: Read text data in the ICL file;

[0015] S112: Use a set of predefined regular expression patterns to match data elements of different levels and types;

[0016] S113: storing the matched data in a nested dictionary structure according to element type and hierarchical relationship;

[0017] S114: Obtain the pre-processed dictionary ICL Database.

[0018] Furthermore, step S200 also includes: S210: performing data modeling on the ICL based on the ICL Database, and expressing the structure and function of the integrated circuit through a directed graph model.

[0019] Furthermore, step S210 also includes:

[0020] S211: Initialize the graph model and create an empty graph G for adding nodes and edges later;

[0021] S212: Start generating nodes in the graph, define each module through the ICL Database, and create corresponding nodes in the graph G according to its type, width and other attributes;

[0022] S213: Generate edges in the graph. According to the description of the connection relationship in the ICL Database, add edges to the nodes in the graph. The attributes of the edges include the connection type and the connection bit width for the connection between ports.

[0023] S214: Processing special nodes. For logic signals LogicSignal and aliases Alias ​​elements that need special processing, creating additional nodes and edges in the graph according to their logic expressions or alias relationships, including parsing operators and operands in the logic expressions, and mapping relationships between targets and sources of aliases;

[0024] S215: For each submodule instance described in the ICL Database, recursively call Algorithm A to convert the complex description of the integrated circuit into a clear directed graph theory model.

[0025] Furthermore, each module includes a port, a register and a multiplexer.

[0026] Furthermore, the algorithm A comprises the following steps:

[0027] Pass in the submodule name and instantiation name; go deeper layer by layer until all modules and submodules are processed; build a complete graph model from the top-level module to the bottom-level module.

[0028] Furthermore, the ICL file includes converting the ICL file into a graph format by using a component SIB and a component TDR, and performing PDL retargeting.

[0029] Furthermore, there are multiple bit connections in the port connection, and an edge is created according to the specific connection situation of each bit, and the specific bit width and direction of the connection are recorded.

[0030] Compared with the known prior art, the technical solution provided by the present invention has the following beneficial effects:

[0031] Automatically identifying the connection relationships in the circuit, including direct and indirect dependencies, helps reduce design errors and improve design reliability; through graph search algorithms, automatically finding the shortest or optimal path from input to output or between specific components, thereby optimizing test coverage and efficiency; the scalability of the graph model makes it easy to add new components or modify existing structures during the design process without destroying the integrity of the overall design. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 It is a schematic diagram of a directed graph in the present invention;

[0034] Figure 2 Generate a flow chart for ICL2Graph;

[0035] Figure 3 Flowchart for modeling ICL using graph theory;

[0036] Figure 4 The following is a schematic diagram of the example test circuit.

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0038] The present invention will be further described below in conjunction with the embodiments.

[0039] Embodiment: An integrated circuit IC modeling method based on graph theory, S100: ICL file data preprocessing: reading the ICL file and using predefined regular expressions to match and extract data elements of different levels and types, and storing these data elements in a structured dictionary ICL Database according to type and level relationship;

[0040] S200: Graph Modeling: Based on the ICL Database, a directed graph model is used to express the structure and function of integrated circuits, and nodes and edges are created to reflect the components in the circuit and their connection relationships.

[0041] Step S100 also includes a construction method for converting the complex hierarchical data in the ICL file into a dictionary format; the construction method includes the following steps:

[0042] S111: Read text data in the ICL file; S112: Use a set of predefined regular expression patterns to match data elements of different levels and types; S113: Store the matched data in a nested dictionary structure according to element type and hierarchical relationship; S114: Obtain the preprocessed dictionary ICL Database.

[0043] Step S200 also includes: S210: performing data modeling on the ICL based on the ICL Database, and expressing the structure and function of the integrated circuit through a directed graph model.

[0044] Step S210 also includes:

[0045] S211: Initialize the graph model and create an empty graph G for adding nodes and edges later;

[0046] S212: Start generating nodes in the graph, define each module through the ICL Database, and create corresponding nodes in the graph G according to its type, width and other attributes;

[0047] S213: Generate edges in the graph. According to the description of the connection relationship in the ICL Database, add edges to the nodes in the graph. The attributes of the edges include the connection type and the connection bit width for the connection between ports.

[0048] S214: Processing special nodes. For logic signals LogicSignal and aliases Alias ​​elements that need special processing, creating additional nodes and edges in the graph according to their logic expressions or alias relationships, including parsing operators and operands in the logic expressions, and mapping relationships between targets and sources of aliases;

[0049] S215: for each submodule instance described in the ICL Database, recursively call Algorithm A to convert the complex description of the integrated circuit into a clear directed graph theory model;

[0050] The algorithm A includes the following steps: inputting the submodule name and instantiation name; going deeper layer by layer until all modules and submodules are processed; and constructing a complete graph model from the top module to the bottom module.

[0051] The present invention relates to an integrated circuit (IC) modeling method based on graph theory, which is used for automated IC test process design. First, by preprocessing the ICL file, data is extracted using regular expressions and stored as an ICL Database. Then, a directed graph model is constructed using this database to represent the structure and function of the IC, including the creation of nodes and the addition of edges. This method automates the conversion from ICL data to graph models, providing a technical basis for PDL retargeting technology.

[0052] Refer to the attached Figure 3 As shown in the figure, the LCL data processing method is shown. Specifically, the data processing of the LCL file is finally realized by utilizing the presence of some dimensions such as port or ScanRegister or ScanMux or Instance in the LCL file, so that it can finally form a clear dictionary format for subsequent use.

[0053] 1. First, preprocess the data in the ICL file so that it can be accessed and managed more conveniently. We define a data structure to effectively convert the complex hierarchical data in the ICL file into a clear and structured dictionary format. The specific implementation includes the following steps:

[0054] 1) Read text data in ICL file;

[0055] 2) Use a set of predefined regular expression patterns to match data elements of different levels and types;

[0056] 3) Store the matched data in a nested dictionary structure according to element type and hierarchical relationship;

[0057] 4) Finally, we get the dictionary after preprocessing, which we will call ICL Database in the following text. It provides a more convenient data source for our later ICL modeling.

[0058] 2. Secondly, we modeled the ICL data based on the ICL Database. The modeling method used here is the directed graph model in graph theory to express the structure and function of the integrated circuit. A directed graph is a basic concept in graph theory, in which the edges have directions, indicating that they point from one node (or vertex) to another node. This model is particularly suitable for representing the signal flow and control process in electronic circuits, because in circuit design, signals and control instructions are usually directional, flowing from source components to target components. The modeling process includes the following key steps:

[0059] 1) First, we need to initialize the graph model, that is, create an empty graph, which we call G, for adding nodes and edges later;

[0060] 2) Next, we start to generate nodes in the graph. We traverse each module defined in the ICL Database. For each port, register, multiplexer and other elements in each module, we create corresponding nodes in the graph G according to their type, width and other attributes.

[0061] 3) Again, generate the edges in the graph. Add edges to the nodes in the graph according to the description of the connection relationship in the ICL Database. The attributes of the edge include the connection type (such as data transmission, scan control, etc.) and the connection bit width. It should be noted that for the connection between ports, if there are multi-bit connections, an edge will be created according to the specific connection status of each bit, and the specific bit width and direction of the connection will be recorded;

[0062] 4) Then, special nodes are processed. For elements that require special processing, such as logic signals and aliases, additional nodes and edges are created in the graph according to their logical expressions or alias relationships. Specific operations include parsing the operators and operands in the logical expressions, as well as the mapping relationship between the target and source of the alias, etc.

[0063] 5) Finally, we start processing the recursive module. For each submodule instance described in the ICL Database, we recursively call Algorithm A. The steps of Algorithm A include:

[0064] a) Pass in the submodule name and instantiation name;

[0065] b) Go deeper layer by layer until all modules and submodules have been processed;

[0066] c) This step ensures the construction of a complete graph model from the top-level module to the bottom-level module.

[0067] Through the above steps, the present invention can convert the complex description of the integrated circuit into a clear directed graph theory model.

[0068] like Figure 4 The circuit shown in the figure above is the structure of the circuit described by the ICL file in our example. As an implementation method, the component SIB and the component TDR can use a component SIB_1 and a component TDR_1, but it is not limited to the current component combination method. We will convert this structure into a graph form and perform PDL retargeting.

[0069] First, we will preprocess the data in the ICL file, and then we will model the ICL Directed Graph based on the ICL Database, as shown in the attached figure. In the figure, we will show the data flow of the above circuit: ijtag_si → TDR_1 → SIB_1 → ijtag_so.

[0070] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

Claims

1. A graph-theory-based integrated circuit IC modeling method, characterized in that: The following steps are involved: S100: ICL file data preprocessing: by reading the ICL file and using predefined regular expressions to match and extract data elements of different levels and types, these data elements are stored in a structured dictionary ICL Database according to type and level relationship; S200: Graph Modeling: Based on the ICL Database, use directed graph models to express the structure and function of integrated circuits, and create nodes and edges to reflect the components in the circuit and their connection relationships; Step S200 also includes: S210: Based on the ICL Database, ICL data modeling is performed to express the structure and function of the integrated circuit through a directed graph model; Step S210 also includes: S211: Initialize the graph model and create an empty graph G for adding nodes and edges later; S212: Start generating nodes in the graph, define each module through the ICL Database, and create corresponding nodes in the graph G according to its type, width and other attributes; S213: Generate edges in the graph. According to the description of the connection relationship in the ICL Database, add edges to the nodes in the graph. The attributes of the edges include the connection type and the connection bit width for the connection between ports. S214: Processing special nodes. For logic signals LogicSignal and aliases Alias ​​elements that need special processing, creating additional nodes and edges in the graph according to their logic expressions or alias relationships, including parsing operators and operands in the logic expressions, and mapping relationships between targets and sources of aliases; S215: For each submodule instance described in the I CL Database, recursively call Algorithm A to convert the complex description of the integrated circuit into a clear directed graph theory model.

2. The integrated circuit IC modeling method based on graph theory according to claim 1, characterized in that: Step S100 also includes a construction method for converting the complex hierarchical data in the ICL file into a dictionary format; the construction method includes the following steps: S111: Read text data in the I CL file; S112: Use a set of predefined regular expression patterns to match data elements of different levels and types; S113: storing the matched data in a nested dictionary structure according to element type and hierarchical relationship; S114: Obtain the pre-processed dictionary I CL Database.

3. The integrated circuit IC modeling method based on graph theory according to claim 1, characterized in that: Each of the modules includes a port, a register and a multiplexer.

4. The integrated circuit IC modeling method based on graph theory according to claim 3, characterized in that: The algorithm A comprises the following steps: Pass in the submodule name and instantiation name; Go deeper layer by layer until all modules and submodules have been processed; Construction of a complete graph model from the top-level module to the bottom-level module.

5. The integrated circuit IC modeling method based on graph theory according to claim 4, characterized in that: The ICL file includes converting the ICL file into a graph format using components SIB and TDR, and performing PDL retargeting.

6. The integrated circuit IC modeling method based on graph theory according to claim 5, characterized in that: There are multiple bit connections in the port connection, and an edge is created according to the specific connection situation of each bit, and the specific bit width and direction of the connection are recorded.

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