A programming method and device for a compute-in-memory chip

Abstract

The application discloses a programming method and device for a memory-computing integrated chip. The method comprises the following steps: step 1, measuring a characteristic curve of a device weight value with programming time by performing full-range programming on a constituent device of the memory-computing integrated chip; step 2, inputting a matrix to be programmed, dividing the constituent device of the memory-computing integrated chip into multiple groups, and performing multiple rounds of parallel programming on each group: in each round of programming, first, calculating a difference value between a to-be-programmed value and a current weight value of the device according to the weight value read out during the last round of verification, and obtaining a corresponding drop rate of the difference value through a programming characteristic lookup table, calculating a programming time of the current round based on the difference value and the drop rate, then starting programming, and verifying the current weight value of the device after the programming is completed, and if there are still devices with incomplete programming, starting the next round of programming. The application can greatly improve the programming speed of the memory-computing integrated chip.

Description

TECHNICAL FIELD

[0001] The present application relates to a fast programming method for the programming characteristics of a memory-compute integrated chip and a device thereof, and belongs to the field of memory-compute integrated architecture chip programming methods. BACKGROUND

[0002] Neural networks have become a core technology requirement for processing image recognition, classification, optimization and other tasks. Neural network training and verification are performed on general-purpose central processors or image processors, and the core matrix multiplication and addition rely on the traditional von Neumann architecture storage and computing separation method. Due to the limited access speed and maximum energy efficiency of the storage unit, bottlenecks in computing speed and chip power consumption are encountered when the data volume is large.

[0003] Based on this, a memory-compute integrated architecture that closely couples computation and storage is proposed, which can complete large data matrix multiplication and accumulation operations at very low power consumption. However, a common problem with current memory-compute integrated architecture chips is slow programming speed. According to actual circuit tests, the programming conductance value of the memory-compute integrated device gradually decreases with external excitation, and the programming characteristics are nonlinear. In the early stage of programming with a high conductance value, the programming speed is fast, and the current drops significantly. However, in the later stage of programming with a small conductance value, the programming speed is much lower than in the early stage. Therefore, if a linear step programming method is used, the programming characteristics of the memory-compute integrated device cannot be fully utilized. On the contrary, by making certain judgments and calculations based on the initial value and target value of each programming, different programming times can be given in different programming stages, so that the target value can be reached faster and the full-chip programming of the memory-compute integrated chip can be completed.

[0004] In Chinese Patent Application CN117032562A, although the irregular curve of the weight value and the input duration is segmented and linearly approximated, the step size is still equal in each weight value interval during device programming, and true customizable programming time has not been achieved. SUMMARY

[0005] To solve the problems in the prior art, the present application proposes a fast programming method for the programming characteristics of a memory-compute integrated chip and a device thereof, which can speed up the programming of the device.

[0006] The technical solution adopted by the present application is as follows:

[0007] A programming method for a memory-compute integrated chip, comprising the following steps:

[0008] Step 1: Perform full-range programming on the constituent devices of the memory-compute integrated chip to measure the characteristic curve of the device weight value with respect to the programming time, segment the characteristic curve according to regions with similar programming speeds, and obtain the drop rate of the weight value with respect to the programming time in different intervals;

[0009] Step 2, input the matrix to be programmed, divide the constituent devices of the storage-computing integrated chip into multiple groups, and perform multiple rounds of parallel programming on each group, i.e., program multiple devices at the same time: for each group of devices, in each round of programming, first calculate the difference between the value to be programmed and the current weight value of the device according to the weight value read out during the last round of verification, and obtain the corresponding drop rate of the difference value through a programming characteristic lookup table, calculate the programming time of the current round based on the difference value and the drop rate, then start programming, and after the programming is completed, verify the current weight value of the device, if there are still devices that have not completed programming, start the next round of programming.

[0010] Further, the step 1 is specifically: measure the discrete device weight values and perform curve fitting, divide the regions with similar programming speeds, i.e., similar curve drop rates, into an interval, and obtain multiple programming intervals.

[0011] Further, after obtaining the multiple programming intervals, the interval with a smaller weight value and a shorter length is merged into the previous interval to reduce the number of programming intervals.

[0012] Further, in the step 2, the programming time t prog is calculated by dividing the difference W diff between the value to be programmed and the current weight value of the device by the corresponding drop rate K, i.e., t prog =W diff / K.

[0013] Further, in the step 2, for each group of devices, multiple weight value differences are calculated in each round of programming, and the corresponding drop rates are obtained, after obtaining the programming times of all devices, the programming times are compared, and the shortest programming time is selected for the current round of programming.

[0014] Further, in the step 2, the programming time is calculated by taking the programming of a single device as a reference, i.e., after calculating the programming times of all devices in parallel programming for each group of devices and comparing the programming times, programming is started, when the devices corresponding to the shortest programming time are programmed and verified, the programming times of all devices in each group are calculated again, if the verification of the devices corresponding to the shortest programming time is correct, the programming time of the devices does not need to be calculated; repeat the foregoing process until all devices programmed in parallel are completed.

[0015] Further, in step 2, all devices in each group are used as a reference when calculating the programming time, that is, after the programming time of all devices programmed in parallel is calculated and compared, the programming is started, when the device corresponding to the shortest programming time is programmed, no verification is performed, the programming signal of the device corresponding to the shortest programming time is directly turned off, the programming of the next stage of device corresponding to the second shortest programming time is continued, the programming time is the second shortest programming time minus the programming time of the last stage, the above process is repeated until all devices programmed in parallel complete the current round of programming, and then verification is performed.

[0016] The application also provides a programming device for the storage-computing integrated chip, which comprises a light input driving module, a light verification module, a programming time control module and a light input top layer control module.

[0017] Further, in the programming time control module, a register or a memory is used to store the characteristic curve of the device weight value with the programming time.

[0018] Further, the programming time control module also outputs a flag bit indicating the validity of the programming time to the light input driving module, and the light input driving module enters the programming state when the flag bit is detected.

[0019] The advantages of the application include that the programming characteristics of the storage-computing integrated device are used, fixed step programming is no longer used, but the programming time of each programming is dynamically adjusted according to the actual programming value, and the technology can be applied to the parallel programming of multiple devices. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 14 is a block diagram of the multi-functional area of ​​the computing unit in an embodiment of the present invention.

[0021] Figure 2 This is a structural diagram of the storage and computing integrated chip in an embodiment of the present invention.

[0022] Figure 3 This is a scatter plot of the programming current-time of the storage-computing integrated chip measured in accordance with an embodiment of the present invention.

[0023] Figure 4 Flowchart of the programming method of the present invention.

[0024] Figure 5 4 is a flow chart of a parallel programming method in an embodiment of the present invention.

[0025] Figure 6 This is a block diagram of the circuit design for implementing the programming method of the present invention. DETAILED DESCRIPTION

[0026] The technical solution of the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] The structure of the optoelectronic storage and computing integrated unit device used in this embodiment is as shown in the attached figure. Figure 1 As shown in Figure 1, it is divided into three functional areas: the carrier control area, the coupling area, and the photogenerated carrier collection and readout area. The carrier control area is used to control and modulate the carriers in the photogenerated carrier collection area and the readout area; the collection area in the photogenerated carrier collection and readout area absorbs photons emitted by the light-emitting unit and collects the generated photogenerated carriers; the readout area in the carrier control area, the photogenerated carrier collection and readout area is connected to the electrical signal, and the readout area is used to output the carriers after being affected by the photogenerated carriers and the electrical signal; the coupling area connects the collection area and the readout area respectively.

[0028] The storage and computing integrated chip structure of this embodiment is shown in the attached Figure 2 As shown, the array consists of multiple integrated optoelectronic storage and computing devices. In the array, the word lines (WLs) connect to the gates of devices in each row, the bit lines (BLs) connect to the drains of devices in each column, and the source lines (SLs) connect to the sources of devices in each column. During programming, the WLs, BLs, and SLs of the corresponding integrated optoelectronic storage and computing device array are turned on. During verification, the WLs and SLs of the corresponding device remain unchanged, the BLs are turned off, and the result is read out at the SL end via an analog-to-digital converter (ADC). Adder is an adder.

[0029] By programming the storage and computing unit device in full range (i.e. programming from maximum value to minimum value), the characteristic curve of the device weight with programming time can be measured. By segmenting this nonlinear curve according to the area with similar programming speed, the rate of decrease of weight in different intervals with programming time can be obtained. This programming characteristic is used as a lookup table for subsequent chip programming. In this embodiment, the target matrix size is 512*256. The specific programming method is as follows: First, the attached matrix is ​​measured according to the full range programming of a single device. Figure 3 The device current (corresponding to the weight)-time scatter plot shown is fitted into a curve. The slopes of different segments of this curve (i.e., the weight drop rate) are used to divide the programming weights with similar slopes into the same interval. The number of programming intervals is different according to the actual programming characteristics of the device. The number of intervals can be determined based on empirical values ​​or the effect of the division. Preferably, a segmentation method with about 10 programming intervals can achieve high programming accuracy while reducing the hardware resource consumption of storing the programming characteristics. After division, a total of 12 intervals are obtained in this embodiment. Due to the error of the ADC itself, intervals with smaller weights and shorter lengths (such as intervals with continuous upper and lower limits and an interval length of 1) can be merged into the previous interval. Therefore, the programming intervals required in the actual application will be less than the above-mentioned number of divisions. In this embodiment, the 12 intervals are simplified to 9 based on the error of the ADC (i.e., the four intervals of the minimum programming value are merged into one, because the error of the ADC is not enough to achieve actual division under smaller weights). Registers or memories are used to store these programming values ​​and corresponding drop rates, and then programming begins.

[0030] The whole chip programming process is as follows Figure 4 , input the matrix to be programmed, and program the storage and computing integrated chip, which specifically includes three stages: calculation time, programming, and verification. For a group of devices, in each round of programming, first calculate the difference between the device's to-be-programmed value and the current weight based on the weight read out during the previous round of verification, and input the weight difference into the programming characteristic lookup table to obtain the corresponding weight decrease rate. Based on the first two, calculate the programming time of this round, and then enter the programming and verification stage. If there are still devices that have not been completed, start the next round of programming. When the weights of all devices in this group have been verified correctly, start programming the next group of devices, and repeat the above process, that is, loop the programming time calculation, device programming, and device verification process of the storage and computing integrated unit devices. Since the computing array has multiple ADCs, multiple unit devices can be programmed in parallel by row or column.

[0031] Example 1

[0032] In actual programming, select 8 unit devices as a group for parallel programming as a minimum loop, as shown in the attached Figure 5 ,The specific process of implementing the method is as follows.

[0033] After the current group of 8 devices is programmed in parallel, the programming can start after the input matrix is ready, which is divided into three main processes: device programming, readout verification and programming time calculation. Specifically, after starting the programming, the programming time of the devices that have not reached the target value is calculated, and the minimum time is taken for programming (in order to avoid over-programming of the devices), and after the programming is completed, the weights are read out, and if all 8 devices reach the target value, the programming is ended, otherwise, if some devices reach the target value, the programming time of these devices is set to the maximum value and the programming of these devices that have completed programming is ended, and the programming of other devices that have not completed is continued until all the devices have completed programming.

[0034] The programming time calculation of the embodiment is referred to a single device. In the first round of programming, a fixed step programming can be performed first (if it can be determined that the target value of the device is far from the initial weight), or no programming can be performed, and then the current weights W real of the 8 devices to be programmed are read out. When reading out, the WL and SL of the devices to be programmed are kept unchanged, the BL is closed, the current is accumulated from the SL, passes through the ADC, and is finally read out to the verification module, which compares whether the target value and the current weight are consistent, and gives information of correct or incorrect verification. The current weight W real will also enter the time calculation module, and the difference between the target value w goal and the current weight W diff is calculated to obtain the remaining programming difference W real of the 8 devices. real The current weight W prog of the device is taken as the address of the programming characteristic lookup table to find the corresponding drop rate K = RAM[W diff ], and the programming time is calculated by t prog_0 = W prog_1 / K, and RAM represents a memory module storing the lookup table. Since the drop rate is a known constant, the reciprocal of the drop rate of each programming interval is stored, and the method for calculating the programming time is to multiply the weight difference by the reciprocal of the drop rate, which avoids the use of non-2 power division operation. The multiplication operation can be directly performed by a multiplication operator, or a multi-cycle multiplier module can be called to complete the operation, the former is suitable for small multiplication operation and is not sensitive to chip area, and has low delay, and the latter is suitable for large multiplication operation and can save chip area, but has certain delay in calculation time.

[0035] The programming times t prog_0 , t prog_1 …t prog_7 of the 8 devices are compared with each other to obtain the minimum value, and after three rounds of comparison, the shortest programming time t prig_min of the 8 devices is obtained and is taken as the programming time of the current round. When the second round of programming starts, the WL, BL and SL corresponding to the column to be programmed are all turned on, and the programming is performed according to the above time t prog_minThe device programming is performed on the memory-computing integrated chip. The numerical comparison can be completed in a single clock cycle using combinational logic or in multiple cycles using grouped comparison, the former is suitable for parallel programming of a small number of devices, and the latter is more general and suitable for multiple device comparison, and the speed and area comparison are balanced. After the end of a round of programming time, the devices to be programmed need to be checked to verify the correctness of the programming value (i.e. the actual weight value of the current device), which is consistent with the above-mentioned checking operation. Then, the programming time calculation phase is repeated, and it is noted that at this time, some devices may have been programmed to the target value, so if the device programming is completed, the programming time of the device does not need to be calculated. According to the signal given by the checking module after reading the current weight value of the device and judging whether the programming is correct or incorrect, the programming time of the device that passes the check is directly set to the maximum value t max , which no longer affects the final comparison result. At the same time, the WL of the device that has been programmed is closed. Then the above process is repeated until all 8 devices are programmed.

[0036] Since the obtained programming characteristics are a lookup table, they can be stored in a register or a memory in the circuit, the former is suitable for a small number of segments, and the latter is used for storage of a large number of segments. When using a register to describe the lookup table, the required interval is determined according to the weight difference, and the drop rate is directly obtained for the next calculation; when using a memory to describe the lookup table, the memory depth needs to be set to the maximum weight W max of the memory-computing integrated device, the memory is initialized according to the characteristic curve of the device, and when used, the current weight W real of the device is used as the memory read address to obtain the drop rate K and perform the next calculation.

[0037] After calculating the programming time of all devices programmed in parallel and comparing, the embodiment starts programming, and after the single device corresponding to the shortest programming time is programmed and checked, the programming time of all devices is calculated again, and the above process is repeated until all parallel programming devices are programmed and checked. This programming method only uses the minimum value in each calculation of the programming time, and the other calculation results are updated by the new programming time in the next round, that is, the number of times of weight checking and programming time calculation of the parallel programming devices is required, and the advantage is that each round of programming can be checked to ensure the correctness of the device programming.

[0038] Embodiment 2

[0039] The above-mentioned parallel programming method of 8 devices can also be programmed in another way, and the programming time calculation is based on all devices programmed in parallel to reduce the number of calculations and checks. Similarly, after the input matrix is prepared, the current weight W real of the 8 devices to be programmed is read out and given to the checking module for judgment, and Wreal Also will enter the programming time calculation module. The calculation process is the same as the method of example 1, that is, first calculate the difference W real and W goal , and find the corresponding falling rate K, so as to calculate the programming time t diff of the 8 devices t prog_0 , t prog_1 …t prog_7 . Different from the method of example 1, not only these programming times are sorted, but also the specific size order of each value is recorded, such as using bubble sort method. After that, the programming time control module stores the value of t prog_i , and stores the size of the sorting number corresponding to each programming time. During programming, the programming time t prog_min with the smallest sorting number is first selected to start the first stage programming, and this programming time t prog_min is also stored. After completion, the light input driving module is not exited, that is, the verification and time calculation are not performed, but the WL of the device corresponding to the shortest programming time is directly turned off, considering that the first round of programming is completed. Then the programming time t′ prog_min with the second smallest sorting number is searched, because it has been programmed once, the new programming time is calculated by t′ prog_min -t prog_min , and the second stage programming is started, and the programming time t′ prog_min is also stored. After completion, the WL of the corresponding device is turned off, and the above process is repeated until the 8 devices in this round are programmed. The programming result of this round is verified, and the second round of programming is entered, the actual weight W real of the to-be-programmed device is re-read, and the programming time of the 8 devices is calculated, and the process is repeated until all are verified correctly, and the next group of 8 devices is programmed.

[0040] For other memory-computing integrated devices in the to-be-programmed matrix, the above parallel programming of 8 devices is used as the basis. Here, the programming is selected to be programmed row by row, that is, the rows to which the 8 devices belong are the same, and the columns to which the 8 devices belong are different. After programming the 8 devices, the to-be-programmed devices in the next 8 columns are jumped to, and when the memory-computing integrated devices in a whole row are programmed, the column counter is reset to zero, and the parallel programming of 8 devices is started again in the next row, and the above process is repeated until the last device in the last column of the last row is programmed, at which time the matrix programming is completed, and a programming completion signal is output.

[0041] After programming a single device, this embodiment does not perform verification. Instead, the strobe signal for the corresponding device is turned off, and programming continues with the next shortest programming time, which is the next shortest programming time minus the previous programming time. This process is repeated until all parallel programming devices have been programmed, at which point verification is performed. This method has the advantage that calculation time is only performed at the beginning of each parallel programming round, eliminating the need for repeated calculations and verification within the parallel programming process.

[0042] Example 3

[0043] The hardware device for device programming is as follows Figure 6 As shown, it includes an optical input driver module, an optical verification module, a programming time control module, and an optical input top-level control module. The optical input top-level control module is responsible for providing the matrix information to be programmed to the optical verification module and the programming time control module, providing the mode switching signal (programming or verification mode) to the optical input driver and optical verification modules, and receiving the optical input end signal from the optical input driver module and the comparison accuracy and error signals from the optical verification module. The programming time control module calculates the programming time based on the weights to be programmed, the current ADC readout weights, and the comparison accuracy and error signals from the optical verification module, and provides it to the optical input driver module. The optical input driver module receives the comparison accuracy and error signals from the optical verification module to switch its internal operating state and provides the current programming row and column information to the optical verification module. The optical verification module receives the row and column signals and the ADC readout weights to verify the weights of the corresponding devices and provides comparison accuracy and error signals to other modules. In addition, the WL, BL, and SL of the storage and computing integrated device are controlled by a multiplexer, which can select the corresponding output of the optical input driver module or the optical verification module based on the mode switching signal.

[0044] During the programming process, there are multiple intermediate states, such as circuit reset, and the interval state of different modes of the storage and computing integrated device. The calculation of programming time can be carried out in parallel with these non-programming and verification states, or exist as a separate state before programming. For the former method, the programming time control module does not need to provide a valid signal. It only needs to wait until the read weight value is valid and the verification result is valid before calculating the programming time. Since the calculation and comparison time is much shorter than the duration of the aforementioned non-programming and verification states, the situation where the programming time is not calculated when entering the programming state will not occur; for the latter method, the programming time control module needs to provide a flag bit to indicate that the programming time is valid. This flag bit follows the comparison output of the last calculation time. When the optical input driver module detects this flag bit, it enters the programming state. This method is more clear for the division and switching of states.

[0045] Example 4

[0046] The optimized programming method is verified and compared by simulation software Questasim. The results shown in the following table can be obtained. For different target weights, the acceleration ratio of the optimized programming can reach 2.70-31.62 times.

[0047] Table 1 result comparison table

[0048]

[0049]

[0050] The above describes only several specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A programming method for an in-memory computing chip, the in-memory computing chip used in the method is composed of an array of a plurality of in-memory computing unit devices arranged in rows and columns, the array includes gate levels WL connected to each row of devices, drain levels BL connected to each column of devices, and source levels SL connected to each column of devices; during programming, the gate levels WL, the drain levels BL, and the source levels SL of the array are turned on, during verification, the gate levels WL and the source levels SL remain unchanged, the drain levels BL are turned off, and the results are read out through an analog-to-digital converter at the source levels SL; characterized in that, The programming method comprises the following steps: Step 1, by programming the full range of the constituting device of the storage-computing integrated chip, the characteristic curve of the device weight value with the programming time is measured, the characteristic curve is segmented according to the region with similar programming speed, and the falling rate of the weight value in different intervals with the programming time is obtained; specifically, the discrete device weight value is measured and curve fitting is performed, the region with similar programming speed, i.e. the falling rate of the curve, is divided into an interval, and a plurality of programming intervals are obtained; then, the interval with smaller weight value and shorter length is merged into the previous interval to reduce the number of programming intervals; Step 2, input the matrix to be programmed, divide the constituent devices of the memory-computing integrated chip into multiple groups, and perform multiple rounds of parallel programming on each group, i.e., program multiple devices at the same time: for each group of devices, in each round of programming, first calculate the difference between the device to be programmed value and the current weight value according to the weight value read out during the last round of verification, and obtain the corresponding drop rate of the difference value through a programming characteristic lookup table, calculate the programming time of this round based on the difference value and the drop rate, then start programming, after the programming is completed, verify the current weight value of the device, if there are still devices that have not completed programming, start the next round of programming; the programming time t prog is calculated in the following manner: the difference W diff between the device to be programmed value and the current weight value is divided by the corresponding drop rate K, i.e., t prog = W diff / K.

2. The programming method for a compute-in-memory chip according to claim 1, wherein, In step 2, for each group of devices, the values of a plurality of weight value differences are calculated in each round of programming, and the corresponding falling rates are obtained; after the programming time of all devices is obtained, the sizes of a plurality of programming times are compared, and the shortest programming time is selected for this round of programming.

3. The programming method for a compute-in-memory chip according to claim 2, wherein, In step 2, the programming of a single device is used as a reference when calculating the programming time, i.e. after the programming time of all devices in parallel programming is calculated for each group of devices and the size comparison of the programming times is made, the programming is started; when the devices corresponding to the shortest programming time are programmed and verified, the programming time of all devices in each group is calculated again; if the verification of the devices corresponding to the shortest programming time is correct, the programming time of the devices does not need to be calculated. The foregoing process is repeated until all devices in parallel programming are programmed and verified.

4. The programming method for a compute-in-memory chip according to claim 2, wherein, In step 2, all devices in each group are used as a reference when calculating the programming time, i.e. after the programming time of all devices in parallel programming is calculated and the size comparison of the programming times is made, the programming is started; when the devices corresponding to the shortest programming time are programmed, no verification is made, the selection signal of the devices corresponding to the shortest programming time is directly turned off, the programming of the devices corresponding to the next shortest programming time is continued, the programming time is the next shortest programming time minus the programming time of the previous stage, and the foregoing process is repeated until all devices in parallel programming are programmed in this round, and then the verification is performed.

5. A programming device for an in-memory computing chip, configured to perform the programming method of claim 1, characterized in that, The programming method comprises the following steps: The light input top-level control module is used for transmitting the to-be-programmed matrix information to the light verification module and the programming time control module, transmitting the mode switching signal to the light input driving module and the light verification module, and receiving the light input end signal of the light input driving module and the comparison correct and error signals of the light verification module; The programming time control module is used for calculating the programming time according to the to-be-programmed device weight value, the current device read weight value and the comparison correct and error signals of the light verification module, and transmitting the programming time to the light input driving module; The light input driving module is used for receiving the comparison correct and error signals of the light verification module to switch the internal working state, and giving the current programming row and column information to the light verification module; The light verification module is used for verifying the weight value of the corresponding device according to the received row and column signals and the current device read weight value, and outputting the comparison correct and error signals.

6. The programming device for the compute-in-memory chip according to claim 5, wherein, In the programming time control module, the register or the memory is used to store the characteristic curve of the device weight value with the programming time.

7. The programming device for the compute-in-memory chip according to claim 5, wherein, The programming time control module also outputs a flag bit identifying the validity of the programming time to the optical input drive module, and the optical input drive module enters a programming state when the flag bit is detected.

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