Universal conversion device for converting LVDS (Low Voltage Differential Signaling) input signal into V-By-One output signal

Abstract

The utility model discloses a universal conversion device for converting an LVDS (Low Voltage Differential Signaling) input signal into a V-By-One output signal, which comprises an LVDS input interface, a master control conversion chip, a V-By-One output interface, an NS / JEIDA configuration, a partition selection configuration, a direct current-direct current circuit, a nonvolatile memory chip and an expansion power supply head, the main control conversion chip is electrically connected with the LVDS input interface and receives a 2-port LVDS signal, the main control conversion chip outputs an 8-Lane V-By-One signal, the V-By-One output interface is electrically connected with the main control conversion chip and receives the 8-Lane V-By-One signal, and the NS / JEIDA configuration is electrically connected to the main control conversion chip.

Description

TECHNICAL FIELD

[0001] The utility model relates to signal transmission field, concretely points to LVDS input signal conversion V-By-One output signal omnipotent conversion device. BACKGROUND

[0002] LVDS is the full name of Low Voltage Differential Signal, which is a low-voltage differential signal, a low-power, low-error rate, low-crosstalk and low-radiation differential signal technology. It can transmit serial data at a speed of up to 155Mbps. Because the voltage signal amplitude is low, and it is driven by a constant current source mode, it only produces very low noise and consumes very small power. In addition, since LVDS transmits data in a differential manner, it is not easily affected by common-mode noise.

[0003] V-By-One is a digital display solution standard interface, which is widely used in liquid crystal televisions at present. The early liquid crystal televisions transmit image signals by using LVDS interface. With the popularization of 4K liquid crystal televisions, LVDS signal cannot meet the transmission of 4K signal under the condition of the same differential pair. V-By-One adopts point-to-point (P2P) transmission data and clock data recovery (CDR) technology, so that the maximum transmission speed of each differential pair is 3.75Gbps, and fewer differential pairs are used to solve the transmission of 4K signal.

[0004] NS / JEIDA: 2K LVDS mainboard output has two standards in data format definition, one is NS standard defined by Video Electronics Standards Association, and the other is JEIDA standard. The difference between NS / JEIDA lies in different arrangement of input LVDS data, which is convenient for LVDS receiver to decode complete image data.

[0005] 1 partition / 2 partition: 4K liquid crystal screen input V-By-One interface also has two different data decoding standards, one is 1 partition interlaced data decoding, that is, the default one image packet is a standard line-by-line data packet, and the other is 2 partition left and right half data decoding, that is, the default one image packet is divided into left half screen data packet and right half screen data packet. In order to solve the matching problem of 2K mainboard and 4K display panel, adapter needs to be added between mainboard and panel. Incorrect adapter matching will cause display abnormality, such as displaying two identical left and right images, or displaying 1 / 4 enlarged display effect of a complete image.

[0006] 2-port LVDS input 8-lane V-By-One output universal adapter belongs to the technical field of liquid crystal display, and converts the 2-port LVDS signal output by the mainboard into an 8-lane V-By-One signal through the universal adapter and outputs the signal to a liquid crystal display screen. There are two common types of liquid crystal television mainboards on the market at present, one is a 2K mainboard with a 2-port LVDS 2K output interface definition, and the other is a 4K mainboard with an 8-lane V-By-One 4K output interface definition. The difference between the 2K mainboard and the 4K mainboard lies in different data processing rates and different output interface definitions, and the cost difference is large. At present, the input interface definition of the liquid crystal screen with a good display effect on the market is 4K V-By-One, and the 2K mainboard should be matched with the 4K panel in consideration of the low-cost scheme and inventory processing. A conversion device is added between the 2K mainboard and the 4K display panel to realize matching display. The existing conversion device on the market needs to obtain the data format standard of the 2K mainboard and the partition format of the 4K liquid crystal display screen, and manually sets the conversion signal function, and cannot be directly used without determining the mainboard format and the liquid crystal screen partition. The conversion device can automatically match and display the 2-port LVDS mainboard output and the 8-lane V-By-One input liquid crystal screen panel. Utility model content

[0007] The design mainly defines the output interface of the liquid crystal television or commercial display mainboard as a 2-port LVDS standard, the input interface of the liquid crystal screen display panel as an 8-lane V-By-One standard, and the universal device can solve the signal conversion function of the mainboard and the display panel, without the need to obtain the signal standard definition of the mainboard or the liquid crystal display screen, and can be directly converted and used.

[0008] In order to solve the above problems, the utility model adopts the technical scheme as follows: the utility model discloses a universal conversion device of LVDS input signal into V-By-One output signal, including LVDS input interface, main control conversion chip, V-By-One output interface, NS / JEIDA configuration, partition selection configuration, direct current-direct current circuit, nonvolatile memory chip and extension power supply head, the LVDS input interface is outputted 2-port LVDS signal outward, main control conversion chip is electrically connected with LVDS input interface and receives 2-port LVDS signal, main control conversion chip exports 8-Lane V-By-One signal, V-By-One output interface is electrically connected with main control conversion chip and receives 8-Lane V-By-One signal, NS / JEIDA configuration is electrically connected on main control conversion chip, partition selection configuration is electrically connected on main control conversion chip, direct current-direct current circuit is electrically connected with LVDS input interface and main control conversion chip respectively, nonvolatile memory chip is electrically connected on main control conversion chip, and extension power supply head is electrically connected on direct current-direct current circuit.

[0009] Further, the main control conversion chip is packaged as LQFP, and the main control conversion chip is KIVIMAGE KIVI7626-LP_LQFP 128 chip.

[0010] Further, the 8-Lane V-By-One is composed of 8 groups of standard differential signals.

[0011] Further, the NS / JEIDA configuration and the partition selection configuration are used to complete the default state option of NS / JEIDA and partition state in the initialization process, complete the input and output data matching under the condition that the front-end LVDS signal format is unknown, and the configuration module is composed of a row of needle jump hats, a dial switch and a resistor.

[0012] Further, the direct current-direct current circuit converts 12V voltage accessed from the LVDS input interface into 3.3V, 1.8V and 1.2V to supply the main control conversion chip.

[0013] Further, the extension power supply head is 12V.

[0014] Preferably, the LVDS input interface, the main control conversion chip, the V-By-One output interface, the NS / JEIDA configuration, the partition selection configuration, the direct current-direct current circuit, the nonvolatile memory chip and the extension power supply head are on the same circuit board.

[0015] Preferably, the extension power supply head is a 2 to 8 PIN patch or a straight plug socket.

[0016] The utility model discloses the beneficial effects achieved by the above structure are as follows:

[0017] 1. The common 2-port LVDS input 8-Lane V-By-One output adapter cannot manually change the signal matching degree, and needs to be programmed and upgraded by SPI flash, which cannot be operated by non-professional technicians, the device can manually set the signal conversion matching degree, without software upgrade, non-professional technicians can complete the whole machine assembly, and technical problems are reduced.

[0018] 2. In the fields of liquid crystal whole machine production, screen replacement, commercial display DIY modification television, selection and purchase of liquid crystal mainboard and liquid crystal screen, the signal and partition standards of the liquid crystal mainboard and the liquid crystal screen do not need to be considered, only the compatibility of the input and output interfaces is considered, many liquid crystal mainboards and liquid crystal screens cannot change the signal and partition standards by themselves, some mainboards need professional technicians to enter the mainboard factory mode to change the signal standard, and the liquid crystal screen needs professional personnel to change the partition state through a programmer or welding, and the universal conversion device improves the selection range of the purchasing personnel in purchasing the liquid crystal mainboard and the liquid crystal screen.

[0019] 3. The liquid crystal screen with 8-Lane V-By-One input does not use the adapter, and the liquid crystal mainboard needs to select the mainboard with V-By-One output, the resolution of the 2-port LVDS output mainboard is 1920*1080, and the resolution of the 8-Lane V-By-One output mainboard is 4096*2160, and since the data processing capacity of the 2-port LVDS mainboard is 1 / 4 of that of the 8-Lane V-By-One mainboard, the cost of the 2-port LVDS mainboard is obviously lower than that of the 8-Lane V-By-One mainboard in main control chip selection, and the low-cost liquid crystal display mainboard can be replaced as a backup mainboard through the device. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The circuit overall structure module diagram is provided for the utility model;

[0021] Figure 2 The LVDS input interface circuit diagram is provided for the utility model;

[0022] Figure 3 The main control conversion chip circuit diagram is provided for the utility model;

[0023] Figure 4 The direct current-direct current circuit diagram is provided for the utility model.

[0024] Wherein, (1), LVDS input interface, (2), master control conversion chip, (3), V-By-One output interface, (4), NS / JEIDA configuration, (5), partition selection configuration, (6), DC-DC circuit, (7), nonvolatile memory chip, (8), extension power supply head. DETAILED DESCRIPTION

[0025] As shown in the description Figure 1 The utility model discloses a LVDS input signal turns V-By-One output signal omnipotent conversion device, including LVDS input interface (1), master control conversion chip (2), V-By-One output interface (3), NS / JEIDA configuration (4), partition selection configuration (5), DC-DC circuit (6), nonvolatile memory chip (7) and extension power supply head (8), and LVDS input interface (1) is outputted 2-port LVDS signal to the outside, and master control conversion chip (2) is electrically connected with LVDS input interface (1) and receives 2-port LVDS signal, and master control conversion chip (2) exports 8-Lane V-By-One signal, and V-By-One output interface (3) is electrically connected with master control conversion chip (2) and receives 8-Lane V-By-One signal, and NS / JEIDA configuration (4) is electrically connected on master control conversion chip (2), and partition selection configuration (5) is electrically connected on master control conversion chip (2), and DC-DC circuit (6) is electrically connected with LVDS input interface (1) and master control conversion chip (2) respectively, and nonvolatile memory chip (7) is electrically connected on master control conversion chip (2), and master control conversion chip (2) is the chip of active configuration operation, and the content of nonvolatile memory chip (7) is read through power-on initialization, and the working mode in chip is completed, and the content of nonvolatile memory chip (7) solidifies the register configuration required for signal conversion, and extension power supply head (8) is electrically connected on DC-DC circuit (6).

[0026] As shown in the description Figures 1-3 Master control conversion chip (2) is packaged as LQFP, and the pin is 128, and the silk screen model is KIVIMAGE KV7626-LP, and ESWIN EW9571-A can also be selected, and the 1st port LVDS data of LVDS input is connected to the 6-15 pin of master control chip, and the 2nd port LVDS data of LVDS input is connected to the 17-26 pin of master control chip, wherein the 6-15 pin and the 17-26 pin of master control chip are standard LVDS differential pair.

[0027] As shown in the description Figure 1As shown, 8-Lane V-By-One is composed of 8 groups of standard differential signals. The V-By-One output interface (3) can drive the 8-Lane V-By-One standard signal liquid crystal display.

[0028] As shown in the accompanying drawings of the specification Figure 1 As shown, the NS / JEIDA configuration (4) and the partition selection configuration (5) are used to complete the default state options of the NS / JEIDA and the partition state in the initialization process, and to complete the input and output data matching in the case of unknown front-end LVDS signal format. The configuration module is composed of pin jump cap, dial switch and resistor.

[0029] As shown in the accompanying drawings of the specification Figure 4 As shown, the DC-DC circuit (6) converts the 12V voltage accessed from the LVDS input interface (1) into 3.3V, 1.8V and 1.2V to supply the main control conversion chip (2).

[0030] As shown in the accompanying drawings of the specification Figure 1 As shown, the extended power supply head (8) is 12V. The V-By-One interface has certain requirements for current, and the power for driving the output display screen is large or small. In the case of large-size display screen, an additional 12V extended power supply head (8) is required.

[0031] In specific use: the LVDS input interface (1) is connected to the input of the main control conversion chip (2), the non-volatile memory chip (7) is connected to the main control conversion chip (2), the NS / JEIDA configuration (4) and the partition selection configuration (5) are connected to the main control conversion chip (2), the output of the main control conversion chip (2) is connected to the V-By-One output interface (3), and the input of the DC-DC circuit (6) is connected to the LVDS input interface (1), and the output is connected to the main control conversion chip (2) and the extended power supply head (8). The device is powered on to initialize the main control conversion chip (2) to read the content of the non-volatile memory chip (7), the function selection and signal conversion requirements of the NS / JEIDA configuration (4) and the partition selection configuration (5), receive the 2-port LVDS signal of the LVDS input interface (1), and output the 8-Lane V-By-One signal to the V-By-One output interface (3) according to the function selection and signal conversion requirements. The DC-DC circuit (6) converts the power provided by the LVDS input interface (1) into the normal working voltage of the main control conversion chip (2), and provides an extended voltage to the extended power supply head (8) for external equipment.

[0032] It should be understood that although the present specification describes the embodiments in the form of a single independent technical solution, the specification is described in this way only for the sake of clarity, and the skilled person should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that the skilled person can understand.

Claims

1. A universal conversion device for converting LVDS input signals into V-By-One output signals, characterized in that: It includes LVDS input interface (1), main control conversion chip (2), V-By-One output interface (3), NS / JEIDA configuration (4), partition selection configuration (5), DC-DC circuit (6), non-volatile memory chip (7) and extended power supply head (8), the LVDS input interface (1) outputs 2-port LVDS signal, the main control conversion chip (2) is electrically connected with the LVDS input interface (1) and receives 2-port LVDS signal, the main control conversion chip (2) outputs 8-Lane V-By-One signal, the V-By-One output interface (3) is electrically connected with the main control conversion chip (2) and receives 8-Lane V-By-One signal, the NS / JEIDA configuration (4) is electrically connected on the main control conversion chip (2), the partition selection configuration (5) is electrically connected on the main control conversion chip (2), the DC-DC circuit (6) is electrically connected with the LVDS input interface (1) and the main control conversion chip (2) respectively, the non-volatile memory chip (7) is electrically connected on the main control conversion chip (2), and the extended power supply head (8) is electrically connected on the DC-DC circuit (6).

2. The universal converter of LVDS input signal to V-By-One output signal according to claim 1, wherein: The main control conversion chip (2) is packaged as LQFP, and the main control conversion chip (2) is KIVIMAGE KIVI7626-LP_LQFP 128 chip.

3. The universal converter of LVDS input signal to V-By-One output signal according to claim 1, wherein: The 8-Lane V-By-One is composed of 8 groups of standard differential signals.

4. The universal converter of LVDS input signal to V-By-One output signal according to claim 1, wherein: The NS / JEIDA configuration (4) and the partition selection configuration (5) are used for completing the default state options of NS / JEIDA and partition state in the initialization process, completing input and output data matching in the case of unknown front-end LVDS signal format, and the configuration module is composed of row pin jump cap, dial switch and resistance.

5. The universal converter of LVDS input signal to V-By-One output signal according to claim 1, wherein: The DC-DC circuit (6) converts 12V voltage accessed from the LVDS input interface (1) into 3.3V, 1.8V and 1.2V to supply the main control conversion chip (2).

6. The universal converter of LVDS input signal to V-By-One output signal according to claim 1, wherein: The extended power supply head (8) is 12V.

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