Method and device for characterizing coupling effect between bit lines

Abstract

The present disclosure provides a method and apparatus for characterizing inter-bitline coupling effects, relating to the field of semiconductor technology. The method comprises: providing a test element group (TEG) test structure, the TEG test structure comprising a bitline to be tested and multiple adjacent bitlines to the bitline to be tested; detecting a first test voltage of the bitline to be tested relative to a reference potential terminal, while the bitline to be tested is in an idle state and a preset operating voltage is applied to the multiple adjacent bitlines; and determining a target adjustment voltage based on the first test voltage, wherein the target adjustment voltage is used to characterize the potential increase of the bitline to be tested due to the inter-bitline coupling effect. According to embodiments of the present disclosure, the characterization accuracy of the inter-bitline coupling effect can be quantitatively characterized.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method and device for characterizing inter-bit line coupling effects. Background Art

[0002] In semiconductor technology, due to process variations and other factors, the potential of one or more bit lines in a memory device may be affected by the voltage of adjacent bit lines, causing them to rise. This phenomenon is known as BL-to-BL coupling. However, it is currently difficult to quantitatively characterize BL-to-BL coupling.

[0003] Therefore, how to quantitatively characterize the inter-bit line coupling effect has become a technical problem that needs to be solved urgently.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The present disclosure provides a method, apparatus, device, and medium for characterizing the coupling effect between bit lines, which at least to some extent overcome the problem in the related art of being unable to quantitatively characterize the coupling effect between bit lines.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a method for characterizing an inter-bit line coupling effect is provided, comprising:

[0008] Providing a test element group TEG test structure, the TEG test structure includes a bit line to be tested and a plurality of adjacent bit lines of the bit line to be tested;

[0009] When the bit line to be tested is in an idle state and a plurality of adjacent bit lines are applied with a preset working voltage, detecting a first test voltage of the bit line to be tested compared to a reference potential end;

[0010] Based on the first test voltage, a target adjustment voltage is determined, wherein the target adjustment voltage is used to characterize the amount of potential raising of the bit line to be tested due to the coupling effect between the bit lines.

[0011] In one embodiment, the plurality of adjacent bit lines include: N first bit lines located on one side of the bit line to be tested, and N second bit lines located on the other side of the bit line to be tested, where N is any positive integer.

[0012] In one embodiment, the method further comprises:

[0013] Under the condition that the bit line to be tested is in an idle state, a preset working voltage is applied to the N first bit lines, and a negative voltage of the preset working voltage is applied to the N second bit lines, detecting a second test voltage of the bit line to be tested compared to the reference potential end;

[0014] The step of determining the target adjustment voltage based on the first test voltage includes:

[0015] Based on the first test voltage and the second test voltage, a target adjustment voltage is determined.

[0016] In one embodiment, determining a target adjustment voltage based on a first test voltage and a second test voltage includes:

[0017] determining a voltage difference between a first test voltage and a second test voltage;

[0018] determining a voltage ratio between an actual operating voltage of the bit line and a preset operating voltage;

[0019] Based on the voltage ratio and the voltage difference, a target adjustment voltage is determined.

[0020] In one embodiment, after determining the target adjustment voltage based on the first test voltage, the method further includes:

[0021] During the wafer testing phase, the target adjustment voltage is used to reduce the sensing margin of the memory cell under test;

[0022] The reduced sensing margin is used to detect failed bits of the memory cell under test.

[0023] In one embodiment, the reduced sensing margin is used to perform failed bit detection on a memory cell to be tested, where the memory cell to be tested is a memory cell to which data is written according to a preset write test mode.

[0024] The preset write test mode is a test mode in which 1 is written into all the memory cells of the test sub-array to which the memory cell to be tested belongs.

[0025] In one embodiment, before detecting a first test voltage of the bit line to be tested compared to a reference potential terminal, the method further includes:

[0026] Connecting the bit line to be tested and a plurality of adjacent bit lines to a reference potential;

[0027] When the current of the bit line to be tested is less than or equal to the preset current threshold and the currents of the adjacent bit lines are less than or equal to the preset current threshold, the bit line to be tested is controlled to be in an idle state and a preset operating voltage is applied to the adjacent bit lines.

[0028] In one embodiment, before detecting the second test voltage of the bit line to be tested compared to the reference potential terminal, the method further includes:

[0029] Connecting the bit line to be tested and a plurality of adjacent bit lines to a reference potential;

[0030] When the current of the bit line to be tested is less than or equal to the preset current threshold, and the current of multiple adjacent bit lines is less than or equal to the preset current threshold, the bit line to be tested is controlled to be in an idle state, a preset operating voltage is applied to the N first bit lines, and a negative voltage of the preset operating voltage is applied to the N second bit lines.

[0031] In one embodiment, the TEG test structure further includes a reference bit line,

[0032] Before detecting a first test voltage of the bit line to be tested compared to the reference potential terminal, the method further includes:

[0033] connecting the reference bit line to a reference potential;

[0034] Detecting a first test voltage of the bit line to be tested compared to a reference potential terminal includes:

[0035] Detecting the potential difference between the bit line to be tested and the reference bit line;

[0036] The potential difference is used as the first test voltage.

[0037] In one embodiment, before detecting a first test voltage of the bit line to be tested compared to a reference potential terminal, the method further includes:

[0038] connecting the reference bit line to a reference potential;

[0039] Detecting the second test voltage of the bit line to be tested compared to the reference potential terminal includes:

[0040] Detecting the potential difference between the bit line to be tested and the reference bit line;

[0041] The potential difference is used as the second test voltage.

[0042] In one embodiment, the structure of each bit line in the TEG test structure is consistent with the structure of the bit line actually fabricated.

[0043] In one embodiment, the N first bit lines are the consecutive N bit lines located on one side of the bit line to be tested and closest to the bit line to be tested, and the N second bit lines are the consecutive N bit lines located on the other side of the bit line to be tested and closest to the bit line to be tested.

[0044] According to another aspect of the present disclosure, a device for characterizing a bit line coupling effect is provided, comprising:

[0045] A TEG test structure, the TEG test structure includes a bit line to be tested and a plurality of adjacent bit lines of the bit line to be tested;

[0046] A voltage detection circuit is used to detect a first test voltage of the bit line to be tested compared to a reference potential end when the bit line to be tested is in an idle state and a plurality of adjacent bit lines are applied with a preset working voltage;

[0047] The voltage determination circuit is used to determine a target adjustment voltage based on a first test voltage, wherein the target adjustment voltage is used to characterize an amount of potential raising of the bit line caused by a coupling effect between the bit lines.

[0048] The method and device for characterizing the inter-bit line coupling effect provided by the embodiments of the present disclosure are such that when the bit line to be tested is in an idle state and a plurality of adjacent bit lines are applied with a preset operating voltage, the potential of the bit line to be tested will be affected by the plurality of adjacent bit lines due to the inter-bit line coupling effect. Therefore, the first test voltage obtained by detection (i.e., the voltage of the bit line to be tested compared to the reference potential end) can be correlated with the amount of potential raising of the bit line due to the inter-bit line coupling effect. Furthermore, since the target adjustment voltage is determined based on the first detection voltage, the target adjustment voltage can accordingly accurately characterize the amount of potential raising of the bit line due to the inter-bit line coupling effect, thereby achieving quantitative characterization of the inter-bit line coupling effect.

[0049] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0051] Figure 1 shows a schematic structural diagram of an exemplary data readout circuit;

[0052] Figure 2 shows a timing diagram of an exemplary data reading and writing process;

[0053] Figure 3 A schematic diagram showing the change of the number of failures of storage cells with the refresh cycle;

[0054] Figure 4 shows a schematic structural diagram of a bit line;

[0055] Figure 5 shows an energy diagram of a failed bit line;

[0056] Figure 6 An exemplary curve of electric potential energy versus distance is shown;

[0057] Figure 7 A schematic structural diagram of an exemplary TEG test structure provided by an embodiment of the present disclosure is shown;

[0058] Figure 8 A schematic flow chart of a method for characterizing inter-bit line coupling effects provided by an embodiment of the present disclosure is shown;

[0059] Figure 9 shows an exemplary schematic diagram of a change in bit line voltage;

[0060] Figure 10 A schematic diagram showing an exemplary bit line voltage after reducing the sensing margin;

[0061] Figure 11 A schematic flow chart of another method for characterizing the coupling effect between bit lines provided by an embodiment of the present disclosure is shown;

[0062] Figure 12 A schematic flow chart of an exemplary method for characterizing the coupling effect between bit lines provided in an embodiment of the present disclosure is shown;

[0063] Figure 13 A schematic diagram of a device for characterizing the coupling effect between bit lines provided by an embodiment of the present disclosure is shown;

[0064] Figure 14 A structural block diagram of an electronic device provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0065] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0066] In addition, the accompanying drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0067] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0068] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0069] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0070] In the semiconductor industry, manufacturing defects caused by process deviations, equipment failures, and other factors often result in a certain amount of defective die on the wafer. To improve chip yield and reduce subsequent packaging and testing costs, CP testing can be performed on each die after wafer fabrication and before packaging.

[0071] Because memory cells can fail due to transistor leakage, charge leakage, and other issues, CP testing involves writing test data to the memory cells under test in a specific write pattern and reading data from the memory cells after a certain period of time. Failed bits (i.e., failed memory cells) in the chip are detected based on whether the written data is inconsistent with the read data.

[0072] For ease of understanding, before introducing the technical solution provided by the embodiment of the present disclosure, the writing mode and data reading process involved in the embodiment of the present disclosure are first explained.

[0073] (1) A preset write mode, which may be referred to as solid top, is a write mode in which all 1s or all 0s are written to the entire storage subarray.

[0074] (2) A first write mode, which may be referred to as 18C topo, is a write mode in which only one bit of 8-bit burst data is written as 1 and the rest are written as 0; or a write mode in which only one bit is written as 0 and the rest are written as 1.

[0075] (3) The data readout process will be described below with reference to the data readout circuit and the timing diagram of the data readout process. Figure 1 A schematic structural diagram of an exemplary data readout circuit is shown. Figure 2A timing diagram of an exemplary data reading and writing process is shown.

[0076] Please also see Figure 1 and Figure 2 Taking the read data "1" as an example, before entering the ACT (activation) phase, the bit line BL and the complementary bit line BLb are both maintained at the first voltage value VBLP. After entering the ACT phase, as the word line WL is turned on, the storage capacitor C S Connected to the bit line BL, the storage capacitor C S The charge on the bit line BL is partially discharged, raising the potential of the bit line BL. Next, during the charge sharing phase, when the voltage difference between the bit line BL and the complementary bit line BLb reaches ΔV, the sense amplifier (SA) begins to operate, detecting and amplifying the voltage difference between the bit line BL and the complementary bit line BLb. This further raises the voltage on the bit line BL to a second voltage value, VARY, while lowering the voltage on the complementary bit line BLb to a third voltage value, VSS. The data is then read in the normal data read (RD) phase. After data reading is complete, the precharge (PRE) phase begins.

[0077] When reading data, if the voltage VBL of the bit line BL is greater than the voltage VBLb of the complementary bit line BLb, data "1" can be read. If the voltage VBL of the bit line BL is less than the voltage VBLb of the complementary bit line BLb, data "0" can be read.

[0078] Furthermore, when writing data "1" to a memory cell, if the voltage on the bit line BL remains at the first voltage value VBLP after the word line WL is turned on due to transistor leakage or other factors, the voltage VBL on the bit line BL will become equal to the voltage VBLb on the complementary bit line BLb, and the data "1" cannot be correctly read during the RD phase. In this case, the memory cell can be determined to be a failed bit based on the data read result.

[0079] After introducing the above content, the following will continue to explain the detection scheme of failed bits.

[0080] Figure 3 The figure shows the change of the failure bit count (FBC) of the memory cell with the refresh cycle (tREF). Figure 3 The solid line in FIG shows a curve showing a change in the number of failures of a memory cell with a refresh cycle in the preset write mode. The dotted line shows a curve showing a change in the number of failures of a memory cell with a refresh cycle in the first write mode.

[0081] pass Figure 3It can be seen that as the refresh cycle increases, the number of failures in the memory cells increases in both the preset write mode and the first write mode. Also, as the refresh cycle increases, the gap between the number of failures in the first write mode and the number of failures in the preset write mode also gradually increases. This gap indicates that when performing a test write in accordance with the preset write mode, some failed bits will not be successfully detected. Accordingly, by Figure 3 It can be seen that the detection accuracy of failed bits in the prior art is relatively low.

[0082] The inventors have discovered through research that the low detection accuracy of failed bits is affected to a certain extent by the coupling effect between bit lines.

[0083] First, for ease of understanding, Figure 4 and attached Figure 5 The principle of the bit line coupling effect (BL to BL coupling) is explained. Figure 4 shows a schematic structural diagram of a bit line, Figure 5 An energy diagram of a failed bit line is shown.

[0084] Please also see Figure 4 and Figure 5 The inventors studied the potential of the failed bit line and found that, according to the second law of thermodynamics, differences in electrochemical potential drive the movement of carriers. In other words, if the system is thermodynamically balanced, carriers everywhere have the same electrochemical potential energy, which is also the Fermi level of electrons.

[0085] The electrochemical potential energy of an electron at phase α in the Fermi space can be expressed as the following formula (1). Correspondingly, the Fermi level of an electron at position α can be expressed as the following formula (1):

[0086]

[0087] in, It is a standard state and is only related to the material. is the concentration term.

[0088] is the electrostatic potential of a single electron.

[0089] Next, the coupling effect is explained in conjunction with the Fermi level of electrons. Specifically, when there are no other memory cells around the failed bit line, the failed bit line ( Figure 4 The Fermi level of the bit line shown by the dotted line, that is, the bit line connected to the failed bit, can be expressed as And, due to the electrostatic potential of the failed bit line is the electric force Line integral from infinity (reference point) to the failed bit line. When there is an adjacent bit line with voltage of VBLP+ΔV around the failed bit line ( Figure 4 The electric field force is The work done by the bit line is reduced, and accordingly, the electrostatic energy of the failed bit line is -φ BL Will decrease accordingly, and the Fermi level of the failed bit line becomes in, That is, the potential of the failed bit line is raised due to the influence of the voltage of the adjacent bit line. At this time, the potential of the failed bit line is affected by the voltage of the adjacent bit line and is raised, which can be called the inter-bit line coupling effect.

[0090] Therefore, when the memory cell to be tested connected to the failed bit line cannot read data 1 due to transistor leakage or other reasons, due to the existence of the coupling effect between the bit lines, After a certain amount of compensation is performed on the potential drop of the failed bit caused by the above reasons (i.e., charge leakage or other reasons), the failed bit can be read as data 1, and the failed bit is misjudged as a normal storage unit, which reduces the detection accuracy of the failed bit.

[0091] Since the inter-bitline coupling effect affects processes such as failed bit detection, in order to facilitate the development of semiconductor testing, manufacturing and other technologies, it is necessary to quantitatively characterize the inter-bitline coupling.

[0092] Based on this, the embodiments of the present disclosure provide a characterization scheme for the bitline coupling effect, which can be applied to the test element group (TEG) verification stage. Exemplarily, it can be applied to the failed bit detection scenario of a memory device such as a dynamic random access memory (DRAM). In the embodiments of the present disclosure, since the first test voltage (i.e., the voltage of the bitline to be tested compared to the reference potential end) obtained by detection can be correlated with the amount of potential lift on the bitline due to the bitline coupling effect, and since the target adjustment voltage is determined based on the first test voltage, the target adjustment voltage can accordingly accurately characterize the amount of potential lift on the bitline due to the bitline coupling effect, thereby achieving quantitative characterization of the bitline coupling effect. Optionally, in the scenario of failure detection based on the target adjustment voltage, the embodiments of the present disclosure utilize the target adjustment voltage to reduce the sensing margin of the memory cell to be tested, thereby avoiding the influence of abnormal voltage lift (the lift of the bitline voltage of the failed memory cell by the adjacent bitline) on the failure detection result (the detection result of the failed bit during the wafer test phase), thereby improving the failure test accuracy.

[0093] The following is a detailed description of the technical solutions provided by the embodiments of the present disclosure. Since the solutions of the embodiments of the present disclosure rely on a test element group (TEG) test structure, for ease of understanding, the TEG test structure involved in the embodiments of the present disclosure will be described before introducing the technical solutions provided by the embodiments of the present disclosure.

[0094] A TEG test structure may include a bit line to be tested and multiple adjacent bit lines. The bit line to be tested may be the bit line to be tested. Adjacent bit lines may be located adjacent to the bit line to be tested and may affect the potential of the bit line to be tested due to inter-bitline coupling.

[0095] Next, the TEG test structure will be specifically described through the specific structures of adjacent bit lines and the TEG test structure.

[0096] In some embodiments, the plurality of adjacent bit lines include: N first bit lines located on one side of the bit line to be tested, and N second bit lines located on the other side of the bit line to be tested, where N is any positive integer.

[0097] Through this embodiment, since the bit line to be tested will be affected by the coupling effect of the bit lines on both sides during actual operation, when the TEG test structure includes a first bit line and a second bit line respectively located on both sides of the bit line to be tested, the target adjustment voltage can characterize the potential raise of the bit line to be tested by the adjacent bit lines on both sides, so that the target adjustment voltage can more accurately measure the potential raise of the bit line to be tested by the coupling effect between the bit lines, thereby realizing accurate quantitative characterization of the coupling effect between the bit lines.

[0098] Optionally, in the case where failed bit detection needs to be performed based on a target adjustment voltage, the sensing margin can be adjusted more precisely based on an accurate target adjustment voltage, thereby improving the detection accuracy of the failed bit.

[0099] It should be noted that, according to actual test scenarios and specific test requirements, other methods such as setting multiple adjacent bit lines to be located on one side of the bit line to be tested may also be used, which will not be described in detail.

[0100] In one embodiment, the N first bit lines may be N consecutive bit lines located on one side of a bit line to be tested and closest to the bit line to be tested, and the N second bit lines may be N consecutive bit lines located on the other side of the bit line to be tested and closest to the bit line to be tested. For example, the first bit lines may include a first bit line, a second bit line, ..., and an Nth bit line located on one side of the bit line to be tested. Similarly, the second bit lines may include a first bit line, a second bit line, ..., and an Nth bit line located on the other side of the bit line to be tested.

[0101] It should be noted that Figure 6 An exemplary curve of potential energy changing with distance is shown. Figure 6 It can be seen that the electric potential energy E P The following formula (2) can be satisfied:

[0102] E P =k·e 2 / r (2)

[0103] Where k is a constant equal to 8.99×10 9 ; e represents the amount of charge; r represents the action distance.

[0104] pass Figure 6 From the above formula (2), we can know that the electric potential energy E P It will decay rapidly as the effective distance r increases. Similarly, the farther the adjacent bit lines are from the bit line to be tested, the less influence the adjacent bit lines have on the inter-bitline coupling effect on the bit line to be tested, that is, the lower the potential rise of the adjacent bit lines on the bit line to be tested. Therefore, the potential of the bit line to be tested is primarily affected by the closest N consecutive first bit lines and N consecutive second bit lines. Therefore, in this embodiment, when the TEG test structure includes the closest N consecutive first bit lines and N consecutive second bit lines located on both sides of the bit line to be tested, the determined target adjustment voltage can represent the potential rise of the bit line by the adjacent bit lines on both sides, so that the target adjustment voltage can further and more accurately measure the potential rise of the bit line by the inter-bitline coupling effect, thereby achieving accurate quantitative characterization of the inter-bitline coupling effect.

[0105] Optionally, in the case where failed bit detection needs to be performed based on the target adjustment voltage, the sensing margin can be further adjusted more precisely based on the accurate target adjustment voltage, thereby further improving the detection accuracy of the failed bit.

[0106] In addition, it should be noted that, based on the TEG test structure provided in this embodiment, the target adjustment voltage in the preset test scheme (i.e., the scheme for testing the potential lift of N consecutive first bit lines closest to each other and N consecutive second bit lines closest to each other on the bit line to be tested) can be tested. The target adjustment voltage obtained by the test can accurately characterize the potential lift of the bit line due to the adjacent bit line when the chip is written in accordance with the preset write mode (i.e., Solid topo) (i.e., the entire storage sub-array is written with 1), thereby improving the accuracy of failed bit detection in the preset write mode.

[0107] It should be noted that, according to actual test conditions and specific test scenarios, N discontinuous first bit lines and N second bit lines, or N continuous / discontinuous first bit lines and N second bit lines that are not closest to the bit line to be tested can also be selected, and there is no specific limitation on this.

[0108] In one example, N is 4. It should be noted that N can be set to other specific values ​​based on actual conditions and specific requirements. For example, when accuracy is not required to be high, N can be set to an integer less than 4 to reduce testing costs. For another example, when accuracy needs to be further improved, N can be set to a value greater than 4, and there is no specific limitation on this.

[0109] It should be noted that the inventors found through research that the electric potential energy E P It will decay rapidly with the increase of the effective distance r, so the bit line to be tested is mainly affected by the four adjacent bit lines. Therefore, when the TEG test structure includes the four consecutive first bit lines and the four consecutive second bit lines that are closest to each other, the target adjustment voltage can accurately measure the potential raising amount of the bit line caused by the coupling effect between the bit lines, and at the same time, it can simplify the structure of the TEG test structure, taking into account both the detection cost and the detection accuracy.

[0110] In a specific example, Figure 7 FIG. 1 shows a schematic diagram of an exemplary TEG test structure provided by an embodiment of the present disclosure. Figure 7 As shown, the TEG test structure may include: a bit line to be tested BL4, four consecutive first bit lines BL0 to BL3 located on one side of the bit line to be tested BL4, and four consecutive first bit lines BL5 to BL8 located on one side of the bit line to be tested BL4.

[0111] After introducing the adjacent bit lines, the specific structure of the TEG test structure is described next.

[0112] In some embodiments, the structure of each bit line in the TEG test structure (including the bit line to be tested and multiple adjacent bit lines) is consistent with the structure of the bit line actually prepared. For example, the hierarchical structure of each bit line in the TEG test structure can be consistent with the hierarchical structure of the bit line actually prepared. For example, the contact parts (contact) such as PC and the upper layer wiring are consistent. For another example, continue to see Figure 7 , the distance x between the bit lines in the TEG test structure is consistent with the distance between the bit lines in the actual prepared semiconductor structure.

[0113] Through this embodiment, since the structure of each bit line in the TEG test structure is consistent with that of the bit line actually prepared, and the target adjustment voltage is determined based on the TEG test structure, accordingly, the target adjustment voltage can accurately measure the amount of potential increase of the bit line in the actually prepared semiconductor storage structure caused by the coupling effect between the bit lines, thereby achieving accurate quantitative characterization of the coupling effect between the bit lines.

[0114] Optionally, when failed bit detection is required based on a target adjustment voltage, the sensing margin of the actually prepared semiconductor storage structure can be more accurately adjusted based on the accurate target adjustment voltage, thereby further improving the detection accuracy of failed bits in the actually prepared semiconductor storage structure.

[0115] In some embodiments, in order to facilitate testing, the TEG test structure may further include a reference bit line. The reference bit line is used as a reference potential terminal. For example, the reference bit line may be as follows: Figure 7 The bit line BL9 is shown by a mid-dash line.

[0116] After introducing the TEG test structure, this exemplary implementation is described in detail below with reference to the accompanying drawings and embodiments.

[0117] First, an embodiment of the present disclosure provides a method for characterizing the coupling effect between bit lines. The method can be executed by any electronic device capable of processing data signals.

[0118] Figure 8 FIG. 1 is a flow chart showing a method for characterizing the coupling effect between bit lines provided by an embodiment of the present disclosure, as shown in FIG. Figure 8 As shown, the method for characterizing the inter-bit line coupling effect provided in the embodiment of the present disclosure includes the following steps S810 to S830.

[0119] S810, providing a TEG test structure. The TEG test structure includes a bit line to be tested and a plurality of adjacent bit lines to be tested. The TEG test structure can be described in detail in conjunction with the above embodiments of the present disclosure. Figure 7 The relevant instructions are not repeated here.

[0120] S820, when the bit line to be tested is in a floating state and a preset operating voltage VDD is applied to a plurality of adjacent bit lines, detecting a first test voltage V1 of the bit line to be tested relative to a reference potential terminal. The floating state may be a state in which no voltage is applied to the bit line to be tested. Furthermore, the first test voltage V1 may be a potential difference between the potential to be tested and the reference potential terminal. The reference potential terminal may be a potential terminal for providing a reference potential. For example, it may be a reference bit line, etc.

[0121] In some embodiments, when the reference potential terminal is a reference bit line, before S820 , the method further includes step C1 .

[0122] Step C1: Connect the reference bit line to a reference potential. The reference potential is a potential used as a reference. For example, the reference potential can be a ground potential. Accordingly, the reference bit line can be connected to the reference potential by grounding it. It should be noted that the reference potential can also be other constant potentials, which are not specifically limited.

[0123] Accordingly, S820 may include the following step C2.

[0124] Step C2 , detecting a potential difference between the bit line to be tested and the reference bit line, and using the detected potential difference as a first test voltage V1 .

[0125] Through this embodiment, since the first test voltage is related to the abnormal potential rise (i.e., the voltage rise of the bit line caused by the coupling effect between the bit lines), and the potential difference between the bit line to be tested and the reference bit line can represent the abnormal rise, accordingly, the first test voltage can be accurately obtained by testing the potential difference between the bit line to be tested and the reference bit line, which improves the convenience of testing the first test voltage and can improve the accuracy of subsequent calculation of the target adjustment voltage and failed bit detection based on the accurate first test voltage.

[0126] S830: Determine a target adjustment voltage based on the first test voltage. The target adjustment voltage is used to characterize the potential increase of the bit line to be tested due to the bit line coupling effect. Optionally, in the disclosed embodiment, the target adjustment voltage may also be used to characterize the potential increase of other bit lines due to the bit line coupling effect.

[0127] In S830 , a target adjustment voltage may be determined based on the first test voltage based on a preset formula or a preset model.

[0128] In some embodiments, the target adjustment voltage VP may satisfy the following formula (3):

[0129]

[0130] Wherein, VBLH is the actual operating voltage of the bit line to be tested, and VDD is the preset operating voltage. For example, the actual operating voltage can be the voltage applied to the bit line to be tested during the actual reading and writing process of the memory cell, for example, the voltage on the bit line to be tested when reading or writing 1.

[0131] Accordingly, S830 may include the following steps A1 and A2.

[0132] In step A1 , a voltage ratio between an actual operating voltage VBLH of a bit line and a preset operating voltage VDD is determined.

[0133] In step A2, a target adjustment voltage VP is determined based on the voltage ratio and the first test voltage V1. For example, the target adjustment voltage VP can be determined by multiplying the voltage ratio by the first test voltage V1. It should be noted that the target adjustment voltage VP can also be determined using other methods, such as by subtracting a safety voltage margin from the product, and this is not particularly limited.

[0134] The method for characterizing the inter-bit line coupling effect provided by the embodiment of the present disclosure is that when the bit line to be tested is in an idle state and a plurality of adjacent bit lines are applied with a preset working voltage, the potential of the bit line to be tested will be affected by the plurality of adjacent bit lines due to the inter-bit line coupling effect. Therefore, the first test voltage obtained by detection (i.e., the voltage of the bit line to be tested compared to the reference potential end) can be related to the amount of potential raising of the bit line caused by the inter-bit line coupling effect. Furthermore, since the target adjustment voltage is determined based on the first detection voltage, accordingly, the target adjustment voltage can accurately characterize the amount of potential raising of the bit line caused by the inter-bit line coupling effect, thereby realizing quantitative characterization of the inter-bit line coupling effect.

[0135] In some embodiments, after S830 , the method for characterizing the inter-bit line coupling effect may further include the following steps B1 and B2 .

[0136] Step B1 , during a wafer testing phase, using a target adjustment voltage to reduce a sensing margin of a memory cell to be tested.

[0137] As for the sensing margin (SM), it can be the weak voltage difference between the amplified bit line and the complementary bit line when the SA is turned on, for example, Figure 2 In some embodiments, if the original sensing margin is ΔV, then after it is reduced by the target adjustment voltage VP, the reduced sensing margin can be expressed as ΔV-VP.

[0138] In some embodiments, the reduced sensing margin is used to detect failed bits in a memory cell under test that is being written with data according to a preset write test pattern. The preset write test pattern is a test pattern in which 1s are written to all memory cells in a test subarray to which the memory cell under test belongs. The preset write pattern can be found in the description of the above embodiments of the present disclosure and will not be further elaborated upon.

[0139] It should be noted that the preset writing mode has a higher writing rate than other writing modes such as the first writing mode, so that the failed bit test based on the preset writing mode has a higher detection efficiency. Figure 3As shown, the preset write mode has lower detection accuracy than other write modes such as the first write mode. The inventors discovered through research that, in the preset write mode, since all memory cells must be written with a 1, the potential of the bit line connected to the failed memory cell is affected by the inter-bit line coupling effect and is elevated, resulting in the inability to successfully detect the failed memory cell. By reducing the sensing margin based on the target adjustment voltage in this embodiment, the test accuracy of the failed bit test based on the preset write mode can be improved while maintaining detection efficiency, thereby achieving a balance between detection accuracy and detection efficiency.

[0140] And, for the reduction process of the sensing margin, the following is Figure 9 and Figure 10 Provide explanation. Figure 9 shows an exemplary schematic diagram of the change of the bit line voltage, Figure 10 FIG. 1 is a schematic diagram showing an exemplary bit line voltage after reducing the sensing margin.

[0141] Please also see Figure 9 and Figure 10 , taking the writing of data "1" during the test process as an example, before reducing the sensing margin, the voltage on each bit line will be affected by the SA mismatch and the coupling effect between bit lines, then the bit line voltage VBL1 of the normal memory cell can be expressed as VBLP+ΔV+VC+VM, and the bit line voltage VBL2 of the failed memory cell can be expressed as VBLP+VC+VM. Since the coupling effect between bit lines will raise the potential of each bit line, the bit line voltage VBL1 of the normal memory cell and the bit line voltage VBL2 of the failed memory cell are both greater than the voltage VBLb of the complementary bit line. At this time, during the data reading process, data "1" can be read from both the normal memory cell and the failed memory cell. According to the data reading result, the failed memory cell cannot be detected as a failed bit. Among them, VC is the actual voltage change caused by the coupling effect between bit lines, VM is the voltage change caused by SA mismatch, and VBLP and ΔV can be found in the above part of the embodiment of the present disclosure in combination. Figure 2 The relevant description will not be repeated here.

[0142] After reducing the sensing margin by lowering the voltage of each bit line by the target adjustment voltage VP, the bit line voltage of the normal memory cell decreases from VBL1 to VBL1′, where the reduced bit line voltage VBL1′ is equal to VBLP + ΔV + VC + VM - VP. Furthermore, the bit line voltage of the failed memory cell decreases from VBL2 to VBL2′, where the reduced bit line voltage VBL2′ is equal to VBLP + VC + VM - VP. At this point, the bit line voltage VBL1′ of the normal memory cell is greater than the complementary bit line voltage VBLb, while the bit line voltage of the failed memory cell is less than the complementary bit line voltage VBLb. During the data read process, data "1" can be read from the normal memory cell, and data "0" can be read from the failed memory cell. Therefore, based on the data read results, the failed memory cell can be accurately detected as a failed bit.

[0143] Step B2: performing failed bit detection on the memory cell to be tested using the reduced sensing margin.

[0144] In one embodiment, in step B2, as described above Figure 10 As shown, the sensing margin can be reduced by reducing the bit line voltage. For example, the bit line voltage during initial sensing can be reduced by the target adjustment voltage VP.

[0145] In some other embodiments, in step B2, the sensing margin may be reduced by increasing the bit line voltage of the complementary bit line. For example, the bit line voltage of the complementary bit line during initial sensing may be pulled up to the target adjustment voltage VP.

[0146] It should be noted that in the embodiments of the present disclosure, other methods may be selected to reduce the sensing margin according to actual conditions and specific scenarios, and there is no specific limitation on this.

[0147] Through the above-mentioned steps B1 and B2, after the sensing margin of the memory cell to be tested is reduced by using the target adjustment voltage, the influence of the voltage increase of the bit line of the failed memory cell by the adjacent bit line on the failure detection result of the failed bit (i.e., the failed memory cell to be tested) in the wafer test stage can be avoided, thereby improving the detection accuracy of the failed bit.

[0148] Furthermore, the inventors discovered through research that, during the TEG verification phase, because the TEG test structure is not a complete circuit, it is impossible to perform the same potential-pulling-up or -pulling-down operations on the bit line as during the charge-sharing phase. Consequently, the TEG verification phase cannot detect failed bits based on the data read and write results of the memory cells. In the disclosed embodiments, the voltage testing function during the TEG verification phase and the failed bit detection function during the wafer test phase can be used in synergy to jointly detect failed bits, achieving optimal utilization of the wafer test process.

[0149] In some embodiments, to improve test accuracy, before S820 , the method for characterizing the inter-bit line coupling effect may further include the following steps C1 and C2 .

[0150] In step C1, the bit line to be tested and the adjacent bit lines are connected to a reference potential. For example, the bit line to be tested and the adjacent bit lines can be grounded. The reference potential can be found in the above description of the embodiment of the present disclosure and will not be repeated here.

[0151] Step C2 : when the current of the bit line to be tested is less than or equal to the preset current threshold and the currents of the adjacent bit lines are less than or equal to the preset current threshold, control the bit line to be tested to be in an idle state and apply a preset operating voltage to the adjacent bit lines.

[0152] The preset current threshold may refer to a current of 0 or approximately 0. For example, when the current of the bit line to be measured and any one of the plurality of adjacent bit lines is less than or equal to the preset current threshold, it may be considered that no current is measured on the bit line.

[0153] In one example, current detection may be performed on the bit line to be detected and each of the plurality of adjacent bit lines, and it may be determined whether the detected current is less than or equal to a preset current threshold.

[0154] In another example, when the duration of the connection to the reference potential is greater than or equal to a preset duration threshold, it may be determined that the currents of the bit line to be tested and the plurality of adjacent bit lines are less than or equal to a preset current threshold.

[0155] It should be noted that in the embodiment of the present disclosure, it is also possible to determine whether the current of the bit line to be tested and the plurality of adjacent bit lines is less than or equal to the preset current threshold based on other conditions, and there is no specific limitation on this.

[0156] This embodiment controls the connection of the bit line to be tested and multiple adjacent bit lines to the reference potential. This allows the first test voltage test to be performed only after no current is detected in the bit line to be tested and its adjacent bit lines. This prevents the influence of existing current in the bit line to be tested and its adjacent bit lines on the test results, ensures the accuracy of the first test voltage, and thus enables accurate quantitative characterization of the coupling effect between bit lines. Alternatively, when failed bit detection based on a target adjustment voltage is required, the test accuracy of failed bits can be further improved while maintaining the first test voltage.

[0157] Figure 11 The present invention is an embodiment of the present invention that optimizes the above embodiments and can be combined with various optional solutions in one or more of the above embodiments.

[0158] like Figure 11 As shown, the method for characterizing the coupling effect between bit lines includes the following steps S1110 to S1140.

[0159] S1110 provides a test element group (TEG) test structure. The TEG test structure includes a bit line to be tested and multiple bit lines adjacent to the bit line to be tested. The TEG test structure may include N first bit lines and N second bit lines. S1110 is similar to S810, and the details of S810 can be found in the description of the TEG test structure in the above-mentioned embodiments of the present disclosure. Further details will not be given here.

[0160] S1120: When the bit line to be tested is in an idle state and a plurality of adjacent bit lines are applied with a preset working voltage, a first test voltage of the bit line to be tested is detected compared to the reference potential end. S1120 is similar to S820, and the details of S820 can be referred to, and will not be described in detail here.

[0161] S1130, when the bit line to be tested is in an idle state, a preset working voltage is applied to N first bit lines, and a negative voltage of the preset working voltage is applied to N second bit lines, a second test voltage of the bit line to be tested is detected compared to the reference potential end. Figure 7 For example, a preset operating voltage VDD may be applied to the first bit lines BL0 to BL3 , and a negative voltage −VDD of the preset operating voltage may be applied to the second bit lines BL5 to BL8 .

[0162] In some embodiments, when the reference potential terminal is a reference bit line, before S1130 , the method for characterizing the coupling effect between bit lines may further include the following step D1 .

[0163] Step D1, connecting the reference bit line to a reference potential. Step D1 is similar to step C1 above, and the details of step C1 can be found in the details, which will not be described in detail. In one embodiment, the reference potential in steps D1 and C1 is the same reference potential. Since the inter-bitline coupling effect of the reference bit line has the same effect on the bit line to be tested in the first test voltage and the second test voltage when connected to the same reference potential, the influence of the inter-bitline coupling effect of the reference bit line can be offset when determining the target adjustment voltage using the first test voltage and the second test voltage, thereby further improving the accuracy of characterizing the inter-bitline coupling effect. Optionally, in the case where failed bit detection is required based on the target adjustment voltage, the test accuracy of the failed bit can be further improved.

[0164] In the case where the method for characterizing the inter-bit line coupling effect includes step D1 , S1130 may include the following steps D2 and D3 .

[0165] Step D2: detecting the potential difference between the bit line to be tested and the reference bit line.

[0166] Step D3: using the potential difference as the second test voltage V2.

[0167] Through this embodiment, the second test voltage related to the potential raise of the bit line caused by the coupling effect between the bit lines can be accurately obtained by testing the potential difference between the bit line to be tested and the reference bit line. While improving the testing convenience of the test voltage, it can improve the accuracy of subsequent calculation of the target adjustment voltage and failed bit detection based on the accurate second test voltage.

[0168] It should be noted that the embodiment of the present disclosure does not impose any specific restrictions on the execution order between S1120 and S1130. S1120 can be executed before S1130, or S1130 can be executed before S1120. There is no specific restriction on this.

[0169] S1140: Determine a target adjustment voltage based on the first test voltage and the second test voltage, wherein the target adjustment voltage is used to represent the potential increase of the bit line due to the coupling effect between the bit lines.

[0170] In some embodiments, the target adjustment voltage can be expressed as the following formula (4):

[0171]

[0172] Accordingly, S1140 may include the following steps E1 to E3.

[0173] Step E1: determining a voltage difference between a first test voltage and a second test voltage.

[0174] Step E2 , determining a voltage ratio between the actual operating voltage VBLH of the bit line and the preset operating voltage VDD.

[0175] In step E3, a target adjustment voltage VP is determined based on the voltage ratio and the voltage difference. For example, the target adjustment voltage VP can be determined by multiplying the voltage ratio and the voltage difference. It should be noted that the target adjustment voltage VP can also be determined using other methods, such as by subtracting a safety voltage margin from the product, and this is not specifically limited.

[0176] Through the above steps E1 to E3, when the N first bit lines are applied with a preset operating voltage and the N second bit lines are applied with a negative voltage of the preset operating voltage, the adjacent bit lines at both ends of the bit line to be tested are structurally symmetrical and have symmetrical potentials. Therefore, the bit line to be tested is not affected by the inter-bitline coupling effect, and the second test voltage can represent the voltage of the bit line to be tested when it is not affected by the inter-bitline coupling effect. Since the first test voltage and the second test voltage are affected by the same factors, such as leakage, except for the inter-bitline coupling effect, the influence of other factors that can cause potential changes, such as leakage, on the test results can be eliminated based on the voltage difference between the first test voltage and the second test voltage, and the potential increase of the bit line to be tested due to the inter-bitline coupling effect in the TEG test structure can be accurately determined. Furthermore, because the electrostatic potential energy is proportional to the operating voltage, when the bitline voltage on the TEG test structure is VDD, the target adjustment voltage calculated is (V2-V1). When the actual voltage on the bitline is the actual operating voltage VBLH, the target adjustment voltage is proportionally scaled based on the ratio of the actual operating voltage VBLH to the preset operating voltage VDD, for example, by VBLH / VDD*(V1-V2). Therefore, after determining the voltage difference, multiplying it by the voltage ratio of the actual operating voltage BLH to the preset operating voltage VDD accurately determines the bitline potential elevation caused by the inter-bitline coupling effect in the actual circuit. Thus, based on steps E1 to E3 above, the inter-bitline coupling effect can be accurately quantitatively characterized. Optionally, when failed bit detection is required based on the target adjustment voltage, while maintaining the first test voltage, the test accuracy of failed bits can be further improved.

[0177] The method for characterizing the bit line coupling effect provided in the embodiment of the present disclosure is that when the bit line to be tested is in an idle state and a plurality of adjacent bit lines are applied with a preset working voltage, the potential of the bit line to be tested will be affected by the plurality of adjacent bit lines due to the bit line coupling effect. Therefore, the first test voltage of the bit line to be tested obtained by detection compared to the reference potential end can be related to the amount of potential raising of the bit line caused by the bit line coupling effect, and then the target adjustment voltage determined based on the first detection voltage can accurately characterize the amount of potential raising of the bit line caused by the bit line coupling effect, thereby realizing quantitative characterization of the bit line coupling effect.

[0178] Furthermore, based on a first test voltage that characterizes the influence of the bit line coupling effect on the bit line to be tested, and a second test voltage that is not affected by the bit line coupling effect, the voltage change of the bit line to be tested that is affected by the bit line coupling effect can be accurately determined, so that a target adjustment voltage that characterizes the amount of potential raising of the bit line caused by the bit line coupling effect can be accurately calculated based on the voltage change, thereby achieving quantitative characterization of the bit line coupling effect.

[0179] In some embodiments, before S1130 , the method for characterizing the inter-bit line coupling effect may further include the following steps F1 and F2 .

[0180] In step F1, the bit line to be tested and a plurality of adjacent bit lines are connected to a reference potential. Step F1 is similar to step C1, and the details of step C1 can be referred to, which will not be described in detail.

[0181] In step F2, when the current of the bit line to be tested is less than or equal to the preset current threshold, and the currents of multiple adjacent bit lines are less than or equal to the preset current threshold, the bit line to be tested is controlled to be in an idle state, a preset operating voltage is applied to the N first bit lines, and a negative voltage of the preset operating voltage is applied to the N second bit lines.

[0182] It should be noted that the rest of the contents of step F2 are similar to those of step C2. Please refer to the specific contents of step C2 and no further details will be given.

[0183] This embodiment controls the connection of the bit line to be tested and multiple adjacent bit lines to the reference potential. This allows the second test voltage to be applied only after no current is detected in the bit line to be tested and its adjacent bit lines. This prevents the influence of existing current in the bit line to be tested and its adjacent bit lines on the test results, ensures the accuracy of the second test voltage, and thus enables accurate quantitative characterization of inter-bitline coupling effects. Alternatively, when failed bit detection based on a target adjustment voltage is required, the accuracy of failed bit testing can be further improved while maintaining the second test voltage.

[0184] After the above content introduces the characterization method of the coupling effect between bit lines in detail, in order to facilitate the overall understanding, the characterization method of the coupling effect between bit lines is described in detail through a specific example.

[0185] Figure 12 A flow chart of an exemplary method for characterizing inter-bit line coupling effects provided by an embodiment of the present disclosure is shown.

[0186] like Figure 12 As shown, Figure 7 Taking the TEG test structure shown in FIG. 1 as an example, the method for characterizing the coupling effect between bit lines may include the following steps S1201 to S1208 .

[0187] S1201 , all bit lines BL0 to BL9 of the TEG test structure are grounded and held for a period of time until no current is measured.

[0188] S1202 , keep the bit line to be tested BL4 floating, keep the reference bit line BL9 grounded, and apply a preset working voltage VDD to the first bit lines BL0 to BL3 and the second bit lines BL5 to BL8 .

[0189] S1203 , measuring the potential difference between the bit line to be tested BL4 and the reference bit line BL9 , which is recorded as a first test voltage V1 .

[0190] S1204 , all bit lines BL0 to BL9 of the TEG test structure are grounded and kept at this state for a period of time until no current is detected.

[0191] S1205 , keep the bit line to be tested BL4 floating, keep the reference bit line BL9 grounded, apply a preset working voltage VDD to the first bit lines BL0 to BL3 , and apply a negative voltage of the preset working voltage -VDD to the second bit lines BL5 to BL8 .

[0192] S1206 , measuring the potential difference between the bit line to be tested BL4 and the reference bit line BL9 , which is recorded as a second test voltage V2 .

[0193] S1207: Determine the voltage difference (V1-V2) between the first test voltage and the second test voltage. This voltage difference is the potential rise of the bit line to be tested caused by the coupling effect between the bit lines in the TEG structure to be tested.

[0194] S1208: Determine a target adjustment amount based on the voltage difference. The target adjustment amount can be calculated using the above formula (4), and is used to characterize the amount of bit line potential rise caused by the bit line coupling effect in an actual circuit.

[0195] Based on the same inventive concept, an embodiment of the present disclosure further provides a device for characterizing the coupling effect between bit lines, such as the following embodiment.

[0196] Figure 13 A schematic diagram of a device for characterizing the coupling effect between bit lines in an embodiment of the present disclosure is shown. Figure 13 As shown, the device 1300 for characterizing the coupling effect between bit lines includes a TEG test structure 1310 , a voltage detection circuit 1320 and a processor 1330 .

[0197] The TEG test structure 1310 includes a bit line to be tested and a plurality of bit lines adjacent to the bit line to be tested.

[0198] The voltage detection circuit 1320 is configured to detect a first test voltage of the bit line to be tested compared to a reference potential end when the bit line to be tested is in an idle state and a plurality of adjacent bit lines are applied with a preset working voltage.

[0199] The processor 1330 is configured to determine a target adjustment voltage based on the first test voltage, wherein the target adjustment voltage is used to represent an amount of potential raising of the bit line to be tested due to the coupling effect between the bit lines.

[0200] In one embodiment, the plurality of adjacent bit lines include: N first bit lines located on one side of the bit line to be tested, and N second bit lines located on the other side of the bit line to be tested, where N is any positive integer.

[0201] In one embodiment, the voltage detection circuit 1320 is also used to detect the second test voltage of the bit line to be tested compared to the reference potential end when the bit line to be tested is in an idle state, the N first bit lines are applied with a preset working voltage, and the N second bit lines are applied with a negative voltage of the preset working voltage.

[0202] Accordingly, the processor 1330 may be specifically configured to determine a target adjustment voltage based on the first test voltage and the second test voltage.

[0203] In one embodiment, the processor 1330 is specifically configured to: determine a voltage difference between the first test voltage and the second test voltage; determine a voltage ratio between an actual operating voltage of the bit line and a preset operating voltage; and determine a target adjustment voltage based on the voltage ratio and the voltage difference.

[0204] In one embodiment, the device 1300 for characterizing the coupling effect between bit lines further includes: a sensing margin adjustment circuit and a failure detection circuit.

[0205] The sensing margin adjustment circuit is used to reduce the sensing margin of the memory cell to be tested by using a target adjustment voltage during a wafer test phase.

[0206] The failure detection circuit is used for performing failure bit detection on the memory cell to be tested by utilizing the reduced sensing margin.

[0207] In one embodiment, the reduced sensing margin is used to detect failed bits in a memory cell under test that is written with data according to a preset write test mode, where the preset write test mode is a test mode in which 1 is written to all memory cells of a test subarray to which the memory cell under test belongs.

[0208] In one embodiment, the device 1300 for characterizing the coupling effect between bit lines further includes a bit line control circuit.

[0209] The bit line control circuit is used to connect the bit line to be tested and multiple adjacent bit lines to a reference potential. Furthermore, when the current in the bit line to be tested and the multiple adjacent bit lines is less than or equal to a preset current threshold, the bit line to be tested is controlled to be in an idle state and a preset operating voltage is applied to the multiple adjacent bit lines.

[0210] In one embodiment, the device 1300 for characterizing the coupling effect between bit lines further includes a bit line control circuit.

[0211] The bit line control circuit is configured to connect the bit line to be tested and a plurality of adjacent bit lines to a reference potential. Furthermore, when the current in the bit line to be tested and the plurality of adjacent bit lines is less than or equal to a preset current threshold, the bit line to be tested is controlled to be in an idle state, a preset operating voltage is applied to the N first bit lines, and a negative voltage of the preset operating voltage is applied to the N second bit lines.

[0212] In one embodiment, the TEG test structure further includes a reference bit line, and the device 1300 for characterizing the coupling effect between bit lines further includes a bit line control circuit.

[0213] The bit line control circuit is used to connect the reference bit line to a reference potential.

[0214] The voltage detection circuit 1320 is specifically configured to: detect the potential difference between the bit line to be tested and the reference bit line; and use the potential difference as the first test voltage.

[0215] In one embodiment, the TEG test structure 1310 further includes a reference bit line, and the device 1300 for characterizing the coupling effect between bit lines further includes a bit line control circuit.

[0216] The bit line control circuit is used to connect the reference bit line to a reference potential.

[0217] The voltage detection circuit 1320 is specifically configured to: detect the potential difference between the bit line to be tested and the reference bit line; and use the potential difference as the second test voltage.

[0218] In one embodiment, the structure of each bit line in the TEG test structure 1310 is consistent with the structure of an actually fabricated bit line.

[0219] In one embodiment, the N first bit lines are the consecutive N bit lines located on one side of the bit line to be tested and closest to the bit line to be tested, and the N second bit lines are the consecutive N bit lines located on the other side of the bit line to be tested and closest to the bit line to be tested.

[0220] The device for characterizing the inter-bit line coupling effect provided by the embodiment of the present disclosure has a structure that, when the bit line to be tested is in an idle state and a plurality of adjacent bit lines are applied with a preset working voltage, the potential of the bit line to be tested will be affected by the plurality of adjacent bit lines due to the inter-bit line coupling effect. Therefore, the first test voltage of the bit line to be tested obtained by detection compared to the reference potential end can be correlated with the amount of potential raising of the bit line caused by the inter-bit line coupling effect. Furthermore, the target adjustment voltage determined based on the first detection voltage can accurately characterize the amount of potential raising of the bit line caused by the inter-bit line coupling effect, thereby achieving quantitative characterization of the inter-bit line coupling effect.

[0221] It should be noted that Figure 13 The device 1300 for characterizing the bit line coupling effect can be performed Figures 8 to 12 The various steps in the method embodiment shown are implemented Figures 8 to 12 The various processes and effects in the illustrated method embodiment are not described in detail here.

[0222] Those skilled in the art will appreciate that various aspects of the present disclosure may be implemented as systems, methods, or program products. Therefore, various aspects of the present disclosure may be implemented in the following forms: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, which may be collectively referred to herein as "circuits," "modules," or "systems."

[0223] Refer to the following Figure 14 1400 according to this embodiment of the present disclosure will be described. Figure 14 The electronic device 1400 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0224] like Figure 14 As shown, electronic device 1400 is implemented as a general-purpose computing device. Components of electronic device 1400 may include, but are not limited to, the aforementioned at least one processing unit 1410, the aforementioned at least one storage unit 1420, and a bus 1430 connecting various system components (including storage unit 1420 and processing unit 1410).

[0225] In which, the storage unit stores program code, and the program code can be executed by the processing unit 1410, so that the processing unit 1410 performs the following steps: obtaining a first test voltage collected by the voltage detection circuit, and determining a target adjustment voltage based on the first test voltage, wherein the target adjustment voltage is used to characterize the amount of potential increase of the bit line to be tested due to the coupling effect between the bit lines.

[0226] The storage unit 1420 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 14201 and / or a cache memory unit 14202 , and may further include a read-only memory unit (ROM) 14203 .

[0227] The storage unit 1420 may also include a program / utility 14204 having a set (at least one) of program modules 14205, such program modules 14205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0228] The bus 1430 may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0229] The electronic device 1400 may also communicate with one or more external devices 1440 (e.g., a keyboard, a pointing device, a Bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 1400, and / or any device that enables the electronic device 1400 to communicate with one or more other computing devices (e.g., a router, a modem, etc.). Such communication may occur through an input / output (I / O) interface 1450.

[0230] Furthermore, the electronic device 1400 can also communicate with one or more networks (eg, a local area network (LAN), a wide area network (WAN) and / or a public network, such as the Internet) through the network adapter 1460 .

[0231] like Figure 14 As shown, the network adapter 1460 communicates with other modules of the electronic device 1400 via the bus 1430 .

[0232] It should be understood that although not shown in the figures, other hardware and / or software modules may be used in conjunction with the electronic device 1400, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0233] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

[0234] In an exemplary embodiment of the present disclosure, a computer-readable storage medium is further provided, which may be a readable signal medium or a readable storage medium. The computer-readable storage medium stores a program product capable of implementing the above method of the present disclosure.

[0235] In some possible embodiments, various aspects of the present disclosure may also be implemented in the form of a program product, which includes program code. When the program product is run on a terminal device, the program code is used to cause the terminal device to perform the following steps: obtaining a first test voltage collected by a voltage detection circuit, and determining a target adjustment voltage based on the first test voltage, wherein the target adjustment voltage is used to characterize the amount of potential raise of the bit line to be tested due to the coupling effect between the bit lines.

[0236] More specific examples of computer-readable storage media in the present disclosure may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fibers, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0237] In the present disclosure, a computer-readable storage medium may include a data signal transmitted in baseband or as part of a carrier wave, wherein the computer-readable program code is carried. Such a transmitted data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof.

[0238] A readable signal medium may also be any readable medium other than a readable storage medium that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

[0239] In some examples, program code embodied on a computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0240] In a specific implementation, the program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as C or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a stand-alone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0241] Where a remote computing device is involved, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0242] The present disclosure provides a computer program product or computer program, comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the following steps: obtaining a first test voltage acquired by a voltage detection circuit; and determining a target adjustment voltage based on the first test voltage, wherein the target adjustment voltage is used to characterize the amount of potential increase on a bit line to be tested due to an inter-bit line coupling effect.

[0243] It should be noted that although several modules or units of the device for action execution are mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units to be concretized.

[0244] Furthermore, although the steps of the method of the present disclosure are described in a particular order in the accompanying drawings, this does not require or imply that the steps must be performed in this particular order, or that all steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0245] Through the description of the above embodiments, those skilled in the art will readily understand that the example embodiments described herein may be implemented by software, or by combining software with necessary hardware.

[0246] Therefore, the technical solution according to the embodiment of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiment of the present disclosure.

[0247] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein.

[0248] This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A method for characterizing bit line coupling effects, characterized in that: The method comprises: Providing a test element group TEG test structure, the TEG test structure comprising a bit line to be tested and a plurality of adjacent bit lines of the bit line to be tested; When the bit line to be tested is in an idle state and a preset working voltage is applied to the plurality of adjacent bit lines, detecting a first test voltage of the bit line to be tested compared to a reference potential end; Determining a target adjustment voltage based on the first test voltage, wherein the target adjustment voltage is used to characterize an amount of potential raising of the bit line to be tested due to an inter-bit line coupling effect; The plurality of adjacent bit lines include: N first bit lines located on one side of the bit line to be tested, and N second bit lines located on the other side of the bit line to be tested, wherein N is any positive integer; The method further comprises: When the bit line to be tested is in the idle state, the N first bit lines are applied with the preset working voltage, and the N second bit lines are applied with a negative voltage of the preset working voltage, detecting a second test voltage of the bit line to be tested compared to the reference potential end; The step of determining a target adjustment voltage based on the first test voltage includes: The target adjustment voltage is determined based on the first test voltage and the second test voltage.

2. The method according to claim 1, characterized in that The determining the target adjustment voltage based on the first test voltage and the second test voltage includes: determining a voltage difference between the first test voltage and the second test voltage; determining a voltage ratio between an actual operating voltage of the bit line and the preset operating voltage; The target adjustment voltage is determined based on the voltage ratio and the voltage difference.

3. The method according to claim 1, characterized in that After determining the target adjustment voltage based on the first test voltage, the method further includes: During a wafer testing phase, the target adjustment voltage is used to reduce a sensing margin of a memory cell to be tested; The reduced sensing margin is used to perform failed bit detection on the memory cell to be tested.

4. The method according to claim 3, characterized in that The reduced sensing margin is used to perform failed bit detection on a memory cell to be tested, wherein the memory cell to be tested is a memory cell to which data is written according to a preset write test mode. The preset write test mode is a test mode for writing 1 into all the memory cells of the test sub-array to which the memory cell to be tested belongs.

5. The method according to claim 1, wherein Before detecting the first test voltage of the bit line to be tested compared to the reference potential end, the method further includes: Connecting the bit line to be tested and the plurality of adjacent bit lines to a reference potential; When the current of the bit line to be tested is less than or equal to a preset current threshold and the currents of the plurality of adjacent bit lines are less than or equal to the preset current threshold, the bit line to be tested is controlled to be in an idle state and the preset operating voltage is applied to the plurality of adjacent bit lines.

6. The method according to claim 1, wherein Before detecting the second test voltage of the bit line to be tested compared to the reference potential end, the method further includes: Connecting the bit line to be tested and the plurality of adjacent bit lines to a reference potential; When the current of the bit line to be tested is less than or equal to a preset current threshold, and the current of the multiple adjacent bit lines is less than or equal to the preset current threshold, the bit line to be tested is controlled to be in an idle state, the preset operating voltage is applied to the N first bit lines, and a negative voltage of the preset operating voltage is applied to the N second bit lines.

7. The method according to claim 1, characterized in that The TEG test structure further includes a reference bit line, Before detecting the first test voltage of the bit line to be tested compared to the reference potential end, the method further includes: connecting the reference bit line to a reference potential; The detecting of a first test voltage of the bit line to be tested compared to a reference potential terminal includes: A potential difference between the bit line to be tested and the reference bit line is detected, and the potential difference is used as the first test voltage.

8. A device for characterizing bit line coupling effects, characterized in that: include: A TEG test structure, the TEG test structure comprising a bit line to be tested and a plurality of adjacent bit lines of the bit line to be tested; a voltage detection circuit, configured to detect a first test voltage of the bit line to be tested compared to a reference potential end when the bit line to be tested is in an idle state and a preset working voltage is applied to the plurality of adjacent bit lines; a processor, configured to determine a target adjustment voltage based on the first test voltage, wherein the target adjustment voltage is used to characterize an amount of potential raising of the bit line to be tested due to an inter-bit line coupling effect; The plurality of adjacent bit lines include: N first bit lines located on one side of the bit line to be tested, and N second bit lines located on the other side of the bit line to be tested, wherein N is any positive integer; When the bit line to be tested is in the idle state, the N first bit lines are applied with the preset working voltage, and the N second bit lines are applied with a negative voltage of the preset working voltage, detecting a second test voltage of the bit line to be tested compared to the reference potential end; The step of determining a target adjustment voltage based on the first test voltage includes: The target adjustment voltage is determined based on the first test voltage and the second test voltage.

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