Antifuse structure, antifuse array, operation method thereof, and memory

Abstract

Embodiments of the present disclosure provide an antifuse structure, an antifuse array, an operation method thereof, and a memory, wherein the antifuse structure includes: a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure formed on the surface of an active area and arranged in sequence; the first gate structure includes a first gate dielectric layer and a first gate conductive layer; the second gate structure includes a second gate dielectric layer and a second gate conductive layer; the third gate structure includes a third gate dielectric layer and a third gate conductive layer; the fourth gate structure includes a fourth gate dielectric layer and a fourth gate conductive layer; wherein the size of the first gate dielectric layer in the third direction is smaller than the size of the second gate dielectric layer in the third direction, and the first gate conductive layer and the second gate conductive layer are electrically connected to each other outside the active area; the size of the fourth gate dielectric layer in the third direction is smaller than the size of the third gate dielectric layer in the third direction, and the fourth gate conductive layer and the third gate conductive layer are electrically connected to each other outside the active area.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and is related to but not limited to an antifuse structure, an antifuse array, an operation method thereof, and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) chips typically have redundant memory cells. These redundant cells can replace defective memory cells in the DRAM chip to repair the DRAM. Repairing DRAM chips often requires the use of one-time programming devices, such as antifuses.

[0003] An antifuse cell typically consists of an antifuse device, a select transistor, and a bit line. During programming, a high voltage is applied to the programming gate of the antifuse device, a low voltage is applied to the bit line, and the select transistor is turned on. The high voltage difference between the programming gate and the bit line causes the gate oxide layer of the programming gate to break down, completing the programming operation. With the rapid development of integrated circuit technology and the continuous reduction in chip size, the area of ​​the antifuse cell must also be reduced to save valuable space in the memory array. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide an antifuse structure, an antifuse array, an operating method thereof, and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides an antifuse structure, comprising:

[0006] A substrate comprising an active region extending along a first direction and a first doping region, a second doping region, a third doping region, a fourth doping region, and a fifth doping region formed in the active region and arranged in sequence;

[0007] a first gate structure located on a surface of the active region between the first doped region and the second doped region, comprising a first gate dielectric layer located on the active region and a first gate conductive layer located on the first gate dielectric layer;

[0008] a second gate structure located on a surface of the active region between the second doping region and the third doping region, comprising a second gate dielectric layer located on the active region and a second gate conductive layer located on the second gate dielectric layer;

[0009] a third gate structure located on the surface of the active region between the third doping region and the fourth doping region, comprising a third gate dielectric layer located on the active region and a third gate conductive layer located on the third gate dielectric layer;

[0010] a fourth gate structure, located on the surface of the active region between the fourth doping region and the fifth doping region, comprising a fourth gate dielectric layer located on the active region and a fourth gate conductive layer located on the fourth gate dielectric layer;

[0011] wherein the size of the first gate dielectric layer in the third direction is smaller than the size of the second gate dielectric layer in the third direction, and the first gate conductive layer and the second gate conductive layer are electrically connected to each other outside the active area; the size of the fourth gate dielectric layer in the third direction is smaller than the size of the third gate dielectric layer in the third direction, and the fourth gate conductive layer and the third gate conductive layer are electrically connected to each other outside the active area;

[0012] The third direction is perpendicular to the plane where the substrate is located.

[0013] In some embodiments, a size of the first gate structure in the first direction is smaller than a size of the second gate structure in the first direction;

[0014] A size of the fourth gate structure in the first direction is smaller than a size of the third gate structure in the first direction.

[0015] In some embodiments, the antifuse structure is an axisymmetric structure, and an extension direction of a symmetry axis of the antifuse structure is perpendicular to the first direction.

[0016] In some embodiments, the antifuse structure further comprises:

[0017] a first conductive line electrically connected to the first doped region;

[0018] a second conductive line electrically connected to the first gate structure and the second gate structure;

[0019] a third conductive line electrically connected to the third doped region;

[0020] a fourth conductive line, electrically connected to the third gate structure and the fourth gate structure;

[0021] A fifth conductive line is electrically connected to the fifth doped region.

[0022] In a second aspect, an embodiment of the present disclosure provides an antifuse array, comprising a plurality of antifuse structures as described in the first aspect; wherein,

[0023] A plurality of the antifuse structures are arranged in an array along the first direction and the second direction;

[0024] The first gate conductive layers of the antifuse structures arranged along the second direction are electrically connected, and the second gate conductive layers of the antifuse structures arranged along the second direction are electrically connected, and the first gate conductive layers and the second gate conductive layers are electrically connected to each other outside the antifuse array;

[0025] The third gate conductive layers of the antifuse structures arranged along the second direction are electrically connected, and the fourth gate conductive layers of the antifuse structures arranged along the second direction are electrically connected, and the third gate conductive layers and the fourth gate conductive layers are electrically connected to each other outside the antifuse array;

[0026] The second direction is parallel to the plane where the substrate is located and intersects with the first direction.

[0027] In some embodiments, the third conductive line extends along the second direction, and a row of the antifuse structures arranged along the second direction is connected to the same third conductive line;

[0028] The first conductive line extends along the first direction, and a row of the antifuse structures arranged along the first direction is connected to the same first conductive line;

[0029] The fifth conductive line extends along the first direction, and a row of the antifuse structures arranged along the first direction is connected to the same fifth conductive line.

[0030] In a third aspect, embodiments of the present disclosure provide an operating method for an antifuse structure, which is applied to the antifuse structure described in the first aspect, wherein the first gate structure, the first doped region, and the second doped region constitute a first programming device, and the fourth gate structure, the fourth doped region, and the fifth doped region constitute a second programming device; the method comprising:

[0031] During a programming operation, a first voltage is applied to the first conductive line, a voltage greater than or equal to the first voltage is applied to the third conductive line, and a second voltage is applied to the second conductive line, so as to break down the first programming device; or a first voltage is applied to the fifth conductive line, a voltage greater than or equal to the first voltage is applied to the third conductive line, and a third voltage is applied to the fourth conductive line, so as to break down the second programming device;

[0032] During a read operation, the second conductive line is first set to the first voltage and then left floating, the first voltage is applied to the third conductive line, and the fourth voltage is applied to the first conductive line, so as to read data from the first programming device; or the fourth conductive line is first set to the first voltage and then left floating, the first voltage is applied to the third conductive line, and the fourth voltage is applied to the fifth conductive line, so as to read data from the second programming device;

[0033] Among them, the second voltage and the third voltage are both greater than the fourth voltage, the fourth voltage is greater than the first voltage, and the first voltage is zero voltage or ground voltage; the difference between the second voltage and the first voltage is greater than the breakdown voltage of the first programming device, and the difference between the third voltage and the first voltage is greater than the breakdown voltage of the second programming device.

[0034] In some embodiments, the second gate structure, the second doping region, and the third doping region constitute a first switching device, and the third gate structure, the third doping region, and the fourth doping region constitute a second switching device; and reading data from the programming device includes:

[0035] When the first programming device is broken down, the first switching device is turned on to obtain a first current in a path between the first conductive line and the third conductive line, thereby reading the first data; or when the second programming device is broken down, the second switching device is turned on to obtain a second current in a path between the third conductive line and the fifth conductive line, thereby reading the first data;

[0036] When the first programming device is not broken down, the first switching device is closed, and a third current in a path between the first conductive line and the third conductive line is obtained to read the second data; or when the second programming device is not broken down, the second switching device is closed, and a fourth current in a path between the third conductive line and the fifth conductive line is obtained to read the second data;

[0037] Among them, the first current is greater than the third current, and the second current is greater than the fourth current; the difference between the second voltage and the first voltage is less than the breakdown voltage of the first switching device, and the difference between the third voltage and the first voltage is less than the breakdown voltage of the second switching device.

[0038] In a fourth aspect, embodiments of the present disclosure provide an antifuse array operating method, comprising: applying to the antifuse array described in the second aspect; wherein the antifuse array includes a plurality of antifuse structures, each antifuse structure including a plurality of first programming devices and a plurality of second programming devices; the method comprising:

[0039] During a programming operation, a first voltage is applied to the third conductive line and the first conductive line or the fifth conductive line corresponding to a programming device to be programmed, and a fifth voltage is applied to the second conductive line or the fourth conductive line corresponding to the programming device to be programmed, so as to breakdown the programming device to be programmed. Simultaneously, a fourth voltage is applied to the other first conductive lines and the other fifth conductive lines in the antifuse array, and the first voltage is applied to the other second conductive lines and the other fourth conductive lines in the antifuse array, so as to prevent breakdown of programming devices other than the programming device to be programmed. The programming device to be programmed is any one of the plurality of first programming devices or the plurality of second programming devices.

[0040] During a read operation, the second conductive line or the corresponding fourth conductive line corresponding to the programming device to be read is first set to the first voltage and then left floating, the first voltage is applied to the third conductive line corresponding to the programming device to be read, and the fourth voltage is applied to the first conductive line or the corresponding fifth conductive line corresponding to the programming device to be read, so as to read data from the programming device to be read. At the same time, the other first conductive lines or the other fifth conductive lines in the antifuse array are left floating, and the fourth voltage is applied to the other second conductive lines, the other third conductive lines, and the other fourth conductive lines in the antifuse array.

[0041] Among them, the fifth voltage is greater than the fourth voltage, the fourth voltage is greater than the first voltage, and the first voltage is zero voltage or ground voltage; the difference between the fifth voltage and the first voltage is greater than the breakdown voltage of the programming device to be programmed, and is less than the breakdown voltage of the switching device corresponding to the programming device to be programmed; the difference between the fourth voltage and the first voltage is less than the breakdown voltage of the programming device to be read.

[0042] In a fifth aspect, an embodiment of the present disclosure provides a memory comprising the antifuse array as described in the second aspect.

[0043] The embodiments of the present disclosure provide an anti-fuse structure, an anti-fuse array, an operation method thereof, and a memory. Since the first gate conductive layer and the second gate conductive layer in the anti-fuse structure are electrically connected to each other, and the third gate conductive layer and the fourth gate conductive layer are electrically connected to each other, the first gate structure and the second gate structure are connected in parallel, and the third gate structure and the fourth gate structure are connected in parallel. In other words, the programming device and the corresponding switching device in the anti-fuse structure are connected in parallel, so that the programming device can be directly programmed without opening the switching device. Therefore, the width of the switching device (that is, the width of the active area corresponding to the second gate structure and the third gate structure) can be reduced, thereby reducing the area of ​​the anti-fuse structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0045] Figure 1 Schematic diagram of the structure of an antifuse array;

[0046] Figure 2 A schematic diagram of the layout structure of an antifuse structure;

[0047] Figure 3 A schematic diagram of the local structure of an antifuse array;

[0048] Figure 4 A schematic diagram of a layout structure of an antifuse structure provided in an embodiment of the present disclosure Figure 1 ;

[0049] Figure 5 A schematic diagram of a layout structure of an antifuse structure provided in an embodiment of the present disclosure Figure 2 ;

[0050] Figure 6 A schematic diagram of a layout structure of an antifuse structure provided in an embodiment of the present disclosure Figure 3 ;

[0051] Figure 7 A schematic structural diagram of an antifuse array provided in an embodiment of the present disclosure;

[0052] Figure 8 A circuit structure diagram of an anti-fuse structure is also provided for the embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0054] In the following description, numerous details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0055] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0056] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0057] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0058] The antifuse structure is a one-time programmable (OTP) device. Once the antifuse structure is programmed, the stored data is permanent. Due to this feature, the antifuse structure is widely used in memories such as DRAM.

[0059] Figure 1Schematic diagram of the structure of an antifuse array, such as Figure 1 As shown, the antifuse array 100 includes a plurality of antifuse structures 100 a arranged at intervals. The plurality of antifuse structures 100 a are arranged at intervals along a first direction (ie, the X-axis direction shown in the figure).

[0060] Figure 2 is a schematic diagram of a layout structure of an antifuse structure 100a, such as Figure 2 As shown, the antifuse structure 100a includes a first antifuse unit 11 and a second antifuse unit 12. The first antifuse unit 11 includes a first gate 101, a first source / drain region 102, a second gate 103, and a second source / drain region 104. The first gate 101 and the active region 13 located below the first gate 101 constitute a first antifuse device, and the first source / drain region 102, the second gate 103, and the second source / drain region 104 constitute a first select transistor. The second antifuse unit 12 includes a third gate 105, a second source / drain region 104, a third source / drain region 106, and a fourth gate 107. The fourth gate 107 and the active region 13 located below the fourth gate 107 constitute a second antifuse device, and the second source / drain region 104, the third gate 105, and the third source / drain region 106 constitute a second select transistor. The first and second select transistors share the second source / drain region 104, and a bit line connection structure 108 electrically connects the second source / drain region 104 to a bit line (BL) 109. For the anti-fuse structure 100a, when writing, a high voltage (for example, about 5 to 5.5 volts) is applied to the first gate 101 of the first anti-fuse device, 0V is set at the corresponding BL terminal, and the first selection transistor is turned on, so that the thin gate oxide of the first anti-fuse device is broken down under the high voltage and the resistance is significantly reduced, thereby achieving the purpose of writing; or, when writing, a high voltage (for example, about 5 to 5.5 volts) is applied to the fourth gate 107 of the second anti-fuse device, 0V is set at the corresponding BL terminal, and the second selection transistor is turned on, so that the thin gate oxide of the second anti-fuse device is broken down under the high voltage and the resistance is significantly reduced, thereby achieving the purpose of writing.

[0061] Please continue to refer to Figure 1 and Figure 2 The first gate 101, the second gate 103, the third gate 105 and the fourth gate 107 in the anti-fuse structure 100a are arranged in sequence along the second direction (i.e., the Y-axis direction shown in the figure), so that the length of the anti-fuse structure 100a is longer, thereby making the area of ​​the anti-fuse array 100 including multiple anti-fuse structures 100a larger.

[0062] Also, please continue to refer to Figure 2When the width of the first selection transistor or the second selection transistor (i.e., the dimension along the X-axis direction) is small, the voltage division of the channel of the first selection transistor or the second selection transistor increases, so that the voltage difference across the corresponding first anti-fuse device or the second anti-fuse device becomes smaller, weakening the energy used to break down the gate oxide in the first anti-fuse device or the second anti-fuse device, resulting in the first anti-fuse device or the second anti-fuse device being difficult to write. Therefore, the first selection transistor or the second selection transistor needs to have a larger width, which limits the reduction of the area of ​​the anti-fuse structure 100a.

[0063] Figure 3 is a partial structural diagram of the antifuse array 100, refer to Figure 3 Typically, an anti-fuse doping region 301 is provided in the substrate below the first and second anti-fuse devices. Due to the extremely high doping concentration of the anti-fuse doping region 301, the doping ions in the anti-fuse doping region 301 may diffuse to the vicinity of the channel doping region 302 of the first and second selection transistors during the high-temperature process, thereby reducing the turn-on voltage of the first and second selection transistors and increasing the risk of leakage. Therefore, the distance A between the first gate 101 and the second gate 103 and the distance C between the third gate 105 and the fourth gate 107 must be maintained at a large distance, for example, significantly larger than the distance B between the second gate 103 and the third gate 105. This makes it difficult to further reduce the length of the anti-fuse structure 100a.

[0064] Based on this, the embodiments of the present disclosure provide an anti-fuse structure, an anti-fuse array, an operation method thereof, and a memory. Since the first gate conductive layer and the second gate conductive layer in the anti-fuse structure are electrically connected to each other, and the third gate conductive layer and the fourth gate conductive layer are electrically connected to each other, the first gate structure and the second gate structure are connected in parallel, and the third gate structure and the fourth gate structure are connected in parallel. That is to say, the programming device and the corresponding switching device in the anti-fuse structure are connected in parallel, so that the programming device can be directly programmed without opening the switching device. Therefore, the width of the switching device (that is, the width of the active area corresponding to the second gate structure and the third gate structure) can be reduced, thereby reducing the area of ​​the anti-fuse structure.

[0065] The antifuse structure and the antifuse array in the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0066] Before introducing the embodiments of the present disclosure, the three directions that may be used to describe the three-dimensional structure in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis and Z-axis directions. The substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, the direction intersecting (for example, perpendicular) with the top surface and the bottom surface of the substrate is defined as the third direction. In the directions of the top surface and the bottom surface of the substrate (that is, the plane where the substrate is located), two directions intersecting (for example, perpendicular to each other) are defined. For example, the direction in which the active area extends can be defined as the first direction, and the plane direction of the substrate can be determined based on the first direction and the second direction. In the embodiment of the present disclosure, the first direction, the second direction and the third direction may be perpendicular to each other. In other embodiments, the first direction, the second direction and the third direction may not be perpendicular. In the embodiment of the present disclosure, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.

[0067] An embodiment of the present disclosure provides an antifuse structure, Figure 4 and Figure 5 A schematic diagram of the layout structure of the antifuse structure provided in the embodiment of the present disclosure is shown in FIG. Figure 4 and Figure 5 As shown, the antifuse structure 200 includes: a substrate, an active region extending along the X-axis direction, and a first doping region 211, a second doping region 212, a third doping region 213, a fourth doping region 214 and a fifth doping region 215 formed in the active region and arranged in sequence;

[0068] A first gate structure 220 is located on the surface of the active region between the first doping region 211 and the second doping region 212 , and includes a first gate dielectric layer 221 located on the active region and a first gate conductive layer 222 located on the first gate dielectric layer 221 ;

[0069] The second gate structure 230 is located on the surface of the active region between the second doping region 212 and the third doping region 213 , and includes a second gate dielectric layer 231 located on the active region and a second gate conductive layer 232 located on the second gate dielectric layer 231 ;

[0070] The third gate structure 240 is located on the surface of the active region between the third doping region 213 and the fourth doping region 214 , and includes a third gate dielectric layer 241 located on the active region and a third gate conductive layer 242 located on the third gate dielectric layer 241 ;

[0071] The fourth gate structure 250 is located on the surface of the active region between the fourth doping region 214 and the fifth doping region 215 , and includes a fourth gate dielectric layer 251 located on the active region and a fourth gate conductive layer 252 located on the fourth gate dielectric layer 251 ;

[0072] Among them, the size of the first gate dielectric layer 221 in the Z-axis direction is smaller than the size of the second gate dielectric layer 231 in the Z-axis direction, and the first gate conductive layer 222 and the second gate conductive layer 232 are electrically connected to each other outside the active area; the size of the fourth gate dielectric layer 251 in the Z-axis direction is smaller than the size of the third gate dielectric layer 241 in the Z-axis direction, and the fourth gate conductive layer 252 and the third gate conductive layer 242 are electrically connected to each other outside the active area.

[0073] In this disclosure, please continue to refer to Figure 4 and Figure 5 The anti-fuse structure 200 includes a first anti-fuse unit 200 a and a second anti-fuse unit 200 b arranged along the X-axis direction, and the first anti-fuse unit 200 a and the second anti-fuse unit 200 b share a third doped region 213 .

[0074] Furthermore, the first anti-fuse unit 200a includes a first programming device and a first switching device. The first gate structure 220, together with the first doped region 211 and the second doped region 212 located on both sides of the first gate structure 220, forms a first programming device (programming transistor). The second gate structure 230, together with the second doped region 212 and the third doped region 213 located on both sides of the second gate structure 230, forms a first switching device (switching transistor). The first gate structure 220 covers the surface of the active region between the first doped region 211 and the second doped region 212 and extends outward along the Y-axis. The second gate structure 230 covers the surface of the active region between the second doped region 212 and the third doped region 213 and extends outward along the Y-axis. The second anti-fuse unit 200b includes a second programming device and a second switching device. The fourth gate structure 250 and the fourth doping region 214 and the fifth doping region 215 located on both sides of the fourth gate structure 250 constitute a second programming device (programming transistor); the third gate structure 240 and the third doping region 213 and the fourth doping region 214 located on both sides of the third gate structure 240 constitute a second switching device (switching transistor); wherein, the third gate structure 240 covers the surface of the active area between the third doping region 213 and the fourth doping region 214, and extends outward along the Y-axis direction; the fourth gate structure 250 covers the surface of the active area between the fourth doping region 214 and the fifth doping region 215, and extends outward along the Y-axis direction.

[0075] Please continue to refer to Figure 4 and Figure 5 The first switching device and the second switching device share the third doping region 213; the third doping region 213 can serve as one of the source region or the drain region of the first switching device and the second switching device; the second doping region 212 can serve as the other of the source region or the drain region of the first switching device, and the fourth doping region 214 can serve as the other of the source region or the drain region of the second switching device.

[0076] In the embodiment of the present disclosure, the second gate dielectric layer 231 and the third gate dielectric layer 241 can have equal dimensions in the Z-axis direction, thereby allowing them to be formed in a single process, simplifying the process and bringing the performance of the first switching device and the second switching device closer together. The first gate dielectric layer 221 and the fourth gate dielectric layer 251 can have equal dimensions in the Z-axis direction, thereby allowing them to be formed in a single process, simplifying the process and bringing the performance of the first programming device and the second programming device closer together.

[0077] In the embodiment of the present disclosure, the first gate conductive layer 222 and the second gate conductive layer 232 can be connected to each other at one end or both ends outside the active region, and the fourth gate conductive layer 252 and the third gate conductive layer 242 can be connected to each other at one end or both ends outside the active region; for example, please continue to refer to Figure 4 The first gate conductive layer 222 and the second gate conductive layer 232 are electrically connected to each other at both ends outside the active region, and the fourth gate conductive layer 252 and the third gate conductive layer 242 are electrically connected to each other at both ends outside the active region. In this way, the first gate structure and the second gate structure are connected in parallel, and the third gate structure and the fourth gate structure are connected in parallel. In other words, the programming device and the corresponding switching device in the antifuse structure are connected in parallel, so that the programming device can be directly programmed without turning on the switching device. Therefore, the width of the switching device (i.e., the width of the active region corresponding to the second gate structure and the third gate structure) can be reduced, thereby reducing the area of ​​the antifuse structure.

[0078] In the embodiment of the present disclosure, the materials of the first gate dielectric layer 221, the second gate dielectric layer 231, the third gate dielectric layer 241 and the fourth gate dielectric layer 251 can be silicon oxide or other suitable materials; the materials of the first gate conductive layer 222, the second gate conductive layer 232, the third gate conductive layer 242 and the fourth gate conductive layer 252 can be any material with good conductive properties, such as any one or more combinations of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), copper (Cu), and polycrystalline silicon.

[0079] In some embodiments, please refer to Figure 4 , the dimension d1 of the first gate structure 220 in the X-axis direction is smaller than the dimension d2 of the second gate structure 230 in the X-axis direction; the dimension d3 of the fourth gate structure 250 in the X-axis direction is smaller than the dimension d4 of the third gate structure 240 in the X-axis direction.

[0080] In the disclosed embodiment, because the spacing between the first doping region 211 and the second doping region 212 is smaller than the spacing between the second doping region 212 and the third doping region 213, the dimension d1 of the first gate structure 220 in the X-axis direction is smaller than the dimension d2 of the second gate structure 230 in the X-axis direction. Because the spacing between the fifth doping region 215 and the fourth doping region 214 is smaller than the spacing between the fourth doping region 214 and the third doping region 213, the dimension d3 of the fourth gate structure 250 in the X-axis direction is smaller than the dimension d4 of the third gate structure 240 in the X-axis direction. This reduces the range of the breakdown points of the first gate dielectric layer 221 and the fourth gate dielectric layer 251, thereby improving the resistance stability of the first programming device and the second programming device after breakdown, thereby not affecting subsequent read operations.

[0081] In some embodiments, please refer to Figure 4 and Figure 5 The antifuse structure is an axisymmetric structure, and the extension direction of the symmetry axis of the antifuse structure is perpendicular to the X-axis direction.

[0082] In this way, on the one hand, the pattern of the layout of the anti-fuse structure 200 is made more uniform, which is conducive to further reducing the difficulty of actual process production; on the other hand, the performance of the two anti-fuse units in the anti-fuse structure 200 is made closer, so that when programming and reading the two anti-fuse units, consistent voltages can be applied to the corresponding wires, simplifying the operation method.

[0083] In some embodiments, please refer to Figure 4 and Figure 6 The anti-fuse structure 200 also includes: a first conductive line 261, electrically connected to the first doped region 211; a second conductive line 271, electrically connected to the first gate structure 220 and the second gate structure; a third conductive line 281, electrically connected to the third doped region 213; a fourth conductive line 291, electrically connected to the third gate structure 240 and the fourth gate structure 250; and a fifth conductive line 201, the fifth conductive line 201 is electrically connected to the fifth doped region 215.

[0084] Here, the second conductive wire 271 connects the first gate conductive layer 222 and the second gate conductive layer 232 and leads out, that is, the second conductive wire 271 is simultaneously connected to the first switching device and the first programming device, so as to turn on the corresponding first switching device or break down the first programming device by applying voltage to the second conductive wire 271; the fourth conductive wire 291 connects the third gate conductive layer 242 and the fourth gate conductive layer 252 and leads out, that is, the fourth conductive wire 291 is simultaneously connected to the second switching device and the second programming device, so as to turn on the corresponding second switching device or break down the second programming device by applying voltage to the fourth conductive wire 291.

[0085] In the embodiment of the present disclosure, the third conductive line 281 is connected to the third doped region 213, and the data written into the first programming device can be detected by reading the current between the third conductive line 281 and the first conductive line 261; alternatively, the data written into the second programming device can be detected by reading the current between the third conductive line 281 and the fifth conductive line 201.

[0086] It should be noted that the second conductive line 271, the third conductive line 281, and the fourth conductive line 291 can all extend along the Y-axis direction and can be electrically connected to the corresponding gate conductive layer via a contact plug 272, wherein the contact plug 272 can be located within the interlayer dielectric layer. The second conductive line 271, the third conductive line 281, and the fourth conductive line 291 are located on the same layer, so that in actual processing, they can be formed by patterning the same conductive material layer, simplifying the process and reducing the number of layers in the interconnect structure.

[0087] It should be noted that both the first conductive line 261 and the fifth conductive line 201 can extend along the X-axis direction, and the first conductive line 261 is electrically connected to the first doped region 211 via a contact plug 262, while the fifth conductive line 201 is electrically connected to the fifth doped region 215 via a contact plug 262. The contact plug 262 can be located within the interlayer dielectric layer. The first conductive line 261 and the fifth conductive line 201 are located on the same layer, so that in actual processing, they can be formed by patterning the same conductive material layer, simplifying the process and reducing the number of layers in the interconnect structure.

[0088] It should also be noted that the metal layer where the fourth conductive line 291, the third conductive line 281 and the second conductive line 271 are located is located below the metal layer where the first conductive line 261 and the fifth conductive line 201 are located. This can avoid circuit problems such as short circuits caused by cross contact between the conductive lines.

[0089] In the embodiment of the present disclosure, the material of the first conductive line 261, the second conductive line 271, the third conductive line 281, the fourth conductive line 291 and the fifth conductive line 201 can be any material with good conductivity, for example, any one or more combinations of titanium, titanium nitride, tungsten nitride, tungsten, cobalt, platinum, palladium, ruthenium and copper.

[0090] In another embodiment of the present disclosure, an antifuse array is provided. Figure 7 , which shows a schematic structural diagram of the antifuse array provided by an embodiment of the present disclosure. Figure 7 As shown, the antifuse array 300 includes a plurality of antifuse structures 200 as in the aforementioned embodiment; wherein the plurality of antifuse structures 200 are arranged in an array along the X-axis direction and the Y-axis direction;

[0091] The first gate conductive layers 222 of the antifuse structures 200 arranged along the Y-axis are electrically connected, and the second gate conductive layers 232 of the antifuse structures 200 arranged along the Y-axis are electrically connected. The first gate conductive layers 222 and the second gate conductive layers 232 are electrically connected to each other outside the antifuse array.

[0092] The third gate conductive layer 242 of the antifuse structure 200 arranged along the Y-axis direction is electrically connected, and the fourth gate conductive layer 252 of the antifuse structure 200 arranged along the Y-axis direction is electrically connected. The third gate conductive layer 242 and the fourth gate conductive layer 252 are electrically connected to each other on the outside of the antifuse array 300.

[0093] It should be noted that the positions of the first gate conductive layer 222, the second gate conductive layer 232, the third gate conductive layer 242 and the fourth gate conductive layer 252 in the Z-axis direction are shown in FIG. Figure 5 Please understand and I will not elaborate on it here.

[0094] In the embodiment of the present disclosure, the first gate conductive layer 222 and the second gate conductive layer 232 can be connected to each other at both ends or one end of the outer side of the antifuse array 300, and the fourth gate conductive layer 252 and the third gate conductive layer 242 can be connected to each other at both ends or one end of the outer side of the antifuse array 300; for example, please continue to refer to Figure 7 The first gate conductive layer 222 and the second gate conductive layer 232 are electrically connected to each other at both ends outside the antifuse array 300, and the fourth gate conductive layer 252 and the third gate conductive layer 242 are electrically connected to each other at both ends outside the antifuse array 300. In other words, the programming device and the corresponding switching device in the antifuse structure are connected in parallel, so that the programming device can be directly programmed without turning on the switching device. Therefore, the width of the switching device can be reduced, thereby reducing the area of ​​the antifuse structure.

[0095] In the disclosed embodiment, the gate conductive layers (i.e., the second gate conductive layer 232) of the multiple first switching devices in the multiple antifuse structures 200 arranged along the Y-axis are interconnected, enabling the multiple first switching devices in the same column to be turned on or off via a single control terminal. The gate conductive layers (i.e., the first gate conductive layer 222) of the first programming devices and the gate conductive layers of the first switching devices in the multiple antifuse structures 200 arranged along the Y-axis are both connected to the second conductive line 271. The gate conductive layers (i.e., the third gate conductive layer 242) of the multiple second switching devices in the multiple antifuse structures 200 arranged along the Y-axis are both interconnected, enabling the multiple second switching devices in the same column to be turned on or off via a single control terminal. The gate conductive layers (i.e., the fourth gate conductive layer 252) of the second programming devices and the gate conductive layers of the second switching devices in the multiple antifuse structures 200 arranged along the Y-axis are both connected to the fourth conductive line 291. In this way, through the second conductive line 271 and / or the fourth conductive line 291, during the programming operation, the current does not need to flow through the switching device, so that the transistor width of the switching device will not affect the success rate of writing to the programming device, and the width of the active area can be significantly reduced; in addition, when reading, the reading current does not flow through the thin gate oxide in the broken-down programming device, but flows through the transistor of the switching device. Since the channel of the transistor of the switching device can be regarded as a conductor, even if the width of the transistor is small, the low-resistance reading current can still be high enough, thereby making the reading accuracy higher.

[0096] In the disclosed embodiment, the first gate conductive layer 222 is connected to the second gate conductive layer 232, and the fourth gate conductive layer 252 is connected to the third gate conductive layer 242. This allows the first gate conductive layer 222 and the second gate conductive layer 232, as well as the fourth gate conductive layer 252 and the third gate conductive layer 242, to be formed simultaneously in an actual process. As the size of the antifuse array continues to shrink, the process window is becoming increasingly narrow. Connecting the gate conductive layers and forming them simultaneously helps expand the process window and reduce manufacturing difficulty.

[0097] In some embodiments, please refer to Figure 7 The third conductive line 281 extends along the Y-axis direction, and a row of anti-fuse structures 200 arranged along the Y-axis direction is connected to the same third conductive line 281; the first conductive line 261 extends along the X-axis direction, and a row of anti-fuse structures 200 arranged along the X-axis direction is connected to the same first conductive line 261; the fifth conductive line 201 extends along the X-axis direction, and a row of anti-fuse structures 200 arranged along the X-axis direction is connected to the same fifth conductive line 201.

[0098] It should be noted that all conductive lines in the antifuse array 300 may be electrically connected to corresponding components via contact plugs, wherein the contact plugs may be located in the interlayer dielectric layer.

[0099] In the embodiments of the present disclosure, reference Figure 7 The active areas of adjacent antifuse structures 200 can be separated by shallow trench isolation structures (not shown). Multiple antifuse structures 200 in the same row are spaced the same distance apart along the X-axis. Multiple antifuse structures 200 in the same column are spaced the same distance apart along the Y-axis. This allows for a uniform layout of the antifuse array 300, effectively utilizing the layout area and reducing the complexity of the antifuse array 300 manufacturing process. Since the length and area of ​​the antifuse structures 200 are reduced, the area of ​​the antifuse array 300 is effectively reduced.

[0100] It should be noted that Figure 7 Only eight antifuse structures 200 are shown in the antifuse array 300 in FIG. 1 . In actual implementation, the antifuse array 300 may include multiple rows and multiple columns formed by multiple antifuse structures 200 .

[0101] The antifuse structure 200 in the antifuse array 300 provided in the embodiment of the present disclosure is similar to the antifuse structure 200 in the above embodiment. For technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and no further details will be given here.

[0102] Another embodiment of the present disclosure further provides an operating method of an antifuse structure, which is applicable to the aforementioned embodiment. Figures 4 to 6 The anti-fuse structure 200 is shown. The first gate structure 220, the first doping region 211, and the second doping region 212 form a first programming device (programming transistor), and the fourth gate structure 250, the fourth doping region 214, and the fifth doping region 215 form a second programming device (programming transistor). The operating method of the anti-fuse structure includes:

[0103] During a programming operation, a first voltage is applied to the first conductive line 261, a voltage greater than or equal to the first voltage is applied to the third conductive line 281, and a second voltage is applied to the second conductive line 271 to break down the first programming device; or a first voltage is applied to the fifth conductive line 201, a voltage greater than or equal to the first voltage is applied to the third conductive line 281, and a third voltage is applied to the fourth conductive line 291 to break down the second programming device;

[0104] In the embodiment of the present disclosure, when programming the first programming device, the first voltage is zero voltage or ground voltage, and the difference between the second voltage and the first voltage is greater than the breakdown voltage of the first programming device and less than the breakdown voltage of the first switching device, so that the first programming device can be broken down under the second voltage and the first switching device will not be broken down. Here, the second voltage can be in the range of 5 to 5.5V, for example, it can be 5.1V, 5.3V or 5.4V, etc.

[0105] In the embodiment of the present disclosure, when programming the second programming device, the third voltage is greater than or equal to the breakdown voltage of the second programming device and less than the breakdown voltage of the second switching device, so that the second programming device can be broken down under the third voltage and the second switching device will not be broken down. Here, the third voltage can be in the range of 5 to 5.5V, for example, it can be 5.1V, 5.3V or 5.4V, etc.

[0106] In the embodiment of the present disclosure, the third conductive line 281 can be applied with zero voltage or a positive voltage (for example, a voltage greater than the first voltage and less than the second voltage). In this way, the voltage difference between the first programming device and the third conductive line 281 can be reduced, or the voltage difference between the second programming device and the third conductive line 281 can be reduced, thereby facilitating the programming operation of the first programming device and the second programming device.

[0107] It should be noted that the voltages of programming devices and corresponding switching devices that do not require programming operations are set to zero voltage or ground voltage. For example, when programming the first programming device, zero voltage or ground voltage is applied to the fourth conductive line 291 and the fifth conductive line 201. For another example, when programming the second programming device, zero voltage or ground voltage is applied to the first conductive line 261 and the second conductive line 271.

[0108] During the reading operation, the second conductive line 271 is first set to the first voltage and then suspended, the first voltage is applied to the third conductive line 281, and the fourth voltage is applied to the first conductive line 261 to read the data in the first programming device; or, the fourth conductive line 291 is first set to the first voltage and then suspended, the first voltage is applied to the third conductive line 281, and the fourth voltage is applied to the fifth conductive line 201 to read the data in the second programming device.

[0109] In the embodiment of the present disclosure, when reading data from the first programming device, the fourth voltage is greater than the first voltage, and the difference between the fourth voltage and the first voltage is less than the breakdown voltage of the first programming device. For example, the fourth voltage may be 1 V. When reading data from the second programming device, the fourth voltage is greater than the first voltage, and the difference between the fourth voltage and the first voltage is less than the breakdown voltage of the second programming device. For example, the fourth voltage may be 1 V.

[0110] It should be noted that in the embodiment of the present disclosure, the voltages of programming devices and corresponding switching devices that do not require a read operation are set to zero voltage or ground voltage. For example, when reading the first programming device, zero voltage or ground voltage is applied to the fourth conductive line 291 and the fifth conductive line 201. For another example, when reading the second programming device, zero voltage or ground voltage is applied to the first conductive line 261 and the second conductive line 271.

[0111] In some embodiments, the second gate structure 230, the second doping region 212, and the third doping region 213 form a first switching device, and the third gate structure 240, the third doping region 213, and the fourth doping region 214 form a second switching device. Reading data in the programming device includes:

[0112] When the first programming device is broken down, the first switching device is turned on to obtain the first current in the path between the first conductive line 261 and the third conductive line 281, thereby reading the first data; or when the second programming device is broken down, the second switching device is turned on to obtain the second current in the path between the third conductive line 281 and the fifth conductive line 201, thereby reading the first data;

[0113] During reading, a fourth voltage is applied to the first conductive line 261 and a first voltage is applied to the third conductive line 281. At this time, since the first programming device is broken down and the first programming device and the first switching device are connected in series, the first switching device is turned on, and a first current flows between the first conductive line 261 and the third conductive line 281, thereby reading data "1." Alternatively, a fourth voltage is applied to the fifth conductive line 201 and a first voltage is applied to the third conductive line 281. At this time, since the second programming device is broken down and the second programming device and the second switching device are connected in series, the second switching device is turned on, resulting in a second current flowing between the fifth conductive line 201 and the third conductive line 281, thereby reading data "1."

[0114] When the first programming device is not broken down, the first switching device is closed, and the third current in the path between the first conductive line 261 and the third conductive line 281 is obtained to read the second data; or when the second programming device is not broken down, the second switching device is closed, and the fourth current in the path between the third conductive line 281 and the fifth conductive line 201 is obtained to read the second data;

[0115] During reading, the fourth voltage is applied to the first conductive line 261 and the first voltage is applied to the third conductive line 281. At this time, because the first programming device has not broken down and the first programming device and the first switching device are connected in series, the first switching device cannot open, and a third current flows between the first conductive line 261 and the third conductive line 281, thereby reading data "0." Alternatively, the fourth voltage is applied to the fifth conductive line 201 and the first voltage is applied to the third conductive line 281. At this time, because the second programming device has not broken down and the second programming device and the second switching device are connected in series, the second switching device cannot open. Therefore, a fourth current flows between the fifth conductive line 201 and the third conductive line 281, thereby reading data "0."

[0116] The first current is greater than the third current, and the second current is greater than the fourth current; and the magnitudes of the third current and the fourth current may be zero.

[0117] In the embodiment of the present disclosure, since the programming device and the corresponding switching device are connected in parallel, the current does not need to flow through the switching device during the programming operation. In this way, the transistor width of the switching device (refer to Figure 4 The size of the switching device along the Y-axis will not affect the success rate of programming device writing, thereby significantly reducing the width of the active area; in addition, when reading, the reading current does not flow through the thin gate oxide in the broken-down programming device, but flows through the transistor of the switching device. Since the conductive channel of the transistor can be regarded as a conductor, even if the width of the transistor is small, the low-resistance read current can still be high enough, thereby making the reading accuracy higher.

[0118] Furthermore, when reading from the first conductive line 261 or the fifth conductive line 201 (ie, the bit line corresponding to the programming device), there is no need to additionally dope the substrate, thereby making the length of the antifuse structure (see Figure 4 The size of the antifuse structure along the Y-axis can also be significantly reduced.

[0119] Another embodiment of the present disclosure further provides an operation method of an antifuse array, which is applied to the aforementioned embodiment. Figure 7 The antifuse array 300 is shown. Figure 7 , wherein the antifuse array includes a plurality of antifuse structures, each antifuse structure includes a plurality of first programming devices and a plurality of second programming devices; the method includes:

[0120] During a programming operation, a first voltage is applied to the third conductive line 281 and the first conductive line 261 or the fifth conductive line 201 corresponding to the programming device to be programmed, and a fifth voltage is applied to the second conductive line 271 or the fourth conductive line 291 corresponding to the programming device to be programmed, so as to breakdown the programming device to be programmed. Simultaneously, a fourth voltage is applied to the other first conductive lines 261 and the other fifth conductive lines 201 in the antifuse array, and a first voltage is applied to the other second conductive lines 271 and the other fourth conductive lines 291 in the antifuse array, so as to prevent the other programming devices except the programming device to be programmed from being broken down. The programming device to be programmed is any one of the multiple first programming devices or the multiple second programming devices.

[0121] In the embodiment of the present disclosure, the first voltage is zero voltage or ground voltage, and the fifth voltage is greater than or equal to the breakdown voltage of the programming device to be programmed and less than the breakdown voltage of the switching device corresponding to the programming device to be programmed, so that the programming device to be programmed can be broken down at the fifth voltage and the switching device corresponding to it will not be broken down. Here, the fifth voltage can be in the range of 5 to 5.5V, for example, it can be 5.1V, 5.3V or 5.4V, etc.

[0122] During a read operation, the second conductive line 271 or the corresponding fourth conductive line 291 corresponding to the programming device to be read is first set to a first voltage and then left floating. A first voltage is applied to the third conductive line 281 corresponding to the programming device to be read, and a fourth voltage is applied to the first conductive line 261 or the corresponding fifth conductive line 201 corresponding to the programming device to be read, so as to read data from the programming device to be read. At the same time, the other first conductive lines 261 or the other fifth conductive lines 201 in the antifuse array are left floating, and the fourth voltage is applied to the other second conductive lines 271, the other third conductive lines 281, and the other fourth conductive lines 291 in the antifuse array.

[0123] The fifth voltage is greater than the fourth voltage, the fourth voltage is greater than the first voltage, and the difference between the fourth voltage and the first voltage is less than the breakdown voltage of the programming device to be read. For example, the fourth voltage may be 1 V. The difference between the fifth voltage and the first voltage is greater than the breakdown voltage of the programming device to be programmed and less than the breakdown voltage of the switching device corresponding to the programming device to be programmed.

[0124] The operating method of the antifuse array 300 provided in the embodiment of the present disclosure is similar to the operating method of the antifuse structure 200 in the above embodiment. For technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and no further details will be given here.

[0125] Figure 8 The present disclosure also provides a circuit structure diagram of an anti-fuse structure, combined with Figure 4 and Figure 8 The anti-fuse structure includes a first anti-fuse unit 200a and a second anti-fuse unit 200b connected in series. The first anti-fuse unit 200a includes a first programming device AF1 and a first switch device XG1, and the first programming device AF1 and the first switch device XG1 are connected in parallel; the second anti-fuse unit 200b includes a second programming device AF2 and a second switch device XG2, and the second programming device AF2 and the second switch device XG2 are connected in parallel, wherein the first anti-fuse unit 200a and the second anti-fuse unit 200b share a third conductive line 281 (corresponding to Figure 8 Middle control wire Ctrl).

[0126] Next, the programming and reading operations on the first programming device AF1 are described in detail as an example. The programming and reading operations on the second programming device AF2 are similar to those on the first programming device AF1 and are not described in detail here.

[0127] Programming operation: When writing to the first programming device AF1, the first conductive line 261 (corresponding to Figure 8 The middle bit line BL1) is applied with 0V, the first switch device XG1 is applied with a high voltage, the voltage on the third conductive line 281 can be 0V, or a positive voltage can be applied (to reduce the voltage difference between the first programming device AF1 and the first switch device XG1), thereby reducing the voltage difference suffered by the transistor of the first switch device XG1 and improving the degradation of the transistor of the first switch device XG1. The second programming device AF2 and the fifth conductive line 201 (corresponding to Figure 8 0V is applied to the middle line BL2).

[0128] Read Operation: Before the read operation, all switching devices are set to 0V. When reading the first programming device AF1, the first programming device AF1 is left floating, a positive voltage is applied to the first conductive line 261, and 0V is applied to the third conductive line 281. 0V is applied to the second programming device AF2 and the fifth conductive line 201.

[0129] If the first programming device AF1 is written and the thin gate oxide corresponding to the first programming device AF1 is broken down, the two ends of the first programming device AF1 will become the same positive voltage as the first conductive line 261. At this time, the transistor of the first switching device XG1 is turned on, and a large current will flow between the first conductive line 261 and the third conductive line 281.

[0130] If the first programming device AF1 has not been written and the thin gate oxide of the first programming device AF1 is intact, the terminal connected to the first switching device XG1 will remain at 0V. At this time, the transistor of the first switching device XG1 is turned off, and no current will flow between the first conductive line 261 and the third conductive line 281.

[0131] Another embodiment of the present disclosure further provides a memory, comprising the antifuse array 300 in any of the aforementioned embodiments (refer to Figure 7 ), the antifuse array 300 includes the antifuse structure 200 in any of the aforementioned embodiments (refer to Figure 4 );

[0132] Among them, multiple anti-fuse structures 200 are arranged in an array along the X-axis direction and the Y-axis direction; the first gate conductive layer 222 of the anti-fuse structure 200 arranged along the Y-axis direction is electrically connected, and the second gate conductive layer 232 of the anti-fuse structure 200 arranged along the Y-axis direction is electrically connected, and the first gate conductive layer 222 and the second gate conductive layer 232 are electrically connected to each other on the outside of the anti-fuse array; the third gate conductive layer 242 of the anti-fuse structure 200 arranged along the Y-axis direction is electrically connected, and the fourth gate conductive layer 252 of the anti-fuse structure 200 arranged along the Y-axis direction is electrically connected, and the third gate conductive layer 242 and the fourth gate conductive layer 252 are electrically connected to each other on the outside of the anti-fuse array 300.

[0133] The antifuse structure 200 includes: a substrate, including an active region extending along the X-axis direction and a first doping region 211, a second doping region 212, a third doping region 213, a fourth doping region 214 and a fifth doping region 215 formed in the active region and arranged in sequence; a first gate structure 220, located on the surface of the active region between the first doping region 211 and the second doping region 212, including a first gate dielectric layer 221 located on the active region and a first gate conductive layer 222 located on the first gate dielectric layer 221; a second gate structure 230, located on the active region between the second doping region 212 and the third doping region 213. a surface of the active region, including a second gate dielectric layer 231 located on the active region and a second gate conductive layer 232 located on the second gate dielectric layer 231; a third gate structure 240, located on the surface of the active region between the third doping region 213 and the fourth doping region 214, including a third gate dielectric layer 241 located on the active region and a third gate conductive layer 242 located on the third gate dielectric layer 241; a fourth gate structure 250, located on the surface of the active region between the fourth doping region 214 and the fifth doping region 215, including a fourth gate dielectric layer 251 located on the active region and a fourth gate conductive layer 252 located on the fourth gate dielectric layer 251;

[0134] Among them, the size of the first gate dielectric layer 221 in the Z-axis direction is smaller than the size of the second gate dielectric layer 231 in the Z-axis direction, and the first gate conductive layer 222 and the second gate conductive layer 232 are electrically connected to each other outside the active area; the size of the fourth gate dielectric layer 251 in the Z-axis direction is smaller than the size of the third gate dielectric layer 241 in the Z-axis direction, and the fourth gate conductive layer 252 and the third gate conductive layer 242 are electrically connected to each other outside the active area.

[0135] In some embodiments, the memory may include but is not limited to random access memory (RAM), such as dynamic random access memory (DRAM).

[0136] In the disclosed embodiment, the memory includes the aforementioned antifuse array 300 . Since the aforementioned antifuse array 300 has a relatively small area, the integration of the memory can be improved, thereby effectively increasing the storage capacity of the memory and improving its performance.

[0137] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in non-targeted ways. The structural embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0138] The features disclosed in several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0139] The above are only some embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An antifuse structure, characterized in that: include: A substrate comprising an active region extending along a first direction and a first doping region, a second doping region, a third doping region, a fourth doping region, and a fifth doping region formed in the active region and arranged in sequence; a first gate structure located on a surface of the active region between the first doped region and the second doped region, comprising a first gate dielectric layer located on the active region and a first gate conductive layer located on the first gate dielectric layer; a second gate structure located on a surface of the active region between the second doping region and the third doping region, comprising a second gate dielectric layer located on the active region and a second gate conductive layer located on the second gate dielectric layer; a third gate structure located on the surface of the active region between the third doping region and the fourth doping region, comprising a third gate dielectric layer located on the active region and a third gate conductive layer located on the third gate dielectric layer; a fourth gate structure, located on the surface of the active region between the fourth doping region and the fifth doping region, comprising a fourth gate dielectric layer located on the active region and a fourth gate conductive layer located on the fourth gate dielectric layer; wherein the size of the first gate dielectric layer in the third direction is smaller than the size of the second gate dielectric layer in the third direction, and the first gate conductive layer and the second gate conductive layer are electrically connected to each other outside the active area; the size of the fourth gate dielectric layer in the third direction is smaller than the size of the third gate dielectric layer in the third direction, and the fourth gate conductive layer and the third gate conductive layer are electrically connected to each other outside the active area; The third direction is perpendicular to the plane where the substrate is located.

2. The antifuse structure according to claim 1, wherein: The size of the first gate structure in the first direction is smaller than the size of the second gate structure in the first direction; A size of the fourth gate structure in the first direction is smaller than a size of the third gate structure in the first direction.

3. The antifuse structure according to claim 2, wherein: The antifuse structure is an axisymmetric structure, and an extending direction of a symmetry axis of the antifuse structure is perpendicular to the first direction.

4. The antifuse structure according to any one of claims 1 to 3, wherein: The antifuse structure further includes: a first conductive line electrically connected to the first doped region; a second conductive line electrically connected to the first gate structure and the second gate structure; a third conductive line electrically connected to the third doped region; a fourth conductive line, electrically connected to the third gate structure and the fourth gate structure; A fifth conductive line is electrically connected to the fifth doped region.

5. An antifuse array, characterized in that: comprising a plurality of antifuse structures as claimed in claim 4; wherein, A plurality of the antifuse structures are arranged in an array along the first direction and the second direction; The first gate conductive layers of the antifuse structures arranged along the second direction are electrically connected, and the second gate conductive layers of the antifuse structures arranged along the second direction are electrically connected, and the first gate conductive layers and the second gate conductive layers are electrically connected to each other outside the antifuse array; The third gate conductive layers of the antifuse structures arranged along the second direction are electrically connected, and the fourth gate conductive layers of the antifuse structures arranged along the second direction are electrically connected, and the third gate conductive layers and the fourth gate conductive layers are electrically connected to each other outside the antifuse array; The second direction is parallel to the plane where the substrate is located and intersects with the first direction.

6. The antifuse array according to claim 5, wherein: The third conductive line extends along the second direction, and a row of the antifuse structures arranged along the second direction is connected to the same third conductive line; The first conductive line extends along the first direction, and a row of the antifuse structures arranged along the first direction is connected to the same first conductive line; The fifth conductive line extends along the first direction, and a row of the antifuse structures arranged along the first direction is connected to the same fifth conductive line.

7. A method for operating an antifuse structure, characterized in that: The antifuse structure according to claim 4, wherein the first gate structure, the first doped region, and the second doped region constitute a first programming device, and the fourth gate structure, the fourth doped region, and the fifth doped region constitute a second programming device; and the method comprises: During a programming operation, a first voltage is applied to the first conductive line, a voltage greater than or equal to the first voltage is applied to the third conductive line, and a second voltage is applied to the second conductive line, so as to break down the first programming device; or a first voltage is applied to the fifth conductive line, a voltage greater than or equal to the first voltage is applied to the third conductive line, and a third voltage is applied to the fourth conductive line, so as to break down the second programming device; During a read operation, the second conductive line is first set to the first voltage and then left floating, the first voltage is applied to the third conductive line, and the fourth voltage is applied to the first conductive line, so as to read data from the first programming device; or the fourth conductive line is first set to the first voltage and then left floating, the first voltage is applied to the third conductive line, and the fourth voltage is applied to the fifth conductive line, so as to read data from the second programming device; Among them, the second voltage and the third voltage are both greater than the fourth voltage, the fourth voltage is greater than the first voltage, and the first voltage is zero voltage or ground voltage; the difference between the second voltage and the first voltage is greater than the breakdown voltage of the first programming device, and the difference between the third voltage and the first voltage is greater than the breakdown voltage of the second programming device.

8. The operating method according to claim 7, characterized in that: The second gate structure, the second doping region and the third doping region constitute a first switching device, and the third gate structure, the third doping region and the fourth doping region constitute a second switching device; Reading data in the programming device, comprising: When the first programming device is broken down, the first switching device is turned on to obtain a first current in a path between the first conductive line and the third conductive line, thereby reading the first data; or when the second programming device is broken down, the second switching device is turned on to obtain a second current in a path between the third conductive line and the fifth conductive line, thereby reading the first data; When the first programming device is not broken down, the first switching device is closed, and a third current in a path between the first conductive line and the third conductive line is obtained to read the second data; or when the second programming device is not broken down, the second switching device is closed, and a fourth current in a path between the third conductive line and the fifth conductive line is obtained to read the second data; Among them, the first current is greater than the third current, and the second current is greater than the fourth current; the difference between the second voltage and the first voltage is less than the breakdown voltage of the first switching device, and the difference between the third voltage and the first voltage is less than the breakdown voltage of the second switching device.

9. A method for operating an antifuse array, characterized in that: The antifuse array according to claim 5 or 6, wherein the antifuse array comprises a plurality of antifuse structures, each antifuse structure comprising a plurality of first programming devices and a plurality of second programming devices; the method comprising: During a programming operation, a first voltage is applied to the third conductive line and the first conductive line or the fifth conductive line corresponding to a programming device to be programmed, and a fifth voltage is applied to the second conductive line or the fourth conductive line corresponding to the programming device to be programmed, so as to breakdown the programming device to be programmed. Simultaneously, a fourth voltage is applied to the other first conductive lines and the other fifth conductive lines in the antifuse array, and the first voltage is applied to the other second conductive lines and the other fourth conductive lines in the antifuse array, so as to prevent breakdown of programming devices other than the programming device to be programmed. The programming device to be programmed is any one of the plurality of first programming devices or the plurality of second programming devices. During a read operation, the second conductive line or the corresponding fourth conductive line corresponding to the programming device to be read is first set to the first voltage and then left floating, the first voltage is applied to the third conductive line corresponding to the programming device to be read, and the fourth voltage is applied to the first conductive line or the corresponding fifth conductive line corresponding to the programming device to be read, so as to read data from the programming device to be read. At the same time, the other first conductive lines or the other fifth conductive lines in the antifuse array are left floating, and the fourth voltage is applied to the other second conductive lines, the other third conductive lines, and the other fourth conductive lines in the antifuse array. Among them, the fifth voltage is greater than the fourth voltage, the fourth voltage is greater than the first voltage, and the first voltage is zero voltage or ground voltage; the difference between the fifth voltage and the first voltage is greater than the breakdown voltage of the programming device to be programmed, and is less than the breakdown voltage of the switching device corresponding to the programming device to be programmed; the difference between the fourth voltage and the first voltage is less than the breakdown voltage of the programming device to be read.

10. A memory, characterized in that: Comprising the antifuse array as claimed in claim 5 or 6.

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