Power Devices

Abstract

The present invention provides a power device, which includes: a liner provided with a conductive layer; a chip provided on the conductive layer; a control component including a mounting substrate and a resistor element provided on the mounting substrate; wherein a mounting position is provided on the conductive layer, one surface of the mounting substrate in the thickness direction thereof is connected to the mounting position, and the resistor element is located on another surface of the mounting substrate in the thickness direction thereof. The technical solution provided by the present application can solve the problem of a high risk of failure of the interconnection process of the resistor element in the related art.

Description

Technical Field

[0001] The present invention relates to the technical field of power devices, and in particular to a power device. Background Art

[0002] At present, the scale and proportion of wind and solar power and other new energy sources connected to the power grid will continue to increase. In order to meet the large-scale development and utilization of renewable energy, power electronic devices play an irreplaceable role in the construction of strong smart grids and the access of new energy sources. Silicon carbide (SiC) devices have the advantages of high voltage resistance, strong current capacity, high operating frequency, and low switching loss. They are suitable for high temperature, high voltage, high frequency, and high power applications. The widespread use of silicon carbide devices in new energy may bring about changes in new power system equipment and technological progress.

[0003] Since the rated current of a single silicon carbide chip is limited, it is necessary to design a multi-chip parallel package in actual application, that is, to use it in the form of a module, which can increase the current level on the one hand and reduce the overall parasitic parameters and design cost of the system on the other hand. When parallel application is adopted, the parallel silicon carbide chips or devices are affected by the chip parameters and packaging parameters, and the fast switching speed of silicon carbide may cause unbalanced current between parallel chips or devices, increasing the risk of failure during the fast switching process.

[0004] In related technologies, series gate resistors are often used to control the switching characteristics of silicon carbide devices, thereby effectively alleviating the module current sharing problem under switching transients. The current process temperature resistance of gate resistors is relatively low, generally below 250°C, while the maximum temperature of the currently popular interconnection process exceeds this temperature, thus increasing the risk of gate resistor failure and the packaging cost of the entire device. Summary of the invention

[0005] The present invention provides a power device to solve the problem of high risk of failure in the interconnection process of resistor elements in the related art.

[0006] The present invention provides a power device, which includes: a liner provided with a conductive layer; a chip provided on the conductive layer; a control component, including a mounting substrate and a resistor element provided on the mounting substrate; wherein a mounting position is provided on the conductive layer, one of the surfaces of the mounting substrate in the thickness direction thereof is connected to the mounting position, and the resistor element is located on the other surface of the mounting substrate in the thickness direction thereof.

[0007] Furthermore, the mounting substrate includes a substrate body and a first metal layer arranged on the substrate body, the substrate body is connected to the mounting position, and the resistance element is arranged on the first metal layer.

[0008] Furthermore, the mounting substrate further includes a second metal layer, the first metal layer and the second metal layer are respectively located on two sides of the substrate body, and the substrate body is connected to the mounting position through the second metal layer.

[0009] Furthermore, the substrate body is a ceramic substrate.

[0010] Furthermore, the substrate body is connected to the mounting position by welding, sintering or bonding.

[0011] Furthermore, the second metal layer is connected to the mounting position by welding.

[0012] Furthermore, the first metal layer and the second metal layer are both copper.

[0013] Further, the resistance element includes a gate resistor.

[0014] Furthermore, the power device includes a plurality of chips, and two adjacent chips are separated by a control component.

[0015] Furthermore, the conductive layer includes a first conductive layer and a second conductive layer, both of which are axisymmetric structures, and the symmetry axes of the first conductive layer and the second conductive layer extend along the first direction. Multiple chips and multiple control components are arranged on the first conductive layer and the second conductive layer, and the multiple chips and multiple control components on the first conductive layer are symmetrically arranged on both sides of the symmetry axis, and the multiple chips and multiple control components on the second conductive layer are symmetrically arranged on both sides of the symmetry axis.

[0016] Furthermore, the first conductive layer includes a first sub-conductive layer and two second sub-conductive layers, the first sub-conductive layer and the second sub-conductive layer are arranged at intervals, the axis of the first sub-conductive layer is coaxial with the symmetry axis, the two second sub-conductive layers are respectively located on both sides of the first sub-conductive layer in a second direction perpendicular to the first direction, chips and control components are arranged on the two second sub-conductive layers, the upper surfaces of the chips on the two second sub-conductive layers are conductively connected to the first sub-conductive layer, and the first sub-conductive layer is conductively connected to the second conductive layer.

[0017] Furthermore, the first sub-conductive layer includes a first segment and a second segment which are perpendicular to each other, the axis of the first segment is coaxial with the axis of symmetry, one end of the first segment is connected to the middle of the second segment, the second segment is arranged between the first segment and the second conductive layer, and the two second sub-conductive layers are respectively located on both sides of the first segment in the second direction, the upper surfaces of the chips on the two second sub-conductive layers are conductively connected to the first segment, and the second segment is conductively connected to the second conductive layer.

[0018] Furthermore, the second conductive layer includes a third sub-conductive layer and a fourth sub-conductive layer, the third sub-conductive layer has a notch at one end facing the first sub-conductive layer in the first direction, the fourth sub-conductive layer extends into the notch, the axis of the fourth sub-conductive layer is coaxial with the axis of symmetry, the third sub-conductive layer is provided with chips and control components at positions on both sides of the notch in the second direction, the first sub-conductive layer is conductively connected to the third sub-conductive layer, and the upper surface of the chip on the third sub-conductive layer is conductively connected to the fourth sub-conductive layer.

[0019] Furthermore, the third sub-conductive layer includes a third segment, a fourth segment and a fifth segment, the third segment and the fifth segment are located on the same side of the fourth segment, the third segment and the fifth segment are respectively connected to two ends of the fourth segment, the side wall of the third segment, the side wall of the fourth segment and the side wall of the fifth segment together form a gap, and the fourth segment is arranged at an end of the third segment away from the first conductive layer.

[0020] Furthermore, the power device further comprises a first interconnection sheet and a second interconnection sheet, the upper surface of the chip is conductively connected to the first conductive layer and / or the second conductive layer via the first interconnection sheet, and the first conductive layer is conductively connected to the second conductive layer via the second interconnection sheet.

[0021] Furthermore, the power device also includes a power terminal, which is a plate-like structure. The power terminal includes a terminal foot section, a first plate section, a second plate section and a lead-out plate section connected in sequence. The terminal foot section and the second plate section are respectively arranged at an angle to the first plate section, and the extension directions of the terminal foot section and the second plate section are opposite. The lead-out plate section is arranged at an end of the second plate section away from the first plate section.

[0022] By applying the technical solution of the present invention, the power device includes a lining, a chip and a control component. The chip is arranged on the conductive layer of the lining. By arranging the control component as a mounting substrate and a resistor element arranged on the mounting substrate, and mounting the resistor element on the conductive layer through the mounting substrate (a mounting position is arranged on the conductive layer, one of the surfaces of the mounting substrate in the thickness direction is connected to the mounting position, and the resistor element is located on the other surface of the mounting substrate in the thickness direction), a miniaturized discrete design of the control component can be realized, and after the control component itself is assembled and processed, the control component is fixed to the mounting position of the lining. Compared with the method of directly connecting the resistor element to the lining in the related art, the risk of failure of the interconnection process of the resistor element and the chain reaction of the overall failure caused by the resistor failure can be reduced or eliminated. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0024] Figure 1An exploded view of a control component of a power device provided in Embodiment 1 of the present invention is shown;

[0025] Figure 2 A schematic diagram showing the structure of a control component of a power device provided in accordance with a first embodiment of the present invention, without showing a resistance element;

[0026] Figure 3 A top view of a control component of a power device provided according to Embodiment 1 of the present invention is shown;

[0027] Figure 4 An exploded view of a control component of a power device provided in accordance with the first embodiment of the present invention from another perspective is shown;

[0028] Figure 5 An exploded view of the control component of the power device provided in the first embodiment of the present invention from another perspective is shown;

[0029] Figure 6 A cross-sectional view showing a control component of a power device provided in accordance with a first embodiment of the present invention without showing a resistance element;

[0030] Figure 7 A cross-sectional view showing a control component of a power device provided in the second embodiment of the present invention without showing a resistance element is shown;

[0031] Figure 8 A schematic diagram of assembling a control component and a fixture of a power device according to an embodiment of the present invention is shown;

[0032] Fig. 9 Shows Figure 8 Schematic diagram of the structure of the fixture;

[0033] Fig.10 A schematic diagram of a part of the structure of a power device provided in an embodiment of the present invention without power terminals is shown;

[0034] Fig.11 A partial structural schematic diagram of a power device provided with power terminals according to an embodiment of the present invention is shown;

[0035] Fig.12 A top view of a partial structure of a power device provided with power terminals according to an embodiment of the present invention is shown;

[0036] Fig.13 A schematic structural diagram of a first interconnection sheet of a power device provided in an embodiment of the present invention is shown;

[0037] Fig.14 A schematic structural diagram of a second interconnection sheet of a power device provided according to an embodiment of the present invention is shown.

[0038] The above drawings include the following reference numerals:

[0039] 10. lining plate; 11. first conductive layer; 111. first sub-conductive layer; 1111. first section; 1112. second section; 112. second sub-conductive layer; 1121. first side edge; 1122. second side edge; 12. second conductive layer; 121. third sub-conductive layer; 1211. notch; 12111. first slot section; 12112. second slot section; 12113. third slot section; 1212. third section; 1213. fourth section; 1214. fifth section; 122. fourth sub-conductive layer; 13. driving signal connected conductive layer; 14. first lining plate; 15. second lining plate; 16. conductive layer;

[0040] 20. Chip;

[0041] 30. first interconnecting sheet; 31. main body section; 32. first interface interconnecting section; 33. second interface interconnecting section; 34. wetting groove; 35. first connecting section; 36. second connecting section; 37. connecting groove;

[0042] 40. second interconnecting sheet; 41. third interface interconnecting section; 42. fourth interface interconnecting section; 43. third connecting section; 44. fourth connecting section;

[0043] 50, control component; 51, mounting substrate; 511, substrate body; 512, first metal layer; 513, second metal layer; 514, soldering piece; 52, resistor element;

[0044] 60, power terminal; 61, terminal foot section; 62, first section; 63, second section; 64, lead-out section; 65, first terminal; 66, second terminal; 67, third terminal;

[0045] 70. Clamp;

[0046] 80. Power module. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] like Figures 1 to 14As shown, the first embodiment of the present invention provides a power device, which includes a liner 10, a chip 20 and a control component 50. The liner 10 is provided with a conductive layer 16, and the chip 20 is arranged on the conductive layer 16. The control component 50 includes a mounting substrate 51 and a resistor element 52 arranged on the mounting substrate 51. Among them, a mounting position is provided on the conductive layer 16, one surface of the mounting substrate 51 in the thickness direction thereof is connected to the mounting position, and the resistor element 52 is located on the other surface of the mounting substrate 51 in the thickness direction thereof.

[0049] By using the power device provided in this embodiment, the control component 50 is set as a mounting substrate 51 and a resistor element 52 is set on the mounting substrate 51, and the resistor element 52 is mounted on the conductive layer 16 through the mounting substrate 51 (a mounting position is set on the conductive layer 16, one surface of the mounting substrate 51 in the thickness direction is connected to the mounting position, and the resistor element 52 is located on the other surface of the mounting substrate 51 in the thickness direction), so that the miniaturized discrete design of the control component 50 can be realized. After the control component 50 itself is assembled and processed, the control component 50 is fixed to the mounting position of the liner 10. Compared with the method of directly connecting the resistor element to the liner in the related art, the risk of interconnection process failure of the resistor element and the chain reaction of the overall failure caused by the resistor failure can be reduced or eliminated.

[0050] In this embodiment, the resistor element 52 includes a gate resistor. The power device controls the switching characteristics of the silicon carbide device in the form of a series gate resistor, thereby effectively alleviating the module current sharing problem under switching transients.

[0051] Specifically, this embodiment separates the gate circuit area and the power area into upper and lower side structures, aiming to avoid failure of the entire liner due to gate resistance failure caused by the process and high temperature, thereby improving the overall packaging yield.

[0052] Since the control components are miniaturized and discrete, batch production can be used to complete the interconnection of gate resistors. Since the gate resistors are not heat resistant enough, there is a probability of failure at high process temperatures. Screening can be introduced after the interconnection process to avoid potential failures. Then the control components can be flexibly fixed to the liner according to the liner layout.

[0053] Furthermore, since the mounting substrate 51 has a certain vertical insulation effect, the insulation area of ​​the horizontal surface of the liner of the power device is effectively saved.

[0054] It should be noted that, by applying the mounting substrate 51, the technical effect of vertical insulation offsetting lateral insulation can be achieved, and the insulation area of ​​the horizontal plane of the liner of the power device can be effectively reduced (that is, "the mounting substrate 51 can effectively save the insulation area of ​​the horizontal plane of the liner of the power device"). This technical effect will be particularly significant under high-voltage conditions.

[0055] like Figures 1 to 6 As shown, the mounting substrate 51 includes a substrate body 511 and a first metal layer 512 disposed on the substrate body 511. The substrate body 511 is connected to the mounting position, and the resistor element 52 is disposed on the first metal layer 512. The first metal layer 512 is conductively connected to the resistor element 52.

[0056] Specifically, the first metal layer 512 is copper. Copper has high electrical conductivity, can reduce resistance, and improve current transmission efficiency. In addition, copper also has good thermal conductivity, which helps to dissipate heat of power devices and improve the stability and life of power devices.

[0057] like Figure 1 As shown, in this embodiment, the mounting substrate 51 also includes a second metal layer 513, the first metal layer 512 and the second metal layer 513 are respectively located on both sides of the substrate body 511, and the substrate body 511 is connected to the mounting position through the second metal layer 513, so that the second metal layer 513 can be used to improve the heat dissipation performance and structural stability of the control component (small warping under heat load).

[0058] The thickness of the first metal layer 512 and the second metal layer 513 is between 0.15 mm and 1.2 mm, and the thickness of the substrate body 511 is between 0.2 mm and 3 mm.

[0059] Specifically, the thickness of the first metal layer 512 and the second metal layer 513 can be 0.15 mm, 0.4 mm, 0.6 mm, 0.8 mm, 1 mm, 1.2 mm, and any other value between 0.15 mm and 1.2 mm. The thickness of the substrate body 511 can be 0.2 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, and any other value between 0.2 mm and 3 mm.

[0060] It should be noted that the ratio of the thickness of the first metal layer 512 and the second metal layer 513 to the thickness of the substrate body 511 is between 0.05 and 6.

[0061] Specifically, the ratio of the thickness of the first metal layer 512 and the second metal layer 513 to the thickness of the substrate body 511 can be 0.05, 0.5, 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6 and any other value between 0.05 and 6.

[0062] In practical applications, the thicknesses of the first metal layer 512 , the second metal layer 513 , and the substrate body 511 are determined according to the vertical insulation requirements, so that the control component 50 meets the vertical insulation requirements.

[0063] It should be noted that in Figure 2 In the embodiment, the second metal layer 513 (not shown in the figure) is located between the soldering piece 514 and the substrate body 511 .

[0064] In this embodiment, the second metal layer 513 is connected to the mounting position by melting and then solidifying (welding) solder, which has the advantage of a firm connection. The second metal layer 513 is copper.

[0065] In other embodiments, the second metal layer 513 is connected to the mounting position by bonding, which has the advantages of simple connection and easy assembly.

[0066] Specifically, the substrate body 511 is a ceramic substrate, which has a good insulation effect and can effectively avoid the influence of power-side heating on the resistance element, thereby improving the reliability of the device under high-temperature applications.

[0067] Ceramic substrates help improve the efficiency, stability and safety of power electronic systems through their unique thermal, mechanical and electrical properties. Ceramic substrates have high thermal conductivity, large heat capacity and strong heat diffusion function, which can effectively conduct the heat generated by the chip in the power module to the outside to achieve good heat dissipation effect. Ceramic substrates have strong electrical insulation capabilities, protecting users from the impact of the electrical system while ensuring electrical safety inside the module.

[0068] Specifically, ceramic substrates can be made of ceramic materials such as aluminum oxide, aluminum nitride, silicon nitride, zirconium oxide, and beryllium oxide. Aluminum oxide has excellent mechanical strength and chemical corrosion resistance, and is suitable for applications with high durability requirements. Zirconia is known for its outstanding toughness and high temperature resistance, and performs well in high temperature and high stress environments. Aluminum nitride has high thermal conductivity and low expansion coefficient, can effectively dissipate heat, and is suitable for high-power electronic devices. The diversity and excellent properties of these ceramic materials provide a wide range of choices and significant performance improvements for the design and application of silicon carbide devices.

[0069] It should be noted that the process of the substrate body 511 includes:

[0070] DBC (Direct Bonded Copper): A composite substrate is made by sintering copper foil directly to the surface of Al2O3 and AlN ceramics at high temperature through hot melt bonding. Due to the high eutectic bonding strength between copper foil and ceramics, the copper thickness of DBC substrates can generally be 100μm to 600μm. At the same time, ceramics and copper have good thermal conductivity, and DBC substrates also have good thermal stability;

[0071] DPC (Direct Plating Copper): It is a ceramic circuit processing technology developed on the basis of ceramic thin film processing. Ceramic is used as the circuit substrate, a metal layer is composited on the substrate surface by sputtering process, and the circuit is formed by electroplating and photolithography process;

[0072] AMB (Active Metal Brazing): AMB is developed based on DBC technology. At high temperature, AgCu solder containing active elements Ti and Zr wets and reacts at the interface between ceramic and metal, thereby achieving heterogeneous bonding between ceramic and metal.

[0073] In other embodiments, the substrate body 511 may be made of a polymer composite board.

[0074] In order to further illustrate the power device provided in this embodiment, the following is explained in conjunction with the packaging method:

[0075] like Figure 8 and Fig. 9 As shown, firstly, the gate resistor is fixed to the mounting substrate separately by using interconnection processes such as reflow soldering, which is different from the previous direct welding of the gate resistor and the chip on a liner. On the one hand, due to the small size of the control component, the space of the fixture 70, which could only realize the interconnection and molding of 4 liner plates at one time, can now place several times more control components in a matrix, thus realizing the batch interconnection of the gate resistors; on the other hand, since the interconnection process temperature can exceed the calibrated temperature resistance of the existing gate resistors, causing some resistors to fail during the process, the present solution can screen out the gate resistors that fail after the process;

[0076] The assembled control assembly is then attached to the liner.

[0077] Traditional modules generally design the gate resistors on the same power liner plane, and the interconnection process needs to be completed in one step. If a single gate resistor fails, the entire liner will fail. In addition, to ensure the insulation capacity of the module, the gate resistor area of ​​the traditional design occupies a large liner area, affecting the overall power density of the module. This embodiment designs a flexible gate resistor packaging solution to avoid the failure of the entire liner caused by the gate resistor failure caused by the process and high temperature, thereby improving the overall packaging yield.

[0078] like Fig.10 As shown, the power device includes a plurality of chips 20 , and two adjacent chips 20 are separated by a control component 50 so that the chips are evenly dispersed and arranged.

[0079] In this embodiment, two adjacent chips 20 are separated by a control component 50 , and “two adjacent chips 20 ” refer to two adjacent chips 20 on the same continuous conductive layer.

[0080] like Fig.10 As shown, the conductive layer 16 includes a first conductive layer 11 and a second conductive layer 12, both of which are axisymmetric structures, and the symmetry axes of the first conductive layer 11 and the second conductive layer 12 extend along the first direction. A plurality of chips 20 and a plurality of control components 50 are arranged on the first conductive layer 11 and the second conductive layer 12, and the plurality of chips 20 and the plurality of control components 50 on the first conductive layer 11 are symmetrically arranged on both sides of the symmetry axis, and the plurality of chips 20 and the plurality of control components 50 on the second conductive layer 12 are symmetrically arranged on both sides of the symmetry axis. By setting the first conductive layer 11 and the second conductive layer 12 as an axisymmetric structure, the chips 20 and the control components 50 can be arranged symmetrically, which is helpful for the dispersed heat dissipation of the chips 20.

[0081] Furthermore, the symmetry axes of the multiple chips 20 on the first conductive layer 11 are the same as the symmetry axes of the first conductive layer 11 and the second conductive layer 12, and the symmetry axes of the multiple chips 20 on the second conductive layer 12 are the same as the symmetry axes of the first conductive layer 11 and the second conductive layer 12, so that the interconnection lengths from the upper surface of the chip 20 to the conductive layer can be equal and moderate. In the related art, the chip layout position is relatively concentrated, resulting in different and generally longer interconnection lengths from the upper surface of the chip to the upper copper layer (conductive layer).

[0082] It should be noted that the conductive layer 16 includes a first conductive layer 11 and a second conductive layer 12, including the following two structures: the first is that the lining plate 10 is an integral structure, and the first conductive layer 11 and the second conductive layer 12 are arranged on the integral lining plate 10; the second is that the lining plate 10 is a split structure, that is, the lining plate 10 includes a first lining plate 14 and a second lining plate 15 arranged at intervals, the first lining plate 14 is provided with the first conductive layer 11, and the second lining plate 15 is provided with the second conductive layer 12.

[0083] In this embodiment, the lining plate 10 is of the second structure and includes two first lining plates 14 and two second lining plates 15 .

[0084] like Fig.10As shown, the first conductive layer 11 includes a first sub-conductive layer 111 and two second sub-conductive layers 112, the first sub-conductive layer 111 and the second sub-conductive layer 112 are arranged at intervals, the axis of the first sub-conductive layer 111 is coaxial with the symmetry axis, the two second sub-conductive layers 112 are respectively located on both sides of the first sub-conductive layer 111 in a second direction perpendicular to the first direction, the two second sub-conductive layers 112 are provided with a chip 20 and a control component 50, the upper surfaces of the chips 20 on the two second sub-conductive layers 112 are conductively connected to the first sub-conductive layer 111, and the first sub-conductive layer 111 is conductively connected to the second conductive layer 12. By separating the two second sub-conductive layers 112 with the first sub-conductive layer 111, and providing the chips 20 and the control component 50 on the two second sub-conductive layers 112, the spacing between the chips 20 can be further increased, so that the chips 20 are arranged as dispersedly as possible, and the heat dissipation performance is improved.

[0085] The first direction is the length direction of the power device, and the second direction is the width direction of the power device.

[0086] like Fig.10 As shown, the first sub-conductive layer 111 includes a first segment 1111 and a second segment 1112 which are perpendicular to each other, the axis of the first segment 1111 is coaxial with the axis of symmetry, one end of the first segment 1111 is connected to the middle of the second segment 1112, the second segment 1112 is arranged between the first segment 1111 and the second conductive layer 12, the two second sub-conductive layers 112 are respectively located on both sides of the first segment 1111 in the second direction, the upper surfaces of the chips 20 on the two second sub-conductive layers 112 are conductively connected to the first segment 1111, and the second segment 1112 is conductively connected to the second conductive layer 12. With the above structure, the perpendicular first segment 1111 and the second segment 1112 together form a T-shaped structure.

[0087] Specifically, the first section 1111 is used to separate the two second sub-conductive layers 112, so as to facilitate the dispersed arrangement of the chips 20. In addition, the second section 1112 is disposed between the first section 1111 and the second conductive layer 12, and then the second section 1112 is conductively connected to the second conductive layer 12, so as to reduce the distance between the first sub-conductive layer 111 and the second conductive layer 12, and facilitate the conductive connection between the first sub-conductive layer 111 and the second conductive layer 12.

[0088] It should be noted that the ratio of the width of the second sub-conductive layer 112 to the width of the first section 1111 is between 1.5 and 1.8. The lower limit (1.5) of the value guarantees the distance between the edge of the chip 20 and the edge of the second sub-conductive layer 112 in the second direction, and the lower limit (1.5) of the value guarantees the distance between the edge of the main section 31 of the first interconnection sheet 30 and the edge of the first section 1111 in the second direction, so that there is a minimum distance in the second direction that meets the insulation requirements. The upper limit (1.8) of the value enables the main section 31 of the first interconnection sheet 30 to have a sufficient width (dimension along the second direction) on the basis that the edge of the main section 31 of the first interconnection sheet 30 and the edge of the first section 1111 have a minimum distance in the second direction that meets the insulation requirements (under the premise) to meet the requirements of reliable interface interconnection, and at the same time have a relatively ideal heat dissipation effect (because the connection area with the first section 1111 is large).

[0089] The width of the first segment 1111 and the width of the second sub-conductive layer 112 are both dimensions in the second direction. In addition, the first interconnection sheet 30 is the first interconnection sheet mentioned below.

[0090] like Fig.10 As shown, the second sub-conductive layer 112 is a rectangular structure, which includes a first side 1121 and a second side 1122 that are perpendicular to each other, the first side 1121 is arranged away from the second section 1112 and is flush with an end of the first section 1111 away from the second section 1112, and the second side 1122 is arranged away from the first section 1111 and is flush with the end of the second section 1112. With the above structure, the shape of the first conductive layer 11 is more regular, which facilitates the uniform and dispersed arrangement of the chips 20.

[0091] It should be noted that the first side 1121 is arranged away from the second section 1112 and is flush with the end of the first section 1111 away from the second section 1112, wherein “the first side 1121 is arranged away from the second section 1112” means that the side of the four sides of the rectangular structure that is farthest from the second section 1112 is the first side 1121.

[0092] It should be noted that the second side 1122 is arranged away from the first section 1111 and is flush with the end of the second section 1112 , wherein “the second side 1122 is arranged away from the first section 1111 ” means that the side of the four sides of the rectangular structure that is farthest from the first section 1111 is the second side 1122 .

[0093] In this embodiment, the second sub-conductive layer 112 is a rectangular structure, which means that the second sub-conductive layer 112 is rectangular in the plane as a whole, but due to manufacturing reasons, its four corners are “rounded”.

[0094] like Fig.10 As shown, the second conductive layer 12 includes a third sub-conductive layer 121 and a fourth sub-conductive layer 122, the third sub-conductive layer 121 has a notch 1211 at one end facing the first sub-conductive layer 111 in the first direction, the fourth sub-conductive layer 122 extends into the notch 1211, the axis of the fourth sub-conductive layer 122 is coaxial with the axis of symmetry, the third sub-conductive layer 121 is provided with chips 20 and control components 50 at positions on both sides of the notch 1211 in the second direction, the first sub-conductive layer 111 is conductively connected to the third sub-conductive layer 121, and the upper surface of the chip 20 on the third sub-conductive layer 121 is conductively connected to the fourth sub-conductive layer 122. The fourth sub-conductive layer 122 is used to separate the chips 20 on the third sub-conductive layer 121, so that the spacing between the chips 20 can be further increased, so that the chips 20 are arranged as dispersedly as possible, and the heat dissipation performance is improved.

[0095] In this embodiment, the third sub-conductive layer 121 includes a third section 1212, a fourth section 1213 and a fifth section 1214, the third section 1212 and the fifth section 1214 are located on the same side of the fourth section 1213, the third section 1212 and the fifth section 1214 are respectively connected to the two ends of the fourth section 1213, the side wall of the third section 1212, the side wall of the fourth section 1213 and the side wall of the fifth section 1214 together form a notch 1211, and the fourth section 1213 is arranged at an end of the third section 1212 away from the first conductive layer 11. With the above structure, the third section 1212, the fourth section 1213 and the fifth section 1214 together form a U-shaped structure, and the two legs of the U-shaped structure are arranged opposite to the second section 1112 of the T-shaped structure, which can further improve the symmetry of the power module.

[0096] It should be noted that the end of the third segment 1212 away from the fourth segment 1213, the end of the fifth segment 1214 away from the fourth segment 1213 and the end of the fourth sub-conductive layer 122 away from the fourth segment 1213 are flush. With the above structure, the shape of the second conductive layer 12 is more regular, which facilitates the uniform and dispersed arrangement of the chips 20.

[0097] like Fig.10 As shown, the gap 1211 includes a first slot segment 12111, a second slot segment 12112 and a third slot segment 12113 which are connected in sequence, and the end of the first slot segment 12111 away from the second slot segment 12112 forms the mouth of the gap 1211, the slot width of the first slot segment 12111 is greater than the slot width of the third slot segment 12113, and the slot width of the second slot segment 12112 gradually decreases in the direction from the first slot segment 12111 to the third slot segment 12113, and the shape of the fourth sub-conductive layer 122 is adapted to the shape of the gap 1211.

[0098] The power device further includes a power terminal 60 , which includes a terminal foot section 61 , and the power terminal 60 is connected to the conductive layer via the terminal foot section 61 .

[0099] In this embodiment, by making the slot width of the first slot segment 12111 greater than the slot width of the third slot segment 12113, the slot width of the second slot segment 12112 gradually decreases in the direction from the first slot segment 12111 to the third slot segment 12113, the fourth sub-conductive layer 122 has a sufficient width, and thus the power terminal 60 correspondingly connected to the fourth sub-conductive layer 122 has a sufficient connection surface.

[0100] like Fig.11 As shown, the power terminal 60 includes a terminal foot plate section 61, a first plate section 62, a second plate section 63 and a lead plate section 64 connected in sequence. In this embodiment, the power terminal 60 includes a first terminal 65, a second terminal 66 and a third terminal 67, and the first terminal 65, the second terminal 66 and the third terminal 67 all include a terminal foot plate section 61, a first plate section 62, a second plate section 63 and a lead plate section 64 connected in sequence.

[0101] Specifically, the first slot section 12111 is wider than the third slot section 12113, which is intended to allow the terminal foot section 61 of the second terminal 66 to have a larger width (the width of the fourth sub-conductive layer 122 at the notch 1211 minus the distance required for insulation (about 1mm) is the maximum width of the terminal foot section under a given conductive layer width). The increase in the width of the terminal foot section is beneficial to: 1. Increasing the reliability of the interconnection between the terminal foot section and the conductive layer (a. The interface interconnection area is increased; b. If solder interconnection is used, the larger width also allows a more suitable wetting groove design); 2. The increase in the width of the terminal foot section leads to an increase in the cross-sectional area of ​​the corresponding first and second plate sections of the terminal, thereby increasing the current carrying capacity of the terminal.

[0102] In other embodiments, if the current is small, so that the width of the terminal foot plate section 61 is appropriately reduced, then the slot width of the first slot section 12111 can be equal to the slot width of the third slot section 12113 .

[0103] like Fig.13 and Fig.14 As shown, the power device further includes a first interconnection sheet 30 and a second interconnection sheet 40 . The upper surface of the chip 20 can be conductively connected to the first conductive layer 11 or the second conductive layer 12 through the first interconnection sheet 30 . The first conductive layer 11 is conductively connected to the second conductive layer 12 through the second interconnection sheet 40 .

[0104] The conductive connection between the chip 20 and the conductive layer is realized by using the sheet-shaped first interconnection sheet 30, and the conductive connection between the conductive layers is realized by using the sheet-shaped second interconnection sheet 40. The heat dissipation area of ​​the first interconnection sheet 30 and the second interconnection sheet 40 is large, which can ensure the rapid conduction of the current and heat flow. In addition, since the first conductive layer 11 and the second conductive layer 12 are both axisymmetric structures, the symmetry axes of the first conductive layer 11 and the second conductive layer 12 extend along the first direction, which can realize the symmetrical and dispersed arrangement of the conductive layers, which is helpful for the dispersed and parallel heat dissipation of the chip 20. Therefore, the first interconnection sheet 30 and the second interconnection sheet 40 can ensure the rapid conduction of the current and heat flow, and the first conductive layer 11 and the second conductive layer 12 can realize the symmetrical and dispersed arrangement of the conductive layers, which is helpful for the dispersed and parallel heat dissipation of the chip 20, thereby improving the heat dissipation capacity of the power module.

[0105] In this embodiment, the width of the first interconnecting sheet 30 is between 1.5 mm and 3.0 mm, and can be specifically 1.5 mm, 2 mm, 2.5 mm, 3.0 mm, or any other value between 1.5 mm and 3.0 mm.

[0106] The width dimension of the first interconnection sheet 30 refers to the width dimensions of the first interface interconnection segment 32 , the second interface interconnection segment 33 , the first connection segment 35 and the second connection segment 36 .

[0107] In this embodiment, the width of the second interconnecting sheet 40 is between 1.5 mm and 4.0 mm, and can be specifically 1.5 mm, 2.0 mm, 3.0 mm, 4.0 mm, or any other value between 1.5 mm and 4.0 mm.

[0108] The width dimension of the second interconnection sheet 40 refers to the width dimensions of the third interface interconnection segment 41 , the fourth interface interconnection segment 42 and the third connection segment 43 .

[0109] The ratio of the width of the first interconnection sheet 30 to the width of the chip 20 is between 0.3 and 0.6, and can be 0.3, 0.4, 0.5, 0.6, or any other value between 0.3 and 0.6.

[0110] In this embodiment, the lower limit of the numerical range of the interconnection sheet width (1.5 mm) is to ensure that the interconnection sheet has a larger width, with three considerations: a. A larger width allows the interconnection sheet to have a wetting groove in the interface interconnection section, which can achieve a three-dimensional interface layer morphology when using welding operations, and increase the interface interconnection strength. b. The increased width allows a larger interface interconnection area, increases the energy required for interface debonding, and is conducive to improving the reliability of interface interconnection. c. When the thickness of the interconnection sheet is constant, a larger width corresponds to a larger cross-sectional area, which increases the flow capacity of the interconnection sheet.

[0111] It should be noted that the increase in the thickness of the interconnecting sheet can also increase the cross-sectional area of ​​the interconnecting sheet, and thus increase the flow capacity of the interconnecting sheet. However, the increase in the thickness of the interconnecting sheet has a "cubic" effect on the increase in the stiffness of the interconnecting sheet, which is much stronger than the "linear" effect of increasing the width on the increase in stiffness, which is not conducive to the reliability of the interface interconnection.

[0112] In this embodiment, the upper limit of the numerical range of the interconnection sheet size width is determined by the width of the interface to be interconnected. For example, the width of the interface interconnection section of the first interconnection sheet 30 in the interconnectable area on the upper surface of the chip 20 is 3.07 mm, so 3.0 mm is taken downward. The width of the conductive layer of the second interconnection sheet 40 in the area to be interconnected near the first groove section 12111 is 6 mm. Considering that the third interface interconnection section 41 of the second interconnection sheet 40 and the boundary of the third sub-conductive layer 121 at the first groove section 12111 must have a recommended minimum distance of 1 mm in the second direction to meet the insulation requirements, the upper limit is 4 mm.

[0113] It should be noted that the recommended minimum distance is the minimum distance recommended from the insulation perspective during design, but this minimum distance is not the minimum limit value in the physical sense.

[0114] like Fig.13 As shown, in this embodiment, the first interconnection sheet 30 includes a main body section 31, a first interface interconnection section 32, and a second interface interconnection section 33. The lower surface of the main body section 31 is conductively connected to the first conductive layer 11 or the second conductive layer 12. The first interface interconnection section 32 is located at the side of the main body section 31 and is connected to the main body section 31, and the lower surface of the first interface interconnection section 32 is conductively connected to the upper surface of one of the two symmetrically arranged chips 20. The second interface interconnection section 33 is located at the side of the main body section 31 and is connected to the main body section 31, and the lower surface of the second interface interconnection section 33 is conductively connected to the upper surface of the other of the two symmetrically arranged chips 20.

[0115] Since the first interconnection sheet 30 connects at least two chips through the first interface interconnection section 32 and the second interface interconnection section 33, the number of connectors in the related art can be reduced, the space occupied in the power module can be reduced, the space utilization rate can be improved, and the arrangement of devices can be facilitated.

[0116] It should be noted that in the related art, the power current conduction between the components inside the power module relies on the metal interconnection interface set on the components and the connectors connecting the metal interconnection interfaces. For example, the interconnection between the upper surface of the chip and the upper copper layer. However, the existing connectors are mostly used to realize the signal connection of two interconnection interfaces. When there are multiple pairs of interfaces that need to be interconnected, such as when there are multiple pairs of chips on a liner, multiple connectors are required, which will occupy a larger space in the module, resulting in low device space utilization and placing greater restrictions on device layout.

[0117] like Fig.13 As shown, the first interconnection sheet 30 has a wetting groove 34 extending along the thickness direction thereof, and the wetting groove 34 extends along the length direction of the first interconnection sheet 30. The wetting groove 34 can wet the solder to form a solder layer with a concave upper surface, which increases the wetting boundary length of the interconnection material compared to the case where there is no groove at the interconnection interface, thereby improving the strength of the interface connection.

[0118] In this embodiment, the wetting groove 34 extends to at least one of the lower surface of the main body section 31 , the lower surface of the first interface interconnection section 32 , and the lower surface of the second interface interconnection section 33 .

[0119] It should be noted that the wetting groove 34 extends along the length direction of the first interconnection sheet 30, so that the wetting groove 34 on the first interconnection sheet 30 has a larger length, thereby making the first interconnection sheet 30 and the chip have a larger wetting boundary length, thereby improving the strength of the interface connection.

[0120] like Fig.13 As shown, the first interconnection sheet 30 further includes a first connection section 35, which is located at the side of the main body section 31, and the two ends of the first connection section 35 are respectively connected to the main body section 31 and the first interface interconnection section 32, and the highest point of the lower surface of the first connection section 35 is higher than the highest point of the lower surface of the main body section 31 and / or the highest point of the lower surface of the first interface interconnection section 32. The first interconnection sheet 30 further includes a second connection section 36, which is located at the side of the main body section 31, and the two ends of the second connection section 36 are respectively connected to the main body section 31 and the second interface interconnection section 33, and the highest point of the lower surface of the second connection section 36 is higher than the highest point of the lower surface of the main body section 31 and / or the highest point of the lower surface of the second interface interconnection section 33. The main body section 31 and the first interface interconnection section 32 are connected by the first connection section 35, and the main body section 31 and the second interface interconnection section 33 are connected by the second connection section 36, which has the advantages of simple structure and easy processing.

[0121] Since the chip is disposed on the substrate, the main body section 31 is connected to the conductive layer of the substrate, and the interface interconnection section is connected to the chip, so that there is a height difference between the main body section 31 and the interface interconnection section. Generally speaking, the lower surface of the interface interconnection section is higher than the lower surface of the main body section 31.

[0122] In this embodiment, the highest point of the lower surface of the first connecting segment 35 is higher than the highest point of the lower surface of the main body segment 31 and the highest point of the lower surface of the first interface interconnection segment 32. The highest point of the lower surface of the second connecting segment 36 is higher than the highest point of the lower surface of the main body segment 31 and the highest point of the lower surface of the second interface interconnection segment 33.

[0123] The first interface interconnection section 32 and the second interface interconnection section 33 are both flat plate structures, which can increase the contact area between the interface interconnection section and the chip, thereby improving the connection strength and heat dissipation capability. In addition, the main body section 31 is a flat plate structure, which can increase the contact area between the main body section 31 and the conductive layer, thereby improving the connection strength and heat dissipation capability.

[0124] Specifically, the first connecting section 35 and / or the second connecting section 36 are both arched plate structures, the upper surface of the first connecting section 35 is higher than the upper surface of the main section 31 and the upper surface of the first interface interconnection section 32, and the upper surface of the second connecting section 36 is higher than the upper surface of the main section 31 and the upper surface of the second interface interconnection section 33.

[0125] In this embodiment, the first connecting section 35 and the second connecting section 36 are both arched plate structures.

[0126] like Fig.13 As shown, the first interconnection sheet 30 also has a connection groove 37 extending through the thickness direction thereof. The connection groove 37 can effectively increase the flexibility of the first interconnection sheet 30, reduce the maximum interlayer stress when relative displacement occurs between different interconnection interfaces, and help improve the reliability of the interconnection interface.

[0127] like Fig.14 As shown, the second interconnection sheet 40 includes a third interface interconnection segment 41, a fourth interface interconnection segment 42 and a third connection segment 43. The lower surface of the third interface interconnection segment 41 is conductively connected to the second conductive layer 12. The lower surface of the fourth interface interconnection segment 42 is conductively connected to the first conductive layer 11. Both ends of the third connection segment 43 are connected to the third interface interconnection segment 41 and the fourth interface interconnection segment 42, respectively.

[0128] In this embodiment, the lower surface of the third connection segment 43 is higher than the lower surface of the third interface interconnection segment 41 and the lower surface of the fourth interface interconnection segment 42 .

[0129] It should be noted that the lower surface of the third interface interconnection segment 41 can be conductively connected to the second conductive layer 12 by ultrasonic terminal welding, and the lower surface of the fourth interface interconnection segment 42 can be conductively connected to the first conductive layer 11 by ultrasonic terminal welding.

[0130] Alternatively, the lower surface of the third interface interconnection segment 41 can be conductively connected to the second conductive layer 12 by welding (solder melting and resolidification), and the lower surface of the fourth interface interconnection segment 42 can be conductively connected to the first conductive layer 11 by welding (solder melting and resolidification).

[0131] In this embodiment, the third interface interconnection section 41 and the fourth interface interconnection section 42 also have a wetting groove penetrating along the thickness direction thereof, and the wetting groove on the second interconnection sheet 40 extends along the length direction of the second interconnection sheet 40 .

[0132] like Fig.14 As shown, the second interconnection sheet 40 further includes a fourth connection segment 44, the third interface interconnection segment 41, the fourth interface interconnection segment 42 and the third connection segment 43 constitute an interconnection main segment, the second interconnection sheet 40 includes two interconnection main segments, the two ends of the fourth connection segment 44 are respectively connected to the two interconnection main segments, and the lower surface of the fourth connection segment 44 is conductively connected to the first sub-conductive layer 111. By providing the fourth connection segment 44, the connection area between the second interconnection sheet 40 and the second segment 1112 can be increased, and the connection reliability can be improved.

[0133] like Fig.11 and Fig.12 As shown, the power device also includes a power terminal 60, which is a plate-like structure. The power terminal 60 includes a terminal foot section 61, a first plate section 62, a second plate section 63 and a lead-out plate section 64 connected in sequence. The terminal foot section 61 and the second plate section 63 are respectively arranged at an angle to the first plate section 62, and the extension directions of the terminal foot section 61 and the second plate section 63 are opposite. The lead-out plate section 64 is arranged at an end of the second plate section 63 away from the first plate section 62.

[0134] With the above structure, the power terminal can realize an "L"-shaped structure, so that the ultrasonic terminal welding technology can be applied to the interconnection interface at the power terminal pin, improving the reliability of the terminal interconnection. Specifically, the above structure helps to realize the interconnection with the conductive layer by ultrasonic terminal welding, thereby avoiding multiple reflow soldering and improving the overall temperature resistance of the module.

[0135] In the related art, the layout of power devices is generally a planar layout, and the chip layout position is relatively concentrated, which easily causes the power terminal to be bent greater than 90 degrees (such as 180 degrees) near the interconnection interface between it and the upper copper layer, making it impossible to use ultrasonic terminal welding technology.

[0136] It should be noted that the ultrasonic terminal welding involved in this embodiment uses a "rod-shaped probe" to squeeze the terminal pins of the power terminal in the direction perpendicular to the interconnection interface and vibrate at a high frequency to achieve the effect of interface interconnection. This embodiment involves three power terminals that are all L-shaped structures near their terminal pins, and the terminal pins are not blocked relative to the interconnection interface, so the "rod-shaped probe" can be used for ultrasonic terminal welding technology. In the related art, due to layout reasons, the power terminals are prone to bending more than 90 degrees (such as 180 degrees) at the terminal pins, resulting in overlapping projections of the power terminals in the plane of the interconnection interface, making it impossible to use ultrasonic terminal welding, that is, the terminal portion above the terminal pin blocks the "rod-shaped probe", making it unable to work normally.

[0137] In this embodiment, the power terminal 60 includes a first terminal 65, a second terminal 66 and a third terminal 67. The number of terminal pin segments 61 of the first terminal 65 and the number of terminal pin segments 61 of the third terminal 67 are both greater than the number of terminal pin segments 61 of the second terminal 66, so that the first terminal 65 and the third terminal 67 have a higher current carrying capacity.

[0138] Specifically, the number of the terminal foot plate segments 61 of the first terminal 65 and the number of the terminal foot plate segments 61 of the third terminal 67 are both 4, and the number of the terminal foot plate segments 61 of the second terminal 66 is 2.

[0139] It should be noted that, in this embodiment, the high voltage side of the liner adopts a symmetrical and dispersed layout, thereby avoiding the coupling effect caused by the concentrated heating of the chip. The symmetrical design of the liner maximizes the contact area with the bottom surface of the power terminal, and the first terminal 65 and the third terminal 67 further improve the current carrying capacity and reliability of the module by increasing the number of terminal pins.

[0140] like Fig.12 As shown, in this embodiment, the power device includes two power modules 80, and the two power modules 80 are arranged at intervals and symmetrically in the second direction to further improve the symmetry of the power device.

[0141] It should be noted that the driving signal connection conductive layer 13 is disposed on the sides of the two power modules 80 that are close to each other, which can further increase the spacing between the chips on the power modules, so that the chips are further dispersedly arranged.

[0142] like Figure 7 As shown, the second embodiment of the present invention provides a power device. The difference between the second embodiment and the first embodiment is that the structure of the mounting substrate 51 in the second embodiment is different from that in the first embodiment.

[0143] In the second embodiment, the mounting substrate 51 is not provided with the second metal layer 513 , and the substrate body 511 is connected to the mounting position by welding, sintering or bonding to fix the mounting substrate 51 on the liner 10 .

[0144] The device provided by the embodiment has the following beneficial effects:

[0145] In this solution, we separate the gate circuit area from the power area and place the gate circuit area above the power area, achieving independent packaging of gate resistors individually and in batches in the early stage, while meeting the timely and efficient screening of gate resistor components after packaging. Since the packaging process can be separated from the power area, the failure of the gate resistor caused by the process and high temperature can be effectively avoided, which leads to the failure of the entire liner, thereby improving the overall packaging yield. At the same time, the structure of this solution makes full use of the space area, increases the use area of ​​the module, and increases the flexibility of the module gate side layout.

[0146] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0147] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present invention. Meanwhile, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to actual proportional relationships. The technology, methods and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, methods and equipment should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and therefore, once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0148] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0149] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0150] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0151] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A power device, characterized in that: The power device comprises: A liner (10) provided with a conductive layer (16); A chip (20) is arranged on the conductive layer (16); A control component (50) comprising a mounting substrate (51) and a resistor element (52) arranged on the mounting substrate (51); A mounting position is provided on the conductive layer (16), one surface of the mounting substrate (51) in the thickness direction thereof is connected to the mounting position, and the resistance element (52) is located on another surface of the mounting substrate (51) in the thickness direction thereof; The conductive layer (16) comprises a first conductive layer (11), the first conductive layer (11) is an axisymmetric structure, the axis of symmetry of the first conductive layer (11) extends along a first direction, a plurality of the chips (20) and a plurality of the control components (50) are arranged on the first conductive layer (11), and the plurality of the chips (20) and the plurality of the control components (50) on the first conductive layer (11) are symmetrically arranged on both sides of the axis of symmetry; The first conductive layer (11) comprises a first sub-conductive layer (111) and two second sub-conductive layers (112); the first sub-conductive layer (111) and the second sub-conductive layer (112) are arranged at intervals; the axis of the first sub-conductive layer (111) is coaxial with the symmetry axis; the two second sub-conductive layers (112) are respectively located on both sides of the first sub-conductive layer (111) in a second direction perpendicular to the first direction; the chip (20) and the control component (50) are arranged on the two second sub-conductive layers (112); and the upper surfaces of the chips (20) on the two second sub-conductive layers (112) are conductively connected to the first sub-conductive layer (111).

2. The power device according to claim 1, characterized in that: The mounting substrate (51) comprises a substrate body (511) and a first metal layer (512) arranged on the substrate body (511); the substrate body (511) is connected to the mounting position; and the resistance element (52) is arranged on the first metal layer (512).

3. The power device according to claim 2, characterized in that: The mounting substrate (51) further comprises a second metal layer (513), the first metal layer (512) and the second metal layer (513) are respectively located on two sides of the substrate body (511), and the substrate body (511) is connected to the mounting position via the second metal layer (513).

4. The power device according to claim 2, characterized in that: The substrate body (511) is a ceramic substrate.

5. The power device according to claim 2, characterized in that: The substrate body (511) is connected to the mounting position by welding, sintering or bonding.

6. The power device according to claim 3, characterized in that: The second metal layer (513) is connected to the mounting position by welding.

7. The power device according to claim 3, characterized in that: The first metal layer (512) and the second metal layer (513) are both copper.

8. The power device according to any one of claims 1 to 7, characterized in that: The resistance element (52) comprises a gate resistor.

9. The power device according to any one of claims 1 to 7, characterized in that: The power device comprises a plurality of the chips (20), and two adjacent chips (20) are separated by a control component (50).

10. The power device according to any one of claims 1 to 7, characterized in that: The conductive layer (16) further comprises a second conductive layer (12), the second conductive layer (12) being an axisymmetric structure, the axis of symmetry of the second conductive layer (12) extending along a first direction, a plurality of the chips (20) and a plurality of the control components (50) being arranged on the second conductive layer (12), and the plurality of the chips (20) and the plurality of the control components (50) on the second conductive layer (12) being symmetrically arranged on both sides of the axis of symmetry.

11. The power device according to claim 10, characterized in that: The first sub-conductive layer (111) is conductively connected to the second conductive layer (12).

12. The power device according to claim 11, characterized in that: The first sub-conductive layer (111) comprises a first section (1111) and a second section (1112) which are perpendicular to each other, the axis of the first section (1111) being coaxial with the axis of symmetry, one end of the first section (1111) being connected to the middle of the second section (1112), the second section (1112) being arranged between the first section (1111) and the second conductive layer (12), the two second sub-conductive layers (112) being respectively arranged on both sides of the first section (1111) in the second direction, the upper surfaces of the chips (20) on the two second sub-conductive layers (112) being conductively connected to the first section (1111), and the second section (1112) being conductively connected to the second conductive layer (12).

13. The power device according to claim 11, characterized in that: The second conductive layer (12) comprises a third sub-conductive layer (121) and a fourth sub-conductive layer (122); the third sub-conductive layer (121) has a notch (1211) at one end facing the first sub-conductive layer (111) in the first direction; the fourth sub-conductive layer (122) extends into the notch (1211); the axis of the fourth sub-conductive layer (122) is coaxial with the symmetry axis; the chip (20) and the control component (50) are arranged at positions on both sides of the notch (1211) of the third sub-conductive layer (121) in the second direction; the first sub-conductive layer (111) is conductively connected to the third sub-conductive layer (121); and the upper surface of the chip (20) on the third sub-conductive layer (121) is conductively connected to the fourth sub-conductive layer (122).

14. The power device according to claim 13, characterized in that: The third sub-conductive layer (121) comprises a third section (1212), a fourth section (1213) and a fifth section (1214); the third section (1212) and the fifth section (1214) are located on the same side of the fourth section (1213); the third section (1212) and the fifth section (1214) are respectively connected to two ends of the fourth section (1213); the side wall of the third section (1212), the side wall of the fourth section (1213) and the side wall of the fifth section (1214) together form the gap (1211); and the fourth section (1213) is arranged at an end of the third section (1212) away from the first conductive layer (11).

15. The power device according to claim 10, characterized in that: The power device further comprises a first interconnection sheet (30) and a second interconnection sheet (40); the upper surface of the chip (20) is conductively connected to the first conductive layer (11) and / or the second conductive layer (12) via the first interconnection sheet (30); and the first conductive layer (11) is conductively connected to the second conductive layer (12) via the second interconnection sheet (40).

16. The power device according to claim 10, characterized in that: The power device further comprises a power terminal (60), the power terminal (60) being a plate-shaped structure, the power terminal (60) comprising a terminal foot plate section (61), a first plate section (62), a second plate section (63) and a lead-out plate section (64) connected in sequence, the terminal foot plate section (61) and the second plate section (63) being arranged at an angle to the first plate section (62), the terminal foot plate section (61) and the second plate section (63) extending in opposite directions, and the lead-out plate section (64) being arranged at an end of the second plate section (63) away from the first plate section (62).

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