Array substrate, display panel and display device

Abstract

Embodiments of the present disclosure provide an array substrate, a display panel and a display device, and relate to the technical field of display, and are used for improving the aperture ratio of the array substrate. The array substrate comprises a substrate and a thin film transistor. The thin film transistor comprises a gate pattern, a semiconductor pattern, a source pattern and a drain pattern. The gate pattern comprises a first sidewall and a second sidewall oppositely arranged along a first direction, the first sidewall is close to the source pattern, and the second sidewall is close to the drain pattern. The semiconductor pattern is in the range of the orthographic projection of the gate pattern on the substrate, and has a spacing with the boundary of the gate pattern. Along the first direction, the spacing between one end of the source pattern close to the first sidewall and the semiconductor pattern is smaller than the spacing between one end of the drain pattern close to the second sidewall and the semiconductor pattern. The spacing between the semiconductor pattern and the first sidewall is smaller than the spacing between the semiconductor pattern and the second sidewall. The array substrate is used for preparing the display device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to an array substrate, a display panel and a display device. BACKGROUND

[0002] A liquid crystal display (LCD) projector is a kind of projector device for displaying images through an LCD display panel, and has the advantages of low cost and portability, and thus is favored by users. The display panel of the LCD projector works in a high-brightness (for example, illumination intensity greater than 200,000 nits) working environment for a long time. In order to reduce the influence of light on the characteristics of thin film transistors, especially the influence of light on the semiconductor layer (also referred to as the active layer or A-Si layer or channel layer, etc.) of the thin film transistor, the semiconductor layer needs to be shaded. At the same time, in order to improve the display effect of the projector, higher requirements are put forward for the light transmittance and the pixel density (PPI) of the display panel. How to improve the PPI of the display panel and the aperture ratio of the display panel under the premise of effectively shading the semiconductor layer is a problem to be solved for the current LCD projector device. SUMMARY

[0003] The embodiments of the present application aim to provide an array substrate, a display panel and a display device for improving the aperture ratio of the array substrate.

[0004] To achieve the above-mentioned purpose, the embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, an array substrate is provided. The array substrate includes a substrate, and a plurality of thin film transistors disposed on the substrate and arranged in an array. The thin film transistor includes a gate pattern, a semiconductor pattern, a source pattern, and a drain pattern. The gate pattern is disposed on the substrate, and the gate pattern includes a first sidewall and a second sidewall oppositely disposed along a first direction, the first sidewall being proximate to the source pattern, and the second sidewall being proximate to the drain pattern. The semiconductor pattern is disposed on a side of the gate pattern distal to the substrate, a projection of the semiconductor pattern on the substrate is within a projection of the gate pattern on the substrate, and a boundary of the semiconductor pattern is spaced apart from a boundary of the gate pattern. The source pattern and the drain pattern are disposed on a side of the semiconductor pattern distal to the substrate, the source pattern and the drain pattern are spaced apart along the first direction, and are respectively electrically connected to two ends of the semiconductor pattern along the first direction. Along the first direction, a spacing between one end of the source pattern proximate to the first sidewall and the semiconductor pattern is less than a spacing between one end of the drain pattern proximate to the second sidewall and the semiconductor pattern. A spacing between the semiconductor pattern and the first sidewall is less than a spacing between the semiconductor pattern and the second sidewall.

[0006] In the array substrate described above, along the first direction, a spacing between one end of the source pattern proximate to the first sidewall (hereinafter referred to as a first end) and the semiconductor pattern is less than a spacing between one end of the drain pattern proximate to the second sidewall (hereinafter referred to as a second end) and the semiconductor pattern. In a case where a size of the drain pattern (such as a size along the first direction) is determined, the end of the drain pattern proximate to the second sidewall is flush with the second sidewall, or at least partially located on a side of the second sidewall distal to the first sidewall, i.e., the second sidewall of the gate pattern is closer to the semiconductor pattern than the third end of the drain pattern. In this way, without additional increase in size of the black matrix, the black matrix can cover the second sidewall of the gate pattern and the drain pattern at the same time, which is beneficial to reduce the size of the black matrix, and further improve the aperture ratio of the opening on the black matrix, and improve the light extraction efficiency of the display panel.

[0007] In some embodiments, the gate pattern further includes a third sidewall and a fourth sidewall oppositely disposed along a second direction intersecting the first direction. The spacing between the semiconductor pattern and the third sidewall, the spacing between the semiconductor pattern and the fourth sidewall, and the spacing between the semiconductor pattern and the second sidewall are substantially equal.

[0008] In some embodiments, the spacing between the semiconductor pattern and the first sidewall is D1, the spacing between the semiconductor pattern and the second sidewall is D2, and a ratio of D1 to D2 is 0.5-0.6.

[0009] In some embodiments, the drain pattern comprises a first sub-portion and a second sub-portion. The first sub-portion extends along a second direction and is electrically connected to the semiconductor pattern. A projection of the first sub-portion on the substrate is within a projection of the gate pattern on the substrate. The second sub-portion is connected to the first sub-portion and extends away from an end of the first sub-portion along the first direction to be flush with the second sidewall or to extend beyond the boundary of the gate pattern. The second direction intersects the first direction.

[0010] In some embodiments, along the first direction, a dimension of the overlapping portion of the source pattern and the semiconductor pattern and a dimension of the overlapping portion of the drain pattern and the semiconductor pattern are substantially equal and are greater than a spacing between the source pattern and the drain pattern. A dimension of the semiconductor pattern along the second direction is greater than the spacing between the source pattern and the drain pattern.

[0011] In some embodiments, along the first direction, a dimension of the overlapping portion of the source pattern and the semiconductor pattern and a dimension of the overlapping portion of the drain pattern and the semiconductor pattern are D3, D3 being 3 μm to 3.85 μm. A dimension of the semiconductor pattern along the second direction is D4, D4 being 3 μm to 3.7 μm. A spacing between the source pattern and the drain pattern is D5, D5 being 1.8 μm to 2.4 μm.

[0012] In some embodiments, the array substrate further comprises a pixel electrode. The pixel electrode is in the same film layer as the semiconductor pattern and a projection of the pixel electrode on the substrate has a spacing from a projection of the gate pattern on the substrate. The pixel electrode comprises an overlap portion which is electrically connected to the drain pattern. A dimension of the overlap portion along the first direction is greater than a dimension of the overlap portion along a second direction. The dimension of the overlap portion along the first direction is D6, D6 being 6.1 μm to 6.5 μm. The dimension of the overlap portion along the second direction is D7, D7 being 1.4 μm to 1.8 μm.

[0013] In some embodiments, the array substrate further comprises a plurality of data lines and a plurality of common voltage signal lines. The plurality of data lines and the plurality of common voltage signal lines are arranged alternately along the first direction and are in the same layer as the source pattern and the drain pattern. In a projection on the substrate, a spacing between the pixel electrode and the common voltage signal line is less than a spacing between the pixel electrode and the data line.

[0014] In some embodiments, the array substrate further comprises a plurality of gate lines arranged at intervals along the second direction. The plurality of gate lines are arranged in the same layer as the gate pattern, and each gate line extends along the first direction. The gate lines are electrically connected to the gate pattern. Along the second direction, the interval between the pixel electrode and the gate pattern is equal to the interval between the pixel electrode and the gate line.

[0015] In some embodiments, the interval between the pixel electrode and the gate pattern is smaller than the interval between the pixel electrode and the common voltage signal line.

[0016] In some embodiments, along the first direction, the size of the data line is substantially equal to the size of the common voltage signal line, and the size of the data line along the first direction is smaller than the size of the overlapping portion of the source pattern and the semiconductor pattern along the first direction.

[0017] In some embodiments, the interval between the pixel electrode and the common voltage signal line along the first direction is D8, and D8 is 2.4 μm to 2.8 μm. The interval between the pixel electrode and the data line along the first direction is D9, and D9 is 3.0 μm to 3.4 μm. The interval between the pixel electrode and the gate line along the second direction is D10, and D10 is 2.0 μm to 2.4 μm. The size of the data line and the common voltage signal line along the first direction is D11, and D11 is 2.4 μm to 2.8 μm.

[0018] In some embodiments, the array substrate further comprises a common electrode. The common electrode is located on the side of the source pattern and the drain pattern away from the substrate, and comprises at least one electrode strip extending along the second direction. Along the second direction, the orthogonal projection of the end of the electrode strip away from the drain pattern on the substrate is located outside the range of the orthogonal projection of the pixel electrode on the substrate.

[0019] In some embodiments, along the second direction, the orthogonal projection of the end of the electrode strip close to the drain pattern on the substrate is located within the range of the orthogonal projection of the pixel electrode on the substrate, and partially overlaps with the orthogonal projection of the drain pattern on the substrate. The common electrode further comprises a first connecting portion connected to the end of the electrode strip close to the drain pattern. The orthogonal projection of the first connecting portion on the substrate partially overlaps with the orthogonal projection of the pixel electrode on the substrate.

[0020] In some embodiments, the common electrode further comprises a plurality of slits arranged at intervals along the first direction. Between any two adjacent slits, there is one electrode strip. Along the first direction, the size of the slit is larger than the size of the electrode strip.

[0021] In some embodiments, along the second direction, a distance between the electrode strip and the pixel electrode away from an end of the drain pattern is 0.9-1.1 μm. A dimension of the slit along the first direction is 2.6-2.9 μm. A dimension of the electrode strip along the first direction is 1.9-2.1 μm.

[0022] In some embodiments, the semiconductor pattern includes a third sub-portion and a fourth sub-portion arranged along the first direction, the third sub-portion is closer to the first sidewall than the fourth sub-portion. A projection of the common electrode on the substrate covers a projection of the third sub-portion on the substrate and does not overlap a projection of the fourth sub-portion on the substrate.

[0023] In some embodiments, along the first direction, a dimension of the third sub-portion is D15, D15 is 0.4-0.6 μm.

[0024] In some embodiments, a boundary of the projection of the common electrode on the substrate substantially coincides with a projection on the substrate of a boundary of the fourth sub-portion away from the third sub-portion and a projection on the substrate of a boundary of the fourth sub-portion close to the pixel electrode.

[0025] In another aspect, a display panel is also provided. The display panel includes a color filter substrate and the array substrate of any of the above embodiments. The color filter substrate is arranged opposite to the array substrate, and the color filter substrate includes a black matrix, a projection of the black matrix on the array substrate covers a thin film transistor of the array substrate.

[0026] In some embodiments, a drain pattern of the thin film transistor includes a first sub-portion and a second sub-portion; a boundary of a projection of the black matrix on a substrate of the array substrate has a distance from a boundary of a projection on the substrate of a gate pattern, a semiconductor pattern and a source pattern of the thin film transistor, and substantially coincides with a boundary of the second sub-portion away from the first sub-portion.

[0027] In some embodiments, along the second direction, a distance between a projection on the substrate of the semiconductor pattern and a projection on the substrate of the black matrix is D16, D16 is 6.4-6.7 μm. And / or, the semiconductor pattern includes a fifth sub-portion between the source pattern and the drain pattern, a minimum distance between a projection on the substrate of the fifth sub-portion and a projection on the substrate of the black matrix is D17, D17 is 5.7-6.0 μm.

[0028] In some embodiments, the array substrate includes a plurality of pedestals arranged in an array, the plurality of pedestals being disposed in the same layer as the source pattern and the drain pattern. The display panel further includes a spacer, the spacer being located between the array substrate and the color filter substrate and connected to the array substrate and the color filter substrate respectively. A projection of the spacer on the substrate is located within a projection of the pedestals on the substrate.

[0029] The black matrix includes a first extension and a second extension. A projection of the first extension on the substrate covers a projection of the thin film transistor on the substrate. A projection of the second extension on the substrate covers projections of the pedestals and the spacer on the substrate. In the second direction, a size of the first extension is smaller than a size of the second extension.

[0030] In some embodiments, a radial dimension of an end surface of the spacer connected to the color filter substrate is D18, and D18 is 8.3 μm to 8.7 μm; and / or, a minimum interval between a projection of the end surface of the spacer connected to the color filter substrate on the black matrix and a boundary of the black matrix is D19, and D19 is 6.8 μm to 7.2 μm.

[0031] In some embodiments, the array substrate includes a common electrode, the common electrode including at least one electrode strip extending in the second direction. A projection of the black matrix on the array substrate at least partially coincides with an end of the electrode strip in the second direction.

[0032] In another aspect, a display device is provided. The display device includes a driving circuit board and the display panel of any of the above embodiments. The driving circuit board is configured to transmit a control signal to the display panel.

[0033] The display panel and the display device have the same structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described here again. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size of the product, the actual flow of the method, the actual timing of the signal, etc. involved in the embodiments of the present disclosure.

[0035] Figure 1 Structure diagram of a display device according to some embodiments;

[0036] Figure 2 A structural diagram of a display panel according to some embodiments;

[0037] Figure 3 A cross-sectional structural diagram of an array substrate according to some embodiments;

[0038] Figure 4 A planar structural diagram of an array substrate according to some embodiments;

[0039] Figure 5 A Figure 4 A partial enlarged view of A1 region in the middle;

[0040] Figure 6 A Figure 2 A partial enlarged view of A2 region in the middle;

[0041] Figure 7 An equivalent circuit diagram of a pixel circuit according to some embodiments;

[0042] Figure 8 Another planar structural diagram of an array substrate according to some embodiments;

[0043] Figure 9 A Figure 8 A partial enlarged view of A3 region in the middle;

[0044] Figure 10 A Figure 2 A partial enlarged view of A5 region in the middle;

[0045] Figure 11 A Figure 8 A partial enlarged view of A4 region in the middle;

[0046] Figure 12 A Figure 2 A partial enlarged view of A6 region in the middle;

[0047] Figure 13 A Figure 8 A partial enlarged view of A7 region in the middle;

[0048] Figure 14 A Figure 2 Another partial enlarged view of A2 region in the middle;

[0049] Figure 15 A Figure 2 A partial enlarged view of A8 region in the middle;

[0050] Figure 16 A Figure 2 Another partial enlarged view of A8 region in the middle. DETAILED DESCRIPTION

[0051] In the following, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0052] Unless otherwise required by context, the term "comprise" and its other forms such as "comprises" and "comprising" are to be construed as open-ended, i.e. as "including, but not limited to", in the description and the claims. In the description, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are not necessarily referring to the same embodiment or example. Furthermore, the described features, structures, materials or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0053] In the following, the terms "first", "second", etc. are used only for the purpose of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0054] In describing some embodiments, "coupled" and "connected" and their derivatives can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium.

[0055] "A, B, and C at least one of them" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0056] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0057] The use of "adapted to" or "configured to" herein is meant as open and inclusive language that does not foreclose devices adapted to or configured to perform additional tasks or steps.

[0058] Additionally, the use of "based on" is meant to be open and inclusive, in that a process, step, calculation, or other action "based on" one or more recited conditions or values may, in practice, be based on additional conditions or values beyond those recited.

[0059] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the recited value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0060] As used herein, "parallel," "perpendicular," "equal" includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can be within an acceptable deviation of, for example, 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also be within an acceptable deviation of, for example, 5°. "Equal" includes absolute equality and near equality, where near equality can be within an acceptable deviation of, for example, less than or equal to 5% of either of the two quantities being compared.

[0061] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0062] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the individual parts of the devices are shown in the figures nor are all of the individual steps of a process shown. It will be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions can be made. These implementation-specific decisions can include, for example, a determination of the shape of regions in the figures, the use of a particular machine or process, or the use of a particular programming language. Such implementation-specific decisions can lead to variations in the exemplary embodiments. Other acts and / or objects not specifically shown in the figures can be included in the exemplary embodiments. It will be appreciated that the exemplary embodiments are not intended to be limited to the specific implementations described herein, but rather are intended to include all implementations consistent with the principles of the exemplary embodiments.

[0063] ​Some embodiments of this disclosure provide a display device, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. Exemplarily, the display device can be any product or component with display functionality, such as a television, laptop computer, tablet computer, mobile phone, projector, personal digital assistant (PDA), navigator, wearable device, augmented reality (AR) device, virtual reality (VR) device, etc.

[0064] In a specific example, such as Figure 1 As shown, the display device 1000 can be a projector, and the display device 1000 (projector) can include a display panel 1100 and a light source 1200 disposed on one side of the display panel 1100. The display panel 1100 can be, for example, a liquid crystal display panel. It is understood that the projector may also include other structures. For example, the projector may also include an imaging module and a projection lens disposed on the side of the display panel 1100 away from the light source 1200, etc., which will not be listed in detail in the embodiments of this disclosure.

[0065] If the display panel 1100 is an LCD display panel, refer to Figure 1 The display panel 1100 may include an array substrate 100 and a color filter substrate 200 disposed opposite to each other, and a liquid crystal layer 300 disposed between the array substrate 100 and the color filter substrate 200. Of course, the display panel 1100 may also include other structures. For example, the display panel 1100 may also include a first alignment film (not shown in the figure) disposed on the side of the array substrate 100 near the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on the side of the color filter substrate 200 near the liquid crystal layer 300, etc., which will not be listed in detail in the embodiments of this disclosure.

[0066] See Figure 2The display panel 1100 includes a plurality of sub-pixels, each of which includes a light-emitting area AA. Exemplarily, the color film substrate 200 includes a black matrix 210 and a plurality of filter parts (not shown in the figure). The black matrix 210 is provided with a plurality of openings 2101, each of which defines a light-emitting area AA of a sub-pixel. At least part of each of the plurality of filter parts is located within an opening 2101 and is used to transmit light of a specific color. Exemplarily, the plurality of filter parts can include a red filter part for transmitting red light, a green filter part for transmitting green light, and a blue filter part for transmitting blue light, so that the light emitted from the color film substrate 200 can form a color picture. The opening rate of the black matrix 210 may, for example, be the ratio of the area of the light-emitting area AA to the area of the sub-pixel, or the opening rate of the black matrix 210 can be understood as the ratio of the area of the light-emitting area AA to the area of the display area of the display panel. The display area refers to the area of the display panel used for displaying images.

[0067] Referring to Figure 3 and Figure 4 The array substrate 100 can include a substrate 10 and a plurality of thin film transistors (TFTs) 20 arranged on the substrate 10 in an array. Figure 3 Only a cross-sectional structure diagram of one thin film transistor 20 is shown, Figure 4 Only the structure of one thin film transistor 20 on the array substrate 100 is exemplarily shown in the figure.

[0068] In the case of a display device 1000 being a projector, the display panel 1100 in the projector needs to work under high light intensity conditions. Due to the light-sensitive characteristics of the thin film transistor 20, the channel region of the thin film transistor 20 will generate photo-generated carriers under light irradiation, causing the channel to generate a leakage current, which in turn causes the display panel 1100 to produce display abnormalities. Therefore, the thin film transistor 20 needs to be shaded to reduce or avoid the generation of a leakage current.

[0069] In the related art, a shading pattern (such as a non-transparent metal block structure) is usually provided on the side of the TFT close to the substrate to shade the TFT. However, this will increase the number of films of the display panel and the preparation process of the display panel, thereby increasing the thickness and preparation cost of the display panel. On the other hand, the area of the shading pattern is generally set to be large, which is not conducive to improving the aperture ratio and PPI of the display panel.

[0070] To solve the above technical problems, the array substrate 100 provided by the embodiments of the present application is described with reference to Figure 3The thin film transistor 20 includes a gate pattern 21, a semiconductor pattern 22, a source pattern 23, and a drain pattern 24. The gate pattern 21 is disposed on the substrate 10, the semiconductor pattern 22 is disposed on a side of the gate pattern 21 away from the substrate 10, and the source pattern 23 and the drain pattern 24 are disposed in the same layer and on a side of the semiconductor pattern 22 away from the substrate 10. That is, the gate pattern 21, the semiconductor pattern 22, the source pattern 23, and the drain pattern 24 of the thin film transistor 20 are sequentially disposed in a direction away from the substrate 10.

[0071] Referring to Figure 4 and Figure 5 , the gate pattern 21 includes a first sidewall 211 and a second sidewall 212 disposed opposite each other in the first direction X. The first sidewall 211 is closer to the source pattern 23 (than the second sidewall 212), and the second sidewall 212 is closer to the drain pattern 24 (than the first sidewall 211). Here, the source pattern 23 and the drain pattern 24 are spaced apart in the first direction X.

[0072] Exemplarily, referring to Figure 3 , the semiconductor pattern 22 and the gate pattern 21 further include a gate insulating layer (English: Gate Insulator; abbreviation: GI) 11 therebetween. The semiconductor pattern 22 is disposed on a side of the gate insulating layer 11 away from the substrate 10, for example, the semiconductor pattern 22 directly contacts the gate pattern 21. The gate insulating layer 11 can separate the semiconductor pattern 22 and the gate pattern 21, form electrical insulation therebetween, and avoid short circuit between the semiconductor pattern 22 and the gate pattern 21. The gate insulating layer 11 may, for example, be a continuous whole layer structure.

[0073] Here, in the embodiments of the present disclosure, “disposed in the same layer” refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate to form by a one-time patterning process. According to different specific patterns, the one-time patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns can also be at different heights or have different thicknesses. Exemplarily, referring to Figure 3 and Figure 5 , the source pattern 23 and the drain pattern 24 are disposed in the same layer, which can mean that the source pattern 23 and the drain pattern 24 are prepared and formed on the surface of the gate insulating layer 11 and the semiconductor pattern 22 away from the substrate 10 by using the same material and the same process. For example, the source pattern 23 and the drain pattern 24 can be disposed on the surface formed by the gate insulating layer 11 and the semiconductor pattern 22 together.

[0074] Referring to Figure 3 , Figure 4 and Figure 5The normal projection of the semiconductor pattern 22 on the substrate 10 is located within the range of the normal projection of the gate pattern 21 on the substrate 10 (not shown in the figure), and the boundary of the semiconductor pattern 22 has a spacing from the boundary of the gate pattern 21. That is, the gate pattern 21 can completely shield the semiconductor pattern 22 from the side (lower side) of the semiconductor pattern 22 close to the substrate 10, so that the semiconductor pattern 22 can be shielded (such as shielding light from the light source) by the gate pattern 21, and thus it is not necessary to specially arrange a light shielding pattern on the side of the thin film transistor 20 close to the substrate 10, which is conducive to reducing the thickness of the array substrate 100, facilitating the light and thin design of the display panel, and can reduce the preparation process of the array substrate 100 and reduce the preparation cost of the array substrate 100.

[0075] Exemplarily, the gate pattern 21 can be made of a light-proof metal material (such as copper or copper alloy), and the thickness of the gate pattern 21 can be flexibly set according to actual needs (such as according to the maximum brightness of the light emitted by the light source) to reduce the light transmittance of the gate pattern 21. The risk of light passing through the gate pattern 21 and irradiating onto the semiconductor pattern 22 is reduced, avoiding the generation of leakage current of the thin film transistor 20 and improving the stability of the thin film transistor 20.

[0076] It can be understood that, as Figure 4 and Figure 5 shown, the array substrate 100 further includes a data line 30 arranged in the same layer as the source pattern 23 and the drain pattern 24, the data line 30 is electrically connected with the source pattern 23, or in other words, the data line 30 and the source pattern 23 are continuous patterns in the actual layout, and the data line 30 and the source pattern 23 are artificially divided into two parts for description. Exemplarily, the film layer where the source pattern 23 and the drain pattern 24 are located is the second conductive layer 102, and the data line 30 is also located in the second conductive layer 102. In the embodiment of the present disclosure, the source pattern 23 refers to the part in the second conductive layer 102 for transmitting data signals, and the normal projection of the source pattern 23 on the substrate 10 is located within the range of the normal projection of the gate pattern 21 on the substrate 10; the data line 30 refers to the part connected with the source pattern 23, and the normal projection of the data line 30 on the substrate 10 does not coincide with the normal projection of the gate pattern 21 on the substrate 10.

[0077] Source pattern 23 and drain pattern 24 are spaced apart along a first direction X, and are electrically connected to both ends of semiconductor pattern 22 along the first direction X. For example, source pattern 23 is electrically connected to the end of semiconductor pattern 22 near the first sidewall 211, and drain pattern 24 is electrically connected to the end of semiconductor pattern 22 near the second sidewall 212. Furthermore, along the first direction X, the distance L1 between the end of source pattern 23 near the first sidewall 211 (hereinafter referred to as the first end) and semiconductor pattern 22 is smaller than the distance L2 between the end of drain pattern 24 near the second sidewall 212 (hereinafter referred to as the second end) and semiconductor pattern 22, i.e., L1 < L2.

[0078] The phrase "along the first direction X, the distance L1 between the end of the source pattern 23 near the first sidewall 211 and the semiconductor pattern 22" can be understood as the distance between the orthographic projection of the end of the source pattern 23 near the first sidewall 211 onto the substrate 10 and the orthographic projection of the semiconductor pattern 22 onto the substrate 10. In the embodiments of this disclosure, similar expressions are used when describing the distance between any two structures; that is, when describing the distance between two structures (A and B) located in different film layers, it can be understood as the distance between the orthographic projection of A onto the substrate and the orthographic projection of B onto the substrate. In other words, in the embodiments of this disclosure, when A and B are located in different film layers, "the distance between A and B" refers to the distance between the orthographic projection of A onto the substrate and the orthographic projection of B onto the substrate. To simplify the expression, similar expressions are used in the embodiments of this application.

[0079] For example, such as Figure 4 As shown, the boundary of the source pattern 23 near the first sidewall 211 is flush with the boundary of the semiconductor pattern 22 near the first sidewall 211; that is, the gap L1 between the first end of the source pattern 23 and the semiconductor pattern 22 is 0 μm. The end of the drain pattern 24 near the second sidewall 212 is at least partially located on the side of the second sidewall 212 away from the first sidewall 211; that is, the gap L2 between the second end of the drain pattern 24 and the semiconductor pattern 22 is greater than 0 μm. In other words, the left boundary of the source pattern 23 is approximately flush with the left boundary of the semiconductor pattern 22, and the right boundary of the drain pattern 24 is further away from the source pattern 23 than the right boundary of the semiconductor pattern 22.

[0080] It should be noted that the left side boundary of the source pattern 23 is substantially flush with the left side boundary of the semiconductor pattern 22, which can be understood as that the two are flush with each other in design, but due to measurement errors and preparation process errors (such as alignment accuracy and manufacturing accuracy) and other factors, the left side boundary of the source pattern 23 and the left side boundary of the semiconductor pattern 22 can have a gap. Exemplarily, L1 < M can be considered as that the left side boundary of the source pattern 23 and the left side boundary of the semiconductor pattern 22 are substantially flush, such as M can be 0.5 μm, 1 μm or 2 μm, etc. Also, in other embodiments of the present disclosure, when it is stated that two components are substantially flush, considering process errors and measurement errors, etc., it can be understood that the two components can have a certain gap therebetween, which is within an acceptable deviation range. In some embodiments, continuing to refer to Figure 5 , the drain pattern 24 includes a first sub-portion 241 and a second sub-portion 242. The first sub-portion 241 extends along the second direction Y and is electrically connected with the semiconductor pattern 22. The second direction Y intersects the first direction X, and exemplarily, the second direction Y is perpendicular to the first direction X. The orthographic projection of the first sub-portion 241 on the substrate 10 is within the range of the orthographic projection of the gate pattern 21 on the substrate 10. The second sub-portion 242 is connected with the first sub-portion 241, and along the first direction X, the end of the second sub-portion 242 away from the first sub-portion 241 (hereinafter referred to as the third end) is flush with the second side wall 212 or protrudes from the second side wall 212. In embodiments of the present disclosure, as shown in Figure 5 , the third end of the second sub-portion 242 is taken as an example to be described.

[0081] It can be understood that, as shown in Figure 6 , the color filter substrate 200 includes a black matrix (English: Black Matrix; abbreviated: BM) 210, which covers the thin film transistor 20 on the array substrate 100 to reduce the reflection of ambient light by the thin film transistor 20 and reduce the risk of light from the side of the thin film transistor 20 away from the substrate 10 to the semiconductor pattern 22. Therefore, the black matrix 210 at least covers the boundary of the thin film transistor 20, that is, the orthographic projection of the black matrix 210 on the substrate 10 covers the orthographic projection of the drain pattern 24 on the substrate 10, and exemplarily, the boundary of the orthographic projection of the black matrix 210 on the substrate 10 is flush with or has a gap with the boundary of the orthographic projection of the drain pattern 24 on the substrate 10, which can reduce the risk of oblique light (light having an angle with the third direction Z) entering the thin film transistor 20.

[0082] Based on this, referring to Figure 5 and Figure 6In a case where the size of the drain electrode pattern 24 (such as the size along the first direction X) is determined, the drain electrode pattern 24 is flush with the second side wall 212 at an end (third end) close to the second side wall 212, or at least partially located on a side of the second side wall 212 away from the first side wall 211, that is, the second side wall 212 of the gate electrode pattern 21 is closer to the semiconductor pattern 22 than the third end of the drain electrode pattern 24. In this way, without the need to additionally increase the size of the black matrix 210, the black matrix 210 can cover the second side wall 212 of the drain electrode pattern 24 and the gate electrode pattern 21 at the same time, which is conducive to reducing the size of the black matrix 210, and further improving the aperture ratio of the opening 2101 on the black matrix 210, and improving the light extraction efficiency of the display panel 1100. It can be understood that if the second side wall 212 of the gate electrode pattern 21 is farther away from the semiconductor pattern than the third end of the drain electrode pattern 24, the size of the black matrix 210 needs to be increased on the right side (close to the second side wall 212) so that the orthographic projection of the black matrix 210 on the substrate 10 can completely cover the thin film transistor 20 (the second side wall 212). It is not conducive to improving the aperture ratio of the display panel 1100.

[0083] Referring to Figure 5 and Figure 6 , based on the difference in the size of the source electrode pattern 23 and the drain electrode pattern 24 along the first direction X (along the first direction X, the third end of the drain electrode pattern 24 protrudes beyond the boundary of the semiconductor pattern 22, and the left boundary of the source electrode pattern 23 is substantially flush with the left boundary of the semiconductor pattern 22),

[0084] In the orthographic projection on the substrate 10, the black matrix 210 is used to cover a part of the thin film transistor 20, and the size L3 of the part (along the first direction X) of the semiconductor pattern 22 located on the side (right side) close to the second side wall 212 is greater than the size L4 of the part (along the first direction X) of the semiconductor pattern 22 located on the side (left side) close to the first side wall 211. In this way, it is conducive to the black matrix 210 covering the source electrode pattern 23 and the drain electrode pattern 24. Wherein, L3 can also be considered as the interval along the first direction X between the right boundary of the semiconductor pattern 22 and the third end of the drain electrode pattern 24, and L4 can also be considered as the interval along the first direction X between the left boundary of the semiconductor pattern 22 and the first side wall 211 of the gate electrode pattern 21.

[0085] In an embodiment of the present disclosure, as Figure 5As shown, the interval D1 between the semiconductor pattern 22 and the first side wall 211 is smaller than the interval D2 between the semiconductor pattern 22 and the second side wall 212. That is, the width of the portion of the gate pattern 21 located on the right side of the semiconductor pattern 22 is greater than the width of the portion of the gate pattern 21 located on the left side of the semiconductor pattern 22. In one aspect, the first side wall 211 is close to the light-emitting region of the array substrate 100, and reducing the interval between the first side wall 211 and the semiconductor pattern 22 is conducive to increasing the area of the light-emitting region, thereby improving the aperture ratio of the array substrate 100. In another aspect, it is conducive to reducing the width of the portion of the gate pattern 21 close to the source pattern 23, thereby reducing the area of the gate pattern 21 and the size of the thin-film transistor 20, and also reducing the area of the black matrix 210, which is conducive to improving the aperture ratio of the display panel, thereby improving the light transmittance of the display panel 1100, and being conducive to realizing high PPI of the display panel.

[0086] In some embodiments, as shown in FIG. 1A, the interval D1 between the semiconductor pattern 22 and the first side wall 211 is smaller than the interval D2 between the semiconductor pattern 22 and the second side wall 212. That is, the width of the portion of the gate pattern 21 located on the right side of the semiconductor pattern 22 is greater than the width of the portion of the gate pattern 21 located on the left side of the semiconductor pattern 22. In one aspect, the first side wall 211 is close to the light-emitting region of the array substrate 100, and reducing the interval between the first side wall 211 and the semiconductor pattern 22 is conducive to increasing the area of the light-emitting region, thereby improving the aperture ratio of the array substrate 100. In another aspect, it is conducive to reducing the width of the portion of the gate pattern 21 close to the source pattern 23, thereby reducing the area of the gate pattern 21 and the size of the thin-film transistor 20, and also reducing the area of the black matrix 210, which is conducive to improving the aperture ratio of the display panel, thereby improving the light transmittance of the display panel 1100, and being conducive to realizing high PPI of the display panel. Figure 5 As shown, the interval D1 between the semiconductor pattern 22 and the first side wall 211 is smaller than the interval D2 between the semiconductor pattern 22 and the second side wall 212. That is, the width of the portion of the gate pattern 21 located on the right side of the semiconductor pattern 22 is greater than the width of the portion of the gate pattern 21 located on the left side of the semiconductor pattern 22. In one aspect, the first side wall 211 is close to the light-emitting region of the array substrate 100, and reducing the interval between the first side wall 211 and the semiconductor pattern 22 is conducive to increasing the area of the light-emitting region, thereby improving the aperture ratio of the array substrate 100. In another aspect, it is conducive to reducing the width of the portion of the gate pattern 21 close to the source pattern 23, thereby reducing the area of the gate pattern 21 and the size of the thin-film transistor 20, and also reducing the area of the black matrix 210, which is conducive to improving the aperture ratio of the display panel, thereby improving the light transmittance of the display panel 1100, and being conducive to realizing high PPI of the display panel.

[0087] As shown, the interval D1 between the semiconductor pattern 22 and the first side wall 211 is smaller than the interval D2 between the semiconductor pattern 22 and the second side wall 212. That is, the width of the portion of the gate pattern 21 located on the right side of the semiconductor pattern 22 is greater than the width of the portion of the gate pattern 21 located on the left side of the semiconductor pattern 22. In one aspect, the first side wall 211 is close to the light-emitting region of the array substrate 100, and reducing the interval between the first side wall 211 and the semiconductor pattern 22 is conducive to increasing the area of the light-emitting region, thereby improving the aperture ratio of the array substrate 100. In another aspect, it is conducive to reducing the width of the portion of the gate pattern 21 close to the source pattern 23, thereby reducing the area of the gate pattern 21 and the size of the thin-film transistor 20, and also reducing the area of the black matrix 210, which is conducive to improving the aperture ratio of the display panel, thereby improving the light transmittance of the display panel 1100, and being conducive to realizing high PPI of the display panel.

[0088] In some embodiments, as shown in FIG. 1A, the interval D1 between the semiconductor pattern 22 and the first side wall 211 is smaller than the interval D2 between the semiconductor pattern 22 and the second side wall 212. That is, the width of the portion of the gate pattern 21 located on the right side of the semiconductor pattern 22 is greater than the width of the portion of the gate pattern 21 located on the left side of the semiconductor pattern 22. In one aspect, the first side wall 211 is close to the light-emitting region of the array substrate 100, and reducing the interval between the first side wall 211 and the semiconductor pattern 22 is conducive to increasing the area of the light-emitting region, thereby improving the aperture ratio of the array substrate 100. In another aspect, it is conducive to reducing the width of the portion of the gate pattern 21 close to the source pattern 23, thereby reducing the area of the gate pattern 21 and the size of the thin-film transistor 20, and also reducing the area of the black matrix 210, which is conducive to improving the aperture ratio of the display panel, thereby improving the light transmittance of the display panel 1100, and being conducive to realizing high PPI of the display panel. Figure 5The gate pattern 21 further includes a third sidewall 213 and a fourth sidewall 214 oppositely arranged along the second direction Y. The interval L5 between the semiconductor pattern 22 and the third sidewall 213, the interval L6 between the semiconductor pattern 22 and the fourth sidewall 214, and the interval D2 between the semiconductor pattern 22 and the second sidewall 212 are substantially equal; that is, L5 = L6 = D2. That is, as shown in FIG. 2, the widths of the portions of the gate pattern 21 on the upper side, the lower side, and the right side of the semiconductor pattern 22 are equal. This facilitates increasing the shielding width of the gate pattern 21 on both sides (the upper side and the lower side) of the semiconductor pattern 22 along the second direction X, reduces the risk of light entering the semiconductor pattern 22 from the two sides of the gate pattern 21 along the second direction Y, and thus reduces the risk of leakage current of the thin film transistor 20 and the risk of crosstalk of the source pattern 23 and the drain pattern 24. In consideration of process errors and measurement errors, substantially equal means completely equal or having a certain deviation, which is within an acceptable deviation range, for example, 5%, 6%, or other specific values. For example, L5 and L6 can be (1 ± 5%) D2 based on the interval D2 between the semiconductor pattern 22 and the second sidewall 212. Similarly, when any two values are equal in the present application, it can be understood that the two values are completely equal or have a deviation within an acceptable range. Figure 5

[0089] It can be understood that, during the preparation of the thin film transistor 20, the process control capability of each pattern (the gate pattern 21, the semiconductor pattern 22, the source pattern 23, and the drain pattern 24) of the thin film transistor 20 along the first direction X is greater than the process control capability along the second direction Y, that is, the dimensional accuracy of each pattern of the thin film transistor 20 along the first direction X is greater than the preparation accuracy along the second direction Y. For example, taking the gate pattern 21 as an example, the dimensional difference rate (error rate or deviation range) of the actually prepared gate pattern 21 along the first direction X is less than the dimensional difference rate along the second direction Y compared with the designed size of the gate pattern 21. Based on this, the interval L5 between the semiconductor pattern 22 and the third sidewall 213 and the interval L6 between the semiconductor pattern 22 and the fourth sidewall 214 are greater than the interval D1 between the semiconductor pattern 22 and the first sidewall 211, which facilitates increasing the width of the gate pattern 21 shielding the semiconductor pattern 22 along the second direction X, and thus reduces the risk of light entering the semiconductor pattern 22 from one side of the substrate 10.

[0090] For example, the interval L5 between the semiconductor pattern 22 and the third sidewall 213 and the interval L6 between the semiconductor pattern 22 and the fourth sidewall 214 are equal to the interval D2 between the semiconductor pattern 22 and the second sidewall 212, and are each 2.5 μm to 3.0 μm.

[0091] ​In some embodiments, referring to Figure 5 , along the first direction X, the size of the portion where the source pattern 23 overlaps the semiconductor pattern 22 and the size of the portion where the drain pattern 24 overlaps the semiconductor pattern 22 are substantially equal (both are marked as D3), which is conducive to improving the uniformity of the source pattern 23 and the drain pattern 24. Moreover, the size D4 of the semiconductor pattern 22 along the second direction Y is greater than the interval D5 between the source pattern 23 and the drain pattern 24, which is conducive to reducing the area of the semiconductor pattern 22 and the area of the orthographic projection of the thin film transistor 20 on the substrate, thereby improving the aperture ratio of the display panel 1100. On the other hand, the width-length ratio of the channel between the source pattern 23 and the drain pattern 24 is greater than 1, which is conducive to improving the saturation current of the thin film transistor 20 and improving the performance of the thin film transistor 20.

[0092] In some embodiments, along the first direction X, the size of the portion where the source pattern 23 and the drain pattern 24 overlap the semiconductor pattern 22 is D3, and D3 is 3 μm to 3.85 μm. In the case where D3 is 3 μm to 3.85 μm, the connection stability between the source pattern 23 and the drain pattern 24 and the semiconductor pattern 22 and the aperture ratio of the display panel can be considered. Illustratively, D3 can be 3 μm, 3.5 μm, or 3.85 μm, and the like, and the embodiments of the present disclosure do not list them one by one.

[0093] It can be understood that if the value of D3 is too small (for example, less than 3 μm), the contact area between the source pattern 23 and the drain pattern 24 and the semiconductor pattern 22 is small, and the source pattern 23 and the drain pattern 24 and the semiconductor pattern 22 can have poor contact or high resistance problems; if the value of D3 is too large (for example, greater than 3.85 μm), it is not conducive to reducing the size of the thin film transistor 20 and improving the aperture ratio of the display panel.

[0094] As shown in Figure 3 , in the case where the boundary of the source pattern 23 and the semiconductor pattern 22 near the first side wall 211 is substantially flush, the size D3 of the portion where the source pattern 23 overlaps the semiconductor pattern 22 along the first direction X can also be understood as the width of the source pattern 23 along the first direction X. In the case where the boundary of the first sub-portion 241 of the drain pattern 24 and the semiconductor pattern 22 near the second side wall 212 is substantially flush, the size D3 of the portion where the drain pattern 24 overlaps the semiconductor pattern 22 along the first direction X can also be understood as the width of the first sub-portion 241 along the first direction X.

[0095] The size of the semiconductor pattern 22 along the second direction Y is D4, and D4 is 3 μm to 3.7 μm. In the case where D4 is 3 μm to 3.7 μm, the performance of the thin film transistor 20 and the aperture ratio of the display panel can be taken into account. Exemplarily, the size D4 of the semiconductor pattern 22 along the second direction Y can be 3 μm, 3.4 μm, 3.7 μm, or the like, and the embodiments of the present disclosure will not be listed one by one. It can be understood that if the value of D4 is too small (for example, less than 3 μm), the width of the semiconductor pattern 22 is too small, and the saturation current of the thin film transistor 20 is small, which is not conducive to improving the performance of the thin film transistor 20; if the value of D4 is too large (for example, greater than 3.7 μm), it is not conducive to reducing the size of the thin film transistor 20, and it is not conducive to improving the aperture ratio of the display panel.

[0096] Along the first direction X, the interval between the source pattern 23 and the drain pattern 24 is D5, and D5 is 1.8 μm to 2.4 μm. In this way, it is conducive to improving the width-length ratio of the channel of the thin film transistor, thereby improving the performance of the thin film transistor 20, reducing the overall size of the thin film transistor 20, and reducing the risk of signal crosstalk between the source pattern 23 and the drain pattern 24. Exemplarily, the interval D5 between the source pattern 23 and the drain pattern 24 can be 1.8 μm, 2.0 μm, 2.28 μm, or 2.4 μm, and the like, and the embodiments of the present disclosure will not be listed one by one.

[0097] It can be understood that if the value of D5 is too small (for example, less than 1.8 μm), signal crosstalk may occur between the source pattern 23 and the drain pattern 24. If the value of D5 is too large (for example, greater than 2.4 μm), the width-length ratio of the channel between the source pattern 23 and the drain pattern 24 is small, which is not conducive to improving the performance of the thin film transistor 20, and is not conducive to reducing the size of the thin film transistor 20 and improving the aperture ratio of the display panel.

[0098] In some embodiments, referring to Figure 4 and Figure 4The array substrate 110 further comprises a pixel electrode 40. The pixel electrode 40 is configured to be electrically connected with the drain electrode pattern 24, and is used to form an electric field with the common electrode. The pixel electrode 40 is located in the same film layer as the semiconductor pattern 22, and the orthogonal projection of the pixel electrode 40 on the substrate 10 is spaced from the orthogonal projection of the gate electrode pattern 21 on the substrate 10. That is, the orthogonal projection of the pixel electrode 40 on the substrate 10 is spaced from the orthogonal projection of the semiconductor pattern 22 on the substrate 10, so that the risk of parasitic capacitance between the pixel electrode 40 and the gate electrode pattern 21 can be reduced, and the adverse effect of the gate electrode pattern 21 on the pixel electrode 40 can be reduced. The pixel electrode 40 and the semiconductor pattern 22 are in the same film layer, but are spaced from each other, so that the pixel electrode 40 and the semiconductor pattern 22 can be electrically insulated from each other, and signal interference between the pixel electrode 40 and the semiconductor pattern 22 can be avoided.

[0099] For example, referring to Figure 4 The array substrate 100 further comprises a gate line 50 disposed in the same layer as the gate electrode pattern 21, and the gate line 50 is electrically connected with the gate electrode pattern 21 and is configured to transmit a scanning signal to the gate electrode pattern 21. The orthogonal projection of the pixel electrode 40 on the substrate 10 is not coincident with (spaced from) the orthogonal projection of the gate line 50 on the substrate 10, so that the risk of parasitic capacitance between the pixel electrode 40 and the gate line 50 can be reduced, and the adverse effect of the gate electrode pattern 21 on the pixel electrode 40 can be reduced. In the embodiments of the present disclosure, the film layer in which the gate electrode pattern 21 and the gate line 50 are located can be referred to as a first conductive layer 101, and the orthogonal projection of the first conductive layer 101 on the substrate 10 is not coincident with the orthogonal projection of the pixel electrode 40 on the substrate 10.

[0100] It can be understood that the pixel electrode 40 and the semiconductor pattern 22 are located in the same film layer means that there is no other film layer between the pixel electrode 40 and the semiconductor pattern 22 along the direction perpendicular to the substrate 10 (the third direction Z), and the pixel electrode 40 and the semiconductor pattern 22 are formed on the surface of the same film layer in the process of preparing the array substrate, and the pixel electrode 40 and the semiconductor pattern 22 are formed independently by two processes. For example, the pixel electrode 40 and the semiconductor pattern 22 are formed on the surface of the gate insulating layer 11 away from the substrate 10 (directly contact with the surface of the gate insulating layer 11 away from the substrate 10). For example, in the process of preparing the array substrate, the semiconductor pattern 22 can be prepared first, and then the pixel electrode 40 can be prepared.

[0101] For example, referring to Figure 4In the case where the array substrate 100 includes the gate line 50, the interval between the pixel electrode 40 and the gate pattern 21 and the interval between the pixel electrode 40 and the gate line 50 are equal and both are D10 along the second direction Y. That is, the pixel electrode 40 is arranged at equal intervals between the gate pattern 21 and the gate line 50. In this way, the uniformity of the electric field formed between the pixel electrode 40 and the common electrode 70 can be improved by avoiding the aggregation of charges in the area of the pixel electrode 40 close to the gate pattern 21 and by uniformly distributing the charges in the edges of the pixel electrode 40 close to the gate pattern 21 and the gate line 50.

[0102] In some embodiments, the interval D10 between the pixel electrode 40 and the gate pattern 21 and the interval D10 between the pixel electrode 40 and the gate line 50 are both 2.0 μm to 2.4 μm. This can not only reduce the parasitic capacitance between the pixel electrode 40 and the gate pattern 21 and the gate line 50, but also maximize the area of the pixel electrode 40. For example, the interval D10 between the pixel electrode 40 and the gate pattern 21 can be 2.0 μm, 2.2 μm or 2.4 μm.

[0103] Referring to Figure 5 and Figure 4 The pixel electrode 40 includes the overlap portion 41 which is electrically connected to the drain pattern 24. The size D6 of the overlap portion 41 along the first direction X is greater than the size D7 of the overlap portion 41 along the second direction Y, which is conducive to reducing the size of the drain pattern 24 (the second sub-portion 242) along the second direction Y, and further reducing the size of the black matrix along the second direction Y, increasing the area of the opening (display area) on the black matrix, and improving the aperture ratio of the display panel. It can be understood that the overlap portion 41 refers to the portion of the pixel electrode 40 which is in contact with the drain pattern 24.

[0104] In some embodiments, the size of the overlap portion 41 along the first direction X is D6, and D6 is 6.1 μm to 6.5 μm. In this way, the contact area between the overlap portion 41 and the drain pattern 24 can be improved, and the connection stability between the overlap portion 41 and the drain pattern 24 can be ensured. For example, the size of the overlap portion 41 along the first direction X can be 6.1 μm, 6.3 μm, 6.4 μm or 6.5 μm, and the like, and the embodiments of the present disclosure will not be listed one by one. It can be understood that if the value of D6 is too small (for example, less than 6.1 μm), the contact area between the drain pattern 24 and the overlap portion 41 is small, and the resistance is large, which is not conducive to the signal transmission between the drain pattern 24 and the overlap portion 41. If the value of D6 is too large (for example, greater than 6.5 μm), the size of the drain pattern 24 along the first direction X is too long, which is not conducive to improving the aperture ratio of the display panel.

[0105] The size of the overlap portion 41 along the second direction Y is D7, and D7 is 1.4 μm to 1.8 μm. In this way, the size of the overlap portion 41 along the second direction Y can be maximally reduced while ensuring stable connection between the overlap portion 41 and the drain pattern 24, and the aperture ratio of the display panel can be increased. Exemplarily, the size of the overlap portion 41 along the second direction Y can be 1.4 μm, 1.6 μm, 1.8 μm, or the like, and the embodiments of the present disclosure will not list them one by one.

[0106] It can be understood that if the value of D7 is too small (for example, less than 1.4 μm), the connection between the drain pattern 24 and the overlap portion 41 can be invalid, which is not conducive to signal transmission between the drain pattern 24 and the overlap portion 41. If the value of D7 is too large (for example, greater than 1.8 μm), the size of the black matrix along the second direction Y will be increased, which is not conducive to improving the aperture ratio of the display panel.

[0107] In some embodiments, referring to Figure 4 , the array substrate 100 further includes a plurality of data lines 30 and a plurality of common voltage signal lines 60. The plurality of data lines 30 and the plurality of common voltage signal lines 60 are arranged alternately along the first direction X. Exemplarily, one common voltage signal line 60 is included between every two adjacent data lines 30, and one data line is included between every two adjacent common voltage signal lines 60. The plurality of data lines 30 and the plurality of common voltage signal lines 60 are provided in the same layer as the source pattern 23 and the drain pattern 24. That is, the data line 30, the common voltage signal line 60, the source pattern 23, and the drain pattern 24 are synchronously prepared by using the same material and process, and are all located in the third conductive layer. It can be understood that Figure 7 only one data line 30 and one common voltage signal line 60 are exemplarily shown in

[0108] The data line 30 is configured to transmit a data signal, which can be a pulse signal for example; and the common voltage signal line 60 is configured to transmit a common voltage signal, which can be a constant voltage signal for example. Referring to Figure 4 , the thin film transistor 20 is configured to be turned on under the control of the scanning signal from the gate line 50, so as to transmit the data signal from the data line 30 to the pixel electrode 40 (node 40).

[0109] Referring to Figure 4 , in the orthographic projection on the substrate 10, the interval D8 between the pixel electrode 40 and the common voltage signal line 60 (along the first direction X) is less than the interval D9 between the pixel electrode 40 and the data line 30 (along the first direction X). In this way, on the one hand, the area of the pixel electrode 40 can be increased, which is conducive to improving the aperture ratio of the display panel 1100, and on the other hand, the risk of signal interference between the pixel electrode 40 and the data line 30 can be reduced.

[0110] It can be understood that, referring to Figure 7 and Figure 4 , a first parasitic capacitance Clc can be generated between the common voltage signal line 60 and the pixel electrode 40, and the first parasitic capacitance Clc has no interference effect on the signal of the pixel electrode 40 because the constant voltage signal is transmitted on the common voltage signal line 60. Therefore, the interval D8 between the pixel electrode 40 and the common voltage signal line 60 (in the first direction X) can be reduced, which is beneficial to increase the area of the pixel electrode 40. The interval D9 between the pixel electrode 40 and the data line 30 is large, which can reduce or avoid the parasitic capacitance generated between the pixel electrode 40 and the data line 30, and further avoid the signal interference of the data line 30 on the pixel electrode 40. If the parasitic capacitance is generated between the pixel electrode 40 and the data line 30, the data signal (pulse signal) transmitted on the data line 30 will cause the voltage of the pixel electrode 40 to fluctuate due to voltage fluctuation, which will cause the light transmittance of the light-emitting area to fluctuate, which is not conducive to the display of the display panel.

[0111] In some embodiments, as shown in Figure 4 , the interval D8 between the pixel electrode 40 and the common voltage signal line 60 in the first direction X is 2.4 μm to 2.8 μm. The interval between the pixel electrode 40 and the common voltage signal line 60 in the first direction X can be minimized, and the area of the pixel electrode 40 can be maximized, thereby improving the aperture ratio of the display panel. For example, the interval D8 between the pixel electrode 40 and the common voltage signal line 60 can be 2.4 μm, 2.6 μm, or 2.8 μm, and the like. Embodiments of the present disclosure will not be listed one by one.

[0112] The interval D9 between the pixel electrode 40 and the data line 30 in the first direction X is 3.0 μm to 3.4 μm. Not only can the risk of forming a parasitic capacitance between the pixel electrode 40 and the data line 30 be reduced, but also the interval between the pixel electrode 40 and the data line 30 can be minimized, which is beneficial to increase the area of the pixel electrode 40. For example, the interval D9 between the pixel electrode 40 and the data line 30 can be 3.0 μm, 3.2 μm, or 3.4 μm, and the like. Embodiments of the present disclosure will not be listed one by one.

[0113] In some embodiments, as shown in Figure 2As shown, the size of the data line 30 along the first direction X is equal to the size of the common voltage signal line 60 along the first direction X, and both are D11. The data line 30 is electrically connected to the source pattern 23. Exemplarily, the size D11 of the data line 30 along the first direction X is less than the size D3 of the overlapping part of the source pattern 23 and the semiconductor pattern 22 along the first direction X, that is, D11 < D3. In this way, the size of the data line 30 and the common voltage signal line 60 along the first direction X can be reduced, and then the size of the part of the black matrix 210 covering the data line 30 and the common voltage signal line 60 along the first direction X can be reduced, and then the area ratio of the opening 2101 can be increased, and the aperture ratio of the display panel can be improved.

[0114] Exemplarily, the size of the data line 30 and the common voltage signal line 60 along the first direction X is D11, and D11 is 2.4 μm to 2.8 μm. In this way, the size of the data line 30 and the common voltage signal line 60 along the first direction X can be maximally reduced while ensuring that the resistance of the data line 30 and the common voltage signal line 60 is not significantly increased, and the aperture ratio of the display panel can be maximally improved. Exemplarily, the size of the data line 30 and the common voltage signal line 60 along the first direction X can be 2.4 μm, 2.6 μm, or 2.8 μm, and the like, and the embodiments of the present disclosure will not list them one by one.

[0115] It can be understood that if the value of D11 is too small (for example, less than 2.4 μm), the resistance value of the data line 30 and the common voltage signal line 60 will be large, which is not conducive to the data line 30 transmitting the data signal, and is also not conducive to the common voltage signal line 60 transmitting the common voltage signal. If the value of D11 is too large (for example, less than 2.8 μm), the size of the pixel electrode 40 along the first direction X will be compressed under the condition that the PPI of the array substrate is constant, that is, the size of the pixel electrode 40 along the first direction X is small, which is not conducive to improving the aperture ratio of the display panel.

[0116] Exemplarily, as shown in FIG. 6, Figure 3 As shown, the size of the part of the black matrix 210 covering the data line 30 and the common voltage signal line 60 along the first direction X is L7, and L7 can be 4.8 μm to 5.2 μm. In this way, the data line 30 and the common voltage signal line 60 can be completely shielded by the black matrix 210, and the light rays from the front side (the side away from the substrate) of the display panel and obliquely incident on the data line 30 and the common voltage signal line 60 can be reduced, and the risk of the light rays emitted by the data line 30 and the common voltage signal line 60 being emitted from the front side of the display panel can be reduced. Exemplarily, L7 can be 4.8 μm, 5.0 μm, or 5.2 μm, and the like, and the embodiments of the present disclosure will not list them one by one.

[0117] It can be understood that if the value of L7 is too small (for example, less than 4.8 μm), the shielding effect of the black matrix 210 on the data line 30 and the common voltage signal line 60 is poor, and part of the light reflected by the data line 30 and the common voltage signal line 60 may be emitted from the display panel, causing poor display. If the value of L8 is too large (for example, greater than 5.2 μm), the area of the black matrix 210 will increase, which is not conducive to increasing the area ratio of the opening 2101 and is not conducive to improving the aperture ratio of the display panel 1100. Therefore, in the embodiments of the present disclosure, the dimension of the part of the black matrix 210 for covering the data line 30 and the common voltage signal line 60 along the first direction X is 4.8 μm-5.2 μm.

[0118] In some embodiments, the interval D10 between the pixel electrode 40 and the gate pattern 21 is less than the interval D8 between the pixel electrode 40 and the common voltage signal line 60, which is conducive to further increasing the dimension of the pixel electrode 40 along the second direction Y and increasing the aperture ratio of the display panel.

[0119] In some embodiments, referring to Figure 8 , the array substrate 100 further includes a common electrode 70. The common electrode 70 is located on the side of the source pattern 23 and the drain pattern 24 away from the substrate 10. Referring to Figure 8 , the common electrode 70 includes at least one electrode strip 71 extending along the second direction Y. An electric field can be formed between the common electrode 70 and the pixel electrode 40. The liquid crystal molecules in the liquid crystal layer 30 are deflected under the action of the electric field, thereby adjusting the light transmittance of the light-emitting area AA to realize different gray-scale display effects. Exemplarily, as shown in Figure 8 , in one light-emitting area AA, the common electrode 70 includes two electrode strips 71 arranged at intervals along the first direction X, which is conducive to improving the aperture ratio and light-emitting efficiency of the display panel 1100.

[0120] In some embodiments, referring to Figure 9 and Figure 7 , the common electrode 70 further includes a plurality of slits 74 arranged at intervals along the first direction X. The two adjacent slits 74 include an electrode strip 71. Along the first direction X, the dimension D13 of the slit 74 is greater than the dimension D14 of the electrode strip 71, which is conducive to increasing the area of the opening of the common electrode 70 in the display area AA and improving the light transmittance of the common electrode 70, thereby improving the light transmittance of the display panel.

[0121] In some embodiments, referring to Figure 8, the size of the slit 74 along the first direction X is D13, and D13 is 2.7 μm to 2.9 μm. In this way, the light transmittance of the display panel can be improved, and the electric field intensity formed between the common electrode 70 and the pixel electrode 40 can be considered. For example, the size of the slit 74 along the first direction X can be 2.7 μm, 2.75 μm, 2.8 μm, or 2.9 μm, and the like, and the embodiments of the present disclosure do not list them one by one. It can be understood that if D13 is too small (for example, less than 2.7 μm), it is not conducive to improving the light transmittance of the display panel, and if D13 is too large (for example, greater than 2.9 μm), the spacing between the electrode strips 71 is too large, which may affect the electric field intensity formed between the electrode strips 71 and the pixel electrode 40. Therefore, in the embodiments of the present disclosure, D13 is 2.7 μm to 2.9 μm.

[0122] The size of the electrode strip 71 along the first direction X is D14, and D14 is 1.9 μm to 2.1 μm. In this way, the processing difficulty of the electrode strip 71 can be reduced, and the resistance and voltage drop on the electrode strip 71 can be reduced. For example, the size of the electrode strip 71 along the first direction X can be 1.9 μm, 2.0 μm, 2.05 μm, or 2.1 μm, and the like, and the embodiments of the present disclosure do not list them one by one. It can be understood that if D14 is too small (for example, less than 1.9 μm), the process of patterning the common electrode 70 requires high processing precision, and the resistance on the electrode strip 71 is large, the voltage drop on the electrode strip 71 is serious, and the electric field uniformity formed between the common electrode 70 and the pixel electrode 40 is poor. If D14 is too large (for example, greater than 2.1 μm), the width of the electrode strip 71 is large, which is not conducive to improving the light transmittance of the display panel 1100. Therefore, in the embodiments of the present disclosure, D14 is 1.9 μm to 2.1 μm.

[0123] Referring to Figure 9 and Figure 8 , along the second direction Y, the orthogonal projection of the end of the electrode strip 71 away from the drain pattern 24 (hereinafter referred to as the fourth end 711) on the substrate 10 is located outside the orthogonal projection of the pixel electrode 40 on the substrate 40. That is, the orthogonal projection of the end of the electrode strip 71 away from the drain pattern 24 (the fourth end 711) on the substrate 10 covers and extends at least part of the boundary of the orthogonal projection of the pixel electrode 40 on the substrate 40. In this way, it is beneficial to reduce the size of the black matrix 210 in the second direction Y, thereby increasing the size of the opening 2101 of the black matrix 210 in the second direction, increasing the area of the light-emitting area AA, and improving the aperture ratio of the display panel.

[0124] It can be understood that, referring to Figure 10, the fourth end 711 of the electrode strip 71 and the sixth sub-portion 72 of the common electrode 70. The direction of the electric field formed between the pixel electrode 40 and the fourth end 711 and the sixth sub-portion 72 of the common electrode 70 is inconsistent with the direction of the electric field formed between the pixel electrode 40 and other parts of the electrode strip 71 (such as the middle part along the second direction Y). This can cause the liquid crystal molecules in the liquid crystal layer 300 to have different deflection angles in the region close to the fourth end 711 of the electrode strip 71 and in other regions (such as the region close to the middle part of the electrode strip 71 along the second direction Y). See Figure 9 To avoid the light transmittance of different regions of the light-emitting area AA being different and to improve the uniformity of the luminance of different regions of the display area, the black matrix 210 needs to cover the fourth end 711 of the electrode strip 71 and the sixth sub-portion 72. Based on the above, the orthographic projection of the end of the electrode strip 71 (the fourth end 711) away from the drain pattern 24 on the substrate 10 is located outside the orthographic projection of the pixel electrode 40 on the substrate 10, which is beneficial to reducing the size of the black matrix 210 along the second direction Y, improving the size of the opening 2101 along the second direction Y, and further improving the aperture ratio of the display panel.

[0125] In some embodiments, see Figure 11 Along the second direction Y, the spacing D12 between the end of the electrode strip 71 (the fourth end 711) away from the drain pattern 24 and the pixel electrode 40 is 0.9 μm to 1.1 μm. That is, the length of the electrode strip 71 extending out of the pixel electrode 40 is 0.9 μm to 1.1 μm. In this way, the length of the electrode strip 71 can be reduced to the greatest extent while improving the aperture ratio of the display panel, and the voltage drop on the electrode strip 71 is reduced. Exemplarily, the spacing D12 between the fourth end 711 of the electrode strip 71 and the pixel electrode 40 can be 0.9 μm, 1 μm, or 1.1 μm, and the like. Embodiments of the present disclosure do not list all of them.

[0126] In some embodiments, see Figure 12 Along the second direction Y, the orthographic projection of the end of the electrode strip 71 (the fifth end 712) close to the drain pattern 24 on the substrate 10 is located within the orthographic projection of the pixel electrode 40 on the substrate 10, and has a spacing with the boundary of the orthographic projection of the pixel electrode 40 on the substrate 10.

[0127] See Figure 12As described above, the black matrix 210 covers the drain pattern 24 in the orthogonal projection on the array substrate 100, and the drain pattern 24 partially overlaps the pixel electrode 40, so the black matrix 210 also covers at least part of the pixel electrode 40 close to the thin film transistor 20. Based on this, the fifth end 712 of the electrode strip 71 is located within the orthogonal projection of the pixel electrode 40 on the substrate 10, and does not increase the width of the black matrix 210 along the second direction Y, so as not to reduce the aperture ratio of the display panel 1100, and is conducive to simplifying the manufacturing difficulty of the common electrode 70.

[0128] For example, referring to Figure 11 , the orthogonal projection of the end (the fifth end 712) of the electrode strip 71 close to the drain pattern 24 on the substrate 10 partially overlaps the orthogonal projection of the drain pattern 24 on the substrate 10, that is, the fifth end 712 of the electrode strip 71 covers part of the drain pattern 24, so that the size of the black matrix 210 along the second direction Y can be reduced without increasing the size of the black matrix 210 along the second direction Y, thereby improving the aperture ratio of the display panel. Moreover, the fifth end 712 of the electrode strip 71 can be covered by the black matrix 210 without increasing the size of the black matrix 210, thereby improving the uniformity of the brightness of the display area AA.

[0129] For example, referring to Figure 9 , the common electrode 70 further includes a first connecting portion 73 connected to the end (the fifth end 712) of the electrode strip 71 close to the drain pattern 24. The first connecting portion 73 can connect two electrode strips 71 into one whole, which is conducive to reducing the resistance of the electrode strip 71, reducing the voltage drop of the common electrode 70, and improving the voltage stability of the common electrode 70. The orthogonal projection of the first connecting portion 73 on the substrate 10 partially overlaps the orthogonal projection of the pixel electrode 40 on the substrate 10, which is conducive to improving the size of the storage capacitor Cst (as shown in Figure 13 ) between the common electrode 70 and the pixel electrode 40 without affecting (reducing) the aperture ratio of the display panel, thereby improving the voltage holding capability of the pixel electrode 40 and the stability of the electric field formed between the pixel electrode 40 and the common electrode 70 in one display period.

[0130] In some embodiments, referring to Figure 13The semiconductor pattern 22 includes a third sub-portion 221 and a fourth sub-portion 222 arranged along the first direction X, and the third sub-portion 221 is closer to the first side wall 211 than the fourth sub-portion 222. The orthogonal projection of the common electrode 70 on the substrate 10 covers the orthogonal projection of the third sub-portion 221 on the substrate 10, and does not overlap the orthogonal projection of the fourth sub-portion 222 on the substrate 10. That is, the orthogonal projection of the common electrode 70 on the substrate 10 partially overlaps the orthogonal projection of the semiconductor pattern 22 on the substrate 10, and the overlapping region is located at the end of the semiconductor pattern 22 closer to the first side wall 211. In other words, the part of the semiconductor pattern 22 and the common electrode 70 on the substrate 10 that overlap each other is the third sub-portion 221, and the other part is the fourth sub-portion 222. As described above, because the interval D1 between the semiconductor pattern 22 and the first side wall 211 is small, the orthogonal projection of the common electrode 70 on the substrate 10 covers the third sub-portion 221, which can reduce the risk of light entering the semiconductor pattern 22 obliquely from the side of the first side wall 211, and improve the light-emitting efficiency of the light-emitting region. It can be understood that, in Figure 13 , the second conductive layer 102 (the source pattern 23 and the drain pattern 24) is omitted in the accompanying drawings for the convenience of showing the positional relationship between the common electrode 70 and the semiconductor pattern 22. Figure 13

[0131] In some embodiments, along the first direction X, the size of the third sub-portion 221 is D15, and D15 is 0.4 μm to 0.6 μm. That is, the width of the orthogonal projection of the common electrode 70 on the substrate 10 covering the orthogonal projection of the semiconductor pattern 22 on the substrate 10 is 0.4 μm to 0.6 μm. In this way, the risk of light entering the semiconductor pattern 22 obliquely can be reduced, and at the same time, the influence of the common electrode 70 on the conductivity of the semiconductor pattern 22 can be reduced, and the stability of the thin film transistor 20 can be improved.

[0132] In some embodiments, referring to Figure 14 , the boundary of the orthogonal projection of the common electrode 70 on the substrate 10 substantially coincides with the orthogonal projection on the substrate 10 of the boundary (the right boundary) of the fourth sub-portion 222 away from the third sub-portion 221, and substantially coincides with the orthogonal projection on the substrate 10 of the boundary of the fourth sub-portion 222 close to the pixel electrode 40. In this way, it is beneficial to reduce the area directly opposite between the common electrode 70 and the semiconductor pattern 22, reduce the influence of the voltage on the common electrode 70 on the semiconductor pattern 22, and maximize the area of the common electrode 70, and reduce the resistance and voltage drop of the common electrode 70.

[0133] ​It should be noted that due to measurement errors, process errors and other factors, the boundary of the orthographic projection of the common electrode 70 on the substrate 10 is approximately coincident with the orthographic projection on the substrate 10 of the right boundary of the fourth sub-portion 222, and it can be understood that the two (the boundary of the orthographic projection of the common electrode 70 on the substrate 10 and the orthographic projection on the substrate 10 of the right boundary of the fourth sub-portion 222) are completely coincident, or at least partially have a spacing, which is within an acceptable deviation range, which can be, for example, less than or equal to 0.5 μm, 1 μm or 2 μm, etc. Also, in other embodiments of the present disclosure, when it is described that the projections of two components are approximately coincident, it can be understood that the projections of the two components are completely coincident, or at least partially, the boundary of the projection of the two components has a spacing, which is within an acceptable deviation range.

[0134] Of course, in some other embodiments, the boundary of the orthographic projection of the common electrode 70 on the substrate 10 can have a spacing from the boundary (right boundary) of the fourth sub-portion 222 away from the third sub-portion 221; and / or, the boundary of the orthographic projection of the common electrode 70 on the substrate 10 can have a spacing from the boundary (upper boundary) of the fourth sub-portion 222 close to the pixel electrode 40. That is, as long as the orthographic projection of the common electrode 70 on the substrate 10 is not coincident with the orthographic projection on the substrate 10 of the fourth sub-portion 222, it is beneficial to reduce the influence of the voltage on the common electrode 70 on the semiconductor pattern 22.

[0135] In some embodiments, referring to Figure 14 , the boundary of the orthographic projection of the black matrix 210 on the substrate 10 of the array substrate 100 has a spacing from the boundary of the orthographic projection on the substrate 10 of the gate electrode pattern 21, the semiconductor pattern 22 and the source electrode pattern 23, and in the case where the drain electrode pattern 24 includes the first sub-portion 241 and the second sub-portion 242, the boundary of the orthographic projection of the black matrix 210 on the substrate 10 of the array substrate 100 is approximately coincident with the boundary (upper boundary) of the second sub-portion 242 away from the first sub-portion 241. In this way, the size of the black matrix 210 along the second direction Y can be minimized, and the area of the opening 2101 on the black matrix 210 can be increased, the area ratio of the display area AA can be increased, and the aperture ratio of the display panel 1100 can be improved. It can be understood that in order to more clearly show the positional relationship between the black matrix 210 and the thin film transistor 20, the common electrode 70 is omitted in the accompanying drawings. Figure 14

[0136] In some embodiments, continuing to refer to Figure 4 ​In some embodiments, referring to FIG. 2, the interval D16 between the boundary of the black matrix 210 and the boundary of the semiconductor pattern 22 in the second direction Y is 6.4 μm to 6.7 μm. In some embodiments, referring to FIG. 2, the semiconductor pattern 22 includes a fifth sub-portion 223, the fifth sub-portion 223 is located between the source electrode pattern 23 and the drain electrode pattern 24, and the minimum interval D17 between the boundary of the fifth sub-portion 223 and the boundary of the black matrix 210 in the second direction Y is 5.7 μm to 6.0 μm. In this way, the width of the black matrix 210 in the second direction Y can be increased to shield the semiconductor pattern 22, thereby reducing the risk of light from the front of the display panel being incident on the semiconductor pattern 22, ensuring that the thin film transistor 20 can work stably, and at the same time, the black matrix 210 can cover the gate electrode pattern 21, the source electrode pattern 23, and the drain electrode pattern 24.

[0137] For example, the interval D16 between the boundary of the black matrix 210 and the boundary of the semiconductor pattern 22 in the second direction Y can be 6.4 μm, 6.55 μm, 6.6 μm, or 6.7 μm, and the like, and the embodiments of the present disclosure will not list them one by one. For example, the minimum interval D17 between the fifth sub-portion 223 and the black matrix 210 in the second direction Y is 5.7 μm, 5.85 μm, 5.9 μm, or 6.0 μm, and the like, and the embodiments of the present disclosure will not list them one by one.

[0138] In some embodiments, referring to Figure 4 The array substrate 100 includes a plurality of pedestals 80 arranged in an array, and the plurality of pedestals 80 are arranged in the same layer as the source electrode pattern 23 and the drain electrode pattern 24, and are located in the second conductive layer 102. For example, as shown in Figure 4 The pedestal 80 is connected to the common voltage signal line 60 as a whole, and the size of the pedestal 80 in the first direction X is greater than the size of the common voltage signal line 60 in the first direction X.

[0139] For example, the shape of the projection of the pedestal 80 on the substrate 10 can be a hexagon, an octagon, a circle, or an ellipse, and the like, and the embodiments of the present disclosure will not be limited specifically. For example, as shown in Figure 15 The shape of the projection of the pedestal 80 on the substrate 10 is an octagon.

[0140] Referring to Figure 16 and Figure 15The display panel 1100 also includes a spacer 400, which is located between the array substrate 100 and the color filter substrate 200, and is connected to both the array substrate 100 and the color filter substrate 200. The spacer 400 supports the array substrate 100 and the color filter substrate 200, ensuring uniform spacing between them. This means the thickness of the liquid crystal layer 300 along the third direction Z is uniform, which improves the brightness uniformity of the display panel. To clearly illustrate the positional relationship between the spacer and the base 80, in... Figure 16 In this design, the pixel electrode 40 and common electrode 70 in the array substrate are omitted, as is the black matrix 210; (Attached) Figure 15 For the attached Figure 15 The graphic is obtained by adding a black matrix 210 to the base.

[0141] It is understandable that, such as Figure 15 As shown, the spacer 400 has a frustum structure. The end face of the spacer 400 that contacts the color filter substrate 200 is the first end face 410, and the surface that contacts the array substrate 100 is the second end face 420. The orthographic projection of the first end face 410 onto the base 80 is within the range of the orthographic projection of the second end face 410 onto the base 80, and there is a gap between the boundary of the first end face 410 and the boundary of the second end face 410.

[0142] The orthographic projection of the spacer 400 onto the substrate 10 lies within the range of the orthographic projection of the abutment 80 onto the substrate 10. For example, the orthographic projection of the second end face 410 onto the abutment 80 lies within the range of the abutment 80. The abutment 80 can support the spacer 400, ensuring uniform stress on the array substrate 100 and reducing the risk of the array substrate 100 being deformed by the spacer 400.

[0143] The shape of the orthographic projection of the spacer 400 onto the substrate 10 may be the same as or different from the shape of the orthographic projection of the base 80 onto the substrate 10. Exemplarily, the shape of the orthographic projection of the spacer 400 onto the substrate 10 may also be hexagonal, octagonal, circular, or elliptical, etc., and the embodiments of this disclosure do not specifically limit this. For example, as... Figure 16 As shown, the shape of the orthographic projection of the spacer 400 onto the substrate 10 is the same as the shape of the orthographic projection of the stage 80 onto the substrate 10, and both are octagonal.

[0144] See Figure 12The black matrix 210 includes a first extending section 2102 and a second extending section 2103. The orthographic projection of the first extending section 2102 on the substrate 10 covers the orthographic projection of the thin film transistor 20 on the substrate 10. The orthographic projection of the second extending section 2103 on the substrate 10 covers the orthographic projection of the base 80 and the spacer 400 on the substrate 10. In the second direction Y, the size D20 of the first extending section 2102 is smaller than the size D21 of the second extending section 2103. That is, the size of the black matrix 210 in the second direction Y can be flexibly set according to the size difference of the thin film transistor 20 and the base 110 in the second direction Y, so as to facilitate reducing the size of the black matrix 210, improving the area of the opening 2101 on the black matrix 210, and improving the aperture ratio of the display panel 1100.

[0145] In some embodiments, the radial size of the end surface (hereinafter referred to as the first end surface 410) of the spacer 400 connected with the color film substrate 200 is D18, and D18 is 8.3 μm to 8.7 μm. On the one hand, the pressure received by the contact position of the color film substrate 200 and the spacer 400 can be reduced, and the risk of extrusion damage of the color film substrate 200 can be reduced. On the other hand, it is beneficial to reduce the size of the spacer 400, thereby reducing the area of the black matrix 210, improving the area of the opening 2101 on the black matrix 210, and improving the aperture ratio of the display panel. Exemplarily, the radial size of the first end surface 410 of the spacer 400 can be 8.3 μm, 8.5 μm, or 8.7 μm, and the like. Embodiments of the present disclosure will not list them one by one.

[0146] It can be understood that the radial size of the first end surface 410 refers to the interval between the two opposite sides of the first end surface 410. Exemplarily, when the shape of the first end surface 410 is octagonal, as shown in FIG. 4B, the radial size of the first end surface 410 can be the interval between the two sides arranged opposite in the second direction Y. Of course, when the shape of the first end surface 410 is circular, the radial size of the first end surface 410 refers to the diameter of the first end surface 410. Figure 2

[0147] The minimum interval between the orthographic projection of the end surface (the first end surface 410) of the spacer 400 connected with the color film substrate 200 on the black matrix 210 and the boundary of the black matrix 210 is D19, and D19 is 6.8 μm to 7.2 μm. That is, the black matrix 210 covers the first end surface 410 of the spacer 400, which can reduce the risk of light leakage of the liquid crystal layer 300 near the spacer 400, and maximally reduce the area of the black matrix 210, increase the area of the opening 2101, and improve the aperture ratio of the display panel. Exemplarily, the minimum interval between the first end surface 410 of the spacer 400 and the boundary of the black matrix 210 can be 6.8 μm, 7.0 μm, or 7.2 μm, and the like. Embodiments of the present disclosure will not list them one by one.​

[0148] In some embodiments, referring to ​ the black matrix on the substrate 10 also covers the orthogonal projections of the gate lines, the data lines and the common voltage signal lines 60 on the substrate 10, so as to reduce the reflection of the light rays entering the display panel from outside on the gate lines, the data lines and the common voltage signal lines.

[0149] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art should be covered in the protection scope of the present disclosure, if any change or replacement is conceived within the technical range disclosed by the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An array substrate, characterized by, The array substrate comprises a substrate, and a plurality of thin film transistors arranged on the substrate in an array, wherein the thin film transistor comprises: a gate pattern arranged on the substrate; a semiconductor pattern arranged on a side of the gate pattern away from the substrate, wherein a projection of the semiconductor pattern on the substrate is located within a projection of the gate pattern on the substrate, and a boundary of the projection of the semiconductor pattern on the substrate is spaced apart from a boundary of the projection of the gate pattern on the substrate; a source pattern and a drain pattern, wherein the source pattern and the drain pattern are arranged in a first direction and are electrically connected to two ends of the semiconductor pattern in the first direction, respectively; wherein the gate pattern comprises a first side wall and a second side wall arranged oppositely in the first direction, the first side wall is close to the source pattern, and the second side wall is close to the drain pattern; in the first direction, a spacing between one end of the source pattern close to the first side wall and the semiconductor pattern is smaller than a spacing between one end of the drain pattern close to the second side wall and the semiconductor pattern, and a spacing between the semiconductor pattern and the first side wall is smaller than a spacing between the semiconductor pattern and the second side wall.

2. The array substrate of claim 1, wherein, The gate pattern further comprises a third side wall and a fourth side wall arranged oppositely in a second direction intersecting the first direction; the spacing between the semiconductor pattern and the third side wall, the spacing between the semiconductor pattern and the fourth side wall, and the spacing between the semiconductor pattern and the second side wall are substantially equal.

3. The array substrate according to claim 2, wherein: a ratio of the spacing between the semiconductor pattern and the first side wall to the spacing between the semiconductor pattern and the second side wall is 0.5-0.

6.

4. The array substrate of claim 1, wherein, The drain pattern comprises: a first sub-portion extending in a second direction and electrically connected to the semiconductor pattern, wherein a projection of the first sub-portion on the substrate is located within the projection of the gate pattern on the substrate, and the second direction intersects the first direction; a second sub-portion connected to the first sub-portion, wherein in the first direction, a projection of an end of the second sub-portion away from the first sub-portion on the substrate is flush with a projection of the second side wall on the substrate, or extends beyond the boundary of the projection of the gate pattern on the substrate.

5. The array substrate according to any one of claims 1-4, wherein: in the first direction, a size of an overlapping portion of the source pattern and the semiconductor pattern and a size of an overlapping portion of the drain pattern and the semiconductor pattern are substantially equal, and a size of the semiconductor pattern in a second direction is greater than a spacing between the source pattern and the drain pattern.

6. The array substrate according to claim 5, wherein: in the first direction, the size of the overlapping portion of the source pattern and the semiconductor pattern and the size of the overlapping portion of the drain pattern and the semiconductor pattern are D3, and D3 is 3-3.85 μm. The size of the semiconductor pattern along the second direction is D4, and D4 is 3 μm-3.7 μm; The interval between the source pattern and the drain pattern is D5, and D5 is 1.8 μm-2.4 μm.

7. The array substrate of claim 1, wherein, Further comprising: A pixel electrode, which is located in the same film layer as the semiconductor pattern, and the orthographic projection of the pixel electrode on the substrate has an interval with the orthographic projection of the gate pattern on the substrate; the pixel electrode comprises an overlap portion, which is electrically connected with the drain pattern; The size of the overlap portion along the first direction is greater than the size of the overlap portion along the second direction.

8. The array substrate according to claim 7, wherein, The size of the overlap portion along the first direction is D6, and D6 is 6.1 μm-6.5 μm; and / or, The size of the overlap portion along the second direction is D7, and D7 is 1.4 μm-1.8 μm.

9. The array substrate of claim 7, wherein, Further comprising: A plurality of data lines and a plurality of common voltage signal lines arranged alternately along the first direction, and the plurality of data lines and the plurality of common voltage signal lines are arranged in the same layer as the source pattern and the drain pattern; In the orthographic projection on the substrate, the interval between the pixel electrode and the common voltage signal line is smaller than the interval between the pixel electrode and the data line.

10. The array substrate of claim 9, wherein, Further comprising: A plurality of gate lines arranged at intervals along the second direction, and each gate line extends along the first direction, and the gate lines are arranged in the same layer as the gate pattern, and the gate lines are electrically connected with the gate pattern; In the orthographic projection on the substrate, the interval between the pixel electrode and the gate pattern is equal to the interval between the pixel electrode and the gate line.

11. The array substrate of claim 10, wherein, The interval between the pixel electrode and the gate pattern is smaller than the interval between the pixel electrode and the common voltage signal line.

12. The array substrate of claim 10, wherein, Along the first direction, the size of the data line is substantially equal to the size of the common voltage signal line, and the size of the data line along the first direction is smaller than the size of the overlapping portion of the source pattern and the semiconductor pattern along the first direction.

13. The array substrate according to claim 12, wherein, The interval between the pixel electrode and the common voltage signal line along the first direction is D8, and D8 is 2.4 μm-2.8 μm; The interval between the pixel electrode and the data line along the first direction is D9, and D9 is 3.0 μm-3.4 μm; The interval between the pixel electrode and the gate line along the second direction is D10, and D10 is 2.0 μm-2.4 μm; The size of the data line and the common voltage signal line along the first direction is D11, and D11 is 2.4 μm-2.8 μm.

14. The array substrate according to any one of claims 7 to 13, wherein, Further comprising: A common electrode, which is located on the side of the source pattern and the drain pattern away from the substrate, and comprises at least one electrode strip extending along the second direction; In the orthographic projection on the substrate, the orthographic projection of the end of the electrode strip away from the drain pattern on the substrate is located outside the range of the orthographic projection of the pixel electrode on the substrate.

15. The array substrate according to claim 14, wherein, In the second direction, a normal projection of an end of the electrode strip close to the drain pattern on the substrate is within a range of a normal projection of the pixel electrode on the substrate, and partially overlaps with the normal projection of the drain pattern on the substrate; The common electrode further comprises a first connecting part connected to the end of the electrode strip close to the drain pattern; a normal projection of the first connecting part on the substrate partially overlaps with a normal projection of the pixel electrode on the substrate.

16. The array substrate of claim 14, wherein, The common electrode further comprises a plurality of slits arranged along the first direction, and each of the slits comprises one of the electrode strips; In the first direction, a size of the slit is greater than a size of the electrode strip.

17. The array substrate of claim 16, wherein, In the second direction, a distance between the end of the electrode strip away from the drain pattern and the pixel electrode is D12, and D12 is 0.9 μm-1.1 μm; A size of the slit along the first direction is D13, and D13 is 2.6 μm-2.9 μm; A size of the electrode strip along the first direction is D14, and D14 is 1.9 μm-2.1 μm.

18. The array substrate of claim 14, wherein, The semiconductor pattern comprises a third sub-part and a fourth sub-part arranged along the first direction, and the third sub-part is closer to the first sidewall than the fourth sub-part; A normal projection of the common electrode on the substrate covers a normal projection of the third sub-part on the substrate, and does not overlap with a normal projection of the fourth sub-part on the substrate.

19. The array substrate of claim 18, wherein, In the first direction, a size of the third sub-part is D15, and D15 is 0.4 μm-0.6 μm.

20. The array substrate of claim 18, wherein, A boundary of a normal projection of the common electrode on the substrate substantially coincides with a normal projection on the substrate of a boundary of the fourth sub-part away from the third sub-part, and substantially coincides with a normal projection on the substrate of a boundary of the fourth sub-part close to the pixel electrode.

21. A display panel, comprising: comprising: The array substrate of any one of claims 1-20; A color filter substrate arranged opposite to the array substrate, and the color filter substrate comprises a black matrix, and a normal projection of the black matrix on the array substrate covers a thin film transistor of the array substrate.

22. The display panel of claim 21, wherein, The drain pattern of the thin film transistor comprises a first sub-part and a second sub-part; A boundary of a normal projection of the black matrix on a substrate of the array substrate has a distance from a boundary of a normal projection on the substrate of a gate pattern, a semiconductor pattern and a source pattern of the thin film transistor, and substantially coincides with a boundary of the second sub-part away from the first sub-part.

23. The display panel of claim 22, wherein, In the second direction, a distance between a boundary of a normal projection of the black matrix on the substrate and a boundary of a normal projection of the semiconductor pattern on the substrate is D16, and D16 is 6.4 μm-6.7 μm; and / or, The semiconductor pattern includes a fifth sub-portion between the source pattern and the drain pattern, a boundary of a normal projection of the black matrix on the substrate is at least partially coincident with an end of the fifth sub-portion along the second direction.

24. The display panel of any one of claims 21-23, wherein, The array substrate includes a plurality of sub-mounts arranged in an array, the plurality of sub-mounts are disposed in the same layer as the source pattern and the drain pattern; The display panel further includes: A spacer between the array substrate and the color filter substrate, and connected to the array substrate and the color filter substrate respectively, a normal projection of the spacer on the substrate is within a range of a normal projection of the sub-mount on the substrate; The black matrix includes: A first extension, a normal projection of the first extension on the substrate covers a normal projection of the thin film transistor on the substrate; A second extension, a normal projection of the second extension on the substrate covers normal projections of the sub-mount and the spacer on the substrate; In the second direction, a size of the first extension is smaller than a size of the second extension.

25. The display panel of claim 24, wherein: A radial size of an end surface of the spacer connected to the color filter substrate is D18, D18 is 8.3 μm-8.7 μm; and / or A minimum interval between a normal projection of the end surface of the spacer connected to the color filter substrate on the black matrix and a boundary of the black matrix is D19, D19 is 6.8 μm-7.2 μm.

26. The display panel of claim 21, wherein, The array substrate includes a common electrode, the common electrode includes at least one electrode strip extending in the second direction; A normal projection of the black matrix on the array substrate is at least partially coincident with an end of the electrode strip along the second direction.

27. A display device comprising: It includes: The display panel of any one of claims 21-26; A drive circuit board configured to transmit a control signal to the display panel.

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