Array substrate, display panel and display device

Abstract

The present disclosure discloses an array substrate, a display panel and a display device to avoid the shaking lines. The array substrate comprises: a first substrate, comprising a sub-pixel region and a wiring region; a thin film transistor, comprising: a first electrode; a first electrode, comprising a plurality of first opening regions; the first opening region has an overlap with the first electrode in the orthographic projection of the first substrate; a second electrode, comprising: a first connecting portion; the first connecting portion comprises: a first sub-connecting portion, and a second sub-connecting portion; the second sub-connecting portion comprises structures respectively located on the opposite sides of the first sub-connecting portion; the orthographic projection of the first sub-connecting portion falls within the orthographic projection of the first opening region on the first substrate, and the orthographic projection of the second sub-connecting portion has an overlap with the orthographic projection of the first electrode and the first opening region on the first substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly relates to an array substrate, a display panel and a display device. BACKGROUND

[0002] With the continuous development and application of display technology, users have higher and higher requirements for the display effect of electronic display products.

[0003] At present, liquid crystal display products adopt a dual gate design to reduce costs. However, due to the parasitic capacitance between the pixel electrode and the common electrode, when the overall pixel electrode corresponding to each sub-pixel is offset due to process deviation, the parasitic capacitance of different pixel electrodes will be greatly different, the charging rate of different pixel electrodes will be greatly different, and thus the brightness of different sub-pixels will be different. When the user moves to watch, for example, shakes his head during the use of the display product, the brightness of the sub-pixels with higher brightness will be superimposed on each other, and the brightness of the sub-pixels with lower brightness will also be superimposed on each other, so that the brightness difference is aggravated, and thus the head-shaking lines appear, which affects the display effect of the display product. SUMMARY

[0004] Embodiments of the present disclosure provide an array substrate, a display panel and a display device to avoid head-shaking lines.

[0005] An array substrate provided by an embodiment of the present disclosure includes:

[0006] A first substrate includes a plurality of sub-pixel regions and a wiring region between adjacent sub-pixel regions, which are arranged in a first direction and a second direction; the first direction intersects the second direction.

[0007] A plurality of thin film transistors are located on one side of the first substrate; each thin film transistor includes a first electrode, a second electrode and a third electrode.

[0008] A first electrode is located on a side of the first electrode away from the first substrate and includes a plurality of first opening regions; the first opening region is in the orthographic projection of the first substrate and falls within the wiring region, and the first opening region in the orthographic projection of the first substrate overlaps the orthographic projection of the first electrode in the first substrate.

[0009] The plurality of second electrodes are located on the same side of the first substrate as the first electrodes; each of the plurality of second electrodes comprises: a first connecting portion; the first connecting portion comprises: a first sub-connecting portion electrically connected to the first electrode, and a second sub-connecting portion electrically connected to the first sub-connecting portion; the second sub-connecting portion comprises structures respectively located on two opposite sides of the first sub-connecting portion; the first sub-connecting portion is located within the first projection of the first substrate, and the second sub-connecting portion has an overlap with the first electrode and the first opening region in the first projection of the first substrate.

[0010] In some embodiments, the second sub-connecting portion comprises a first structure and a second structure;

[0011] In the first direction, the first structure and the second structure are respectively located on two sides of the first sub-connecting portion.

[0012] In some embodiments, the first structure comprises a first region adjacent to the first sub-connecting portion, and the second structure comprises a second region adjacent to the first sub-connecting portion;

[0013] In the first direction, the distance between the first sub-connecting portion and the edge of the first opening region on the side of the first sub-connecting portion facing the first structure in the first projection of the first substrate is less than the width of the first region in the first projection of the first substrate, and the distance between the first sub-connecting portion and the edge of the first opening region on the side of the first sub-connecting portion facing the second structure in the first projection of the first substrate is less than the width of the second region in the first projection of the first substrate.

[0014] In some embodiments, in the second direction, the maximum width of the first sub-connecting portion in the first projection of the first substrate is less than the width of the first opening region in the first projection of the first substrate, the maximum width of the first sub-connecting portion in the first projection of the first substrate is greater than the total width of the second sub-connecting portion of the first region in the first projection of the first substrate, and the maximum width of the first sub-connecting portion in the first projection of the first substrate is greater than the total width of the second sub-connecting portion of the second region in the first projection of the first substrate.

[0015] In some embodiments, the first structure comprises at least one first sub-structure connected to the first sub-connecting portion; the second structure comprises at least one second sub-structure connected to the first sub-connecting portion;

[0016] In the second direction, the total width of the first sub-structure of the first region in the first projection of the first substrate is equal to the total width of the second sub-structure of the second region in the first projection of the first substrate.

[0017] In some embodiments, the plurality of sub-pixel regions and the plurality of wiring regions are divided into a plurality of sub-pixel columns arranged along a first direction and extending along a second direction; the plurality of second electrodes include a plurality of first sub-electrodes and a plurality of second sub-electrodes;

[0018] The first sub-electrode and the thin film transistor electrically connected thereto are located in the same sub-pixel column;

[0019] The second sub-electrode and the thin film transistor electrically connected thereto are located in different sub-pixel columns.

[0020] In some embodiments, the second electrode further includes: a pixel portion corresponding to the sub-pixel region and connected to the first connecting portion;

[0021] The second sub-connecting portion of the first sub-electrode further includes: a third structure; in the second direction, the third structure is located between the first structure and the pixel portion; the third structure is electrically connected to the pixel portion, and at least one of the first sub-connecting portion and the first structure is connected to the third structure.

[0022] In some embodiments, in the first sub-electrode, the third structure does not overlap with the first opening region in the first substrate substrate.

[0023] In some embodiments, in the first sub-electrode and its corresponding thin film transistor, in the first direction, the first structure and the second electrode are located on the same side of the first opening region; the third structure and the second electrode have an overlap in the first substrate substrate.

[0024] In some embodiments, in the first sub-electrode, in the first direction, the length of the first structure in the first substrate substrate is greater than the length of the second structure in the first substrate substrate.

[0025] In some embodiments, the third structure has an overlap with the first opening region in the first substrate substrate.

[0026] In some embodiments, in the first sub-electrode, the second sub-connecting portion further includes a fourth structure; in the second direction, the third structure and the fourth structure are respectively located on both sides of the first sub-connecting portion.

[0027] In some embodiments, in the first sub-electrode, the third structure includes a third region adjacent to the first sub-connecting portion, and the fourth structure includes a fourth region adjacent to the first sub-connecting portion;

[0028] In the second direction, a distance between the first substrate substrate's orthogonal projection of the first sub-connection portion and an edge of the first opening region of the first sub-connection portion toward the third structure side in the first substrate substrate's orthogonal projection is less than a width of the third region in the first substrate substrate's orthogonal projection, and a distance between the first substrate substrate's orthogonal projection of the first sub-connection portion and an edge of the first opening region of the first sub-connection portion toward the fourth structure side in the first substrate substrate's orthogonal projection is less than a width of the fourth region in the first substrate substrate's orthogonal projection.

[0029] In some embodiments, the third structure includes at least one third sub-structure connected with the first sub-connection portion, and the fourth structure includes at least one fourth sub-structure connected with the first sub-connection portion.

[0030] In the first direction, a total width of the third sub-structure of the third region in the first substrate substrate's orthogonal projection is equal to a total width of the fourth sub-structure of the fourth region in the first substrate substrate's orthogonal projection.

[0031] In some embodiments, the second sub-connection portion of the second sub-electrode further includes a fifth structure connected with the first structure and the pixel portion between the first structure and the pixel portion in the second direction.

[0032] In some embodiments, the pixel portion of the first sub-electrode has a first overlapping area with the first electrode in the first substrate substrate's orthogonal projection, the pixel portion of the second sub-electrode has a second overlapping area with the first electrode in the first substrate substrate's orthogonal projection; the first connection portion of the first sub-electrode has a third overlapping area with the first electrode in the first substrate substrate's orthogonal projection, and the first connection portion of the second sub-electrode has a fourth overlapping area with the first electrode in the first substrate substrate's orthogonal projection; the first overlapping area is substantially equal to the second overlapping area, and the third overlapping area is substantially equal to the fourth overlapping area.

[0033] In some embodiments, the first electrode further includes a plurality of second opening regions in the wiring region; the second opening region has an overlapping with the first connection portion of the second sub-electrode in the first substrate substrate's orthogonal projection.

[0034] In some embodiments, in the first direction, the first sub-electrode and the second sub-electrode are arranged alternately, and in the second direction, the first sub-electrode and the second sub-electrode are arranged alternately.

[0035] In some embodiments, the array substrate further includes:

[0036] A plurality of data lines are located on the side of the first electrode facing the first substrate and are arranged in the first direction and extend in the second direction; each data line of the plurality of data lines is electrically connected to the second electrode of the thin film transistor; two adjacent data lines are separated by two columns of sub-pixels;

[0037] The plurality of wiring regions are divided into a plurality of wiring region rows extending in the first direction; each wiring region row includes a plurality of first sub-regions and a plurality of second sub-regions; each first sub-region of the plurality of first sub-regions is adjacent to a sub-pixel region in the second direction, and the first sub-region is located between two adjacent data lines; each second sub-region of the plurality of second sub-regions is adjacent to a sub-pixel region in the second direction, and the second sub-region is located between two adjacent data lines; in the second direction, the first sub-regions and the second sub-regions are alternately arranged;

[0038] The plurality of thin film transistors include a plurality of first thin film transistors and a plurality of second thin film transistors; the first thin film transistors are electrically connected to the first sub-electrodes, and the second thin film transistors are electrically connected to the second sub-electrodes; the first thin film transistors are located in the first sub-regions, and the second thin film transistors are located in the second sub-regions;

[0039] In the Mth wiring region row, two first sub-regions are separated by m second sub-regions; in the (M+1)th wiring region row, two second sub-regions are separated by m first sub-regions; wherein M is an integer greater than or equal to 1, m is an integer greater than 1, and (M+1) is less than or equal to the total number of wiring region rows.

[0040] In some embodiments, m=2.

[0041] In some embodiments, the array substrate further comprises:

[0042] A plurality of scan lines are located on the side of the wiring region facing the first electrode; the plurality of scan lines extend in the first direction and are arranged in the second direction; the plurality of scan lines include a plurality of first scan lines and a plurality of second scan lines; the first scan lines and the second scan lines are alternately arranged; between two adjacent sub-pixel regions in the second direction, there is one first scan line and one second scan line; the scan lines are disposed in the same layer as and electrically connected to the third electrode of the thin film transistor; the scan lines include a first compensation portion corresponding to the thin film transistor;

[0043] The first electrode of the thin film transistor includes a first portion, and a second portion and a third portion located on the two sides of the first portion in the first direction, respectively;

[0044] The first portion is projected onto the region between the third electrode and the first compensation portion in the first substrate, the second portion has an overlap with the third electrode in the first substrate, and the third portion has an overlap with the first compensation portion in the first substrate.

[0045] In some embodiments, in the second direction, the width of the third portion in the orthogonal projection of the first substrate and the width of the second portion on the side close to the first portion in the orthogonal projection of the first substrate are equal.

[0046] In some embodiments, in the first sub-region, the scan line comprises: a first portion extending along the first direction, and a second portion extending along the third direction and connected with the first portion; the third direction intersects with the first direction and the second direction; the first compensation portion is located on the side of the second portion facing the third electrode.

[0047] In some embodiments, in the second sub-region, the scan line comprises: a second portion extending along the first direction, and a third portion extending along the third direction and connected with the second portion; the third direction intersects with the first direction and the second direction; the first compensation portion is located on the side of the third portion facing the third electrode.

[0048] In some embodiments, in the second sub-region, the scan line comprises: a second portion extending along the first direction; the first compensation portion is connected with the second portion in the second direction, and in the second direction, the first compensation portion and the third electrode are located on the same side of the second portion.

[0049] In some embodiments, in the second sub-region, the orthogonal projection of the second opening region on the first substrate and the scan line do not overlap, and the orthogonal projection of the second opening region on the first substrate falls within the region between the adjacent two first compensation portions in the orthogonal projection of the first substrate.

[0050] In some embodiments, in at least part of the second sub-region, the second opening regions corresponding to the two first connection portions are integrally connected.

[0051] In some embodiments, the array substrate comprises a plurality of scan lines;

[0052] The orthogonal projection of the pixel portion on the first substrate and the orthogonal projection of the scan line on the first substrate have an overlap.

[0053] In some embodiments, the first electrode comprises a plurality of slit units, or the pixel portion comprises a slit unit; the orthogonal projection of the slit unit on the first substrate and the sub-pixel region have an overlap;

[0054] The slit unit comprises: first sub-units and second sub-units arranged alternately in the second direction; the first sub-unit comprises a plurality of first slits extending along the fourth direction and arranged along the first direction, and the second sub-unit comprises a plurality of second slits extending along the fifth direction and arranged along the first direction; the fourth direction intersects with the fifth direction, and the fourth direction intersects with the first direction and the second direction; the fifth direction intersects with the first direction and the second direction;

[0055] The array substrate further includes a plurality of first electrode lines extending along the first direction and arranged along the second direction on a side of the first electrode facing the first substrate;

[0056] The first electrode line has an overlapping portion with the first sub-unit and the second sub-unit in the orthogonal projection of the first substrate.

[0057] In some embodiments, the array substrate further includes a peripheral electrode line; the orthogonal projection of the peripheral electrode line on the first substrate surrounds the plurality of sub-pixel regions and the plurality of wiring regions.

[0058] The first electrode line is electrically connected to the peripheral first electrode line.

[0059] In some embodiments, the array substrate further includes:

[0060] a plurality of data lines;

[0061] a plurality of second electrode lines arranged in the same layer as the first electrode lines in the wiring regions and electrically connected to the first electrode lines, extending along the second direction; two adjacent second electrode lines are separated by two sub-pixel columns; the second electrode lines and the data lines are alternately arranged along the first direction.

[0062] The display panel provided by the embodiments of the present disclosure includes:

[0063] The array substrate provided by the embodiments of the present disclosure includes:

[0064] The opposite substrate is arranged opposite to the array substrate.

[0065] The liquid crystal layer is arranged between the array substrate and the opposite substrate.

[0066] In some embodiments, the array substrate includes a plurality of data lines; the opposite substrate includes:

[0067] a second substrate;

[0068] a plurality of spacers arranged on a side of the second substrate facing the liquid crystal layer; the orthogonal projection of the spacers on the first substrate falls in the wiring regions, and the orthogonal projection of the spacers on the first substrate has an overlapping portion with the orthogonal projection of the data lines on the first substrate.

[0069] The display device provided by the embodiments of the present disclosure includes the display panel provided by the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0070] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings in the following description only some of the embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0071] Figure 1 A structural schematic diagram of an array substrate provided by the related art;

[0072] Figure 2 A structural schematic diagram of an array substrate provided by the present disclosure;

[0073] Figure 3 A structural schematic diagram of an array substrate provided by the present disclosure along AA'; Figure 2

[0074] A structural schematic diagram of another array substrate provided by the present disclosure; Figure 4

[0075] A structural schematic diagram of still another array substrate provided by the present disclosure; Figure 5

[0076] A structural schematic diagram of still another array substrate provided by the present disclosure; Figure 6

[0077] A structural schematic diagram of still another array substrate provided by the present disclosure; Figure 7

[0078] A structural schematic diagram of still another array substrate provided by the present disclosure; Figure 8

[0079] A structural schematic diagram of still another array substrate provided by the present disclosure; Figure 9

[0080] A structural schematic diagram of still another array substrate provided by the present disclosure; Figure 10

[0081] A structural schematic diagram of still another array substrate provided by the present disclosure; Figure 11

[0082] A structural schematic diagram of still another array substrate provided by the present disclosure; Figure 12

[0083] A structural schematic diagram of still another array substrate provided by the present disclosure; Figure 13

[0084] A structural schematic diagram of still another array substrate provided by the present disclosure; Figure 14A structure schematic diagram of an array substrate provided by another embodiment of the present disclosure is shown in FIG. 6;

[0085] Figure 15 A structure schematic diagram of an array substrate provided by another embodiment of the present disclosure is shown in FIG. 6;

[0086] Figure 16 A structure schematic diagram of a first electrode line and a second electrode line provided by an embodiment of the present disclosure is shown in FIG. 7;

[0087] Figure 17 A structure schematic diagram of a display panel provided by an embodiment of the present disclosure is shown in FIG. 8;

[0088] Figure 18 A structure schematic diagram of a display panel provided by another embodiment of the present disclosure is shown in FIG. 9. DETAILED DESCRIPTION

[0089] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Moreover, the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict, if possible. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0090] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood as the common meanings thereof by those having ordinary skills in the art to which the present disclosure belongs. The terms “first”, “second” and similar words used in the present disclosure do not represent any order, number or importance, but are only used to distinguish different constituent parts. The terms “comprise”, “contain” and similar words mean that the elements or objects before the words cover the elements or objects listed after the words and their equivalents, without excluding other elements or objects. The terms “connect” or “connected” and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0091] It should be noted that the sizes and shapes of the figures in the drawings do not reflect the true proportions, but only serve to illustrate the present disclosure. Moreover, the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout the drawings.

[0092] In the related art, as shown in FIG. 1, a display panel 100 includes an array substrate 110 and a color filter substrate 120. Figure 1As shown, the array substrate includes a common electrode 21 and a plurality of pixel electrodes 22, the common electrode 21 has an opening region 2101, the pixel electrodes 22 are divided into three parts a, b and c, wherein the a part falls within the opening region 2101 in the orthographic projection of the substrate substrate (not shown), the c part does not overlap with the opening region 2101 in the orthographic projection of the substrate substrate, the b part connects the a part and the c part, the b-1 region of the b part does not overlap with the opening region 2101 in the orthographic projection of the substrate substrate, and the b-2 region of the b part has overlap with the opening region 2101 in the orthographic projection of the substrate substrate. That is, in the pixel electrode 22, the c part and the b-1 region have overlap with the common electrode 21 in the orthographic projection of the substrate substrate. Generally, the orthographic projection of the c part corresponding to each sub-pixel on the substrate substrate has the same overlap area with the orthographic projection of the common electrode on the substrate substrate, which is S1, and even if there is process deviation, it will not affect the overlap area with the common electrode. The width of the b part of each pixel electrode 22 in the first direction X is L1, and in the ideal case, the width of the b-1 region in the second direction Y is L2, the overlap area S2 of the b part of each pixel electrode 22 on the orthographic projection of the substrate substrate with the orthographic projection of the common electrode 21 on the substrate substrate is L1xL2, and the overlap area S3 of the pixel electrode 22 on the orthographic projection of the substrate substrate with the orthographic projection of the common electrode 21 on the substrate substrate is S1+S2. However, in the second direction Y, if the plurality of pixel electrodes 22 as a whole are shifted upward or downward, the pixel electrode 22 as a whole is shifted upward by ΔL, Figure 1 The width of the b-1 region of the pixel electrode 22-1 in the second direction Y is L2-ΔL, and the overlap area of the b part of the pixel electrode 22-1 on the orthographic projection of the substrate substrate with the orthographic projection of the common electrode 21 on the substrate substrate is S2'=L1x(L2-ΔL)<S2, and the corresponding overlap area S3' of the pixel electrode 22-1 on the orthographic projection of the substrate substrate with the orthographic projection of the common electrode 21 on the substrate substrate is <S3; Figure 1The width of the b-1 region of the middle pixel electrode 22-2 in the second direction Y is L2+AL, the overlapping area of the b part of the pixel electrode 22-2 in the orthographic projection of the substrate substrate and the orthographic projection of the common electrode 21 on the substrate substrate is S2'=L1x(L2+AL)>S2, and the corresponding overlapping area S3' of the orthographic projection of the pixel electrode 22-2 on the substrate substrate and the orthographic projection of the common electrode 21 on the substrate substrate is greater than S3. That is, in the second direction Y, if the plurality of pixel electrodes 22 as a whole is shifted upward or downward, the width of the b-1 region of part of the pixel electrodes in the second direction Y is greater than L2, the width of the b-1 region of part of the pixel electrodes in the second direction Y is less than L2, and the corresponding overlapping area of the b part of part of the pixel electrodes in the orthographic projection of the substrate substrate and the orthographic projection of the common electrode on the substrate substrate is greater than S2, and the overlapping area of the b part of part of the pixel electrodes in the orthographic projection of the substrate substrate and the orthographic projection of the common electrode 21 on the substrate substrate is less than S2. Further, the overlapping area of the orthographic projection of part of the pixel electrodes on the substrate substrate and the orthographic projection of the common electrode on the substrate substrate is greater than S3, and the overlapping area of the orthographic projection of part of the pixel electrodes on the substrate substrate and the orthographic projection of the common electrode on the substrate substrate is less than S3. The parasitic capacitance between different pixel electrodes is different, resulting in a large difference in the charging rate of different pixel electrodes, thereby causing a difference in the brightness of different sub-pixels, easily causing a shaking line, and affecting the user experience.

[0093] The embodiment of the present disclosure provides an array substrate, as shown in the figure, the array substrate comprises: Figures 2-3 As shown in the figure, the array substrate comprises:

[0094] A first substrate substrate 1 comprises a plurality of sub-pixel regions 101 and wiring regions 102 between adjacent sub-pixel regions 101 arranged in an array along a first direction X and a second direction Y; the first direction X and the second direction Y intersect;

[0095] A plurality of thin film transistors 2 are located on one side of the first substrate substrate 1; each thin film transistor 2 of the plurality of thin film transistors 2 comprises a first electrode D, a second electrode S, and a third electrode G;

[0096] A first electrode 3 is located on the side of the first electrode D away from the first substrate substrate 1 and comprises a plurality of first opening regions 301; the orthographic projection of the first opening region 301 on the first substrate substrate 1 falls within the wiring region 102, and the orthographic projection of the first opening region 301 on the first substrate substrate 1 and the orthographic projection of the first electrode D on the first substrate substrate 1 have an overlap;

[0097] The plurality of second electrodes 4 are located on the same side of the first substrate 1 as the first electrodes 3. Each of the plurality of second electrodes 4 comprises a first connecting portion 401. The first connecting portion 401 comprises a first sub-connecting portion 4011 electrically connected to the first electrode D, and a second sub-connecting portion 4012 electrically connected to the first sub-connecting portion 4011. The second sub-connecting portion 4012 comprises portions respectively located on opposite sides of the first sub-connecting portion 4011. The first sub-connecting portion 4011 is located within the first opening region 301 in the first substrate 1 in the orthographic projection of the first substrate 1. The second sub-connecting portion 4012 has an overlap with the first electrode 3 in the orthographic projection of the first substrate 1.

[0098] It should be noted that the second sub-connecting portion comprises portions respectively located on opposite sides of the first sub-connecting portion. For example, the second sub-connecting portion 4012 can comprise portions respectively located on opposite sides of the first sub-connecting portion 4011 in the first direction X, as shown in FIG. 4A. Figure 2 Alternatively, as shown in FIG. 4B, the second sub-connecting portion 4012 can comprise portions respectively located on opposite sides of the first sub-connecting portion 4011 in the second direction Y. Of course, the second sub-connecting portion can comprise portions respectively located on opposite sides of the first sub-connecting portion in the first direction X and portions respectively located on opposite sides of the first sub-connecting portion in the second direction Y. Figure 4

[0099] ​The array substrate provided by the embodiments of the present disclosure, the second electrode includes a first sub-connection part and a part of the second sub-connection part located on the opposite sides of the first sub-connection part, the first sub-connection part is in the first opening area of the first electrode in the orthographic projection of the substrate substrate, and the part of the second sub-connection part on the opposite sides of the first sub-connection part has an overlap with the first electrode and the first opening area in the orthographic projection of the substrate substrate, when all the second electrodes included in the array substrate are offset due to process deviation, that is, the second sub-connection parts located on the opposite sides of the first sub-connection part are all offset, compared with the case where no offset occurs, the opposite sides of the first sub-connection part are connected with the second sub-electrode, in each second electrode, the part of the second sub-connection part located on one side of the first sub-connection part increases the overlapping area with the first electrode in the orthographic projection of the substrate substrate, and the part of the second sub-connection part located on the other side of the first sub-connection part decreases the overlapping area with the first electrode in the orthographic projection of the substrate substrate, because the offset amounts of the second sub-connection parts located on the opposite sides of the first sub-connection part are the same, the changes of the overlapping areas of the parts of the second sub-connection parts located on the opposite sides of the first sub-connection part with the first electrode in the orthographic projection of the substrate substrate can be complementary, even if the positions of the second electrodes are offset due to process deviation, the parasitic capacitances of the second electrodes and the first electrode are still equal, and the large difference in the charging rates of different second electrodes caused by the different parasitic capacitances of different second electrodes and the first electrode is avoided, when the array substrate is applied to a display product, the difference in the brightness of different sub-pixel areas is avoided, when a user moves to watch, the brightness difference is avoided from being aggravated, the shaking lines are avoided from appearing, the display effect is improved, and the user experience is improved.

[0100] It should be noted that, Figure 2 In the figures, only a part of the array substrate is shown, and in order to intuitively show the positional relationship of the orthographic projection of the first electrode and the second electrode on the substrate substrate, Figure 2 In the figures, the first substrate substrate and the thin film transistor are not shown. Figure 2 In the figures, the first direction X and the second direction Y are perpendicular as an example. Figure 3 In the figures, Figure 2 In the figures, the cross-sectional view of AA' is shown.

[0101] In some embodiments, as shown in Figure 2 , Figure 5 The array substrate multiple sub-pixel areas 101 and multiple wiring areas 102 are divided into: multiple sub-pixel columns 7 arranged along the first direction X and extending along the second direction Y, multiple sub-pixel rows 24 extending along the first direction X and arranged along the second direction Y, and multiple wiring area rows 10 extending along the first direction X and arranged along the second direction Y; in the second direction Y, the sub-pixel rows 24 and the wiring area rows 10 are arranged alternately;

[0102] As Figure 5 shown, the array substrate further comprises:

[0103] a plurality of scan lines 14, located at the side of the first electrode 3 facing the first substrate 1 in the wiring area 102; the plurality of scan lines 14 extend along the first direction X and are arranged along the second direction Y; the plurality of scan lines 14 comprise a plurality of first scan lines 14-1 and a plurality of second scan lines 14-2; the first scan lines 14-1 and the second scan lines 14-2 are arranged alternately; one first scan line 14-1 and one second scan line 14-2 are included between two adjacent sub-pixel areas 101 in the second direction Y; the scan lines 14 are arranged in the same layer as the third electrode G of the thin film transistor 2 and are electrically connected.

[0104] In a specific implementation, the scan lines are located in the wiring area rows, and one first scan line and one second scan line correspond to one row of sub-pixel area rows between two rows of wiring area rows; that is, one first scan line and one second scan line are respectively located on the two sides of one row of sub-pixel area rows in the second direction.

[0105] That is, the scan lines of the array substrate provided in the embodiments of the present disclosure are designed as Dual Gate (double gate).

[0106] In some embodiments, as Figure 5 shown, the array substrate further comprises:

[0107] a plurality of data lines 20, located at the side of the first electrode 3 facing the first substrate 1 in the wiring area 102, arranged along the first direction X and extending along the second direction Y; each data line 20 in the plurality of data lines 20 is electrically connected to the second electrode S of the thin film transistor 2; two sub-pixel columns 7 are spaced between two adjacent data lines 20;

[0108] a plurality of first electrode lines 18, located at the side of the first electrode 3 facing the first substrate 1, extending along the first direction X and arranged along the second direction Y;

[0109] a plurality of second electrode lines 23, arranged in the same layer as the wiring area 102 and electrically connected to the first electrode line 18, extending along the second direction Y; two sub-pixel columns 7 are spaced between two adjacent second electrode lines 23; the second electrode lines 23 and the data lines 20 are arranged alternately in the first direction X.

[0110] In some embodiments, as Figure 5 shown, in the wiring area 102 between two adjacent rows of sub-pixel areas 24, the data lines 20 located between two adjacent sub-pixel area columns 7 are respectively electrically connected to two thin film transistors 2, and the two thin film transistors 2 are respectively located on the two sides of the data line 24 in the first direction X.

[0111] The array substrate provided by the embodiments of the present disclosure can reduce the number of data lines and reduce costs because the scan lines are designed as Dual Gate and one data line can drive multiple columns of sub-pixel area columns.

[0112] In some embodiments, as shown in Figure 3 The second electrode 4 is located on the side of the first electrode 3 away from the first substrate 1. The first electrode 3 is, for example, a planar electrode, and a plurality of first opening regions 301 are arranged to avoid the connection between the second electrode 4 and the first electrode D of the thin film transistor 2.

[0113] In specific implementation, the third electrode is arranged in the same layer as the scan line, and the electrically connected third electrode and scan line can be integrally connected; the first electrode, the second electrode and the data line are arranged in the same layer, and the electrically connected second electrode and data line can be integrally connected.

[0114] It should be noted that in the present disclosure, "in the same layer" means that a film layer used for manufacturing a specific pattern is formed by using the same film forming process, and then the layer structure is formed by using the same mask plate through one patterning process. That is, one patterning process corresponds to one mask (also known as a photomask). According to different specific patterns, one patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns can be at the same height or have the same thickness, or can be at different heights or have different thicknesses.

[0115] In specific implementation, for example, the first electrode of the thin film transistor is the drain electrode, the second electrode of the thin film transistor is the source electrode, and the third electrode of the thin film transistor is the gate electrode. The first electrode is a common electrode, which is, for example, arranged in an entire layer; the second electrode is a pixel electrode. That is, the array substrate provided by the embodiments of the present disclosure has the common electrode located between the thin film transistor and the pixel electrode. The first electrode, that is, the common electrode of the array substrate provided by the embodiments of the present disclosure is arranged in an entire layer and is designed to be hollow only in the first opening region, so that the first electrode arranged in the entire layer can effectively shield the signals of the scan line and the data line, and can also shield the signals of the thin film transistor, so that the second electrode is not interfered by the signal line below, and the parasitic capacitance between the scan line and the second electrode is not generated, thereby not affecting the display quality.

[0116] It should be noted that the plurality of sub-pixel regions correspond to the regions divided by the plurality of scan lines, the plurality of data lines and the plurality of second electrode lines, and when the array substrate is applied to a display product, the sub-pixel region corresponds to the sub-pixel opening region of the display product, that is, the sub-pixel region and the sub-pixel opening region of the display product are in the orthographic projection of the first substrate. The wiring region corresponds to the sub-pixel non-opening region of the display product.

[0117] In some embodiments, as shown in Figure 2 , Figure 5As shown, the plurality of second electrodes 4 includes a plurality of first sub-electrodes 9 and a plurality of second sub-electrodes 11;

[0118] The plurality of thin film transistors 2 includes a plurality of first thin film transistors 2-1 and a plurality of second thin film transistors 2-2; the first thin film transistors 2-1 are electrically connected with the first sub-electrodes 9, and the second thin film transistors 2-2 are electrically connected with the second sub-electrodes 11;

[0119] The first sub-electrodes 9 and the thin film transistors 2 electrically connected therewith, i.e. the first thin film transistors 2-1, are located in the same sub-pixel column 7;

[0120] The second sub-electrodes 11 and the thin film transistors 2 electrically connected therewith, i.e. the second thin film transistors 2-2, are located in different sub-pixel columns 7.

[0121] In some embodiments, as shown in FIG. 1, the plurality of second electrodes 4 includes a plurality of first sub-electrodes 9 and a plurality of second sub-electrodes 11; Figure 2 、 Figure 5 As shown, in the first direction X, the first sub-electrodes 9 and the second sub-electrodes 11 are arranged alternately, and in the second direction Y, the first sub-electrodes 9 and the second sub-electrodes 11 are arranged alternately.

[0122] In some embodiments, as shown in FIG. 1, the plurality of second electrodes 4 includes a plurality of first sub-electrodes 9 and a plurality of second sub-electrodes 11; Figure 5 As shown, the plurality of wiring areas 102 is divided into a plurality of wiring area rows 10 extending along the first direction X; the wiring area rows 10 include a plurality of first sub-areas 102-1 and a plurality of second sub-areas 102-2; each of the plurality of first sub-areas 102-1 is adjacent to the sub-pixel area 101 in the second direction Y, and the first sub-area 102-1 is located between two adjacent data lines 20; each of the plurality of second sub-areas 102-2 is adjacent to the sub-pixel area 101 in the second direction Y, and the second sub-area 102-2 is located between two adjacent data lines 20; in the second direction Y, the first sub-areas 102-1 and the second sub-areas 102-2 are arranged alternately;

[0123] The first thin film transistors 2-1 are located in the first sub-areas 102-1, and the second thin film transistors 2-2 are located in the second sub-areas 102-2;

[0124] In the Mth wiring area row 10-M, two first sub-areas 102-1 are separated by m second sub-areas 102-2; in the (M+1)th wiring area row, two second sub-areas 102-2 are separated by m first sub-areas 102-1; wherein M is an integer greater than or equal to 1, m is an integer greater than 1, and (M+1) is less than or equal to the total number of the wiring area rows.

[0125] In some embodiments, as shown in FIG. 1, m = 2. Figure 5

[0126] ​That is, in the Mth row of the wiring region row 10-M, one first sub-region 102-1 and two second sub-regions 102-2 serve as the repeating unit of the Mth row, and in the (M+1)th row of the wiring region row 10-(M+1), two first sub-regions 102-1 and one second sub-region 102-2 serve as the repeating unit of the Mth row.

[0127] In a specific implementation, Figure 5 The arrangement of the plurality of second electrodes 4 and the connection with the thin film transistor 2 shown can serve as a repeating unit.

[0128] In some embodiments, as shown in Figure 2 、 Figure 8 The second sub-connection part 4012 includes a first structure 5 and a second structure 6.

[0129] In the first direction X, the first structure 5 and the second structure 6 are respectively located on both sides of the first sub-connection part 4011.

[0130] It should be noted that, Figure 2 The first connection part 401 shown in Figure 8 The first connection part 401 shown in

[0131] In some embodiments, as shown in Figure 2 、 Figure 8 The second electrode 4 further includes a pixel part 402 corresponding to the sub-pixel region 101 and connected with the first connection part 401.

[0132] As shown in Figure 2 The second sub-connection part 4012 of the first sub-electrode 9 further includes a third structure 41; in the second direction Y, the third structure 41 is located between the first structure 5 and the pixel part 402; the third structure 41 is electrically connected with the pixel part 402, and at least one of the first sub-connection part 4011 and the first structure 5 is connected with the third structure 41.

[0133] As shown in Figure 8 The second sub-connection part 4012 of the second sub-electrode 11 further includes a fifth structure 42, which is connected with the first structure 5 and the pixel part 402 between the first structure 5 and the pixel part 402 in the second direction Y.

[0134] It should be noted that the connection of at least one of the first sub-connection part and the first structure with the third structure means that only the first sub-connection part is connected with the third structure; or only the first structure is connected with the third structure; or both the first sub-connection part and the first structure are connected with the third structure.

[0135] It should be noted that the pixel portion and the first opening region do not overlap each other in the orthographic projection of the substrate, and thus the positional deviation of the pixel portion due to process errors does not affect the overlapping area of the pixel portion and the first electrode. In specific implementations, for example, the overlapping area of the orthographic projection of the pixel portion and the orthographic projection of the first electrode in each second electrode is equal.

[0136] The array substrate provided by the embodiments of the present disclosure is configured such that the first structure and the second structure are located on the two sides of the first sub-connection portion in the first direction X. When all the second electrodes included in the array substrate are deviated in the first direction X due to process deviation, that is, the first structure and the second structure located on the opposite sides of the first sub-connection portion in the first direction X are both deviated, compared with the case where no deviation occurs in the first direction X, in each first connection portion, the overlapping area of the orthographic projection of one of the first structure and the second structure and the orthographic projection of the first electrode on the first substrate increases, and the overlapping area of the orthographic projection of the other of the first structure and the second structure and the orthographic projection of the first electrode on the first substrate decreases. Since the deviation amounts of the first structure and the second structure are the same, the changes in the overlapping areas of the first structure and the second structure and the orthographic projection of the first electrode on the first substrate can be complementary. Even if the positions of the second electrodes are deviated due to process deviation, the parasitic capacitances of each second electrode and the first electrode are still equal, thereby avoiding the large difference in the charging rates of different second electrodes caused by the different parasitic capacitances of different second electrodes and the first electrode. When the array substrate is applied to a display product, the difference in the brightness of different sub-pixel regions can be avoided, and thus the brightness difference can be avoided when the user moves to watch, the shaking lines can be avoided, the display effect can be improved, and the user experience can be improved.

[0137] In some embodiments, as shown in Figure 2 , Figure 8 The first structure 5 includes a first region 501 adjacent to the first sub-connection portion 4011, and the second structure 6 includes a second region 601 adjacent to the first sub-connection portion 4011.

[0138] In the first direction X, the distance L4 between the orthographic projection of the first sub-connection portion 4011 on the first substrate and the edge of the first opening region 301 on the first sub-connection portion 4011 toward the first structure in the orthographic projection of the first substrate is less than the width L9 of the first region 501 in the orthographic projection of the first substrate, and the distance L3 between the orthographic projection of the first sub-connection portion 4011 on the first substrate and the edge of the first opening region 301 on the first sub-connection portion 4011 toward the second structure in the orthographic projection of the first substrate is less than the width L10 of the second region 601 in the orthographic projection of the first substrate.

[0139] In some embodiments, asFigure 2 、 Figure 8 As shown in FIG. 1, the first structure 5 includes at least one first sub-structure 5-1, and the second structure 6 includes at least one second sub-structure 6-1.

[0140] In the second direction Y, the total width H1 of the first sub-structure 5-1 of the first region 501 in the orthographic projection of the first substrate is equal to the total width H2 of the second sub-structure 6-1 of the second region 601 in the orthographic projection of the first substrate.

[0141] It should be noted that, in an ideal case, i.e., the first connecting portion does not shift in the first direction X, the overlapping area of the first sub-structure included in the first structure in the orthographic projection of the first substrate and the orthographic projection of the first electrode on the first substrate is S4, and the overlapping area of the second sub-structure included in the second structure in the orthographic projection of the first substrate and the orthographic projection of the first electrode on the first substrate is S5. Taking an example in which each second electrode included in the array substrate shifts left by ΔL, and taking an example in which Figure 2 Figure 2 In the second electrode 4-1, the overlapping area S4' of the first sub-structure 5-1 included in the first structure 5 in the orthographic projection of the first substrate and the orthographic projection of the first electrode 3 on the first substrate is S4+H1×ΔL, the overlapping area S5' of the second sub-structure 6-1 included in the second structure 6 in the orthographic projection of the first substrate and the orthographic projection of the first electrode 3 on the first substrate is S5-H2×ΔL, S4'+S5' = S4+H1×ΔL+S5-H2×ΔL, and since H1 = H2, S4'+S5' = S4+S5; in the second electrode 4-2, the overlapping area S4'' of the first sub-structure 5-1 included in the first structure 5 in the orthographic projection of the first substrate and the orthographic projection of the first electrode 3 on the first substrate is S4-H1×ΔL, the overlapping area S5'' of the second sub-structure 6-1 included in the second structure 6 in the orthographic projection of the first substrate and the orthographic projection of the first electrode 3 on the first substrate is S5+H2×ΔL, S4''+S5'' = S4-H1×ΔL+S5+H2×ΔL, and since H1 = H2, S4''+S5'' = S4+S5. As can be seen, even if the second electrode shifts due to process deviation, the overlapping area of the first connecting portion of different second electrodes and the first electrode in the orthographic projection of the substrate is still equal, the parasitic capacitance of each second electrode and the first electrode is still equal, and a large difference in the charging rate of different second electrodes caused by the different parasitic capacitances of different second electrodes and the first electrode is avoided, so that when the array substrate is applied to a display product, the difference in brightness of different sub-pixel regions can be avoided, and when the user moves to watch, the brightness difference can be avoided to be aggravated, the shaking lines can be avoided, the display effect can be improved, and the user experience can be improved.

[0142] ​It should be noted that, ideally, assuming no offset of the first connection portion in the first direction X, L9-L4 is not less than the offset error in the first direction X, i.e., the relative offset between the first and second electrodes caused by process deviation, and L10-L3 is not less than the offset error in the first direction X. Ideally, in each second electrode, L4 = L3, and in different second electrodes (i.e., different first sub-electrodes and different second sub-electrodes), L4 and L3 are equal. If the second electrode is offset in the first direction, then in each second electrode, L4 is not equal to L3; in some second electrodes, L4 is greater than L3, and in others, L4 is less than L3; L4 and L3 are not completely equal in different second electrodes. Ideally, the range of L4 = L3 is greater than or equal to 1.0 micrometer and less than or equal to 5 micrometers, and the offset error between the first and second electrodes is, for example, greater than or equal to 1.5 micrometers and less than or equal to 4 micrometers. L9-L4 and L10-L3 are, for example, greater than or equal to 2.5 micrometers and less than or equal to 10 micrometers.

[0143] In some embodiments, such as Figure 2 , Figure 8 As shown, in the second direction Y, the maximum width L11 of the first sub-connection portion 4011 in the orthographic projection of the first substrate is less than the width L12 of the first opening region 301 in the orthographic projection of the first substrate. The maximum width L11 of the first sub-connection portion 4011 in the orthographic projection of the first substrate is greater than the total width H1 of the first substructure 5-1 in the orthographic projection of the first region 501 in the orthographic projection of the first substrate. The maximum width L11 of the first sub-connection portion 4011 in the orthographic projection of the first substrate is greater than the total width H2 of the second substructure 6-1 in the orthographic projection of the second region 601 in the orthographic projection of the second substrate.

[0144] It should be noted that, Figure 2 , Figure 8 The example provided illustrates this by using the first structure 5, which includes a first substructure 5-1, and the second structure 6, which includes a second substructure 6-1. In specific implementations, such as... Figure 6 As shown, the second structure 6 can also include multiple second substructures 6-1. Figure 6 The second structure 6 includes two second substructures 6-1 arranged along the second direction Y. Of course, in specific implementations, the first structure may also include multiple first substructures. Figure 6 The first sub-electrode 9 will be used as an example for illustration. Of course, when the first structure in the second sub-electrode includes multiple first sub-structures, the multiple first sub-structures are arranged along the second direction, and when the second structure includes multiple second sub-structures, the multiple second sub-structures are arranged along the second direction, which will not be elaborated here.

[0145] In a specific implementation, when the first structure includes a plurality of first sub-structures in the first direction X, the widths of the projections of the plurality of first sub-structures on the first substrate in the second direction Y can all be equal, and when the second structure includes a plurality of second sub-structures, the widths of the projections of the plurality of first sub-structures on the first substrate in the second direction Y can all be equal. Of course, the widths of the projections of the plurality of first sub-structures on the first substrate in the second direction Y can all be unequal or not completely equal, and the widths of the projections of the plurality of second sub-structures on the first substrate in the second direction Y can all be unequal or not completely equal.

[0146] It should be noted that, as shown in Figure 2 , Figure 6 , Figure 8 In the second direction Y, the total width H1 of the projections of the first sub-structures 5-1 included in the first structure 5 on the first substrate is the sum of the widths L7 of the projections of the first sub-structures 5-1 included in the first structure 5 on the first substrate in the second direction Y; and in the second direction Y, the total width H2 of the projections of the second sub-structures 6-1 included in the second structure 6 on the first substrate is the sum of the widths L8 of the projections of the second sub-structures 6-1 included in the second structure 6 on the first substrate in the second direction Y. Figure 2 , Figure 8 In the case where the first structure 5 includes one first sub-structure 5-1 and the second structure 6 includes one second sub-structure 6-1, i.e., H1=L7=H2=L8. Figure 6 In the case where the first structure 5 includes one first sub-structure 5-1 and the second structure 6 includes two second sub-structures 6-1, the widths L8 of the two second sub-structures 6-1 included in the second structure 6 are equal, and thus H1=L7=H2=2×L8.

[0147] It should be noted that in different first sub-electrodes, each first structure includes the same number of first sub-structures, each second structure includes the same number of second sub-structures, the width L7 of the orthographic projection of the first sub-structure in each first structure is equal, and the width L8 of the orthographic projection of the second sub-structure in each second structure is equal. Similarly, in different second sub-electrodes, each first structure includes the same number of first sub-structures, each second structure includes the same number of second sub-structures, the width L7 of the orthographic projection of the first sub-structure in each first structure is equal, and the width L8 of the orthographic projection of the second sub-structure in each second structure is equal. The width L7 of the orthographic projection of the first sub-structure in the first structure of a first sub-electrode and the width L7 of the orthographic projection of the first sub-structure in the first structure of a second sub-electrode in the first sub-electrode can be equal or unequal.

[0148] In some embodiments, such as Figure 2 As shown, when the first structure 5 includes a first substructure 5-1, the second structure 6 includes a second substructure 6-1, and L7 = L8, the edge of the first substructure 5-1 of the first structure 5 near the pixel portion 402 and the edge of the second substructure 6-1 of the second structure 6 near the pixel portion 402 are on the same straight line, and the edge of the first substructure 5-1 of the first structure 5 away from the pixel portion 402 and the edge of the second substructure 6-1 of the second structure 6 away from the pixel portion 402 are on the same straight line. Of course, it can also be as follows... Figure 7 As shown, the edge of the first substructure 5-1 of the first structure 5 near the pixel portion 402 and the edge of the second substructure 6-1 of the second structure 6 near the pixel portion 402 are on different straight lines, and the edge of the first substructure 5-1 of the first structure 5 away from the pixel portion 402 and the edge of the second substructure 6-1 of the second structure 6 away from the pixel portion 402 are on different straight lines.

[0149] It should be noted that, Figure 7 Taking the first sub-electrode 9 as an example, in a specific implementation, the second sub-electrode can also be configured such that the edges of the first sub-structure of the first structure near the pixel and the edges of the second sub-structure of the second structure near the pixel are on different straight lines, and the edges of the first sub-structure of the first structure away from the pixel and the edges of the second sub-structure of the second structure away from the pixel are on different straight lines.

[0150] In practice, the relative positions of the first and second structures can be set according to actual needs. For example, they can be set based on the available wiring space.

[0151] It should be noted that, as shown in Figure 2 L6 is the distance from one end of the first structure 5 away from the first sub-connection part 4011 to the edge of the first opening area 301 in the first direction X; and L5 is the distance from one end of the second structure 6 away from the first sub-connection part 4011 to the edge of the first opening area 301 in the first direction X.

[0152] In a specific implementation, L6+L4 is greater than or equal to L9, and L3+L5 is greater than or equal to L10.

[0153] It should be noted that, Figure 2 L6+L4 is greater than L9 and L3+L5 is greater than L10. When L6+L4 is greater than L9, in the second direction, the first sub-structure of the part outside the first area in the first structure in the orthographic projection of the first substrate substrate can be equal to the width of the orthographic projection of the first sub-structure in the first area of the first substrate substrate, of course, the width of the orthographic projection of the first sub-structure of the part outside the first area in the first structure in the first substrate substrate can also be not equal to the width of the orthographic projection of the first sub-structure in the first area of the first substrate substrate, the width of the orthographic projection of the first sub-structure of the part outside the first area in the first structure in the first substrate substrate is greater than the width of the orthographic projection of the first sub-structure in the first area of the first substrate substrate, or the width of the orthographic projection of the first sub-structure of the part outside the first area in the first structure in the first substrate substrate is less than the width of the orthographic projection of the first sub-structure in the first area of the first substrate substrate. When L3+L5 is greater than L10, in the second direction, the second sub-structure of the part outside the second area in the second structure in the orthographic projection of the first substrate substrate can be equal to the width of the orthographic projection of the second sub-structure in the second area of the first substrate substrate, of course, the width of the orthographic projection of the second sub-structure of the part outside the second area in the second structure in the first substrate substrate can also be not equal to the width of the orthographic projection of the second sub-structure in the second area of the first substrate substrate, the width of the orthographic projection of the second sub-structure of the part outside the second area in the second structure in the first substrate substrate is greater than the width of the orthographic projection of the second sub-structure in the second area of the first substrate substrate, or the width of the orthographic projection of the second sub-structure of the part outside the second area in the second structure in the first substrate substrate is less than the width of the orthographic projection of the second sub-structure in the second area of the first substrate substrate.

[0154] In some embodiments, as shown in Figure 2 In the first sub-electrode 9, the third structure 41 is electrically connected to the first structure 5, and the orthographic projection of the third structure 41 on the first substrate 1 does not overlap with the orthographic projection of the first opening area 301 on the first substrate 1.

[0155] That is, the array substrate provided by the embodiment of the present disclosure, the third structure does not overlap with the orthographic projection of the first opening area on the first substrate substrate, that is, the first connecting part does not include the part connected to the two sides of the first sub connecting part in the second direction, so that in the second direction, even if the second electrode is offset, it will not affect the overlapping area of the second electrode and the first electrode, avoiding the appearance of different parasitic capacitances between multiple second electrodes resulting in head shake lines.

[0156] In some embodiments, as shown in Figure 2 The third structure 41 is electrically connected to the first structure 5 at one end away from the first opening area 301 in the extension direction of the first structure 5.

[0157] Of course, in some embodiments, the third structure can also be electrically connected to the first structure in other areas of the first structure.

[0158] In some embodiments, as shown in Figure 2 , Figure 8 In the first direction X, the length L6+L4 of the orthographic projection of the first structure 5 on the first substrate substrate is greater than the length L3+L5 of the orthographic projection of the second structure 6 on the first substrate substrate.

[0159] That is, the array substrate provided by the embodiment of the present disclosure, in the first sub electrode, the first sub connecting part is connected to the pixel part through the longer first structure and the third structure.

[0160] In some embodiments, as shown in Figure 3 In the first sub electrode 9 and its corresponding thin film transistor 2, in the first direction X, the first structure 5 and the second electrode S are located on the same side of the first opening area 301.

[0161] The orthographic projection of the first structure 5 on the first substrate substrate 1 overlaps with the orthographic projection of the second electrode S on the first substrate substrate 1.

[0162] In some embodiments, in the second sub electrode and its corresponding thin film transistor, in the first direction X, the first structure and the second electrode are located on different sides of the first opening area.

[0163] It should be noted that in the related art, when the second electrode and the thin film transistor are located in the same column, the connection mode between the second electrode and the thin film transistor is short connection, that is, the pixel part and the first sub-connection part are directly connected through the connection part between the two regions; and when the second electrode and the thin film transistor are located in different columns, the connection mode between the second electrode and the thin film transistor is long connection, that is, the pixel part and the first sub-connection part need to be connected with the pixel part through the connection part across the adjacent sub-pixel columns. The overlapping area of the short connection connection part and the first electrode is much smaller than the overlapping area of the long connection connection part and the first electrode, so the parasitic capacitance between the second electrode and the first electrode of the short connection and the parasitic capacitance between the second electrode and the first electrode of the long connection cause a large difference in the charging rate of different second electrodes, thereby causing a difference in the brightness of different sub-pixels, easily causing a shaking line, and affecting the user experience.

[0164] The array substrate provided by the embodiments of the present disclosure is provided. In the first sub-electrode, the first sub-connection part is connected with the pixel part through the longer first structure and the third structure, that is, the first sub-connection part in the first sub-electrode is also connected with the pixel part in a long connection mode. Compared with the short connection mode in the prior art, the occupied area of the first connection part is improved, and the overlapping area between the first connection part in the first sub-electrode and the first electrode is further improved, which is beneficial to balance the parasitic capacitance between the first sub-electrode and the first electrode, the second sub-electrode and the first electrode, avoid the difference in the brightness of different sub-pixels, avoid the appearance of shaking lines, and improve the user experience.

[0165] In some embodiments, the pixel part of the first sub-electrode has a first overlapping area with the first electrode in the orthographic projection on the first substrate, and the pixel part of the second sub-electrode has a second overlapping area with the first electrode in the orthographic projection on the first substrate; the first connection part of the first sub-electrode has a third overlapping area with the first electrode in the orthographic projection on the first substrate, and the first connection part of the second sub-electrode has a fourth overlapping area with the first electrode in the orthographic projection on the first substrate; the first overlapping area is substantially equal to the second overlapping area, and the third overlapping area is substantially equal to the fourth overlapping area. Therefore, the overlapping area of the first sub-electrode and the first electrode in the orthographic projection on the first substrate is substantially equal to the overlapping area of the second sub-electrode and the first electrode in the orthographic projection on the first substrate, there is no large difference in the parasitic capacitance between the first sub-electrode and the first electrode and the parasitic capacitance between the second sub-electrode and the first electrode, the difference in the brightness of different sub-pixels is avoided, the shaking line is avoided, and the user experience is improved.

[0166] It should be noted that the difference between the first overlapping area and the second overlapping area is within a reasonable process error range, and the first overlapping area and the second overlapping area are approximately equal. The difference between the third overlapping area and the fourth overlapping area is within a reasonable process error range, and the third overlapping area and the fourth overlapping area are approximately equal.

[0167] In specific implementation, as shown in Figure 2 , Figure 8 The overlapping area of the first structure 5, the second structure 6 and the third structure 41 in the first sub-electrode 9 in the orthographic projection of the first substrate and the orthographic projection of the first electrode 3 on the first substrate is equal to the overlapping area of the first structure 5, the second structure 6 and the fifth structure 42 in the second sub-electrode 11 in the orthographic projection of the first substrate and the orthographic projection of the first electrode 3 on the first substrate.

[0168] In specific implementation, taking the first structure including one first sub-structure and the second structure including one second sub-structure as an example, for example, the line width of the remaining part of the first connecting part in the first sub-electrode except the first sub-connecting part is, for example, 3 microns to 10 microns; the line width of the remaining part of the first connecting part in the second sub-electrode except the first sub-connecting part is, for example, 3 microns to 8 microns. The line width of the remaining part of the first connecting part in the first sub-electrode except the first sub-connecting part can be the same as the line width of the remaining part of the first connecting part in the second sub-electrode except the first sub-connecting part, or can be different.

[0169] Alternatively, in some embodiments, as shown in Figure 9 The third structure 41 in the orthographic projection of the first substrate (not shown) has an overlapping with the first opening area 301 in the orthographic projection of the first substrate.

[0170] In some embodiments, as shown in Figure 9 The third structure 41 includes at least one third sub-structure 41-1 connected with the first sub-connecting part 4011 in the second direction Y.

[0171] It should be noted that Figure 9 In the third structure 41 includes one third sub-structure 41-1 as an example in the third structure 41, of course, in specific implementation, the third structure can also include a plurality of third sub-structures, and the plurality of third sub-structures are arranged along the first direction.

[0172] In some embodiments, as shown in Figure 9 In the first sub-electrode 9, in the first direction X, the length L16 of the orthographic projection of the first structure 5 on the first substrate is equal to the length L15 of the orthographic projection of the second structure 6 on the first substrate.

[0173] Of course, in actual implementation, the first structure in the first direction X on the orthographic projection of the first substrate and the length of the second structure on the orthographic projection of the first substrate can also be set to be unequal.

[0174] In some embodiments, as shown in FIG. 9, in the first sub-electrode 9, the second sub-connection part 4012 further includes a fourth structure 8; the fourth structure 8 includes at least one fourth sub-structure 8-1. Figure 9

[0175] In the second direction Y, the third structure 41 and the fourth structure 8 are respectively located on both sides of the first sub-connection part 4011.

[0176] The array substrate provided by the embodiments of the present disclosure is provided. In the second direction Y, the third structure and the fourth structure are respectively located on both sides of the first sub-connection part. When all the first sub-electrodes included in the array substrate are offset in the second direction Y due to process deviation, that is, the third structure and the fourth structure located on the opposite sides of the first sub-connection part of the first sub-electrode in the second direction Y are both offset, compared with the case where there is no offset in the second direction Y, in the first sub-connection part of each first sub-electrode, the overlapping area between the orthographic projection of the third structure or the fourth structure on the first substrate and the orthographic projection of the first electrode on the substrate increases, and the overlapping area between the orthographic projection of the other of the third structure and the fourth structure on the first substrate and the orthographic projection of the first electrode on the substrate decreases. Since the offset amount of the third structure and the fourth structure is the same, the change in the overlapping area between the third structure or the fourth structure and the first electrode on the orthographic projection of the first substrate can be complementary. Even if the position of the first sub-electrode is offset due to process deviation, the parasitic capacitance of each first sub-electrode and the first electrode is still equal, thereby avoiding the large difference in the charging rate of different second electrodes caused by the different parasitic capacitances of different first sub-electrodes and the first electrode. When the array substrate is applied to a display product, the difference in brightness of different sub-pixel regions can be avoided. When the user moves to watch, the brightness difference can be avoided to be aggravated, the shaking lines can be avoided to appear, the display effect can be improved, and the user experience can be improved.

[0177] The array substrate provided by the embodiments of the present disclosure is provided. In the second direction Y, the third structure and the fourth structure are respectively located on both sides of the first sub-connection part. When all the first sub-electrodes included in the array substrate are offset in the second direction Y due to process deviation, that is, the third structure and the fourth structure located on the opposite sides of the first sub-connection part of the first sub-electrode in the second direction Y are both offset, compared with the case where there is no offset in the second direction Y, in the first sub-connection part of each first sub-electrode, the overlapping area between the orthographic projection of the third structure or the fourth structure on the first substrate and the orthographic projection of the first electrode on the substrate increases, and the overlapping area between the orthographic projection of the other of the third structure and the fourth structure on the first substrate and the orthographic projection of the first electrode on the substrate decreases. Since the offset amount of the third structure and the fourth structure is the same, the change in the overlapping area between the third structure or the fourth structure and the first electrode on the orthographic projection of the first substrate can be complementary. Even if the position of the first sub-electrode is offset due to process deviation, the parasitic capacitance of each first sub-electrode and the first electrode is still equal, thereby avoiding the large difference in the charging rate of different second electrodes caused by the different parasitic capacitances of different first sub-electrodes and the first electrode. When the array substrate is applied to a display product, the difference in brightness of different sub-pixel regions can be avoided. When the user moves to watch, the brightness difference can be avoided to be aggravated, the shaking lines can be avoided to appear, the display effect can be improved, and the user experience can be improved. Figure 9 ​In the array substrate shown, the first sub-connection portion 4011 of the first sub-electrode 9 is connected to the second sub-connection portion on both opposite sides in the first direction X and on both opposite sides in the second direction Y. Therefore, even if the position of the first sub-electrode shifts in the first direction X and / or the second direction Y due to process deviations, the parasitic capacitance of each first sub-electrode and the first electrode remains equal. This avoids significant differences in the charging rate of different second electrodes caused by differences in the parasitic capacitance of different first sub-electrodes and the first electrode. When the array substrate is used in a display product, it can avoid differences in brightness between different sub-pixel areas. When the user moves to view the display, it can prevent the brightness difference from worsening, avoid the appearance of head-shaking patterns, improve the display effect, and enhance the user experience.

[0178] It should be noted that, since the first sub-connection portion of the second sub-electrode is not connected to the second sub-connection portion on both sides in the second direction Y, even if there is an offset in the second direction Y, it will not affect the parasitic capacitance between the second sub-electrode and the first electrode.

[0179] In some embodiments, such as Figure 9 As shown, in the first sub-electrode 9, the third structure 41 includes a third region 30 adjacent to the first sub-connection portion, and the fourth structure 8 includes a fourth region 31 adjacent to the first sub-connection portion.

[0180] In the second direction Y, the distance L19 between the orthographic projection of the first sub-connection portion 4011 on the first substrate and the edge of the first opening region 301 on the side of the first sub-connection portion 4011 facing the third structure on the first substrate is less than the width L20 of the orthographic projection of the third region 30 on the first substrate. The distance L17 between the orthographic projection of the first sub-connection portion 4011 on the first substrate and the edge of the first opening region 301 on the side of the first sub-connection portion 4011 facing the fourth structure 8 on the first substrate is less than the width L18 of the orthographic projection of the fourth region 31 on the first substrate.

[0181] In the first direction X, the total width H3 of the orthographic projection of the third substructure 41-1 included in the third region 30 onto the first substrate is equal to the total width H4 of the orthographic projection of the fourth substructure 8-1 included in the fourth region 31 onto the first substrate.

[0182] It should be noted that, ideally, assuming the first connection portion does not shift in the second direction Y, the overlap area of ​​the third substructure included in the third structure on the orthographic projection of the first electrode on the first substrate is S6, and the overlap area of ​​the fourth substructure included in the fourth structure on the orthographic projection of the first electrode on the first substrate is S7. Taking the example where each second electrode included in the array substrate is shifted upward by ΔL, and assuming... Figure 9 Let's take an example to illustrate this.Figure 9 In the first sub-electrode 9 with the reference sign 4-1, the third sub-structure 41-1 included in the third structure 41 has an overlapping area S6' = S6 + H3 x AL with the orthogonal projection of the first electrode 3 on the first substrate, and the fourth sub-structure 8-1 included in the fourth structure 8 has an overlapping area S7' = S7 - H4 x AL with the orthogonal projection of the first electrode 3 on the first substrate, S6' + S7' = S6 + H3 x AL + S7 - H4 x AL, and since H3 = H4, S6' + S7' = S6 + S7. In the first sub-electrode 9 with the reference sign 4-2, the third sub-structure 41-1 included in the third structure 41 has an overlapping area S6" = S6 - H3 x AL with the orthogonal projection of the first electrode 3 on the first substrate, and the fourth sub-structure 8-1 included in the fourth structure 8 has an overlapping area S7" = S7 + H4 x AL with the orthogonal projection of the first electrode 3 on the first substrate, S6" + S7" = S6 - H3 x AL + S5 + H4 x AL, and since H3 = H4, S4" + S7" = S6 + S7. Thus, even if the first sub-electrode position is offset due to process deviation, the overlapping areas of the first connecting portions of different first sub-electrodes with the orthogonal projection of the first electrode on the substrate are still equal, and the parasitic capacitances of the first sub-electrodes and the first electrode are still equal, thereby avoiding a large difference in the charging rate of different first sub-electrodes caused by different parasitic capacitances of different first sub-electrodes and the first electrode, and when the array substrate is applied to a display product, the difference in brightness of different sub-pixel regions can be avoided. When a user moves to watch, the brightness difference can be avoided from being aggravated, the shaking lines can be avoided from appearing, the display effect can be improved, and the user experience can be improved.

[0183] It should be noted that, in an ideal case, i.e. the first connecting part of the first sub-electrode does not shift in the second direction Y, L20-L19 is not less than the relative shift amount of the first electrode and the second electrode caused by the shift error in the second direction Y, i.e. the process deviation, and L18-L17 is not less than the shift error in the second direction Y. In an ideal case, in each first sub-electrode, L19=L17, and in different first sub-electrodes, L19 is equal and L17 is equal. If the first sub-electrode shifts in the second direction, in each first sub-electrode, L19 is not equal to L17, L19 is greater than L17 in part of the first sub-electrodes, L19 is less than L17 in the rest of the first sub-electrodes, L19 is not completely equal in different first sub-electrodes, and L17 is not completely equal in different first sub-electrodes. In an ideal case, the range of L19=L17 is greater than or equal to 1.0 microns and less than or equal to 5 microns, and the shift error of the first electrode and the second electrode is greater than or equal to 1.5 microns and less than or equal to 4 microns. L20-L19 and L18-L17 are greater than or equal to 2.5 microns and less than or equal to 10 microns, for example.

[0184] In some embodiments, as shown in FIG. 4A, in the first direction X, the maximum width L21 of the first sub-connection part 4011 in the orthogonal projection of the first substrate is less than the width L22 of the first opening area 301 in the orthogonal projection of the first substrate, the maximum width L21 of the first sub-connection part 4011 in the orthogonal projection of the first substrate is greater than the total width H3 of the third sub-structure 41-1 of the third structure 41 in the orthogonal projection of the first substrate, and the maximum width L21 of the first sub-connection part 4011 in the orthogonal projection of the first substrate is greater than the total width H4 of the fourth sub-structure 8-1 of the fourth structure 8 in the orthogonal projection of the first substrate. Figure 9 It should be noted that,

[0185] Figure 9 In the embodiment shown in FIG. 4A, the third structure 41 includes one third sub-structure 41-1, and the fourth structure 8 includes one fourth sub-structure 8-1. In specific implementation, as shown in FIG. 4B, the fourth structure 8 can include a plurality of fourth sub-structures 8-1, and the plurality of fourth sub-structures 8-1 are arranged along the first direction X. Figure 10 Figure 10 In the embodiment shown in FIG. 4A, the fourth structure 8 includes two fourth sub-structures 8-1 arranged along the first direction X. Of course, in specific implementation, the third structure can also include a plurality of third sub-structures.

[0186] ​​In a specific implementation, in the second direction Y, when the third structure includes a plurality of third sub-structures, the widths of the projections of the plurality of third sub-structures on the first substrate in the first direction X can be equal, of course, the widths of the projections of the plurality of third sub-structures on the first substrate in the first direction X can not be equal or not completely equal. In the second direction Y, when the fourth structure includes a plurality of fourth sub-structures, the widths of the projections of the plurality of fourth sub-structures on the first substrate in the first direction X can be equal, of course, the widths of the projections of the plurality of fourth sub-structures on the first substrate in the first direction X can not be equal or not completely equal.

[0187] It should be noted that, as shown in Figure 9 , Figure 10 , in the first direction X, the total width H3 of the projection of the third sub-structure 41-1 included in the third structure 41 on the first substrate in the first direction X refers to the sum of the widths L13 of the projections of each third sub-structure 41-1 included in the third structure 41 on the first substrate in the first direction X; in the first direction X, the total width H4 of the projection of the fourth sub-structure 8-1 included in the fourth structure 8 on the first substrate in the first direction X refers to the sum of the widths L14 of the projections of each fourth sub-structure 8-1 included in the fourth structure 8 on the first substrate in the first direction X. Figure 9 In the case where the third structure 41 includes one third sub-structure 41-1 and the fourth structure 8 includes one fourth sub-structure 8-1, i.e., H3 = L13 = H4 = L14. Figure 10 In the case where the third structure 41 includes one third sub-structure 41-1 and the fourth structure 8 includes two fourth sub-structures 8-1, the widths L14 of the two second sub-connection portions 4012 included in the fourth structure 8 are equal, then H3 = L13 = H4 = 2 x L14.

[0188] It should be noted that, in different first sub-electrodes, the number of third sub-structures included in each third structure is equal, the number of fourth sub-structures included in each fourth structure is equal, the widths L13 of the projections of the third sub-structures included in each third structure on the first substrate in the first direction X are equal, and the widths L14 of the projections of the fourth sub-structures included in each fourth structure on the first substrate in the first direction X are equal.

[0189] In some embodiments, as shown in Figure 9 , when the third structure 41 includes one third sub-structure 41-1, the fourth structure 8 includes one fourth sub-structure 8-1, and L13 = L14, the third sub-structure 41-1 of the third structure 41 close to the edge of the first structure 5 and the fourth sub-structure 8-1 of the fourth structure 8 close to the edge of the first structure 5 are located on the same straight line, and the third sub-structure 41-1 of the third structure 41 away from the edge of the first structure 5 and the fourth sub-structure 8-1 of the fourth structure 8 away from the edge of the first structure 5 are located on the same straight line. Of course, it can also be thatFigure 11 As shown, the third substructure 41-1 of the third structure 41 close to the edge of the first structure 5 is located on a different straight line from the fourth substructure 8-1 of the fourth structure 8 close to the edge of the first structure 5, and the third substructure 41-1 of the third structure 41 away from the edge of the first structure 5 is located on a different straight line from the fourth substructure 8-1 of the fourth structure 8 away from the edge of the first structure 5.

[0190] In specific implementation, the relative positions of the third structure and the fourth structure can be set according to actual needs. For example, the relative positions of the third structure and the fourth structure can be set according to wiring space.

[0191] It should be noted that, when the first structure includes one first substructure and the second structure includes one second substructure, Figure 9 For example, in the second direction Y, the width of the first substructure included in the first structure in the orthographic projection of the first substrate, and the width of the second substructure included in the second structure in the orthographic projection of the first substrate are both less than the width of the first subconnection in the orthographic projection of the first substrate. In specific implementation, it can also be set that, in the second direction Y, the width of the first substructure included in the first structure in the orthographic projection of the first substrate, and the width of the second substructure included in the second structure in the orthographic projection of the first substrate are both equal to the width of the first subconnection in the orthographic projection of the first substrate. In the second direction Y, the width of the first substructure included in the first structure in the orthographic projection of the first substrate, the width of the second substructure included in the second structure in the orthographic projection of the first substrate, and the width of the first subconnection in the orthographic projection of the first substrate are greater than or equal to 3 microns and less than or equal to 10 microns, for example.

[0192] In specific implementation, in the second direction Y, the width of the third structure in the orthographic projection of the first substrate can be equal to the width of the fourth structure in the orthographic projection of the first substrate, or can not be equal.

[0193] In specific implementation, in the second direction Y, the width of the third structure in the orthographic projection of the first substrate is greater than or equal to L20, and the width of the fourth structure in the orthographic projection of the first substrate is greater than or equal to L18. Figure 9 For example, the width of the third structure in the orthographic projection of the first substrate is greater than L20, and the width of the fourth structure in the orthographic projection of the first substrate is greater than L18.

[0194] In specific implementation, as Figures 9-11The arrangement of the first sub-electrode shown can still achieve approximately equal third and fourth overlapping areas. For example, the overlapping area of ​​the orthographic projections of the third, fourth, second, and first structures in the first sub-electrode onto the first substrate and the orthographic projection of the first electrode onto the first substrate is equal to the overlapping area of ​​the orthographic projections of the fifth, second, and first structures in the second sub-electrode onto the first substrate and the orthographic projection of the first electrode onto the first substrate.

[0195] In some embodiments, such as Figure 12 As shown, the first electrode 3 also includes a plurality of second opening regions 302 located in the wiring region 102; the second opening regions 302 overlap with the first connection portion 401 of the second sub-electrode 11 in the orthographic projection of the first substrate 1.

[0196] The array substrate provided in this embodiment includes a second opening region corresponding to the first connection portion of the second sub-electrode, which can reduce the overlap area between the second sub-electrode and the first electrode, and is beneficial to achieve the same overlap area between the first sub-electrode and the first electrode and the second sub-electrode and the first electrode.

[0197] In a specific implementation, when the first electrode includes a second opening region corresponding to the second sub-electrode, the first connecting portion of the first sub-electrode can be adopted. Figure 2 , Figure 4 , Figures 6-7 , Figures 9-11 Any method within it.

[0198] In specific implementation, such as Figure 12 As shown, the second sub-connection portion 4012 of the first structure 5 of the second sub-electrode 11 overlaps with the second opening region 302 in the orthographic projection of the first substrate. Furthermore, the first structure 5 of the second sub-connection portion 4012 overlaps with the second opening region 302 in the orthographic projection of the first substrate.

[0199] In some embodiments, such as Figure 12 As shown, the orthographic projection of the second opening region 302 onto the first substrate does not overlap with the orthographic projection of the scan line 14 onto the first substrate. This avoids the second opening exposing the scan line, which could lead to parasitic capacitance between the scan line and the second sub-electrode.

[0200] In some embodiments, such as Figure 13 , Figure 14 As shown, scan line 14 includes a first compensation section 1401 corresponding to thin film transistor 2;

[0201] The first electrode D of the thin film transistor 2 includes a first portion D-1, and a second portion D-2 and a third portion D-3 respectively located on both sides of the first portion D-1 in the first direction X;

[0202] The first portion D-1 is in the region between the third electrode G and the first compensation portion 1401 in the orthographic projection of the first substrate 1, the second portion D-2 has an overlap with the third electrode G in the orthographic projection of the first substrate 1, and the third portion D-3 has an overlap with the first compensation portion 1401 in the orthographic projection of the first substrate 1.

[0203] It should be noted that, since the first electrode (i.e., the drain electrode) of the thin film transistor has an overlap with the film layer (hereinafter referred to as the first conductive layer) in which the third electrode (i.e., the gate electrode) and the scan line are located, a capacitor Cgs is formed between the first electrode and the first conductive layer. If all the first electrodes included in the array substrate are offset in the first direction due to process deviation, for example, offset to the right, the overlapping area between the first electrode and the first conductive layer in some thin film transistors increases, and the overlapping area between the first electrode and the first conductive layer in some thin film transistors decreases, which can cause the capacitor Cgs formed between the first electrode and the first conductive layer in different thin film transistors to be different.

[0204] The array substrate provided by the embodiments of the present disclosure has the following advantages. The scan line includes the first compensation portion, the first electrode includes the second portion having an overlap with the third electrode and the third portion having an overlap with the first compensation portion, the capacitor formed between the second portion and the third electrode is Cgs1, and the capacitor formed between the third portion and the first compensation portion is Cgs2. If all the first electrodes included in the array substrate are offset in the first direction due to process deviation, for each thin film transistor and the scan line electrically connected thereto, if the overlapping area between the second portion and the third electrode increases, the overlapping area between the third portion and the first compensation portion decreases, and if the overlapping area between the second portion and the third electrode decreases, the overlapping area between the third portion and the first compensation portion increases. That is, one of Cgs1 and Cgs2 increases and the other decreases, which can compensate for the influence of process deviation on the capacitor Cgs formed between the first electrode and the first conductive layer, avoid the capacitor Cgs formed between different first electrodes and the first conductive layer being different, and avoid affecting the display effect.

[0205] It should be noted that, Figure 13 The region corresponding to the second thin film transistor 2-2 is shown in FIG. 2B. Figure 14 The region corresponding to the first thin film transistor 2-1 is shown in FIG. 2A.

[0206] In some embodiments, in the second direction Y, the width of the orthographic projection of the third portion is equal to the width of the orthographic projection of the first substrate on the side of the second portion close to the first portion.

[0207] Specifically, let's take the second thin-film transistor as an example to illustrate, such as... Figure 13 As shown, the second part D-2 includes a fifth region 32 adjacent to the first part D-1, and the third part D-3 includes a sixth region 33 adjacent to the first part D-1. In the second direction Y, the width L29 of the orthographic projection of the fifth region 32 onto the first substrate is equal to the width L30 of the orthographic projection of the sixth region 33 onto the first substrate.

[0208] It should be noted that, ideally, assuming the first electrode does not shift in the first direction X, the overlapping area of ​​the orthographic projections of the second part and the third electrode on the first substrate is S8, and the overlapping area of ​​the orthographic projections of the third part and the first compensation part on the first substrate is S9. Taking an example where each first electrode in the array substrate is shifted to the left by ΔL, and considering... Figure 13 Let's take an example to illustrate this. Figure 13 In the attached figure, in the first pole D2 (D2-1), the overlapping area of ​​the second part D-2 (D-2) and the third pole G2 (D-2) on the first substrate (not shown) is S8' = S8 + L29 × ΔL. The overlapping area of ​​the third part D-3 (D-3) and the first compensation part 1401 on the first substrate is S9' = S9 - L30 × ΔL. S8' + S9' = S8 + L29 × ΔL + S9 - L30 × ΔL. Since L29 = L30, therefore S8' + S9' = S8 +S9; In the attached figure, in the first electrode D2 marked D2-2, the overlapping area of ​​the second part D-2 and the third electrode G2 on the first substrate is S8”=S8-L29×ΔL, and the overlapping area of ​​the third part D-3 and the first compensation part 1401 on the first substrate is S9”=S9+L30×ΔL. S8”+S9”=S8-L29×ΔL+S9+L30×ΔL. Since L29=L30, S8”+S9”=S8+S9. It can be seen that even if the position of the first electrode is shifted due to process deviation, the overlapping area of ​​the first conductive layer where different first electrodes, third electrodes and scan lines are located on the substrate is still equal, and the capacitance Cgs of each first electrode, third electrode and scan line is still equal, avoiding the difference in capacitance Cgs of different first electrodes, third electrodes and scan lines that would affect the display effect.

[0209] In some embodiments, in the second direction Y, the width of the first part projected onto the first substrate is greater than the width of the fifth region projected onto the first substrate, and the width of the first part projected onto the first substrate is greater than the width of the sixth region projected onto the first substrate.

[0210] It should be noted that,Figure 13 For example, the edge of the fifth area 32 extending along the first direction X and the edge of the sixth area 33 extending along the first direction X are not located on the same straight line. Of course, in actual implementation, the edge of the fifth area 32 extending along the first direction X and the edge of the sixth area 33 extending along the same side of the first direction X can be located on the same straight line.

[0211] In some embodiments, L29, L30 are greater than or equal to 2 microns and less than or equal to 8 microns, for example.

[0212] In some embodiments, as shown in FIG. 1, in the first direction X, the width L25 of the first projection of the fifth area 32 on the first substrate is greater than the distance L27 between the first projection of the first part D-1 and the first projection of the third electrode G2 on the first substrate, and the width L26 of the first projection of the sixth area 33 on the first substrate is greater than the distance L28 between the first projection of the first part D-1 and the first projection of the first compensation part 1401 on the first substrate. Figure 13

[0213] It should be noted that, in an ideal case, i.e., the first electrode does not shift in the first direction X, L25-L27 is not less than the relative shift amount of the first electrode and the first conductive layer caused by the shift error in the first direction X, and L26-L28 is not less than the shift error in the first direction X. In an ideal case, in each first electrode, L27=L28, and in different first electrodes, L27 is equal and L28 is equal. If the second electrode shifts in the first direction, in each second electrode, L27 is not equal to L28, L27 is greater than L28 in part of the second electrodes, L27 is less than L28 in the remaining part of the second electrodes, L27 is not completely equal in different second electrodes, and L28 is not completely equal in different second electrodes. In an ideal case, the range of L27=L28 is greater than or equal to 2.0 microns and less than or equal to 5.0 microns, and the shift error of the first electrode and the first conductive layer is greater than or equal to 0.5 microns and less than or equal to 2.0 microns, for example. L25-L27, L26-L28 are greater than or equal to 2.5 microns and less than or equal to 10 microns, for example.

[0214] In some embodiments, as shown in FIG. 1, in the first sub-area 102-1, the scan line 14 includes: a first part 1404 extending along the first direction X, and a second part 1405 extending along the third direction X’ and connected to the first part 1404; the third direction X’ intersects the first direction X and the second direction Y; the first compensation part 1401 is located on one side of the second part 1405 facing the third electrode G. Figure 14

[0215] ​​It should be noted that if the first electrode does not include the second opening region, the pattern of the scan lines in the second sub-region can also be... Figure 14 As shown. In some embodiments, in the second sub-region, the scan line includes: a second portion extending along a first direction X, and a third portion extending along a third direction X' and connected to the second portion; the third direction X' intersects both the first direction X and the second direction Y; a first compensation portion is located on the side of the third portion facing the third pole.

[0216] In some embodiments, such as Figure 13 As shown, the first electrode 3 includes a second opening region 302. In the second sub-region 102-2, the scan line 14 includes a second portion 1402 extending along the first direction X; a first compensation portion 1401 is connected to the second portion 1402 in the second direction Y, and in the second direction Y, the first compensation portion 1401 and the three electrodes are located on the same side of the second portion 1402.

[0217] In some embodiments, such as Figure 13 As shown, in the second sub-region 102-2, the second opening region 302 does not overlap with the scan line 14 in the orthographic projection of the first substrate 1, and the second opening region 302 falls into the region between two adjacent first compensation parts 1401 within the orthographic projection of the first substrate 1.

[0218] In some embodiments, in at least a portion of the second sub-region, such as Figure 12 As shown, the two first connecting parts 401 are integrally connected to the second opening areas 302 corresponding to them.

[0219] In some embodiments, such as Figure 12 As shown, the width L23 of the second opening region 302 projected onto the first substrate (not shown) in the first direction X is greater than or equal to 5 micrometers and less than or equal to 15 micrometers, and the width L24 of the second opening region 302 projected onto the first substrate in the second direction Y is greater than or equal to 10 micrometers and less than or equal to 40 micrometers.

[0220] In some embodiments, the first electrode includes a plurality of slit units, or as... Figure 5 As shown, the first part includes a slit unit 15; the slit unit 15 overlaps with the sub-pixel region 101 in the orthographic projection of the first substrate 1.

[0221] The slit unit 15 includes first sub-units 1501 and second sub-units 1502 arranged alternately in the second direction Y; the first sub-units 1501 include a plurality of first slits 16 extending in a fourth direction X" and arranged in the first direction X, and the second sub-units 1502 include a plurality of second slits 17 extending in a fifth direction X'" and arranged in the first direction X; the fourth direction X" intersects the fifth direction X'", and the fourth direction X" intersects the first direction X and the second direction Y; the fifth direction X'" intersects the first direction X and the second direction Y;

[0222] The first electrode line 18 has an overlap in the planar projection of the first substrate 1 at the connection of the first sub-unit 1501 and the second sub-unit 1502.

[0223] The array substrate provided by the embodiments of the present disclosure sets the first electrode line electrically connected to the first electrode at the region corresponding to the connection of the first sub-unit and the second sub-unit, i.e., sets the first electrode line at the corner dark area in the middle of the sub-pixel, thereby avoiding affecting the sub-pixel aperture ratio.

[0224] In some embodiments, the line width of the first electrode line, i.e., the width in the second direction, is greater than or equal to 2 microns and less than or equal to 8 microns.

[0225] In specific implementation, as shown in Figure 5 , the first electrode line 18 is connected to the second electrode line 23, and the second electrode line 23 is connected to the first electrode (not shown) through the first via 36. Figure 5 The pattern of the first electrode line 18 and the second electrode line 23 in Figure 16 is shown.

[0226] In specific implementation, as shown in Figure 3 , the thin film transistor 2 further includes an active layer 201, a gate insulating layer 26, and an interlayer insulating layer 27. As shown in Figure 3 , the array substrate further includes a first protective layer 29 between the first electrode 3 and the second electrode 4, a planarization layer 28 between the first electrode 3 and the first pole D and the second pole S of the thin film transistor 2, and a buffer layer 25 between the first substrate 1 and the thin film transistor 2. Figure 3 Take the top gate structure of the thin film transistor as an example for illustration. Of course, in specific implementation, the thin film transistor can also be a bottom gate structure, etc.

[0227] In a specific implementation, when the thin film transistor is in a top-gate structure, the first electrode and the second electrode are electrically connected to the conductorized region of the active layer through first vias penetrating the interlayer insulating layer and the gate insulating layer, respectively. The insulating layer between the second electrode line and the first electrode is the planarization layer, the interlayer insulating layer, and the gate insulating layer, and the first electrode is electrically connected to the second electrode line through a first via penetrating the planarization layer, the interlayer insulating layer, and the gate insulating layer.

[0228] In a specific implementation, when the thin film transistor is in a bottom-gate structure, the active layer is located on the side of the third electrode away from the buffer layer, and the gate insulating layer is located between the active layer and the third electrode, and the second electrode and the first electrode are directly overlapped with the active layer of the thin film transistor. The insulating layer between the second electrode line and the first electrode is the planarization layer and the gate insulating layer, and the first electrode is electrically connected to the second electrode line through a first via penetrating the planarization layer and the gate insulating layer.

[0229] In some embodiments, as shown in FIG. 1, the first via 36 has a projection on the first substrate that falls within the projection of the second electrode line 23 on the first substrate; and the projection of the first via 36 on the first substrate falls within the projection of the end of the second electrode line 23 away from the first electrode line 18 on the first substrate. Figure 5

[0230] The array substrate provided by the embodiments of the present disclosure has the following advantages. The second electrode line is located in the region between two adjacent sub-pixel columns, and the second electrode line and the data line are arranged alternately, so that the region where the data line is not arranged can be reasonably utilized, and the second electrode line and the first electrode are electrically connected through the first via, while avoiding affecting the transmittance of the sub-pixel. When the array substrate is applied to a liquid crystal product, the alignment precision can also be ensured.

[0231] In some embodiments, the projection of the first via 36 on the first substrate is circular. The diameter of the circular shape is greater than or equal to 3 microns and less than or equal to 10 microns, for example.

[0232] In some embodiments, as shown in FIG. 1, the array substrate further comprises a peripheral electrode line 19; the projection of the peripheral electrode line 19 on the first substrate 1 surrounds the plurality of sub-pixel regions (not shown) and the plurality of wiring regions (not shown). Figure 15 At least part of the plurality of first electrode lines 18 is electrically connected to the peripheral first electrode line 18.

[0233] For example, both ends of each first electrode line 18 in the extension direction are electrically connected to the peripheral first electrode line 18.

[0234]

[0235] ​​The array substrate provided by the embodiments of the present disclosure further includes a peripheral electrode line, the peripheral electrode line surrounds the plurality of sub-pixel regions and the plurality of first regions, that is, the peripheral electrode line is located in a peripheral region of the array substrate. When the array substrate is applied to a display product, the peripheral region corresponds to a non-display region of the display product. The peripheral connection lead is electrically connected with the first electrode line, so that the impedance of the signal line electrically connected with the first electrode can be reduced without affecting the display and without losing the resolution of the display product, and then the line width of the peripheral electrode line can be reduced and the size of the peripheral region can be reduced, which is beneficial to realize a narrow frame display.

[0236] In some embodiments, the line width of the peripheral electrode line is greater than or equal to 40 microns and less than or equal to 300 microns.

[0237] In some embodiments, the array substrate further includes a plurality of binding terminals bound with the flexible circuit board, and part of the binding terminals in the plurality of binding terminals are electrically connected with the peripheral electrode line. For example, as shown in FIG. 4, the array substrate further includes a plurality of connection leads 35 electrically connected with the peripheral electrode line 19 and the binding terminals 34. Figure 15

[0238] In some embodiments, as shown in FIG. 4, the orthographic projection of the pixel portion 402 on the first substrate 1 overlaps with the orthographic projection of the scan line 14 on the first substrate 1. Figure 5

[0239] The array substrate provided by the embodiments of the present disclosure, the pixel portion extends to the wiring region and has an overlapping area with the scan line, which can increase the setting space of the first slit and the second slit included in the pixel portion in the second direction, that is, the length of the first slit and the second slit can be increased, and then the transmittance of the sub-pixel can be improved.

[0240] ​​In specific implementation, the substrate substrate is, for example, a glass substrate. The material of the active layer can be amorphous silicon (a-Si), polysilicon (poly), oxide (such as indium gallium zinc oxide IGZO), or the like. The material of the first electrode, the second electrode, the third electrode, the scan line, the data line, the first electrode line, the second electrode line, and the peripheral electrode line can include copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), or the like. The first electrode, the second electrode, the third electrode, the scan line, the data line, the first electrode line, the second electrode line, and the peripheral electrode line can be a single-layer structure or a laminated structure, for example, a laminated structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer. In specific implementation, the third electrode, the scan line, the first electrode line, the second electrode line, and the peripheral electrode line are arranged in the same layer and are a first conductive layer. The first electrode and the second electrode are arranged in the same layer and are a second conductive layer. The material of the first conductive layer can be different from that of the second conductive layer, for example, the material of the first conductive layer is Cu and the material of the second conductive layer is Al. Alternatively, the material of the first conductive layer and the material of the second conductive layer can be the same, for example, the material of the first conductive layer and the material of the second conductive layer are both Cu. The material of the first electrode and the second electrode is the same, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The material of the buffer layer, the gate insulating layer, the interlayer insulating layer, and the first protective layer is, for example, at least one of silicon nitride and silicon oxide. The material of the planarization layer is, for example, PI.

[0241] Based on the same inventive concept, the display panel provided by the embodiments of the present disclosure is also provided. Figure 17 As shown in the figure, the display panel comprises:

[0242] The array substrate 37 provided by the embodiments of the present disclosure is provided.

[0243] The counter substrate 38 is arranged opposite to the array substrate 37.

[0244] The liquid crystal layer 39 is located between the array substrate 37 and the counter substrate 38.

[0245] It should be noted that, since the display device solves the problem by the similar principle as the above-mentioned array substrate, the implementation of the display device can refer to the above-mentioned embodiments of the array substrate, and the repeated parts will not be described herein.

[0246] In some embodiments, the array substrate comprises a plurality of data lines; the counter substrate comprises:

[0247] The second substrate substrate;

[0248] The plurality of spacers are located on the side of the second substrate substrate facing the liquid crystal layer.

[0249] In specific implementation, the side of the array substrate close to the liquid crystal layer and the side of the opposite substrate close to the liquid crystal layer are further provided with an alignment layer.

[0250] In specific implementation, the opposite substrate includes a second substrate. In some embodiments, the opposite substrate further includes a black matrix and a color filter on the side of the second substrate facing the liquid crystal layer. The black matrix has an opening region, and the color filter is located in the opening region; the spacers are located on the side of the black matrix facing the liquid crystal layer.

[0251] In specific implementation, the black matrix is in the orthographic projection of the array substrate falls into the wiring region. The color filter corresponds to the sub-pixel region one by one, and the color filter is in the orthographic projection of the array substrate falls into the sub-pixel region. The display panel includes a sub-pixel corresponding to the sub-pixel region one by one, and the sub-pixel includes a red sub-pixel, a blue sub-pixel and a green sub-pixel. Correspondingly, the color filter includes a red color filter corresponding to the red sub-pixel, a blue color filter corresponding to the blue sub-pixel and a green color filter corresponding to the green sub-pixel.

[0252] In some embodiments, as shown in Figure 18 The orthographic projection of the spacers 40 on the first substrate falls into the wiring region 102, and the orthographic projection of the spacers 40 on the first substrate has an overlap with the orthographic projection of the data line 20 on the first substrate.

[0253] The display panel provided by the embodiments of the present disclosure, the orthographic projection of the spacers on the first substrate falls into the wiring region, and the orthographic projection of the spacers on the first substrate has an overlap with the orthographic projection of the data line on the first substrate, that is, the orthographic projection of the spacers on the first substrate has an overlap with the region between the two thin film transistors. Since the insulating layer under the first electrode is a planarization layer, the planarization layer is usually an organic film layer with a thickness greater than or equal to 1.5 microns and less than or equal to 4 microns, which can effectively fill the height difference of the thin film transistor at different positions, so that the overlap between the spacers and the region between the two thin film transistors in the wiring region does not affect the height difference of the liquid crystal panel. Moreover, the data line and the thin film transistor correspond to the region covered by the black matrix, the orthographic projection of the spacers on the first substrate has an overlap with the orthographic projection of the data line on the first substrate, and the orthographic projection of the spacers on the first substrate has an overlap with the region between the two thin film transistors. The region covered by the black matrix can be used to make the spacers have less influence on the aperture ratio of the sub-pixel, thereby improving the transmittance of the sub-pixel.

[0254] In specific implementation, the shape of the orthographic projection of the spacers on the first substrate can be circular, elliptical, hexagonal, etc. The maximum width of the orthographic projection of the spacers on the first substrate in the first direction or the second direction is greater than or equal to 9 microns and less than or equal to 25 microns, for example.

[0255] The display device provided by the embodiments of the present disclosure comprises the display panel provided by the embodiments of the present disclosure.

[0256] In some embodiments, the display device provided by the embodiments of the present disclosure can further comprise a backlight module located on the light-incident side of the array substrate. The backlight module can be a direct backlight module or a side backlight module.

[0257] In specific implementation, the side backlight module can comprise a lamp strip, a reflector sheet, a light guide plate, a diffusion sheet, a prism group and the like, and the lamp strip is located on one side of the light guide plate in the thickness direction. The direct backlight module can comprise a matrix light source, a reflector sheet, a diffusion plate and a brightness enhancement film and the like which are stacked on the light-incident side of the matrix light source, and the reflector sheet comprises openings which are arranged opposite to the positions of the lamp beads in the matrix light source. The lamp beads in the lamp strip and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED and the like). The micro light-emitting diode with a sub-millimeter level or even a micron level is a self-luminous device like an organic light-emitting diode (OLED). Like the organic light-emitting diode, the micro light-emitting diode has a series of advantages such as high brightness, ultra-low delay, ultra-large viewing angle and the like. Moreover, since the inorganic light-emitting diode emits light based on a metal semiconductor with more stable properties and lower resistance, it has the advantages of lower power consumption, longer service life and better resistance to high and low temperatures compared with the organic light-emitting diode which emits light based on organic matter. When the micro light-emitting diode is used as a backlight source, it can realize more precise dynamic backlight effect, effectively improve the screen brightness and contrast, and solve the glare phenomenon caused by the traditional dynamic backlight between the bright and dark areas of the screen, thereby optimizing the visual experience.

[0258] In some embodiments, the display device provided by the embodiments of the present disclosure can be any product or component with display function, such as a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and the like. Optionally, the display device provided by the embodiments of the present disclosure includes, but is not limited to, a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip, and the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like. For example, the control chip can further include a memory, and can further include a power module, and the like, and the power supply and signal input and output functions are realized through wires, signal lines, and the like arranged additionally. For example, the control chip can further include hardware circuitry and computer executable code, and the like. The hardware circuitry can include conventional very large scale integration (VLSI) circuitry or gate array, and existing semiconductors or other discrete elements such as logic chips, transistors, and the like; the hardware circuitry can also include field programmable gate array, programmable array logic, programmable logic device, and the like. In addition, those skilled in the art can understand that the above structure does not constitute a limitation on the display device provided by the embodiments of the present disclosure, in other words, the display device provided by the embodiments of the present disclosure can include more or less components, or combine certain components, or different component arrangements.

[0259] In summary, the array substrate, the display panel and the display device provided by the embodiments of the present disclosure, the second electrode includes a first sub-connection part and a second sub-connection part located on the opposite sides of the first sub-connection part and connected with the first sub-connection part, the first sub-connection part is in the first opening area of the first electrode in the orthographic projection of the substrate substrate, the second sub-connection part on the opposite sides of the first sub-connection part has an overlap with the first electrode and the first opening area in the orthographic projection of the substrate substrate, when all the second electrodes included in the array substrate are offset due to process deviation, that is, the second sub-connection parts on the opposite sides of the first sub-connection part are all offset, compared with the case where no offset occurs, the opposite sides of the first sub-connection part are connected with the second sub-electrode, in each second electrode, the second sub-connection part on one side of the first sub-connection part increases the overlapping area with the first electrode in the orthographic projection of the substrate substrate, and the second sub-connection part on the other side of the first sub-connection part reduces the overlapping area with the first electrode in the orthographic projection of the substrate substrate, since the offset amount of the second sub-connection parts on the opposite sides of the first sub-connection part is the same, the change of the overlapping area of the second sub-connection parts on the opposite sides of the first sub-connection part with the first electrode in the orthographic projection of the substrate substrate can be complementary, even if the position of the second electrode is offset due to process deviation, the parasitic capacitance of each second electrode and the first electrode is still equal, avoiding the large difference in charging rate of different second electrodes caused by the different parasitic capacitances of different second electrodes and the first electrode, when the array substrate is applied to a display product, thereby avoiding the difference in brightness of different sub-pixel areas. When the user moves to watch, the brightness difference can be avoided to be aggravated, and the shaking lines can be avoided to appear, the display effect is improved, and the user experience is improved.

[0260] Although preferred embodiments of the application have been described, those skilled in the art will be able to make additional changes and modifications without departing from the spirit and scope of the application. Therefore, the appended claims are intended to cover all such changes and modifications that fall within the scope of the application.

[0261] Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, The array substrate comprises: a first substrate including a plurality of sub-pixel regions and a plurality of wiring regions between adjacent sub-pixel regions arranged in a first direction and a second direction, the first direction intersecting the second direction; a plurality of thin film transistors on a side of the first substrate, each thin film transistor of the plurality of thin film transistors including a first electrode, a second electrode, and a third electrode; a first electrode on a side of the first substrate opposite the first electrode, the first electrode including a plurality of first opening regions, the first opening regions in a projection of the first substrate falling within the wiring regions, and the first opening regions in the projection of the first substrate overlapping the first electrode in the projection of the first substrate; a plurality of second electrodes on the same side of the first substrate as the first electrode, each second electrode of the plurality of second electrodes including a first connecting portion, the first connecting portion including a first sub-connecting portion electrically connected to the first electrode, and a second sub-connecting portion electrically connected to the first sub-connecting portion, the second sub-connecting portion including structures on opposite sides of the first sub-connecting portion, respectively, the first sub-connecting portion in the projection of the first substrate falling within the first opening regions in the projection of the first substrate, and the second sub-connecting portion in the projection of the first substrate overlapping the first electrode and the first opening regions in the projection of the first substrate.

2. The array substrate according to claim 1, wherein, The second sub-connecting portion includes a first structure and a second structure; In the first direction, the first structure and the second structure are on opposite sides of the first sub-connecting portion, respectively.

3. The array substrate according to claim 2, wherein, The first structure includes a first region adjacent to the first sub-connecting portion, and the second structure includes a second region adjacent to the first sub-connecting portion; In the first direction, a distance between the first sub-connecting portion in the projection of the first substrate and an edge of the first opening region on a side of the first sub-connecting portion facing the first structure in the projection of the first substrate is less than a width of the first region in the projection of the first substrate, and a distance between the first sub-connecting portion in the projection of the first substrate and an edge of the first opening region on a side of the first sub-connecting portion facing the second structure in the projection of the first substrate is less than a width of the second region in the projection of the first substrate.

4. The array substrate according to claim 3, wherein, The first structure includes at least one first sub-structure connected to the first sub-connecting portion, and the second structure includes at least one second sub-structure connected to the first sub-connecting portion. In the second direction, a maximum width of a projection of the first sub-connection portion on the first substrate is less than a width of a projection of the first opening region on the first substrate, a maximum width of a projection of the first sub-connection portion on the first substrate is greater than a total width of a projection of the first sub-structure of the first region on the first substrate, and a maximum width of a projection of the first sub-connection portion on the first substrate is greater than a total width of a projection of the second sub-structure of the second region on the first substrate.

5. The array substrate according to claim 4, wherein, In the second direction, a total width of a projection of the first sub-structure of the first region on the first substrate is equal to a total width of a projection of the second sub-structure of the second region on the first substrate.

6. The array substrate according to any one of claims 2 to 5, wherein, The plurality of sub-pixel regions and the plurality of wiring regions are divided into a plurality of sub-pixel columns arranged along the first direction and extending along the second direction; the plurality of second electrodes comprises a plurality of first sub-electrodes and a plurality of second sub-electrodes; The first sub-electrode and the thin film transistor electrically connected thereto are located in the same sub-pixel column; The second sub-electrode and the thin film transistor electrically connected thereto are located in different sub-pixel columns.

7. The array substrate according to claim 3, wherein, The second electrode further comprises a pixel portion corresponding to the sub-pixel region and connected to the first connection portion; The second sub-connection portion of the first sub-electrode further comprises a third structure; in the second direction, the third structure is located between the first structure and the pixel portion; the third structure is electrically connected to the pixel portion, and at least one of the first sub-connection portion and the first structure is connected to the third structure.

8. The array substrate according to claim 7, wherein, In the first sub-electrode, a projection of the third structure on the first substrate does not overlap with the first opening region.

9. The array substrate of claim 7, wherein, In the first sub-electrode and the thin film transistor corresponding thereto, in the first direction, the first structure and the second electrode are located on the same side of the first opening region; a projection of the first structure on the first substrate overlaps with a projection of the second electrode on the first substrate.

10. The array substrate of claim 9, wherein, In the first sub-electrode, in the first direction, a length of a projection of the first structure on the first substrate is greater than a length of a projection of the second structure on the first substrate.

11. The array substrate of claim 7, wherein, The third structure has an overlap with the first opening region in a projection on the first substrate.

12. The array substrate of claim 11, wherein, In the first sub-electrode, the second sub-connection portion further comprises a fourth structure; in the second direction, the third structure and the fourth structure are located on two sides of the first sub-connection portion, respectively.

13. The array substrate of claim 12, wherein, In the first sub-electrode, the third structure comprises a third region adjacent to the first sub-connection portion, and the fourth structure comprises a fourth region adjacent to the first sub-connection portion; In the second direction, a distance between a projection of the first sub-connection portion on the first substrate and an edge of the first opening region of the first sub-connection portion toward the third structure on the projection of the first substrate is less than a width of the third region on the projection of the first substrate, and a distance between the projection of the first sub-connection portion on the first substrate and an edge of the first opening region of the first sub-connection portion toward the fourth structure on the projection of the first substrate is less than a width of the fourth region on the projection of the first substrate.

14. The array substrate of claim 13, wherein, The third structure includes at least one third sub-structure connected with the first sub-connection portion, and the fourth structure includes at least one fourth sub-structure connected with the first sub-connection portion. In the first direction, a total width of the third sub-structure in the third region on the projection of the first substrate is equal to a total width of the fourth sub-structure in the fourth region on the projection of the first substrate.

15. The array substrate according to any one of claims 7 to 14, wherein, The second sub-connection portion of the second sub-electrode further includes a fifth structure connected with the first structure and the pixel portion between the first structure and the pixel portion in the second direction.

16. The array substrate according to any one of claims 7 to 14, wherein, The pixel portion of the first sub-electrode on the projection of the first substrate has a first overlapping area with the first electrode on the projection of the first substrate, and the pixel portion of the second sub-electrode on the projection of the first substrate has a second overlapping area with the first electrode on the projection of the first substrate; the first sub-connection portion of the first sub-electrode on the projection of the first substrate has a third overlapping area with the first electrode on the projection of the first substrate, and the first sub-connection portion of the second sub-electrode on the projection of the first substrate has a fourth overlapping area with the first electrode on the projection of the first substrate; the first overlapping area is substantially equal to the second overlapping area, and the third overlapping area is substantially equal to the fourth overlapping area.

17. The array substrate of claim 6, wherein, The first electrode further includes a plurality of second opening regions in the wiring region; the second opening region on the projection of the first substrate has an overlapping area with the first sub-connection portion of the second sub-electrode on the projection of the first substrate.

18. The array substrate of claim 17, wherein, In the first direction, the first sub-electrode and the second sub-electrode are arranged alternately, and in the second direction, the first sub-electrode and the second sub-electrode are arranged alternately.

19. The array substrate of claim 18, wherein, The array substrate further includes: a plurality of data lines on a side of the first electrode toward the first substrate, arranged along the first direction and extending along the second direction; each of the data lines in the plurality of data lines is electrically connected with the second electrode of the thin film transistor; two adjacent data lines are spaced apart by two sub-pixel columns. The plurality of wiring regions are divided into a plurality of wiring region rows extending in the first direction; the wiring region rows include a plurality of first sub-regions and a plurality of second sub-regions; each of the first sub-regions in the plurality of first sub-regions is adjacent to the sub-pixel region in the second direction, and the first sub-region is located between two adjacent data lines; each of the second sub-regions in the plurality of second sub-regions is adjacent to the sub-pixel region in the second direction, and the second sub-region is located between two adjacent data lines; in the second direction, the first sub-regions and the second sub-regions are alternately arranged; The plurality of thin film transistors include a plurality of first thin film transistors and a plurality of second thin film transistors; the first thin film transistors are electrically connected to the first sub-electrodes, and the second thin film transistors are electrically connected to the second sub-electrodes; the first thin film transistors are located in the first sub-regions, and the second thin film transistors are located in the second sub-regions; In the Mth wiring region row, two first sub-regions are separated by m second sub-regions; in the (M+1)th wiring region row, two second sub-regions are separated by m first sub-regions; wherein M is an integer greater than or equal to 1, m is an integer greater than 1, and (M+1) is less than or equal to the total number of the wiring region rows.

20. The array substrate of claim 19, wherein, m=2。 21. The array substrate of claim 19, wherein, The array substrate further comprises: A plurality of scan lines are located on the side of the first electrode facing the first substrate; the plurality of scan lines extend in the first direction and are arranged in the second direction; the plurality of scan lines include a plurality of first scan lines and a plurality of second scan lines; the first scan lines and the second scan lines are alternately arranged; between two adjacent sub-pixel regions in the second direction, one first scan line and one second scan line are included; the scan lines are disposed in the same layer as and electrically connected to the third electrode of the thin film transistor; the scan lines include a first compensation portion corresponding to the thin film transistor; The first electrode of the thin film transistor includes a first portion, and a second portion and a third portion located on the two sides of the first portion in the first direction, respectively; The first portion is projected onto the region between the third electrode and the first compensation portion on the first substrate, the second portion has an overlap with the third electrode on the first substrate, and the third portion has an overlap with the first compensation portion on the first substrate.

22. The array substrate of claim 21, wherein, In the second direction, the width of the third portion on the first substrate is equal to the width of the second portion on the first substrate close to the first portion.

23. The array substrate of claim 21, wherein, In the first sub-region, the scan line includes a first part extending in the first direction and a second part extending in a third direction and connected to the first part; the third direction intersects both the first direction and the second direction; the first compensation portion is located on the side of the second part facing the third electrode.

24. The array substrate of claim 21, wherein, In the second sub-region, the scan line comprises a second portion extending along the first direction, and a third portion extending along a third direction and connected with the second portion; the third direction intersects with the first direction and the second direction; the first compensation portion is located on a side of the third portion facing the third electrode.

25. The array substrate of claim 21, wherein, In the second sub-region, the scan line comprises a second portion extending along the first direction; the first compensation portion is connected with the second portion in the second direction, and in the second direction, the first compensation portion and the three electrodes are located on the same side of the second portion.

26. The array substrate of claim 25, wherein, In the second sub-region, the second opening region does not overlap with the scan line in the orthographic projection of the first substrate, and the orthographic projection of the region where the orthographic projection of the second opening region falls between the two adjacent first compensation portions is within the orthographic projection of the first substrate.

27. The array substrate of claim 26, wherein, In at least part of the second sub-region, the first connection portions of the two second sub-electrodes are integrally connected with the corresponding second opening regions.

28. The array substrate according to any one of claims 7 to 14, 17 to 22, 26, 27, wherein, The array substrate comprises a plurality of scan lines; The orthographic projection of the pixel portion and the scan line have an overlap in the orthographic projection of the first substrate.

29. The array substrate according to any one of claims 7 to 14, 17 to 22, 26, 27, wherein, The first electrode comprises a plurality of slit units, or the pixel portion comprises a slit unit; The slit unit has an overlap with the sub-pixel region in the orthographic projection of the first substrate; The slit unit comprises first sub-units and second sub-units arranged alternately in the second direction; the first sub-units comprise a plurality of first slits extending along a fourth direction and arranged along the first direction, and the second sub-units comprise a plurality of second slits extending along a fifth direction and arranged along the first direction; the fourth direction intersects with the fifth direction, and the fourth direction intersects with the first direction and the second direction; the fifth direction intersects with the first direction and the second direction; The array substrate further comprises a plurality of first electrode lines extending along the first direction and arranged along the second direction on a side of the first electrode facing the first substrate; the first electrode lines are electrically connected with the first electrode; The orthographic projection of the first electrode line has an overlap with the connection between the first sub-units and the second sub-units in the orthographic projection of the first substrate.

30. The array substrate of claim 29, wherein, The array substrate further comprises: a plurality of data lines; a plurality of second electrode lines arranged in the same layer as the first electrode lines in the wiring region and electrically connected, extending along the second direction; two adjacent second electrode lines are separated by two sub-pixel columns; in the first direction, the second electrode lines and the data lines are arranged alternately.

31. A display panel, wherein, The display panel comprises: The array substrate according to any one of claims 1-30; the array substrate comprises a plurality of data lines; a counter substrate arranged opposite to the array substrate; a liquid crystal layer between the array substrate and the counter substrate; The counter substrate includes a second substrate and a plurality of spacers on a side of the second substrate facing the liquid crystal layer; the spacers are in the projection of the first substrate and the spacers have an overlap with the projection of the data line on the first substrate.

32. A display device comprising: The display device includes the display panel according to claim 31.

Images