An edge-passivated crystalline silicon cell and a perovskite crystalline silicon stacked cell and preparation thereof

Abstract

The present invention provides an edge-passivated crystalline silicon cell and a perovskite crystalline silicon stacked cell and preparation thereof, wherein the crystalline silicon cell is a cut cell, and the cut end surface of the cut cell is covered with GeSe 2 The crystalline silicon cell provided by the present invention is a cut cell, and the cut end surface is covered with GeSe 2 The passivation layer confines the photogenerated carriers inside the crystalline silicon cell, preventing the non-radiative recombination of the photogenerated carriers at the cut end faces, reducing the charge accumulation at the edge of the crystalline silicon cell, thereby reducing the surface recombination rate of the crystalline silicon cell, and thus improving the photoelectric conversion efficiency of the crystalline silicon cell.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and relates to an edge-passivated crystalline silicon cell, and in particular to an edge-passivated crystalline silicon cell and a perovskite crystalline silicon stacked cell and their preparation. Background Art

[0002] Perovskite crystalline silicon tandem solar cells have shown great potential in recent years. The use of two light-absorbing materials, wide-bandgap perovskite and narrow-bandgap crystalline silicon, can improve the utilization of the solar spectrum. Its theoretical efficiency exceeds 45%. Currently, the laboratory has achieved 33.9%, which is much higher than crystalline silicon cells. However, in tandem cells, the crystalline silicon cells of silicon wafer size produced by the production line need to be cut into small cells to match the perovskite process. Since new dangling bonds will be generated at the edge of the cell after cutting, it will cause larger edge recombination problems, which will have an adverse effect on the power generation performance of the bottom cell and even the entire tandem cell. Therefore, effective passivation treatment of the cell edge is a key step to improve the performance of the bottom cell and the tandem cell.

[0003] The commonly used edge passivation method is to deposit a layer of aluminum oxide film on the edge of the cross section of the battery by atomic layer deposition (ALD), and then perform electrical injection annealing treatment, which can reduce the carrier recombination rate to a certain extent, thereby improving the performance of the battery. Another method of battery edge passivation is to deposit a layer of silicon oxide passivation film by coating the slurry and irradiating the slurry with ultraviolet light, and achieve local oxidation of only the edge area of ​​the crystalline silicon solar cell by using photocatalytic oxidation technology.

[0004] CN104538464A discloses a silicon heterojunction solar cell and a manufacturing method thereof. The silicon heterojunction solar cell comprises: a crystalline silicon substrate, a first amorphous silicon passivation layer, a first transparent electrode and a first gate line electrode sequentially arranged on the upper surface of the crystalline silicon substrate, a second amorphous silicon passivation layer, a second transparent electrode and a second metal electrode sequentially arranged on the lower surface of the crystalline silicon substrate, and an edge passivation layer, wherein the edge passivation layer at least covers the same side of the crystalline silicon substrate, the first amorphous silicon passivation layer and the second amorphous silicon passivation layer; the edge passivation layer can increase the passivation effect of the side of the silicon heterojunction solar cell, improve the open circuit voltage and fill factor of the silicon heterojunction solar cell, improve the conversion efficiency of the silicon heterojunction solar cell, and can insulate the first transparent electrode and the second transparent electrode, thereby effectively preventing the occurrence of side leakage of the silicon heterojunction solar cell and improving the performance of the silicon heterojunction solar cell.

[0005] CN111509091A discloses a method for passivating the edge of a battery, which comprises printing a slurry onto the edge of the crystalline silicon battery that needs to be passivated by coating, and irradiating the edge with ultraviolet light to form a layer of silicon oxide passivation film on the edge under conditions of photocatalytic oxidation; the slurry contains hydrogen peroxide and SiO2 powder; after the silicon oxide passivation film is formed on all the edges of the crystalline silicon battery that need to be passivated, the crystalline silicon battery that has completed photocatalytic oxidation is annealed.

[0006] CN115148858A discloses a passivation method for a silicon solar cell. The passivation method for a silicon solar cell comprises: providing a silicon solar cell slice, wherein the silicon solar cell slice has a cut surface, wherein the cut surface has a surface layer and a sub-surface layer, wherein the sub-surface layer of the cut surface is located inside the surface layer of the cut surface; performing a passivation treatment on the cut surface in a passivation solution; and after the passivation treatment, performing a light injection treatment on the cut surface, wherein the light injection treatment is suitable for forming polar fixed charges on the surface layer and the sub-surface layer of the cut surface to increase the potential of the surface layer and the sub-surface layer of the cut surface.

[0007] The edge-passivated crystalline silicon cells disclosed in the prior art have certain defects. The passivation effect of the passivation layer on the cut end face of the crystalline silicon cell is poor, and the cut edge of the crystalline silicon cell still has serious non-radiative recombination caused by dangling bonds, which leads to the problem of low photoelectric conversion efficiency of the crystalline silicon cell. Therefore, it is very important to develop and design a new type of edge-passivated crystalline silicon cell and perovskite crystalline silicon stacked cell and preparation. Summary of the invention

[0008] In view of the shortcomings of the prior art, the purpose of the present invention is to provide an edge-passivated crystalline silicon cell and a perovskite crystalline silicon stacked cell and their preparation. The crystalline silicon cell provided by the present invention is a cut cell, and the cut end face is covered with a GeSe2 passivation layer. The photogenerated carriers will be confined inside the crystalline silicon cell, preventing the non-radiative recombination of the photogenerated carriers at the cut end face, reducing the charge accumulation at the edge of the crystalline silicon cell, thereby reducing the surface recombination rate of the crystalline silicon cell, and thus improving the photoelectric conversion efficiency of the crystalline silicon cell.

[0009] To achieve this object, the present invention adopts the following technical solutions:

[0010] In a first aspect, the present invention provides a crystalline silicon cell with edge passivation, wherein the crystalline silicon cell is a cut cell, and a cut end surface of the cut cell is covered with a GeSe2 passivation layer.

[0011] The crystalline silicon cell provided by the present invention is a cut cell, and the cut end face is covered with a GeSe2 passivation layer. The photogenerated carriers will be confined inside the crystalline silicon cell, preventing the non-radiative recombination of the photogenerated carriers at the cut end face, reducing the charge accumulation at the edge of the crystalline silicon cell, thereby reducing the surface recombination rate of the crystalline silicon cell, and thus improving the photoelectric conversion efficiency of the crystalline silicon cell.

[0012] Preferably, the thickness of the GeSe2 passivation layer is 1~40nm, for example, it can be 1nm, 3nm, 5nm, 7nm, 10nm, 20nm, 30nm or 40nm, but it is not limited to the listed values. Other unlisted values ​​within the numerical range are also applicable, preferably 10~20nm.

[0013] The band gap of the GeSe2 material in the GeSe2 passivation layer provided by the present invention is 2.7eV. When the thickness of the GeSe2 passivation layer is less than 10nm, due to the quantum confinement effect, its band gap will be widened; for example, when GeSe2 is a monolayer (about 1.09nm), its band gap is widened to 2.98eV, and the band gap of the crystalline silicon cell light absorption layer is 1.10~1.12eV. Therefore, after the cut end face of the cell is covered with the GeSe2 passivation layer after cutting, the photogenerated carriers will be confined in the crystalline silicon material to prevent non-radiative recombination from occurring at the cut end face.

[0014] In a second aspect, the present invention provides a method for preparing the crystalline silicon cell according to the first aspect, the method comprising:

[0015] After a GeSe2 layer is deposited on the cut end surface of the cut cell, light passivation and heat treatment are simultaneously performed to obtain a crystalline silicon cell with a GeSe2 passivation layer covering the cut end surface.

[0016] The method for preparing the crystalline silicon cell provided by the present invention realizes the deposition of a GeSe2 passivation layer on the cut end face of the cell after cutting, thereby improving the photoelectric conversion efficiency of the crystalline silicon cell.

[0017] Preferably, the cut cell is obtained by cutting an N-type solar cell or a P-type solar cell;

[0018] The N-type solar cell or the P-type solar cell is independently a solar cell of silicon wafer size.

[0019] The cut battery provided by the present invention can be, for example, a 25mm×25mm small battery formed by laser cutting a 182mm×182mm crystalline silicon cell, and the four sides of the small battery are all produced after laser cutting; it can also be a 50mm×50mm small battery formed by laser cutting a 210mm×210mm crystalline silicon cell, and the four sides of the small battery are all produced after laser cutting; but it is not limited to the listed small batteries, and the small batteries obtained after cutting of crystalline silicon cells in the prior art can be applicable.

[0020] Preferably, the cutting method comprises laser cutting.

[0021] The N-type solar cell described in the present invention includes but is not limited to a TOPCon cell, and any N-type solar cell in the prior art that can be cut to obtain a cut cell is applicable.

[0022] Preferably, before the deposition, at least two cut cells are stacked and arranged, and the cut end faces of the cut cells are located on the same vertical side surface to obtain a stacked cell, and then the top surface of the obtained stacked structure is shielded to obtain a shielded stacked cell;

[0023] or,

[0024] Before the deposition, the top surface of the single cut cell is shielded to obtain a shielded single cell.

[0025] Preferably, the number of cut batteries stacked in the stacked battery is 2 to 400 pieces, for example, it can be 2 pieces, 4 pieces, 8 pieces, 12 pieces, 20 pieces, 40 pieces, 60 pieces, 80 pieces, 100 pieces, 150 pieces, 200 pieces, 250 pieces, 300 pieces, 350 pieces or 400 pieces, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0026] Preferably, the shielding comprises covering the top surface of the shielded stacked cells or the shielded single cells with glass, and the bottom surface of the glass can completely cover the entire top surface of the shielded stacked cells or the shielded single cells.

[0027] Preferably, the deposition method comprises chemical vapor deposition, and the precursors used in the chemical vapor deposition comprise Se powder and GeSe powder;

[0028] The chemical vapor deposition comprises:

[0029] Se powder, GeSe powder and shielded stacked cells or shielded single cells are placed in a sintering container, sintered in a protective atmosphere containing a reducing gas, and then cooled to obtain a stacked cell with a GeSe2 layer deposited thereon.

[0030] Preferably, the chemical vapor deposition comprises:

[0031] (1) Se powder, GeSe powder and at least one group of shielded stacked cells or shielded single cells are arranged in a sintering container in sequence along one direction, and a protective gas is introduced into the sintering container, wherein the protective gas flows from the Se powder to the stacked structure;

[0032] (2) The first area where the GeSe powder and the shielded stacked battery or the shielded single battery in the sintering container are located is heated for a first time, and the first area is kept warm for a first time while the second area where the Se powder is located is heated for a second time. A mixed gas of reducing gas and protective gas is introduced while stopping the introduction of protective gas, and the first area and the second area are kept warm for a second time. After cooling, a shielded stacked battery or a shielded single battery with a GeSe2 layer deposited on the cut end face is obtained.

[0033] Preferably, the sintering container includes a quartz tube, and the Se powder and GeSe powder are both placed in a magnetic boat. The magnetic boat containing the GeSe powder is located in the middle of the quartz tube, the magnetic boat containing the Se powder is located in the quartz tube near the gas inlet, and the stacked structure is placed in the quartz tube near the gas outlet.

[0034] Preferably, before introducing the protective gas, the method further comprises: evacuating the sintering container.

[0035] Preferably, after the protective gas is introduced to atmospheric pressure, the protective gas is continuously introduced for 40 to 80 minutes, for example, 40 minutes, 45 minutes, 50 minutes, 55 minutes, 60 minutes, 65 minutes, 70 minutes, 75 minutes or 80 minutes, but is not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0036] Preferably, the first heating rate is 40-60°C / min, and the end point temperature is 600-800°C.

[0037] The first heating rate of the present invention is 40-60°C / min, for example, it can be 40°C / min, 42°C / min, 44°C / min, 46°C / min, 48°C / min, 50°C / min, 52°C / min, 54°C / min, 56°C / min, 58°C / min or 60°C / min, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0038] In the present invention, the endpoint temperature of the first heating is 600-800°C, for example, it can be 600°C, 620°C, 640°C, 660°C, 680°C, 700°C, 720°C, 740°C, 760°C, 780°C or 800°C, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0039] Preferably, the temperature of the first insulation is the end temperature of the first heating, and the time is the time of the second heating.

[0040] Preferably, the heating rate of the second heating is 300-360°C / min, and the end point temperature is 300-420°C.

[0041] The heating rate of the second temperature increase in the present invention is 300~360℃ / min, for example, it can be 300℃ / min, 310℃ / min, 320℃ / min, 330℃ / min, 340℃ / min, 350℃ / min or 360℃ / min, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0042] Preferably, the temperature of the first region in the second heat preservation is the end point temperature of the first temperature rise, and the temperature of the second region is the end point temperature of the second temperature rise.

[0043] Preferably, the volume concentration of the reducing gas in the mixed gas is 5-10%, for example, 5%, 6%, 7%, 8%, 9% or 10%, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0044] Preferably, the reducing gas comprises hydrogen.

[0045] Preferably, the second insulation time is 1 to 20 minutes, for example, it can be 1 minute, 3 minutes, 5 minutes, 7 minutes, 9 minutes, 10 minutes, 12 minutes, 14 minutes, 16 minutes, 18 minutes or 20 minutes, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0046] Preferably, the cooling comprises natural cooling to room temperature.

[0047] Preferably, the photopassivation comprises irradiating the deposited GeSe2 layer with sunlight having a light intensity of 20 to 100 times the light intensity;

[0048] The temperature of the heat treatment is 200-500°C;

[0049] The time for the simultaneous photopassivation and heat treatment is 80 to 160 seconds.

[0050] The photopassivation described in the present invention includes irradiating the deposited GeSe2 layer with sunlight having a light intensity of 20 to 100 light intensities, for example, 20 light intensities, 30 light intensities, 40 light intensities, 50 light intensities, 60 light intensities, 70 light intensities, 80 light intensities, 90 light intensities or 100 light intensities, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0051] The temperature of the heat treatment in the present invention is 200-500°C, for example, it can be 200°C, 250°C, 300°C, 350°C, 400°C, 450°C or 500°C, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0052] The time for the photopassivation and heat treatment performed simultaneously in the present invention is 80 to 160 seconds, for example, it can be 80 seconds, 90 seconds, 100 seconds, 110 seconds, 120 seconds, 130 seconds, 140 seconds, 150 seconds or 160 seconds, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0053] As a preferred technical solution of the preparation method of the present invention, the preparation method comprises:

[0054] (I) stacking 2 to 400 cut batteries so that the cut end faces of the cut batteries are located on the same vertical side to obtain a stacked battery, and then shielding the top surface of the obtained stacked structure to obtain a shielded stacked battery;

[0055] or,

[0056] Before the deposition, the top surface of the single cut battery is shielded to obtain a shielded single battery;

[0057] (II) Se powder, GeSe powder and at least one group of shielded stacked cells or shielded single cells obtained in step (I) are sequentially arranged in a sintering container along one direction, and a protective gas is introduced into the sintering container, wherein the protective gas flows in a direction from the Se powder to the stacked structure;

[0058] (III) The first region where the GeSe powder and the shielded stacked battery or the shielded single battery are located in the sintering container is heated to 600-800°C at a heating rate of 40-60°C / min, and the second region where the Se powder is located is heated to 300-420°C at a heating rate of 300-360°C / min while the first region is kept warm, and a mixed gas of reducing gas and protective gas is introduced while stopping the introduction of protective gas, wherein the volume concentration of reducing gas in the mixed gas is 5-10%, and the first region and the second region are kept warm for 1-20 minutes, and after cooling, a shielded stacked battery or a shielded single battery with a GeSe2 layer deposited on the cut end face is obtained;

[0059] (IV) The shielded stacked cells or shielded single cells having a GeSe2 layer deposited on the cut end faces obtained in step (III) are simultaneously subjected to photopassivation and heat treatment for 80 to 160 seconds, wherein the photopassivation comprises irradiating the deposited GeSe2 layer with sunlight having a light intensity of 20 to 100 times the light intensity, and the heat treatment temperature is 200 to 500°C, to obtain at least one crystalline silicon cell having a GeSe2 passivation layer covered on the cut end faces.

[0060] In the present invention, 2 to 400 cells are cut and stacked, the top surface is shielded to obtain a stacked cell, and then a GeSe2 passivation layer is prepared, the purpose is to improve the preparation efficiency of the GeSe2 passivation layer, and finally 2 to 400 crystalline silicon cells are directly obtained.

[0061] In a third aspect, the present invention provides a perovskite crystalline silicon tandem cell, wherein the perovskite crystalline silicon tandem cell comprises the crystalline silicon cell described in the first aspect.

[0062] In a fourth aspect, the present invention provides a preparation process of the perovskite crystalline silicon tandem cell according to the third aspect, the preparation process comprising:

[0063] The crystalline silicon cell described in the first aspect is used as a substrate, and a layer of solar top cell is prepared on the substrate to obtain a perovskite crystalline silicon stacked cell.

[0064] Compared with the prior art, the present invention has the following beneficial effects:

[0065] The crystalline silicon cell provided by the present invention is a cut cell, and the cut end face is covered with a GeSe2 passivation layer. The photogenerated carriers will be confined inside the crystalline silicon cell, preventing the non-radiative recombination of the photogenerated carriers at the cut end face, reducing the charge accumulation at the edge of the crystalline silicon cell, thereby reducing the surface recombination rate of the crystalline silicon cell, and thus improving the photoelectric conversion efficiency of the crystalline silicon cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1Schematic diagram of depositing GeSe2 layer in a sintering container after shielding the stacked cells in Example 1.

[0067] Among them, 1-Se powder; 2-GeSe powder 2; 3-shielded stacked cells; 4-sintering container; 5-first area; 6-second area. DETAILED DESCRIPTION

[0068] The technical solution of the present invention is further described below by specific implementation methods. It should be understood by those skilled in the art that the embodiments are only to help understand the present invention and should not be regarded as specific limitations of the present invention.

[0069] Example 1

[0070] This embodiment provides a crystalline silicon cell with edge passivation. The crystalline silicon cell is a cut cell obtained by cutting a commercial TOPCon cell. The cut end surface of the cut cell is covered with a GeSe2 passivation layer with a thickness of 10 nm.

[0071] The method for preparing the edge-passivated crystalline silicon cell comprises:

[0072] (I) The structure of a commercial TOPCon cell is a stacked Ag electrode, a silicon nitride film, an aluminum oxide film, a p-type doped silicon layer, a single crystal silicon layer, a silicon oxide film, an n-type polycrystalline silicon layer and a silicon nitride film. A 182×182 mm commercial TOPCon cell is cut by laser to obtain 300 small cells of 25×25 mm. The four sides of each small cell are produced by laser cutting. Then, a 10% HF solution is used to remove the silicon nitride film on the surface of the n-type polycrystalline silicon layer of each small cell to obtain a cut cell.

[0073] 300 cut batteries are stacked and arranged so that the cut end faces of the cut batteries are located on the same vertical side to obtain two groups of stacked batteries, and then the top surface of the obtained stacked structure is shielded to obtain two groups of shielded stacked batteries 3;

[0074] (II) If Figure 1 As shown, Se powder 1, GeSe powder 2 and the shielded stacked cells 3 obtained in step (I) of group 2 are sequentially arranged in a sintering container 4 along one direction, and argon gas is introduced into the sintering container 4, and the argon gas flows in the direction from Se powder 1 to the stacked structure;

[0075] (III) The GeSe powder 2 in the sintering container 4 and the first region 5 where the shielded laminated battery 3 is located are heated to 700°C at a heating rate of 50°C / min, and the first region 5 is kept warm while the second region 6 where the Se powder 1 is located is heated to 360°C at a heating rate of 330°C / min, and a mixed gas of hydrogen and argon is introduced while stopping the introduction of argon, wherein the volume concentration of hydrogen in the mixed gas is 8%, and the first region 5 and the second region 6 are kept warm for 10 minutes, and after cooling, a shielded laminated battery 3 with a GeSe2 layer deposited on the cut end face is obtained;

[0076] (IV) The shielded stacked cell 3 with the GeSe2 layer deposited on the cut end surface obtained in step (III) is simultaneously subjected to photopassivation and heat treatment for 120 seconds, wherein the photopassivation comprises irradiating the deposited GeSe2 layer with sunlight of a light intensity of 60 times the light intensity, and the temperature of the heat treatment is 350°C, thereby obtaining 300 crystalline silicon cells with the cut end surface covered with a GeSe2 passivation layer.

[0077] This embodiment also provides a perovskite crystalline silicon stacked cell, and the preparation process of the perovskite crystalline silicon stacked cell includes:

[0078] Using the above-obtained crystalline silicon cell as a substrate, an ITO layer with a thickness of 25 nm is prepared on the surface of the n-type polycrystalline silicon layer of the substrate by magnetron sputtering;

[0079] Then, a layer of nickel oxide (NiOx) with a thickness of 15 nm is sputtered on the ITO layer by magnetron sputtering as a hole transport layer;

[0080] A perovskite light-absorbing layer is then deposited on the NiOx layer, and the deposition process is as follows: 2.8 mmol of cesium iodide, 11.2 mmol of formamidine iodide, 0.07 mmol of phenethylammonium iodide, 5.6 mmol of lead iodide, and 8.4 mmol of lead bromide are weighed and mixed to obtain a mixture, 8 mL of N,N-dimethylformamide and 2 mL of dimethyl sulfoxide are added to the mixture, and the mixture is stirred sufficiently to be completely dissolved, and a precursor solution is formed after filtering; a perovskite film of about 500 nm is prepared as a perovskite light-absorbing layer by a solution method;

[0081] Then, about 25 nm of fullerene (C60) is deposited on the obtained perovskite light-absorbing layer by vacuum evaporation as an electron transport layer.

[0082] Then, a layer of SnO2 with a thickness of 18 nm is deposited on the electron transport layer by atomic layer deposition to reduce the damage to the substrate during the subsequent sputtering process;

[0083] Then, a transparent oxide ITO layer with a thickness of 40 nm is prepared on the SnO2 layer by magnetron sputtering;

[0084] Then, a metal silver electrode with a thickness of 1000 nm is deposited on the transparent oxide ITO layer by vacuum evaporation to obtain a perovskite crystalline silicon stacked cell.

[0085] Example 2

[0086] The present embodiment provides a crystalline silicon cell with edge passivation, wherein the crystalline silicon cell is a cut cell obtained by cutting an N-type solar cell or a P-type solar cell of silicon wafer size, and the cut end surface of the cut cell is covered with a 1 nm thick layer.

[0087] The method for preparing the edge-passivated crystalline silicon cell comprises:

[0088] (I) The structure of a commercial TOPCon cell is a stacked Ag electrode, a silicon nitride film, an aluminum oxide film, a p-type doped silicon layer, a single crystal silicon layer, a silicon oxide film, an n-type polycrystalline silicon layer and a silicon nitride film. A 182×182mm commercial TOPCon cell is cut by laser to obtain 400 small cells of 25×25mm. The four sides of each small cell are produced by laser cutting. Then, a 10% HF solution is used to remove the silicon nitride film on the surface of the n-type polycrystalline silicon layer of each small cell to obtain a cut cell.

[0089] 400 cut batteries are stacked and arranged so that the cut end faces of the cut batteries are located on the same vertical side to obtain three groups of stacked batteries, and then the top surface of the obtained stacked structure is shielded to obtain three groups of shielded stacked batteries 3;

[0090] (II) Se powder 1, GeSe powder 2 and three groups of shielded stacked cells 3 obtained in step (I) are sequentially arranged in a sintering container 4 along one direction, and argon gas is introduced into the sintering container 4, wherein the argon gas flows in a direction from Se powder 1 to the stacked structure;

[0091] (III) The GeSe powder 2 in the sintering container 4 and the first region 5 where the shielded laminated battery 3 is located are heated to 600°C at a heating rate of 40°C / min, and the first region 5 is kept warm while the second region 6 where the Se powder 1 is located is heated to 300°C at a heating rate of 300°C / min, and a mixed gas of hydrogen and argon is introduced while stopping the introduction of argon, wherein the volume concentration of hydrogen in the mixed gas is 10%, and the first region 5 and the second region 6 are kept warm for 1 minute, and after cooling, a shielded laminated battery 3 with a GeSe2 layer deposited on the cut end face is obtained;

[0092] (IV) The shielded stacked cell 3 with a GeSe2 layer deposited on the cut end surface obtained in step (III) is simultaneously subjected to photopassivation and heat treatment for 160 seconds, wherein the photopassivation comprises irradiating the deposited GeSe2 layer with sunlight of a light intensity of 20 times the light intensity, and the temperature of the heat treatment is 500°C, thereby obtaining 400 pieces of crystalline silicon cells with a GeSe2 passivation layer covered on the cut end surface.

[0093] This embodiment also provides a perovskite crystalline silicon stacked cell, and the preparation process of the perovskite crystalline silicon stacked cell includes:

[0094] Using the above-obtained crystalline silicon cell as a substrate, an ITO layer with a thickness of 25 nm is prepared on the surface of the n-type polycrystalline silicon layer of the substrate by magnetron sputtering;

[0095] Then, a layer of nickel oxide (NiOx) with a thickness of 15 nm is sputtered on the ITO layer by magnetron sputtering as a hole transport layer;

[0096] A perovskite light-absorbing layer is then deposited on the NiOx layer, and the deposition process is as follows: 2.8 mmol of cesium iodide, 11.2 mmol of formamidine iodide, 0.07 mmol of phenethylammonium iodide, 5.6 mmol of lead iodide, and 8.4 mmol of lead bromide are weighed and mixed to obtain a mixture, 8 mL of N,N-dimethylformamide and 2 mL of dimethyl sulfoxide are added to the mixture, and the mixture is stirred sufficiently to be completely dissolved, and a precursor solution is formed after filtering; a perovskite film of about 500 nm is prepared as a perovskite light-absorbing layer by a solution method;

[0097] Then, about 25 nm of fullerene (C60) is deposited on the obtained perovskite light-absorbing layer by vacuum evaporation as an electron transport layer.

[0098] Then, a layer of SnO2 with a thickness of 8 nm is deposited on the electron transport layer by atomic layer deposition to reduce the damage to the substrate during the subsequent sputtering process;

[0099] Then, a transparent oxide ITO layer with a thickness of 40 nm is prepared on the SnO2 layer by magnetron sputtering;

[0100] Then, a metal silver electrode with a thickness of 1000 nm is deposited on the transparent oxide ITO layer by vacuum evaporation to obtain a perovskite crystalline silicon stacked cell.

[0101] Example 3

[0102] This embodiment provides a crystalline silicon cell with edge passivation, which is a cut cell obtained by cutting an N-type solar cell or a P-type solar cell of silicon wafer size, and the cut end surface of the cut cell is covered with a 40nm thick layer.

[0103] The method for preparing the edge-passivated crystalline silicon cell comprises:

[0104] (I) The structure of a commercial TOPCon cell is a stacked Ag electrode, a silicon nitride film, an aluminum oxide film, a p-type heavily doped silicon layer, a single crystal silicon layer, a silicon oxide film, an n-type polycrystalline silicon layer and a silicon nitride film. A 182×182mm commercial TOPCon cell is cut by laser to obtain two 25×25mm small cells. The four sides of each small cell are produced by laser cutting. Then, a 10% HF solution is used to remove the silicon nitride film on the surface of the n-type polycrystalline silicon layer of each small cell to obtain a cut cell.

[0105] The top surface of each single cut battery is masked to obtain two masked single batteries;

[0106] (II) Se powder 1, GeSe powder 2 and the shielded single cells obtained in step (I) are sequentially arranged in a sintering container 4 along one direction, and argon gas is introduced into the sintering container 4, wherein the argon gas flows in a direction from Se powder 1 to the stacked structure;

[0107] (III) The GeSe powder 2 in the sintering container 4 and the first region 5 where the shielded single cell is located are heated to 800°C at a heating rate of 60°C / min, and the first region 5 is kept warm while the second region 6 where the Se powder 1 is located is heated to 420°C at a heating rate of 360°C / min, and a mixed gas of hydrogen and argon is introduced while stopping the introduction of argon, wherein the volume concentration of hydrogen in the mixed gas is 5%, and the first region 5 and the second region 6 are kept warm for 20 minutes, and after cooling, a shielded single cell with a GeSe2 layer deposited on the cut end face is obtained;

[0108] (IV) The shielded single cell with a GeSe2 layer deposited on the cut end surface obtained in step (III) is simultaneously subjected to photopassivation and heat treatment for 80 seconds, wherein the photopassivation comprises irradiating the deposited GeSe2 layer with sunlight of a light intensity of 100 times the light intensity, and the temperature of the heat treatment is 200°C, thereby obtaining two crystalline silicon cells with a GeSe2 passivation layer covered on the cut end surface.

[0109] This embodiment also provides a perovskite crystalline silicon stacked cell, and the preparation process of the perovskite crystalline silicon stacked cell includes:

[0110] Using the above-obtained crystalline silicon cell as a substrate, an ITO layer with a thickness of 25 nm is prepared on the surface of the n-type polycrystalline silicon layer of the substrate by magnetron sputtering;

[0111] Then, a layer of nickel oxide (NiOx) with a thickness of 15 nm is sputtered on the ITO layer by magnetron sputtering as a hole transport layer;

[0112] A perovskite light-absorbing layer is then deposited on the NiOx layer, and the deposition process is as follows: 2.8 mmol of cesium iodide, 11.2 mmol of formamidine iodide, 0.07 mmol of phenethylammonium iodide, 5.6 mmol of lead iodide, and 8.4 mmol of lead bromide are weighed and mixed to obtain a mixture, 8 mL of N,N-dimethylformamide and 2 mL of dimethyl sulfoxide are added to the mixture, and the mixture is stirred sufficiently to be completely dissolved, and a precursor solution is formed after filtering; a perovskite film of about 500 nm is prepared as a perovskite light-absorbing layer by a solution method;

[0113] Then, about 25 nm of fullerene (C60) is deposited on the obtained perovskite light-absorbing layer by vacuum evaporation as an electron transport layer.

[0114] Then, a layer of SnO2 with a thickness of 8 nm is deposited on the electron transport layer by atomic layer deposition to reduce the damage to the substrate during the subsequent sputtering process;

[0115] Then, a transparent oxide ITO layer with a thickness of 40 nm is prepared on the SnO2 layer by magnetron sputtering;

[0116] Then, a metal silver electrode with a thickness of 1000 nm is deposited on the transparent oxide ITO layer by vacuum evaporation to obtain a perovskite crystalline silicon stacked cell.

[0117] Example 4

[0118] This embodiment provides a crystalline silicon cell with edge passivation, which is the same as that of the first embodiment except that the thickness of the GeSe2 passivation layer is 20 nm.

[0119] This embodiment also provides a perovskite crystalline silicon stacked cell, and the preparation process of the perovskite crystalline silicon stacked cell is the same as that of Example 1.

[0120] Example 5

[0121] This embodiment provides a crystalline silicon cell with edge passivation, which is the same as that of the first embodiment except that the thickness of the GeSe2 passivation layer is 25 nm.

[0122] This embodiment also provides a perovskite crystalline silicon stacked cell, and the preparation process of the perovskite crystalline silicon stacked cell is the same as that of Example 1.

[0123] Example 6

[0124] This embodiment provides a crystalline silicon cell with edge passivation, which is the same as that of the first embodiment except that the thickness of the GeSe2 passivation layer is 5 nm.

[0125] This embodiment also provides a perovskite crystalline silicon stacked cell, and the preparation process of the perovskite crystalline silicon stacked cell is the same as that of Example 1.

[0126] Example 7

[0127] This embodiment provides a crystalline silicon cell with edge passivation, which is the same as that of the first embodiment except that the thickness of the GeSe2 passivation layer is 30 nm.

[0128] This embodiment also provides a perovskite crystalline silicon stacked cell, and the preparation process of the perovskite crystalline silicon stacked cell is the same as that of Example 1.

[0129] Example 8

[0130] This embodiment provides a crystalline silicon cell with edge passivation, which is the same as that of Embodiment 1 except that the thickness of the GeSe2 passivation layer is 100 nm.

[0131] This embodiment also provides a perovskite crystalline silicon stacked cell, and the preparation process of the perovskite crystalline silicon stacked cell is the same as that of Example 1.

[0132] Example 9

[0133] This embodiment provides a crystalline silicon cell with edge passivation, which is the same as that of the first embodiment except that the thickness of the GeSe2 passivation layer is 0.5 nm.

[0134] This embodiment also provides a perovskite crystalline silicon stacked cell, and the preparation process of the perovskite crystalline silicon stacked cell is the same as that of Example 1.

[0135] Comparative Example 1

[0136] This comparative example provides a crystalline silicon cell, which is the same as Example 1 except that the cut end face of the cell after cutting is not covered by the GeSe2 passivation layer.

[0137] This comparative example also provides a perovskite crystalline silicon stacked cell, and the preparation process of the perovskite crystalline silicon stacked cell is the same as that of Example 1.

[0138] The test environment was controlled at 25°C by a cooling controller, and the crystalline silicon cells and perovskite crystalline silicon stacked cells provided in the above embodiments and comparative examples were tested for photoelectric conversion efficiency (PCE), open circuit voltage (Voc), short circuit current (Jsc) and fill factor (FF) by a solar simulator and an IV tester, wherein the current and voltage were collected by a source meter, and the light intensity of the solar simulator needed to be calibrated by a "standard wafer" (standard performance cell). The test results of the crystalline silicon cells are shown in Table 1, and the test results of the perovskite crystalline silicon stacked cells are shown in Table 2.

[0139] Table 1

[0140] PCE (%) Voc(V) <![CDATA[Jsc(mA·cm -2 )]]> FF(%) Example 1 22.2 0.701 38.87 81.66 Example 2 20.8 0.694 38.1 78.83 Example 3 21.4 0.699 38.12 80.32 Example 4 22.0 0.698 38.75 81.51 Example 5 22.3 0.702 38.94 81.72 Example 6 22.2 0.701 38.91 81.54 Example 7 21.2 0.682 38.74 80.24 Example 8 20.5 0.687 38.21 78.14 Example 9 18.2 0.668 37.11 73.42 Comparative Example 1 16.9 0.661 36.98 69.52

[0141] Table 2

[0142] PCE (%) Voc(V) <![CDATA[Jsc(mA·cm -2 )]]> FF(%) Example 1 29.4 1.87 19.44 80.75 Example 2 27.7 1.86 19.05 77.98 Example 3 28.5 1.87 19.06 80.14 Example 4 29.2 1.87 19.38 80.63 Example 5 29.4 1.87 19.47 80.75 Example 6 29.2 1.87 19.46 80.21 Example 7 28.7 1.85 19.37 79.87 Example 8 27.5 1.86 19.11 77.43 Example 9 24.3 1.84 18.56 71.25 Comparative Example 1 22.3 1.83 18.49 65.73

[0143] From Table 1, we can get:

[0144] (1) The edge-passivated crystalline silicon cells provided in Examples 1 to 7 have higher photoelectric conversion efficiency, higher open circuit voltage, higher short-circuit current and higher fill factor; and the perovskite crystalline silicon stacked cells obtained by preparing a layer of solar top cells on the edge-passivated crystalline silicon cells provided as substrates also have higher photoelectric conversion efficiency, higher open circuit voltage, higher short-circuit current and higher fill factor;

[0145] (2) By comparing Example 1 with Examples 8 and 9, it can be seen that the thickness of the GeSe2 passivation layer in the present invention will affect the performance of the edge-passivated crystalline silicon cell; when the thickness of the GeSe2 passivation layer is too low, the defects caused by cutting cannot be completely passivated, which will lead to lower photoelectric conversion efficiency, lower open circuit voltage, lower short circuit current and lower fill factor of the crystalline silicon cell. Due to the reduced efficiency of the bottom cell, the photoelectric conversion efficiency of the perovskite crystalline silicon stacked cell prepared based on the crystalline silicon cell will be reduced; when the thickness of the GeSe2 passivation layer is too high, the performance of the crystalline silicon cell is not improved, and the preparation time of the preparation method of the crystalline silicon cell is too long, which will not only increase the preparation cost, but also reduce the preparation cost;

[0146] (3) By comparing Example 1 with Comparative Example 1, it can be seen that the crystalline silicon cell provided by the present invention is a cut cell, and the cut end face is covered with a GeSe2 passivation layer. The photogenerated carriers will be confined inside the crystalline silicon cell, preventing the non-radiative recombination of the photogenerated carriers at the cut end face, reducing the charge accumulation at the edge of the crystalline silicon cell, thereby reducing the surface recombination rate of the crystalline silicon cell, and thus improving the photoelectric conversion efficiency of the crystalline silicon cell.

[0147] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention are within the protection scope and disclosure scope of the present invention.

Claims

1. A crystalline silicon cell with edge passivation, characterized in that: The crystalline silicon cell is a cut cell, and the cut end surface of the cut cell is covered with a GeSe2 passivation layer, and the GeSe2 passivation layer is obtained by simultaneously performing photo-passivation and heat treatment on the GeSe2 layer.

2. The crystalline silicon cell according to claim 1, characterized in that: The thickness of the GeSe2 passivation layer is 1-40 nm.

3. A method for preparing a crystalline silicon cell according to claim 1 or 2, characterized in that: The preparation method comprises: After a GeSe2 layer is deposited on the cut end surface of the cut cell, light passivation and heat treatment are simultaneously performed to obtain a crystalline silicon cell with a GeSe2 passivation layer covering the cut end surface.

4. The preparation method according to claim 3, characterized in that: The cut cell is obtained by cutting an N-type solar cell or a P-type solar cell; The N-type solar cell or the P-type solar cell is independently a solar cell of silicon wafer size.

5. The preparation method according to claim 3, characterized in that: Before the deposition, at least two cut batteries are stacked and arranged, and the cut end faces of the cut batteries are located on the same vertical side to obtain a stacked battery, and then the top surface of the obtained stacked structure is shielded to obtain a shielded stacked battery; or, Before the deposition, the top surface of the single cut cell is shielded to obtain a shielded single cell.

6. The preparation method according to claim 3, characterized in that: The deposition method includes chemical vapor deposition, and the precursors used in the chemical vapor deposition include Se powder and GeSe powder; The chemical vapor deposition comprises: Se powder, GeSe powder and shielded stacked cells or shielded single cells are placed in a sintering container, sintered in a protective atmosphere containing a reducing gas, and then cooled to obtain a stacked cell with a GeSe2 layer deposited thereon.

7. The preparation method according to claim 3, characterized in that: The photopassivation includes irradiating the deposited GeSe2 layer with sunlight having a light intensity of 20 to 100 times the light intensity; The temperature of the heat treatment is 200-500°C; The time for the simultaneous photopassivation and heat treatment is 80 to 160 seconds.

8. The preparation method according to claim 3, characterized in that: The preparation method comprises: (I) stacking 2 to 400 cut batteries so that the cut end faces of the cut batteries are located on the same vertical side to obtain a stacked battery, and then shielding the top surface of the obtained stacked structure to obtain a shielded stacked battery; or, Before the deposition, the top surface of the single cut battery is shielded to obtain a shielded single battery; (II) Se powder, GeSe powder and at least one group of shielded stacked cells or shielded single cells obtained in step (I) are sequentially arranged in a sintering container along one direction, and a protective gas is introduced into the sintering container, wherein the protective gas flows in a direction from the Se powder to the stacked structure; (III) The first region where the GeSe powder and the shielded stacked battery or the shielded single battery are located in the sintering container is heated to 600-800°C at a heating rate of 40-60°C / min, and the second region where the Se powder is located is heated to 300-420°C at a heating rate of 300-360°C / min while the first region is kept warm, and a mixed gas of reducing gas and protective gas is introduced while stopping the introduction of protective gas, wherein the volume concentration of reducing gas in the mixed gas is 5-10%, and the first region and the second region are kept warm for 1-20 minutes, and after cooling, a shielded stacked battery or a shielded single battery with a GeSe2 layer deposited on the cut end face is obtained; (IV) The shielded stacked cells or shielded single cells having a GeSe2 layer deposited on the cut end faces obtained in step (III) are simultaneously subjected to photopassivation and heat treatment for 80 to 160 seconds, wherein the photopassivation comprises irradiating the deposited GeSe2 layer with sunlight having a light intensity of 20 to 100 times the light intensity, and the heat treatment temperature is 200 to 500°C, to obtain at least one crystalline silicon cell having a GeSe2 passivation layer covered on the cut end faces.

9. A perovskite crystalline silicon tandem battery, characterized in that: The perovskite crystalline silicon stacked cell comprises the crystalline silicon cell according to claim 1 or 2.

10. A process for preparing the perovskite crystalline silicon tandem battery according to claim 9, characterized in that: The preparation process comprises: The crystalline silicon cell according to claim 1 or 2 is used as a substrate, and a layer of solar top cell is prepared on the substrate to obtain a perovskite crystalline silicon stacked cell.

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