A DPWM modulation method

Abstract

The present application discloses a DPWM modulation method, including the following process: a common mode component V modulated by DPWMA in a single modulation cycle is modulated; c_dpwma Partially replace the common mode component V modulated by SVPWM c_svpwm ; Fit the three-phase sine wave with the replaced common-mode component waveform to obtain a DPWM modulated wave. Alternatively, in the entire working cycle including multiple modulation cycles, SVPWM modulation and DPWMA modulation are respectively used for at least one pair of adjacent modulation cycles to obtain a DPWM modulated wave. The beneficial effects of the present application: it retains the advantage of high DPWMA modulation efficiency and combines the advantage of small bus half-voltage fluctuation of SVPWM modulation. In the application of inverter engineering, it can well realize the heat distribution, and will not cause the inductor temperature to be too high due to switching loss, nor will it cause the capacitor temperature to be too high due to large half-bus voltage fluctuation.

Description

Technical Field

[0001] The present application relates to the field of renewable energy power generation, and in particular to a DPWM modulation method. Background Art

[0002] In the inverter control process of renewable energy power generation, the commonly used PWM modulation methods are mainly divided into SPWM, SVPWM and DPWM, among which DPWM is further divided into DPWMMIN, DPWMMAX, DPWM0, DPWM1, DPWM2, DPWM3, DPWMA and DPWMB according to different common mode voltages.

[0003] At present, SVPWM and DPWMA modulation modes are most widely used. However, in actual applications, SVPWM modulation brings about smaller bus half-voltage fluctuations, but the efficiency is slightly lower than that of DPWMA; DPWMA modulation has higher efficiency, but brings about larger bus half-voltage fluctuations, especially under the trend of smaller bus capacitance of current products, the impact of bus half-voltage fluctuations is getting bigger and bigger, such as higher device temperature rise, higher output current distortion rate, etc. Summary of the invention

[0004] One of the objectives of the present application is to provide a DPWM modulation method that can solve at least one of the defects in the above-mentioned background technology.

[0005] In order to achieve at least one of the above purposes, the technical solution adopted by the present application is: a DPWM modulation method, comprising the following process: respectively calculating the common mode component V of the three-phase sine wave under the SVPWM and DPWMA modulation modes c_svpwm and V c_dpwma , and obtain the middle value V of the three-phase sine wave in real time middle ; Based on the key area of ​​DPWMA modulation wave and the common mode component V in this area c_dpwma With the intermediate value V middle The comparison relationship is that the common mode component V in at least part of the key area of ​​the DPWMA modulation wave c_dpwma Replaced by the common mode component V at the corresponding position c_svpwm ; The common mode component of the three-phase sine wave and the DPWMA modulation wave key area is replaced by waveform fitting to obtain the DPWM modulation wave.

[0006] Preferably, the key areas of the DPWMA modulation wave include the peak clamping area at the maximum voltage position, the valley clamping area at the minimum voltage position, and the zero-crossing clamping area at the zero voltage position; c_dpwma When replacing, it is suitable to clamp at least part of the common mode component V in the three clamping regions c_dpwma Replaced by the common mode component V at the corresponding positionc_svpwm .

[0007] Preferably, for the common mode component V in the zero-crossing clamping region c_dpwma , replaced by the common mode component V at the corresponding position c_svpwm .

[0008] Preferably, for the common mode component V in the peak clamping region c_dpwma , if the common mode component V c_dpwma ≥V middle , the common mode component V in the peak clamping region c_dpwma Replaced by the common mode component V at the corresponding position c_svpwm , otherwise remain unchanged.

[0009] Preferably, the common mode component V c_dpwma When replacing, for the DPWMA modulation wave with no wave interval, the common mode component V c_dpwma The judgment is based on V c_dpwma ≥V middle +V delta ; Among them, V delta Represents the variable used to adjust the proportion of the non-wave interval in a single modulation cycle.

[0010] Preferably, for the common mode component V in the valley clamping region c_dpwma , if the common mode component V c_dpwma ≤V middle , the common mode component V in the valley clamping region c_dpwma Replaced by the common mode component V at the corresponding position c_svpwm , otherwise remain unchanged.

[0011] Preferably, the common mode component V c_dpwma When replacing, for the DPWMA modulation wave with no wave interval, the common mode component V c_dpwma The judgment is based on V c_dpwma ≤V middle -V delta ; Among them, V delta Represents the variable used to adjust the proportion of the non-wave interval in a single modulation cycle.

[0012] A DPWM modulation method includes the following process: in a whole working cycle including a plurality of modulation cycles, SVPWM modulation and DPWMA modulation are respectively adopted for at least one pair of adjacent modulation cycles, thereby obtaining a DPWM modulation wave.

[0013] Preferably, the continuous time of SVPWM modulation and DPWMA modulation is at least one modulation cycle.

[0014] Preferably, SVPWM modulation and DPWMA modulation are suitable for switching at a zero-crossing position.

[0015] Compared with the prior art, the beneficial effects of this application are:

[0016] Compared with the traditional modulation method, the present application not only retains the advantage of high efficiency of DPWMA modulation, but also combines the advantage of small bus half-voltage fluctuation of SVPWM modulation. In inverter engineering applications, especially in inverters with small bus capacitance values, it can well achieve heat distribution, and will not cause excessive inductor temperature due to switching loss, nor will it cause excessive capacitor temperature due to large half-bus voltage fluctuations. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a waveform diagram of the traditional three-phase modulation wave using SVPWM modulation.

[0018] Figure 2 for Figure 1 Schematic diagram of the waveform of the single-phase modulation wave.

[0019] Figure 3 Based on Figure 1 Schematic diagram of the waveform of the common-mode component of the three-phase modulation wave shown.

[0020] Figure 4 This is a waveform diagram of a three-phase modulation wave using traditional DPWMA modulation.

[0021] Figure 5 for Figure 4 Schematic diagram of the waveform of the single-phase modulation wave.

[0022] Figure 6 Based on Figure 4 Schematic diagram of the waveform of the common-mode component of the three-phase modulation wave shown.

[0023] Figure 7 This is a flow chart of the first embodiment of DPWM modulation in the present application.

[0024] Figure 8 This is a waveform diagram of a three-phase DPWM modulation wave obtained by using Example 1 in this application.

[0025] Fig. 9 For this application Figure 8 Schematic diagram of the waveform of the single-phase DPWM modulation wave.

[0026] Fig.10 This application is based on Figure 8 Schematic diagram of the waveform of the common-mode component of the three-phase modulation wave shown.

[0027] Fig.11This is a flow chart of the second embodiment of DPWM modulation in the present application. DETAILED DESCRIPTION

[0028] Below, the present application is further described in conjunction with specific implementation methods. It should be noted that in the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms should not be understood as necessarily being directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0029] In the description of the present application, it should be noted that directional words, such as the terms "center", "lateral", "longitudinal", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., indicating directions and positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of narrating the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and cannot be understood as limiting the specific scope of protection of the present application.

[0030] It should be noted that the terms "first", "second", etc. in the description and claims of the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0031] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be connected, detachably connected, or integrated; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0033] The terms "including" and "having" and any variations thereof in the specification and claims of the present application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or apparatuses.

[0034] In order to facilitate the understanding of this solution, the specific characteristics of the SVPWM and DPWMA modulation methods can be briefly described below in conjunction with the accompanying drawings.

[0035] like Figure 1 As shown in the figure, it is a waveform diagram of the three-phase modulation wave under the SVPWM modulation mode. In order to facilitate waveform analysis, the structure of the single-phase modulation wave can be analyzed, that is, Figure 2 As shown in the figure, it can be seen from the waveform of the SVPWM modulation mode that the duration of the peak and valley of the waveform is basically consistent with the duration of the buck-boost, which makes the bus half-voltage fluctuation caused by the SVPWM modulation mode smaller.

[0036] like Figure 4 As shown in the figure, it is a waveform diagram of the three-phase modulation wave under the DPWMA modulation mode. In order to facilitate waveform analysis, the structure of the single-phase modulation wave can be analyzed, that is, Figure 5 As shown in the waveform of the DPWMA modulation method, it can be seen that the duration of the peak and valley values ​​is short, which makes the bus half-voltage fluctuation caused by the DPWMA modulation method larger. The larger bus half-voltage fluctuation will lead to an increase in the temperature rise of the capacitor components in the circuit.

[0037] like Figure 3 As shown in FIG. 1 , a waveform diagram of the common-mode component of the three-phase modulation wave of the SVPWM modulation method is shown. It can be seen from the common-mode waveform corresponding to the SVPWM modulation method that the waveform is in the form of a triangle wave as a whole, which makes the efficiency of the common-mode waveform low. The low efficiency will lead to increased switching losses, thereby increasing the temperature of the inductor in the circuit.

[0038] like Figure 6 As shown, it is a waveform diagram of the common mode component of the three-phase modulation wave of the DPWMA modulation mode. It can be seen from the common mode waveform corresponding to the DPWMA modulation mode that the peak area and the valley area of ​​the waveform account for a large proportion, making the common mode waveform more efficient.

[0039] Based on the above analysis results, the core idea of ​​the technical solution of this application is to combine the low bus half-voltage fluctuation characteristics of the SVPWM modulation method and the high efficiency characteristics of the DPWMA modulation method; in order to achieve the combination of the two, a DPWM modulation method is proposed.

[0040] Embodiment 1:

[0041] A DPWM modulation method, such as 7 and Figure 8 As shown, one preferred embodiment includes the following process: respectively calculating the common mode component V of the three-phase sine wave under the SVPWM and DPWMA modulation modes c_svpwm and V c_dpwma , and obtain the middle value V of the three-phase sine wave in real time middle Based on the key area of ​​DPWMA modulation wave and the common mode component V in this area c_dpwma With the intermediate value V middle The comparison relationship is that the common mode component V in at least part of the key area of ​​the DPWMA modulation wave c_dpwma Replaced by the common mode component V at the corresponding position c_svpwm The DPWM modulation wave is obtained by waveform fitting the common mode component of the three-phase sine wave and the key area of ​​the DPWMA modulation wave. It should be known that the middle value of the three-phase sine wave is the middle value of the three waveform voltages corresponding to each other in the three-phase circuit.

[0042] It can be understood that the core idea of ​​this embodiment is to use the common-mode waveform under the DPWMA modulation mode as the basis, and to replace the disadvantageous part of the common-mode waveform under the DPWMA modulation mode with the advantage part of the common-mode waveform under the SVPWM modulation mode, so as to achieve complementary advantages between the two. Therefore, this application not only retains the advantage of high DPWMA modulation efficiency, but also combines the advantage of small bus half-voltage fluctuation of SVPWM modulation. In the application of inverter engineering, especially in inverters with small bus capacitance values, it can well achieve heat distribution, and will not cause the inductor temperature to be too high due to switching loss, nor will it cause the capacitor temperature to be too high due to large bus half-voltage fluctuation. At the same time, after the bus half-voltage fluctuation is reduced, the total harmonic distortion (THD) of the inverter output current can also be reduced.

[0043] Specifically, after completing the complementary advantages of the common-mode components in the key area of ​​the DPWMA modulation wave, this embodiment can fit the complementary waveform with the three-phase sine wave to obtain the required DPWM modulation wave. The DPWM modulation wave has the advantages of high DPWMA modulation efficiency and small SVPWM modulation bus half-voltage fluctuation. At the same time, the waveform in the non-critical area still maintains a sinusoidal smooth waveform, which can further reduce current distortion.

[0044] Specifically, the implementation method of this embodiment is partial replacement of a single modulation cycle. The so-called partial replacement of a single modulation cycle is to consider the real-time efficiency of the modulation wave and the bus half-voltage fluctuation. The entire working cycle includes multiple modulation cycles, and the common mode component V of some key areas in each modulation cycle is replaced. c_dpwma Replace it with the common mode component V at the corresponding position c_svpwm That is, in a single modulation cycle, the common mode component V c_dpwma and V c_svpwm The waveform is advantageously fitted to obtain a new waveform, which has the characteristics of high real-time efficiency and small bus half-voltage fluctuation, so that the capacitor temperature and inductor temperature in the circuit are always maintained at a low level.

[0045] It should be known that the key area of ​​the modulation wave is the area that has the greatest impact on the waveform structure of the common-mode component of the modulation wave, that is, the area that can have a greater impact on the efficiency corresponding to the modulation wave and the bus half-voltage fluctuation. There are multiple key areas in a single modulation cycle, such as the peak position, trough position, zero-crossing position of the modulation wave, and the intersection position of the multi-phase modulation wave. In this embodiment, the key areas at which specific positions need to be replaced can be determined according to the actual needs of technicians in this field.

[0046] In this embodiment, combined with the above analysis process of SVPWM modulation wave and DPWMA modulation wave, it can be known that there are three key areas that have a greater impact on the common mode component waveform of this embodiment, namely the peak clamping area at the maximum voltage position, the valley clamping area at the minimum voltage position, and the zero-crossing clamping area at the zero voltage position. c_dpwma When replacing, at least part of the common mode component V corresponding to the three clamping regions of the DWPMA modulation wave can be replaced according to the actual waveform state. c_dpwma Replaced by the common mode component V at the corresponding position c_svpwm For ease of understanding, the specific process of replacing the common-mode components in the three clamping intervals may be described in detail below.

[0047] Specifically, first, the common mode component V c_dpwma The position of the common mode component V c_dpwma In the zero-crossing clamping area, Figure 3 and Figure 6 It can be seen that the common mode component V c_svpwm The slope of the waveform relative to the common mode component V c_dpwma The waveform slope is relatively slow, so the common mode component V in the zero-crossing clamping area can be directly c_dpwma Directly replace with the common mode component V at the corresponding position c_svpwm .

[0048] If the common-mode component V c_dpwma In the peak clamping region, the common mode component V c_dpwma With the intermediate value V middle For comparison. If the common mode component V c_dpwma ≥V middle , indicating that the common mode component V c_dpwma This may cause the current distortion to increase, so it is necessary to adjust the common mode component V in the clamping area. c_dpwma Therefore, the common mode component V in the peak clamping area can be c_dpwma Replaced by the common mode component V at the corresponding position c_svpwm , otherwise remain unchanged.

[0049] If the common-mode component V c_dpwma In the valley clamping region, the common mode component V c_dpwma With the intermediate value V middle For comparison. If the common mode component V c_dpwma ≤V middle , indicating that the common mode component V c_dpwma This may cause the current distortion to increase, so it is necessary to adjust the common mode component V c_dpwma Therefore, the common mode component V in the peak clamping area can be c_dpwma Replaced by the common mode component V at the corresponding position c_svpwm , otherwise remain unchanged.

[0050] It should be noted that in actual engineering applications, the modulation wave may also have a non-wave interval. Therefore, for the DPWMA modulation wave with a non-wave interval, the common mode component V c_dpwma When judging the replacement of c_dpwma ≥V middle +V delta To make a judgment; in the valley clamping area, the common mode component V c_dpwma When judging the replacement of c_dpwma ≤V middle -V delta To make a judgment. Among them, V delta Represents a variable used to adjust the proportion of the non-wave interval in a single modulation cycle. By adjusting V deltaThe size of can change the proportion of the non-wave interval in a modulation cycle to the entire modulation cycle.

[0051] It should be known that the three-phase sine wave can be represented by V A 、V B and V C To express, for the common mode component V c_dpwma The local common-mode components that are replaced in the three clamping regions can be obtained by V c_newdpwm Then V c_newdpwm According to the above judgment process, the common mode component V at the corresponding position can be taken c_svpwm , that is, V c_newdpwm =V c_svpwm ; It can also remain unchanged, that is, V c_newdpwm =V c_dpwma Then we can make V A1 =V A +V c_newdpwm , V B1 =V B +V c_newdpwm , V C1 =V C +V c_newdpwm ; then V A1 、V B1 and V C1 That is the DPWM modulation wave required by this application.

[0052] Specifically, Figure 8 and Fig. 9 As shown, the DPWM modulation wave obtained in this embodiment is based on a sine wave as a whole, and the fitting waveform of the sine wave and the SVPWM modulation wave is adopted in the zero-crossing clamping area of ​​the DPWM modulation wave; in the peak clamping area and the valley clamping area of ​​the DPWM modulation wave, according to the comparison result of the common-mode component of the DPWMA modulation wave and the set threshold, the fitting waveform of the sine wave and the SVPWM modulation wave is adopted, or the fitting waveform of the sine wave and the DPWM modulation wave is adopted.

[0053] For ease of understanding, the DPWM modulation wave obtained in this application can be specifically analyzed below. In order to facilitate the analysis of the waveform of the DPWM modulation wave, the waveform of the single-phase DPWM modulation wave can be analyzed, that is, Fig. 9 As shown. Fig. 9 It can be seen from the waveform shown that after the complementary replacement of the SVPWM modulation wave and the DPWMA modulation wave, the waveform of the DPWM modulation wave has the constant characteristics of the DPWMA modulation wave at the peak and trough positions, and there is still a constant area with higher voltage near the peak and trough, which makes it have the characteristics of long duration of the SVPWM modulation wave, thereby ensuring that the bus half-voltage fluctuation of the DPWM modulation wave is low.

[0054] At the same time, if Fig.10 As shown, it is a waveform diagram of the common-mode component corresponding to the three-phase DPWM modulation wave of the present application. It can be seen from the figure that by replacing the waveform of the common-mode component of the DPWMA modulation wave at the zero-crossing position, it can be ensured that the common-mode component waveform corresponding to the DPWM modulation wave is divided into two upper and lower waveform structures with higher voltage amplitudes at the zero-crossing position, that is, the low voltage amplitude area of ​​the common-mode component is concentrated at the zero-crossing position and the duration is short, thereby ensuring that the DPWM modulation wave of the present application has a higher efficiency.

[0055] Embodiment 2:

[0056] A DPWM modulation method, such as Fig.11 As shown, one of the preferred embodiments includes the following process: in the entire working cycle including multiple modulation cycles, SVPWM modulation and DPWMA modulation are respectively used for at least one pair of adjacent modulation cycles to obtain a DPWM modulation wave.

[0057] It can be understood that, compared with the situation of considering a single modulation cycle in the first embodiment, the present embodiment is considered from the perspective of the entire working cycle. That is, in the entire working cycle including multiple modulation cycles, SVPWM modulation and DPWMA modulation can be respectively adopted according to the different modulation cycles. For the convenience of understanding, it can be considered from the perspective of device heating. When SVPWM modulation is adopted in the stage of the working cycle with a duration of at least one modulation cycle, the low efficiency in this stage will lead to an increase in switching loss in the circuit, thereby increasing the temperature of the inductor in the circuit; at the same time, the bus half-voltage fluctuation is low in this stage, so that the operation of the capacitor in the circuit is stable, and the temperature generated by the capacitor is low. Then, in order to reduce the temperature of the inductor, the DPWMA modulation method can be adopted in the next stage. In this stage, the high efficiency of DPWMA modulation can reduce the switching loss, thereby realizing the cooling of the inductor in the circuit; but at the same time, the temperature rise of the capacitor will be aggravated due to the increase in bus half-voltage fluctuation. Therefore, in the entire working cycle, the alternation of SVPWM modulation and DPWMA modulation can ensure that both the inductor and the capacitor are below the specified temperature threshold. At the same time, the efficiency of this embodiment in the entire working cycle is higher than that of using only SVPWM modulation, and the bus half-voltage fluctuation is lower than that of using only DPWMA modulation.

[0058] It should be known that the continuous time of SVPWM modulation and DPWMA modulation is at least one modulation cycle. For example, SVPWM modulation can be switched from three modulation cycles to two modulation cycles after DPWMA modulation. The specific continuous time of SVPWM modulation and DPWMA modulation and the number of alternating switches can be determined according to the specific heating conditions of the relevant components in the circuit.

[0059] In this embodiment, when switching between SVPWM modulation and DPWMA modulation, the switching location can be any position of the waveform, such as a peak, a zero crossing point, or a trough position. Figure 1 and Figure 4 As can be seen from the waveform diagram shown, the common mode voltages of the SVPWM modulation wave and the DPWMA modulation wave are consistent at the zero-crossing position. Therefore, when switching the modulation mode in non-same cycles, the present embodiment can select to switch between DPWMA modulation and SVPWM modulation at the zero-crossing position.

[0060] The above describes the basic principles, main features and advantages of the present application. Those skilled in the art should understand that the present application is not limited by the above embodiments, and the above embodiments and the specification only describe the principles of the present application. The present application may have various changes and improvements without departing from the spirit and scope of the present application, and these changes and improvements fall within the scope of the present application for which protection is sought. The scope of protection claimed by the present application is defined by the attached claims and their equivalents.

Claims

1. A DPWM modulation method, characterized in that: The process includes the following: Calculate the common mode component V of the three-phase sine wave under SVPWM and DPWMA modulation modes respectively c_svpwm and V c_dpwma , and obtain the middle value V of the three-phase sine wave in real time middle ; Based on the key area of ​​DPWMA modulation wave and the common mode component V in this area c_dpwma With the intermediate value V middle The comparison relationship is that the common mode component V in at least part of the key area of ​​the DPWMA modulation wave c_dpwma Replaced by the common mode component V at the corresponding position c_svpwm ; The DPWM modulation wave is obtained by waveform fitting the common mode component that replaces the key area of ​​the three-phase sine wave with the DPWMA modulation wave.

2. The DPWM modulation method according to claim 1, characterized in that: The key areas of the DPWMA modulation wave include the peak clamping area at the maximum voltage position, the valley clamping area at the minimum voltage position, and the zero-crossing clamping area at the zero voltage position.

3. The DPWM modulation method according to claim 2, characterized in that: For the common mode component V in the zero-crossing clamping region c_dpwma , replaced by the common mode component V at the corresponding position c_svpwm .

4. The DPWM modulation method according to claim 2, characterized in that: For the common mode component V in the peak clamping region c_dpwma , if the common mode component V c_dpwma ≥V middle , the common mode component V in the peak clamping region c_dpwma Replaced by the common mode component V at the corresponding position c_svpwm , otherwise remain unchanged.

5. The DPWM modulation method according to claim 4, characterized in that: The common mode component V c_dpwma When replacing, for the DPWMA modulation wave with no wave interval, the common mode component V c_dpwma The judgment is based on V c_dpwma ≥V middle +V delta ; Among them, V delta Represents the variable used to adjust the proportion of the non-wave interval in a single modulation cycle.

6. The DPWM modulation method according to claim 2, characterized in that: For the common mode component V in the valley clamping region c_dpwma , if the common mode component V c_dpwma ≤V middle , the common mode component V in the valley clamping region c_dpwma Replaced by the common mode component V at the corresponding position c_svpwm , otherwise remain unchanged.

7. The DPWM modulation method according to claim 6, characterized in that: The common mode component V c_dpwma When replacing, for the DPWMA modulation wave with no wave interval, the common mode component V c_dpwma The judgment is based on V c_dpwma ≤V middle -V delta ; Among them, V delta Represents the variable used to adjust the proportion of the non-wave interval in a single modulation cycle.

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