A sampling and holding amplifier, a high-speed analog-to-digital converter, and an electronic device

Abstract

The present application provides a sample-and-hold amplifier, a high-speed analog-to-digital converter, and an electronic device. The sample-and-hold amplifier, the high-speed analog-to-digital converter, and the electronic device provided by the present application are provided with a first-stage non-Foster circuit and a second-stage non-Foster circuit in the sample-and-hold amplifier. The first-stage non-Foster circuit and the second-stage non-Foster circuit use negative capacitance to offset the internal parasitic capacitance, so that the nonlinear distortion caused by the parasitic capacitance can be reduced and the linearity of the sample-and-hold amplifier can be improved. In addition, the first-stage non-Foster circuit focuses on providing preliminary gain and parasitic capacitance compensation to ensure that the circuit can effectively process the input signal and reduce the impact of non-dominant poles on the overall performance. The second-stage non-Foster circuit further optimizes the gain and stability, so that the sample-and-hold circuit as a whole can achieve faster stability.

Description

Technical Field

[0001] The present application relates to the technical field of electronic appliances, and in particular to a sample-and-hold amplifier, a high-speed analog-to-digital converter and an electronic device. Background Art

[0002] As the demand for higher data rates and larger data bandwidths continues to rise in areas such as mobile communications, fiber-optic communications, and wireless networks, high-speed analog-to-digital converters (ADCs) play a vital role in meeting the growing demand for data bandwidth. They can quickly convert analog signals into high-precision digital signals, thereby supporting high-speed data transmission, real-time signal processing, and complex modulation and demodulation processes.

[0003] In order to achieve multi-GS / s sampling rates, various time-interleaved structures are used to improve the speed and efficiency of the sub-ADCs. However, when further improving performance, the mismatch between channels becomes a key issue. To address this issue, various types of sample-and-hold amplifiers are used in high-speed analog-to-digital converters. However, existing sample-and-hold amplifiers have linear limitations that seriously affect the overall performance of the analog-to-digital converter. Summary of the invention

[0004] In view of this, the present application provides a sample-and-hold amplifier, a high-speed analog-to-digital converter and an electronic device, so as to enable the sample-and-hold amplifier to achieve better linearity and faster stability, thereby improving the overall performance of the high-speed analog-to-digital converter.

[0005] Specifically, the present application is implemented through the following technical solutions:

[0006] In a first aspect, the present application provides a sample-and-hold amplifier, the sample-and-hold amplifier comprising a cascaded filter capacitor, a first-stage non-Foster circuit, a second-stage non-Foster circuit and an output circuit, wherein:

[0007] The input end of the filter capacitor is also connected to the output end of the output circuit through a first control switch;

[0008] The first-level non-Foster circuit includes an equivalent tri-state gate and a first equivalent negative capacitor; wherein the enable control terminal of the equivalent tri-state gate is connected to a voltage source, the input terminal of the equivalent tri-state gate is connected to the first terminal of the first equivalent negative capacitor to form the input terminal of the first-level non-Foster circuit; the output terminal of the equivalent tri-state gate forms the output terminal of the first-level non-Foster circuit; the second terminal of the first equivalent negative capacitor is grounded;

[0009] The second-level non-Foster circuit comprises a first equivalent NOT gate and a second equivalent negative capacitor; wherein the input end of the first equivalent NOT gate and the first end of the second equivalent negative capacitor are connected to form the input end of the second-level non-Foster circuit; the output end of the first equivalent NOT gate forms the output end of the second-level non-Foster circuit; the second end of the second equivalent negative capacitor is grounded;

[0010] The output circuit comprises a second equivalent NOT gate and a load capacitor; wherein the input end of the second equivalent NOT gate constitutes the input end of the output circuit; the output end of the second equivalent NOT gate is connected to the first end of the load capacitor to constitute the output end of the output circuit; the second end of the load capacitor is grounded;

[0011] The first-stage non-Foster circuit and the second-stage non-Foster circuit offset internal parasitic capacitance through equivalent negative capacitance to obtain better linearity and faster stability.

[0012] A second aspect of the present application provides a high-speed analog-to-digital converter, which includes at least one sample-and-hold amplifier provided in the first aspect of the present application.

[0013] A third aspect of the present application provides an electronic device, comprising a high-speed analog-to-digital converter as described in any one of the second aspect of the present application.

[0014] The sample-and-hold amplifier, high-speed analog-to-digital converter, and electronic device provided by the present application are provided with a first-stage non-Foster circuit and a second-stage non-Foster circuit in the sample-and-hold amplifier. The first-stage non-Foster circuit and the second-stage non-Foster circuit use an equivalent negative capacitor to offset the internal parasitic capacitance, so that the nonlinear distortion caused by the parasitic capacitance can be reduced and the linearity of the sample-and-hold amplifier can be improved. In addition, the design of the first-stage non-Foster circuit focuses on providing preliminary gain and parasitic capacitance compensation to ensure that the circuit can effectively process the input signal and reduce the impact of the non-dominant pole on the overall performance. The second-stage non-Foster circuit further optimizes the gain and stability, so that the sample-and-hold circuit as a whole achieves faster stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A circuit diagram of a sample-and-hold amplifier embodiment 1 provided in the present application;

[0016] Figure 2 A performance diagram of a sample-and-hold amplifier shown in an exemplary embodiment of the present application;

[0017] Figure 3 A circuit diagram of a sample-and-hold amplifier according to an exemplary embodiment of the present application;

[0018] Figure 4 A circuit diagram of a tri-state gate shown as an exemplary embodiment of the present application;

[0019] Figure 5 A circuit schematic diagram of a two-stage amplifier with a non-Foster circuit according to an exemplary embodiment of the present application;

[0020] Figure 6 for Figure 5 A curve diagram showing the variation of equivalent capacitance values ​​of two feedback capacitors of the non-Foster circuit shown;

[0021] Figure 7 A test result diagram of a sample-and-hold amplifier according to an exemplary embodiment of the present application;

[0022] Figure 8 A transient response diagram of a sample-and-hold amplifier shown in an exemplary embodiment of the present application;

[0023] Fig. 9 A circuit diagram of a first embodiment of a high-speed analog-to-digital converter provided in the present application;

[0024] Fig.10 A circuit diagram of an input buffer is shown as an exemplary embodiment of the present application.

[0025] Description of reference numerals:

[0026] 1: First level non-Foster circuit;

[0027] 2: Second level non-Foster circuit;

[0028] 3: Output circuit;

[0029] CS: filter capacitor;

[0030] K1: first control switch;

[0031] T1: equivalent three-state gate;

[0032] CN1: first equivalent negative capacitance;

[0033] N1: first equivalent NOT gate;

[0034] CN2: second equivalent negative capacitance;

[0035] N2: the second equivalent NOT gate;

[0036] CL: load capacitance;

[0037] T11: the first three-state gate;

[0038] T12: second three-state gate;

[0039] C1: first capacitor;

[0040] C2: second capacitor;

[0041] K2: second control switch;

[0042] M1: the first MOS tube;

[0043] M2: the second MOS tube;

[0044] K3: the third control switch;

[0045] N11: first NOT gate;

[0046] N12: the second NOT gate;

[0047] C3: the third capacitor;

[0048] C4: fourth capacitor;

[0049] N21: the third NOT gate;

[0050] N22: the fourth NOT gate;

[0051] CF: feedback capacitor;

[0052] 91: Sample and Hold Amplifier

[0053] 92: Input buffer

[0054] 93: Sub-Analog-to-Digital Converter

[0055] R1: first resistor;

[0056] R2: second resistor;

[0057] C5: fifth capacitor;

[0058] C6: sixth capacitor;

[0059] M3: the third MOS tube;

[0060] M4: the fourth MOS tube;

[0061] M5: the fifth MOS tube;

[0062] M6: the sixth MOS tube;

[0063] R3: the third resistor;

[0064] R4: the fourth resistor. DETAILED DESCRIPTION

[0065] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0066] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items.

[0067] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0068] High-speed Analog-to-Digital Converters (ADCs) play a vital role in meeting the growing data bandwidth requirements of modern communication systems. In order to achieve high sampling rates, various time-interleaved structures have emerged to improve the speed and efficiency of sub-ADCs. However, without a track-and-hold amplifier (THA), if the number of sub-ADCs is further increased, the SFDR (Spurious-Free Dynamic Range) of the high-speed ADC will be significantly reduced due to bandwidth mismatch and time offset between channels.

[0069] In order to solve this problem, a sample-and-hold amplifier is provided in a high-speed analog-to-digital converter. However, the conventional sample-and-hold amplifier has a limitation in linearity.

[0070] The sampling and holding amplifier provided in the present application breaks the trade-off between loop gain and phase margin of the traditional sampling and protection amplifier by introducing negative capacitance, thereby achieving sufficient loop gain and rapid stabilization.

[0071] Specifically, the parasitic capacitance of the traditional sample-and-hold amplifier limits the non-dominant pole, reducing the balanced loop gain and stabilization speed. Furthermore, the parasitic capacitance inside the sample-and-hold amplifier can be offset by introducing negative capacitance, thereby pushing the non-dominant pole to a higher frequency to obtain better loop gain and faster stability (obtaining better linearity and faster stability).

[0072] The sampling and holding amplifier provided by the present application pushes the non-dominant pole away through a non-Foster circuit and adjusts the feedback factor only through a capacitor without increasing additional power consumption.

[0073] Specific embodiments are given below to introduce the technical solution of the present application in detail.

[0074] Figure 1 This is a circuit diagram of the first embodiment of the sampling and holding amplifier provided in this application. Please refer to Figure 1 The sample-and-hold amplifier provided in this embodiment may include a cascaded filter capacitor CS, a first-stage non-Foster circuit 1, a second-stage non-Foster circuit 2 and an output circuit 3, wherein:

[0075] The input end of the filter capacitor CS is also connected to the output end of the output circuit 3 through the first control switch K1;

[0076] The first-stage non-Foster circuit 1 comprises an equivalent tri-state gate T1 and a first equivalent negative capacitor CN1; wherein the enable control terminal of the equivalent tri-state gate T1 is connected to a voltage source, the input terminal of the equivalent tri-state gate T1 is connected to the first terminal of the first equivalent negative capacitor CN1 to form the input terminal of the first-stage non-Foster circuit 1; the output terminal of the equivalent tri-state gate T1 forms the output terminal of the first-stage non-Foster circuit 1; the second terminal of the first equivalent negative capacitor CN1 is grounded;

[0077] The second-stage non-Foster circuit 2 includes a first equivalent NOT gate N1 and a second equivalent negative capacitor CN2; wherein the input end of the first equivalent NOT gate N1 and the first end of the second equivalent negative capacitor CN2 are connected to form the input end of the second-stage non-Foster circuit 2; the output end of the first equivalent NOT gate N1 forms the output end of the second-stage non-Foster circuit 2; the second end of the second equivalent negative capacitor CN2 is grounded;

[0078] The output circuit 3 comprises a second equivalent NOT gate N2 and a load capacitor CL; wherein the input end of the second equivalent NOT gate N2 constitutes the input end of the output circuit 3; the output end of the second equivalent NOT gate N2 is connected to the first end of the load capacitor CL to constitute the output end of the output circuit 3; the second end of the load capacitor CL is grounded;

[0079] The first-stage non-Foster circuit 1 and the second-stage non-Foster circuit 2 offset internal parasitic capacitances through equivalent negative capacitances to obtain better linearity and faster stability.

[0080] Specifically, the first-stage non-Foster circuit 1 offsets the internal parasitic capacitance through the first equivalent negative capacitor CN1, and the second-stage non-Foster circuit 2 offsets the internal parasitic capacitance through the second equivalent negative capacitor CN2.

[0081] For details, please refer to Figure 1 The output end of the filter capacitor CS is respectively connected to the first end of the first equivalent negative capacitor CN1 and the input end of the equivalent three-state gate T1, the first end of the first equivalent negative capacitor CN1 is grounded, the enable end of the equivalent three-state gate T1 is connected to the voltage source, the output end of the equivalent three-state gate T1 is respectively connected to the first end of the second equivalent negative capacitor CN2 and the input end of the first equivalent NOT gate N1, the output end of the first equivalent NOT gate N1 is connected to the input and output of the second equivalent NOT gate N2, the output end of the second equivalent NOT gate N2 is respectively connected to the other end of the first control switch K1 and the first end of the load capacitor CL, the second end of the load capacitor CL is grounded, and the first control switch K1 is connected between the input end of the filter capacitor CS and the first end of the load capacitor CL.

[0082] Specifically, the equivalent three-state gate T1 is a logic circuit, which is a logic circuit having three states: high level, low level and high impedance.

[0083] It should be noted that the first equivalent negative capacitor CN1 can offset the parasitic capacitance inside the first-stage non-Foster circuit 1, thereby pushing the non-dominant pole of the first-stage non-Foster circuit 1 away and improving the phase margin and stability of the circuit.

[0084] For further information, please refer to Figure 1 The equivalent NOT gate is a logic circuit whose function is to invert the logic value of the input signal. For example, in one embodiment, if the input signal of the second-stage non-Foster circuit 2 is a high level, then after the input signal is inverted by the first equivalent NOT gate N1, the output signal of the second-stage non-Foster circuit 2 will become a low level.

[0085] It should be noted that the parasitic capacitance inside the second-stage non-Foster circuit 2 can be offset by the second equivalent negative capacitor CN2, thereby improving the phase margin and stability of the circuit.

[0086] Specifically, in the design of the amplifier, parasitic capacitance is an unavoidable factor, which will introduce additional poles in the amplifier. The pole refers to the frequency point in the transfer function of the amplifier that makes the gain drop to zero or close to zero. These poles will reduce the bandwidth of the amplifier, resulting in a decrease in the performance of the amplifier. Non-dominant poles refer to those poles that have a smaller impact on the overall circuit, but when the non-dominant poles are close to the bandwidth range of the amplifier, they will affect the phase margin and stability of the circuit. In the present application, a first equivalent negative capacitor CN1 and a second equivalent negative capacitor CN2 are introduced into the first-stage non-Foster circuit 1 and the second-stage non-Foster circuit 2 respectively to offset the parasitic capacitance, push the non-dominant poles away from the circuit working bandwidth range, thereby improving the linearity and stability of the circuit, so that it has better linearity and faster stability.

[0087] Figure 2 This is a performance diagram of a sample-and-hold amplifier shown in an exemplary embodiment of the present application. Figure 2 The sampling and holding amplifier provided in the present application has a faster stabilization speed and better linearity, and can achieve a balance between the stabilization speed and the linearity.

[0088] Optional, Figure 3 The circuit diagram of the sample-and-hold amplifier shown in an exemplary embodiment of the present application is shown in FIG. Figure 3 In a possible implementation, based on the above embodiment, the equivalent tri-state gate T1 is formed by the first tri-state gate T11 and the second tri-state gate T12; the first equivalent negative capacitor CN1 is formed by the first capacitor C1 and the second capacitor C2; wherein,

[0089] The input end of the first tri-state gate T11 and the input end of the second tri-state gate T12 constitute the input end of the equivalent tri-state gate T1, and are used to receive the input first differential signal;

[0090] The enable control terminal of the first tri-state gate T11 and the enable control terminal of the second tri-state gate T12 are respectively connected to a voltage source;

[0091] The output end of the first tri-state gate T11 and the output end of the second tri-state gate T12 respectively constitute the output end of the equivalent tri-state gate T1, and are used to output a second differential signal;

[0092] The first end of the first capacitor C1 is connected to the input end of the first tri-state gate T11, and the second end of the first capacitor C1 is connected to the output end of the second tri-state gate T12;

[0093] A first end of the second capacitor C2 is connected to an input end of the second tri-state gate T12, and a second end of the second capacitor C2 is connected to an output end of the first tri-state gate T11;

[0094] The capacitance values ​​of the first capacitor C1 and the second capacitor C2 are equal, and a negative capacitor is equivalently connected between the input end of the first tri-state gate T11 and the input end of the second tri-state gate T12 through the first capacitor C1 and the second capacitor C2.

[0095] Specifically, Figure 4 This is a circuit diagram of a tri-state gate according to an exemplary embodiment of the present application. Figure 4 On the basis of the above embodiment, the first tri-state gate T11 and / or the second tri-state gate T12 includes a second control switch K2, a first MOS transistor M1, a second MOS transistor M2 and a third control switch K3; wherein,

[0096] The gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are connected to form the input end of the tri-state gate;

[0097] The drain of the first MOS transistor M1 and the drain of the second MOS transistor M2 are connected to form the output end of the tri-state gate;

[0098] The source of the first MOS transistor M1 is connected to a voltage source through the second control switch K2; the second control switch K2 is controlled by an initial control signal from a controller;

[0099] The source of the second MOS transistor M2 is grounded through the third control switch K3; the third control switch K3 is controlled by the inverted signal of the initial control signal.

[0100] For further information, please refer to Figure 3 , Optionally, in a possible implementation, the first equivalent NOT gate N1 is formed by a first NOT gate N11 and a second NOT gate N12, and the second equivalent negative capacitor CN2 is formed by a third capacitor C3 and a fourth capacitor C4; wherein,

[0101] The input end of the first NOT gate N11 and the input end of the second NOT gate N12 constitute the input end of the first equivalent NOT gate N1, and are used to receive the second differential signal;

[0102] The output end of the first NOT gate N11 and the output end of the second NOT gate N12 constitute the output end of the first equivalent NOT gate N11, which is used to output a third differential signal;

[0103] A first end of the third capacitor C3 is connected to the input end of the first NOT gate N11, and a second end of the third capacitor C3 is connected to the output end of the second NOT gate N122;

[0104] A first end of the fourth capacitor C4 is connected to an input end of the second NOT gate N12, and a second end of the fourth capacitor C4 is connected to an output end of the first NOT gate N11;

[0105] The capacitance values ​​of the third capacitor C3 and the fourth capacitor C4 are equal, and a negative capacitor is equivalently formed between the input end of the first NOT gate N11 and the input end of the second NOT gate N12 through the third capacitor C3 and the fourth capacitor C4.

[0106] Specifically, the capacitance values ​​of the first capacitor C1 and the third capacitor C3 are set according to actual needs and are not limited in this embodiment. For example, in a possible implementation, the capacitance value of the first capacitor C1 may be less than or equal to the capacitance value of the third capacitor C3.

[0107] Optionally, in a possible implementation manner, a capacitance value of the first capacitor C1 is greater than a capacitance value of the third capacitor C3.

[0108] For further information, please refer to Figure 3 In a possible implementation, the second equivalent NOT gate N2 is formed by two parallel NOT gates. Figure 3 In the example shown, the second equivalent NOT gate N2 is formed by a third NOT gate N21 and a fourth NOT gate N22 .

[0109] A detailed explanation is given below to illustrate that the first equivalent capacitance CN1 formed by the first capacitor C1 and the second capacitor C2 is a negative capacitance, and the second equivalent capacitance CN2 formed by the third capacitor C3 and the fourth capacitor C4 is a negative capacitance.

[0110] Specifically, Figure 5 This is a circuit diagram of a two-stage amplifier with a non-Foster circuit according to an exemplary embodiment of the present application. Figure 5 , a feedback capacitor CF is placed between the input and output of the second stage with different polarity. 1 and p 2 Represent the poles of the first-stage amplifier and the second-stage amplifier respectively. By calculating the input admittance Y in , the equivalent capacitance values ​​of the two feedback capacitors CF can be further derived.

[0111] Specifically, the equivalent capacitance values ​​of the two feedback capacitors CF can be calculated by the following formula:

[0112] ;

[0113] in, CF is the capacitance value of the feedback capacitor;

[0114] is the capacitance value of capacitor C20 on the second stage of the two-stage amplifier;

[0115] is the capacitance value of capacitor C20 on the second stage of the two-stage amplifier;

[0116] Said is a frequency variable;

[0117] is the frequency value of the pole of the second stage amplifier;

[0118] Said is the transconductance of the second stage amplifier.

[0119] It is understandable that when ;

[0120] when hour, .

[0121] Furthermore, Figure 6 for Figure 5 The equivalent capacitance value curve of the two feedback capacitors of the non-Foster circuit is shown in the figure. Figure 6 ,from Figure 6 It can be seen that the equivalent capacitance value has the following characteristics: it is negative at low frequencies, but becomes positive sharply at higher frequencies. Therefore, if the frequency of p2 is higher than that of p1 in a two-stage amplifier, this characteristic will extend the bandwidth of the first stage. This non-Foster circuit accelerates the settling speed of the previous stage by introducing negative capacitance. In addition, this non-Foster circuit works immediately when the amplifier starts working, avoiding the complexity of adjusting the negative capacitance working point during rapid amplification.

[0122] For further information, please refer to Figure 3 , in order to verify Figure 3 The effect of the sample-and-hold amplifier is shown and a verification test is performed on it.

[0123] Please continue to refer to Figure 3 ,exist Figure 3 The sample-and-hold amplifier shown includes two non-Foster circuits, through which fast stability is achieved and the performance of the holding stage is optimized. Specifically, since the output stage of the second non-Foster circuit 2 is smaller and exhibits a lighter capacitive load, the response speed of the second non-Foster circuit 2 is relatively fast. Furthermore, in order to further improve the stability of the overall circuit, the second non-Foster circuit 2 uses a negative capacitor to compensate for the parasitic capacitance output by the first non-Foster circuit 1, thereby pushing the non-dominant pole away.

[0124] In addition, the first-stage non-Foster circuit is mainly used to compensate the parasitic capacitance at the input end of the entire circuit, increase the feedback factor, and significantly improve the linearity and gain bandwidth of the circuit.

[0125] Figure 7 This is a test result diagram of a sample-and-hold amplifier according to an exemplary embodiment of the present application. Figure 8 This is a transient response diagram of a sample-and-hold amplifier according to an exemplary embodiment of the present application. Figure 7 and Figure 8 , Figure 7 and Figure 8 The sample-and-hold amplifier provided by the present application (the conventional one indicated in the figure) is compared with the conventional sample-and-hold amplifier (the improved one indicated in the figure). Figure 7 , Figure 7 The horizontal and vertical scales represent the frequency, and the vertical scale represents the AC gain. Figure 7 Indicates the change of AC gain with frequency, please refer to Figure 7 and Figure 8 For a multi-GS / s ADC input buffer, it is required to maintain good stability while responding quickly. Compared with the traditional sample-and-hold amplifier, the sample-and-hold amplifier provided by the present application, the first-stage non-Foster circuit 1 and the second-stage non-Foster circuit 2 work in coordination to jointly provide a gain of about 40 dB, thereby effectively suppressing the nonlinear effect. In addition, from the perspective of transient response, compared with the stabilization time of 260 ps of the traditional sample-and-hold amplifier, the sample-and-hold amplifier can achieve a short stabilization time of 200 ps, ​​shortening the stabilization time by about 70 ps, ​​and the power consumption is only 6 mW, which meets the requirements of the input buffer of the high-speed analog-to-digital converter for fast response.

[0126] In addition, please refer to Figure 8 The sampling and holding circuit provided in this application effectively reduces the pre-ringing phenomenon of the circuit (pre-ringing phenomenon is a common oscillation phenomenon in the signal conversion process, which usually affects the transient response and stability of the system). By setting a two-stage non-Foster circuit, the gain bandwidth and phase margin of the circuit are optimized, making the signal transition smoother, improving the conversion rate, and ensuring that the stable state is reached in a shorter time.

[0127] In the sample-and-hold amplifier provided in this embodiment, the first-stage non-Foster circuit focuses on providing preliminary gain and parasitic capacitance compensation to ensure that the circuit can effectively process the input signal and reduce the influence of non-dominant poles, and the second-stage non-Foster circuit further optimizes the gain and stability, especially through its smaller output stage and lighter capacitive load, so that its response speed is relatively fast, thereby achieving a faster stabilization time in the circuit as a whole. The synergistic effect of the two-stage non-Foster circuit not only improves the linearity and gain bandwidth of the sample-and-hold amplifier, but also effectively suppresses the nonlinear distortion in the signal, ensuring a high-performance input buffer function.

[0128] The sample-and-hold amplifier provided in this embodiment provides a first-stage non-Foster circuit and a second-stage non-Foster circuit in the sample-and-hold amplifier. The first-stage non-Foster circuit and the second-stage non-Foster circuit use an equivalent negative capacitor to offset the internal parasitic capacitance, thereby reducing the nonlinear distortion caused by the parasitic capacitance and improving the linearity of the sample-and-hold amplifier. In addition, the design of the first-stage non-Foster circuit focuses on providing preliminary gain and parasitic capacitance compensation to ensure that the circuit can effectively process the input signal and reduce the impact of the non-dominant pole on the overall performance. The second-stage non-Foster circuit further optimizes the gain and stability, thereby achieving faster stability of the sample-and-hold circuit as a whole.

[0129] Corresponding to the above-mentioned embodiment of a sample-and-hold amplifier, the present application further provides an embodiment of a high-speed analog-to-digital converter. The high-speed analog-to-digital converter provided by the present application is introduced below.

[0130] The high-speed analog-to-digital converter provided in the present application includes at least one sampling and holding amplifier provided in the first aspect of the present application.

[0131] Specifically, the high-speed analog-to-digital converter may further include an input buffer and a sub-analog-to-digital converter; wherein the sample-and-hold amplifier is arranged between the input buffer and the sub-analog-to-digital converter.

[0132] Specifically, the number of input buffers and sample holders may be one-to-one, i.e. one input buffer is connected to one sample holder. Furthermore, the number of input buffers and sample holders may be one-to-many, i.e. one input buffer is connected to multiple sample holders.

[0133] Furthermore, the quantitative correspondence between the sampling and holding amplifiers and the sub-analog-to-digital converters can also be a one-to-one relationship, that is, one sampling and holding amplifier is connected to a sub-analog-to-digital converter; further, the quantitative correspondence between the sampling and holding amplifiers and the sub-analog-to-digital converters can be a one-to-many relationship, that is, one sampling and holding amplifier is connected to multiple sub-analog-to-digital converters.

[0134] Referring to the above description, the corresponding relationship between the number of input buffers and sample-and-hold devices, and the corresponding relationship between the number of sample-and-hold amplifiers and sub-analog-to-digital converters are set according to actual needs, and are not limited in this embodiment. For example, in one possible implementation, one input buffer is connected to one sample-and-hold amplifier, and one sample-and-hold amplifier is connected to four sub-analog-to-digital converters.

[0135] The high-speed analog-to-digital converter provided in this embodiment has a sampling and holding amplifier that pushes the non-dominant pole away through a two-stage non-Foster circuit and increases the feedback factor only through a capacitor without increasing additional power consumption. The sampling and holding amplifier has better linearity and faster stability, which is beneficial to improving the overall performance of the high-speed analog-to-digital converter.

[0136] Fig. 9 This is a circuit diagram of the first embodiment of the high-speed analog-to-digital converter provided in this application. Fig. 9 The high-speed analog-to-digital converter provided in this embodiment includes two sampling and holding amplifiers 91; the high-speed analog-to-digital converter also includes an input buffer 92 and four sub-analog-to-digital converters 93; wherein,

[0137] The output end of the input buffer 92 is connected to the input ends of the two sampling and holding amplifiers 91 respectively; the output end of each sampling and holding amplifier 91 is connected to the input ends of two sub-analog-to-digital converters 93 respectively; the output ends of the four sub-analog-to-digital converters 93 are connected to form the output end of the high-speed analog-to-digital converter;

[0138] The high-speed analog-to-digital converter combines the output data of the four sub-analog-to-digital converters 93 through time interleaving technology to increase the sampling rate.

[0139] Specifically, the function of the input buffer 92 is to transfer the external input signal to the sample-and-hold amplifier and provide a certain current driving capability, which isolates the internal circuit of the high-speed analog-to-digital converter from the external signal source to prevent the impedance change of the signal source from affecting the performance of the high-speed analog-to-digital converter. In addition, it can also amplify the signal to ensure that the amplitude of the signal is suitable for the input range of the high-speed analog-to-digital converter.

[0140] Optional, Fig.10 This is a circuit diagram of an input buffer according to an exemplary embodiment of the present application. Fig.10 , the input buffer includes two level converters and a push-pull source follower; wherein,

[0141] Each level converter includes a first resistor R1, a second resistor R2, a fifth capacitor C5 and a sixth capacitor C6; the first end of the first resistor R1 and the first end of the second resistor R2 respectively constitute the bias input end of the level converter, for receiving the bias voltage; the second end of the first resistor R1 and the second end of the second resistor R2 respectively constitute the output end of the level converter;

[0142] The fifth capacitor C5 is connected between the second end of the first resistor R1 and the second end of the second resistor R2;

[0143] The first end of the sixth capacitor C6 constitutes the signal input end of the level converter, and is used to receive an input signal;

[0144] The push-pull source follower includes a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a third resistor R3 and a fourth resistor R4; wherein,

[0145] The gate of each MOS tube constitutes the input end of the push-pull source follower and is respectively connected to the output ends of the two level converters;

[0146] The drain of the third MOS tube M3 is connected to a voltage source, and the substrate of the third MOS tube M3 is connected to the source of the third MOS tube M3 and then connected to the drain of the fourth MOS tube M4;

[0147] The substrate of the fourth MOS transistor M4 is connected to the first end of the third resistor R3, and the other end of the third resistor R3 constitutes the first bias input end of the push-pull source follower, which is used to receive the bias voltage;

[0148] The source of the fourth MOS transistor M4 is connected to the source of the fifth MOS transistor M5 to form the output end of the push-pull source follower;

[0149] The substrate of the fifth MOS transistor M5 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 constitutes the second bias input end of the push-pull source follower, which is used to receive the bias voltage;

[0150] The drain of the fifth MOS tube M5 is connected to the source of the sixth MOS tube M6 , the source of the sixth MOS tube M6 is connected to the substrate of the sixth MOS tube M6 ; the drain of the sixth MOS tube M6 is grounded.

[0151] Specifically, the resistances of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are set according to actual needs, and in this embodiment, their specific values ​​are not limited. In addition, the capacitance values ​​of the fifth capacitor C5 and the sixth capacitor C6 are also set according to actual needs, and in this embodiment, they are not limited.

[0152] It should be noted that, in this embodiment, the third resistor R3 and the fourth resistor R4 are respectively connected to the substrates of the fourth MOS tube M4 and the fifth MOS tube M5, which reduces the voltage variation between the source and the substrate in the MOS tube and improves the linearity of the high-frequency signal.

[0153] For further information, please refer to Fig. 9 The sampling and holding amplifier 91 is arranged between the input buffer 92 and the four sub-analog-to-digital converters 93. The function of the sampling and holding amplifier 91 is to sample and hold the voltage value of the input signal. Specifically, in the sampling stage, the sampling and holding amplifier 91 captures the instantaneous voltage value of the input signal onto a capacitor; in the holding stage, the voltage value on the capacitor is kept unchanged so that the subsequent sub-analog-to-digital converter 93 can perform stable digital conversion on it. In this way, the instantaneous fluctuation of the signal can be eliminated and the conversion accuracy can be improved.

[0154] For further information, please refer to Fig. 9 In this embodiment, four sub-ADCs 93 work in parallel based on time interleaving technology. Each sub-ADC 93 samples the input signal at different time intervals, performs analog-to-digital conversion on the sampled signal, generates corresponding digital outputs, and finally combines these digital outputs to achieve a higher total sampling rate.

[0155] Optionally, in a possible implementation, each sub-ADC 93 includes a 4-bit flash ADC, an 8-fold residual amplifier, and a 9-bit SAR ADC with 1-bit redundancy. The specific circuit structure and working principle of the sub-ADC can be found in the description of the related art, which will not be repeated here.

[0156] Optionally, in one possible implementation, each sub-ADC 93 is a 12-bit 800 MS / s ADC slice, and by combining four 12-bit 800 MS / s ADC slices using time interleaving technology, a 3.2 GS / s 12-bit high-speed ADC can be implemented.

[0157] It should be noted that the high-speed analog-to-digital converter provided in this embodiment can be manufactured using a 28 nm CMOS process.

[0158] Furthermore, in order to verify the performance of the high-speed analog-to-digital converter provided in this application, a performance test was also performed on it, as follows:

[0159] The output spectrum of the high-speed analog-to-digital converter was tested at a sampling rate of 3.2 GS / s. The results showed that the analog-to-digital converter achieved a SNDR (Signal to Noise and Distortion Ratio, SNDR for short) of 54.1 dB and a SFDR (Spurious-Free Dynamic Range, SFDR for short) of 78.4 dB at a 30 MHz input, and a SNDR of 52.7 dB and a SFDR of 74.3 dB at a 1500 MHz input, with a power consumption of 150 mW.

[0160] The high-speed analog-to-digital converter provided in this embodiment simplifies the time offset adjustment of two sampling and holding amplifier paths and reduces the bandwidth mismatch between the four sub-analog-to-digital converters.

[0161] The present application also provides an electronic device, comprising a high-speed analog-to-digital converter as described in any one of the second aspects of the present application.

[0162] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A sample-and-hold amplifier, characterized in that: The sample-and-hold amplifier comprises a cascaded filter capacitor, a first-stage non-Foster circuit, a second-stage non-Foster circuit and an output circuit, wherein: The input end of the filter capacitor is also connected to the output end of the output circuit through a first control switch; The first-level non-Foster circuit includes an equivalent tri-state gate and a first equivalent negative capacitor; wherein the enable control terminal of the equivalent tri-state gate is connected to a voltage source, the input terminal of the equivalent tri-state gate is connected to the first terminal of the first equivalent negative capacitor to form the input terminal of the first-level non-Foster circuit; the output terminal of the equivalent tri-state gate forms the output terminal of the first-level non-Foster circuit; the second terminal of the first equivalent negative capacitor is grounded; The second-level non-Foster circuit comprises a first equivalent NOT gate and a second equivalent negative capacitor; wherein the input end of the first equivalent NOT gate and the first end of the second equivalent negative capacitor are connected to form the input end of the second-level non-Foster circuit; the output end of the first equivalent NOT gate forms the output end of the second-level non-Foster circuit; the second end of the second equivalent negative capacitor is grounded; The output circuit comprises a second equivalent NOT gate and a load capacitor; wherein the input end of the second equivalent NOT gate constitutes the input end of the output circuit; the output end of the second equivalent NOT gate is connected to the first end of the load capacitor to constitute the output end of the output circuit; the second end of the load capacitor is grounded; The first-stage non-Foster circuit and the second-stage non-Foster circuit offset internal parasitic capacitance through equivalent negative capacitance to obtain better linearity and faster stability.

2. The sample-and-hold amplifier according to claim 1, wherein: The equivalent three-state gate is formed by the first three-state gate and the second three-state gate; the first equivalent negative capacitor is formed by the first capacitor and the second capacitor; wherein, The input end of the first tri-state gate and the input end of the second tri-state gate constitute the input end of the equivalent tri-state gate, and are used to receive the input first differential signal; The enable control terminal of the first tri-state gate and the enable control terminal of the second tri-state gate are respectively connected to a voltage source; The output end of the first tri-state gate and the output end of the second tri-state gate respectively constitute the output end of the equivalent tri-state gate, and are used to output a second differential signal; A first end of the first capacitor is connected to an input end of the first tri-state gate, and a second end of the first capacitor is connected to an output end of the second tri-state gate; A first end of the second capacitor is connected to an input end of the second tri-state gate, and a second end of the second capacitor is connected to an output end of the first tri-state gate; The capacitance values ​​of the first capacitor and the second capacitor are equal, and a negative capacitor is equivalently connected between the input end of the first tri-state gate and the input end of the second tri-state gate through the first capacitor and the second capacitor.

3. The sample-and-hold amplifier according to claim 2, characterized in that: The first equivalent NOT gate is formed by a first NOT gate and a second NOT gate, and the second equivalent negative capacitance is formed by a third capacitor and a fourth capacitor; wherein, The input end of the first NOT gate and the input end of the second NOT gate constitute the input end of the first equivalent NOT gate, and are used to receive the second differential signal; The output end of the first NOT gate and the output end of the second NOT gate constitute the output end of the first equivalent NOT gate, and are used to output a third differential signal; A first end of the third capacitor is connected to an input end of the first NOT gate, and a second end of the third capacitor is connected to an output end of the second NOT gate; A first end of the fourth capacitor is connected to an input end of the second NOT gate, and a second end of the fourth capacitor is connected to an output end of the first NOT gate; The capacitance values ​​of the third capacitor and the fourth capacitor are equal, and a negative capacitor is equivalently formed between the input end of the first NOT gate and the input end of the second NOT gate through the third capacitor and the fourth capacitor.

4. The sample-and-hold amplifier according to claim 2, wherein: The first tri-state gate and / or the second tri-state gate comprises a second control switch, a first MOS transistor, a second MOS transistor and a third control switch; wherein, The gate of the first MOS tube and the gate of the second MOS tube are connected to form an input end of a tri-state gate; The drain of the first MOS tube and the drain of the second MOS tube are connected to form the output end of the tri-state gate; The source of the first MOS tube is connected to a voltage source through the second control switch; the second control switch is controlled by an initial control signal from a controller; The source of the second MOS tube is grounded through the third control switch; the third control switch is controlled by an inverted signal of the initial control signal.

5. The sample-and-hold amplifier according to claim 1, wherein: The second equivalent NOT gate is formed by two parallel-connected NOT gates.

6. The sample-and-hold amplifier according to claim 3, characterized in that: The capacitance value of the first capacitor is greater than the capacitance value of the third capacitor.

7. A high-speed analog-to-digital converter, characterized in that: The high-speed analog-to-digital converter comprises at least one sample-and-hold amplifier according to any one of claims 1-6.

8. The high-speed analog-to-digital converter according to claim 7, characterized in that: The high-speed analog-to-digital converter includes two sample-and-hold amplifiers; the high-speed analog-to-digital converter also includes an input buffer and four sub-analog-to-digital converters; wherein, The output end of the input buffer is connected to the input ends of the two sampling and holding amplifiers respectively; the output end of each sampling and holding amplifier is connected to the input ends of two sub-analog-to-digital converters respectively; the output ends of the four sub-analog-to-digital converters are connected to form the output end of the high-speed analog-to-digital converter; The high-speed analog-to-digital converter combines the output data of the four sub-analog-to-digital converters through time interleaving technology to increase the sampling rate.

9. The high-speed analog-to-digital converter according to claim 8, characterized in that: The input buffer includes two level converters and a push-pull source follower; wherein, Each level converter includes a first resistor, a second resistor, a fifth capacitor and a sixth capacitor; the first end of the first resistor and the first end of the second resistor respectively constitute the bias input end of the level converter, for receiving the bias voltage; the second end of the first resistor and the second end of the second resistor respectively constitute the output end of the level converter; The fifth capacitor is connected between the second end of the first resistor and the second end of the second resistor; The first end of the sixth capacitor constitutes a signal input end of the level converter, and is used to receive an input signal; The push-pull source follower includes a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a third resistor and a fourth resistor; wherein, The gate of each MOS tube constitutes the input end of the push-pull source follower and is respectively connected to the output ends of the two level converters; The drain of the third MOS tube is connected to a voltage source, and the substrate of the third MOS tube is connected to the source of the third MOS tube and then connected to the drain of the fourth MOS tube; The substrate of the fourth MOS tube is connected to the first end of the third resistor, and the other end of the third resistor constitutes the first bias input end of the push-pull source follower, which is used to receive the bias voltage; The source of the fourth MOS tube is connected to the source of the fifth MOS tube to form the output end of the push-pull source follower; The substrate of the fifth MOS transistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor constitutes the second bias input end of the push-pull source follower, which is used to receive the bias voltage; The drain of the fifth MOS tube is connected to the source of the sixth MOS tube, the source of the sixth MOS tube is connected to the substrate of the sixth MOS tube; the drain of the sixth MOS tube is grounded.

10. An electronic device, characterized in that: The electronic device comprises the high-speed analog-to-digital converter according to any one of claims 7-9.

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