Memory cell structure and method of operation thereof, memory array structure and method of operation thereof

Abstract

The embodiment of the present disclosure relates to the technical field of semiconductor, and provides a storage unit structure and an operating method thereof, a storage array structure and an operating method thereof, the storage unit structure comprising: a substrate; a first transistor located on the surface of the substrate, the first transistor comprising a first semiconductor layer, a first gate and a second gate located on the opposite sides of the first semiconductor layer, a first electrode and a second electrode electrically connected with different regions of the first semiconductor layer, and the first gate, the second gate, the first electrode and the second electrode being insulated from each other in pairs; and a second transistor located on the side of the first transistor away from the substrate, the second transistor comprising a second semiconductor layer, a third gate, a third electrode and a fourth electrode electrically connected with different regions of the second semiconductor layer, the third electrode being electrically connected with the first gate, and the third gate, the third electrode and the fourth electrode being insulated from each other in pairs. The embodiment of the present disclosure is at least beneficial to improving the electrical performance of the storage unit structure and improving the integration density of the storage unit structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a memory cell structure and an operating method thereof, and a memory array structure and an operating method thereof. Background Art

[0002] Common dynamic random access memory (DRAM) is a 1T1C type, where a single transistor source or drain is electrically connected to a capacitor to form a single memory cell. This structure uses capacitors to store data, but reading data consumes the capacitor's charge, and the capacitor itself leaks electricity, requiring constant refreshing. This results in high DRAM power consumption and unstable electrical performance. Furthermore, the large area required to manufacture the capacitor makes scaling down the capacitor challenging.

[0003] To overcome the problem caused by capacitance, a 2T0C type memory cell structure is used, that is, the source or drain of a transistor is electrically connected to the gate of another transistor to form a memory cell structure. Summary of the Invention

[0004] The embodiments of the present disclosure provide a memory cell structure and an operating method thereof, a memory array structure and an operating method thereof, which are at least beneficial for improving the electrical performance of the memory cell structure while increasing the integration density of the memory cell structure.

[0005] According to some embodiments of the present disclosure, on the one hand, the embodiments of the present disclosure provide a storage unit structure, including: a substrate; a first transistor located on the surface of the substrate, the first transistor including a first semiconductor layer, a first gate and a second gate located on opposite sides of the first semiconductor layer, and a first electrode and a second electrode electrically connected to different regions of the first semiconductor layer, wherein the first gate, the second gate, the first electrode and the second electrode are insulated from each other in pairs; a second transistor located on a side of the first transistor away from the substrate, the second transistor including a second semiconductor layer, a third gate, and a third electrode and a fourth electrode electrically connected to different regions of the second semiconductor layer, the third electrode is also electrically connected to the first gate, and the third gate, the third electrode and the fourth electrode are insulated from each other in pairs.

[0006] In some embodiments, the first semiconductor layer encloses a first chamber, the first chamber is a chamber having a first opening, or the first chamber is a chamber having two first openings arranged opposite to each other; the first semiconductor layer has a first inner side and a first outer side relative to each other, the first gate is opposite to at least a portion of the first inner side, and the second gate is opposite to at least a portion of the first outer side; the first transistor also includes: a first gate dielectric layer, located between the first gate and the first semiconductor layer; and a second gate dielectric layer, located between the second gate and the first semiconductor layer.

[0007] In some embodiments, the second gate dielectric layer covers an area of ​​the first outer side extending in a direction perpendicular to the surface of the substrate, and in the direction perpendicular to the surface of the substrate, the first electrode is opposite to a portion of the side wall of the first gate dielectric layer, and the second electrode is opposite to a portion of the other side wall of the first gate dielectric layer; the memory cell structure also includes: an isolation layer, the isolation layer is located between the first electrode and the second gate dielectric layer, and between the second electrode and the second gate dielectric layer; a first electrical connection layer, one end of the first electrical connection layer is electrically contacted with the first electrode, and the other end is electrically contacted with a portion of the top surface of the first semiconductor layer; a second electrical connection layer, one end of the second electrical connection layer is electrically contacted with the second electrode, and the other end is electrically contacted with a portion of the other top surface of the first semiconductor layer.

[0008] In some embodiments, the second gate dielectric layer is located in a partial area of ​​the first outer side, and the first electrode and the second electrode are respectively in contact with different areas of other areas of the first outer side.

[0009] In some embodiments, the first chamber is a chamber having two first openings arranged opposite to each other, the first semiconductor layer has a first bottom surface close to the substrate and a first top surface away from the substrate, one of the first electrode and the second electrode is in contact with the first bottom surface, and the other of the first electrode and the second electrode is in contact with the first top surface.

[0010] In some embodiments, the second semiconductor layer encloses a second chamber, the second chamber is a chamber having a second opening, or the second chamber is a chamber having two second openings arranged opposite to each other; the second semiconductor layer has a second inner side and a second outer side opposite to each other, and the third gate is opposite to a partial area of ​​the second inner side; the second transistor also includes: a third gate dielectric layer, located between the third gate and the second semiconductor layer.

[0011] In some embodiments, along a direction perpendicular to the surface of the substrate, the second semiconductor layer includes a first part, a second part and a third part, and the first part is not directly opposite the third gate; the fourth electrode surrounds the second outer side of the third part; along a direction perpendicular to the surface of the substrate, the third electrode surrounds the second outer side of the first part for at least part of the height, and / or the third electrode is in contact with the second bottom surface of the second semiconductor layer near the substrate; the memory cell structure also includes: an isolation layer, which surrounds the second outer side of the second part.

[0012] In some embodiments, the orthographic projection of the first gate on the substrate is located in the orthographic projection of the third electrode on the substrate.

[0013] In some embodiments, a material of the first semiconductor layer includes at least one of IGZO or ITO, and a material of the second semiconductor layer includes at least one of IGZO or ITO.

[0014] According to some embodiments of the present disclosure, on the other hand, an operating method of a storage cell structure is further provided, comprising: providing a storage cell structure as described in any one of the above items, wherein the electrically connected third electrode and the first gate constitute a storage node; and performing a write operation or a read operation on the storage node.

[0015] In some embodiments, performing the write operation on the storage node includes: providing a first voltage to the third gate, providing a second voltage to the fourth electrode and the second electrode, and providing a third voltage to the first electrode, so as to perform the write operation on the storage node; wherein, the first voltage is the turn-on voltage of the second transistor, and the difference in potential at the storage node results in a difference in the threshold voltage of the first transistor; during the write operation on the storage node, no voltage signal is provided to the second gate.

[0016] In some embodiments, performing the read operation on the storage node includes: providing a fourth voltage to the second gate, providing a third voltage to the first electrode, detecting the current in the first transistor through the second electrode to determine the potential stored at the storage node, so as to perform the read operation on the storage node; during the read operation on the storage node, no voltage signal is provided to the third gate.

[0017] In some embodiments, the level of the fourth voltage is adjusted according to the usage time of the memory cell structure.

[0018] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a storage array structure, comprising: a plurality of storage cell structures as described in any one of the above items, the plurality of storage cell structures being spaced apart and arranged in an array along a first direction and a second direction, the first direction and the second direction being parallel to the substrate surface, and the first direction and the second direction intersecting; a first word line extending along the first direction, and the plurality of third gates spaced apart and arranged along the first direction being electrically connected to the same first word line; a bit line extending along the second direction, and the same bit line including the plurality of fourth electrodes spaced apart and arranged along the second direction; a third electrical connection layer, a third electrical connection layer contacting and connecting a bit line and a second electrode; a second word line extending along the first direction, and the plurality of second gates spaced apart and arranged along the first direction being electrically connected to the same second word line.

[0019] In some embodiments, the first transistors are arranged in a quadrilateral along the first direction and the second direction, and the second transistors are arranged in a quadrilateral along the first direction and the second direction.

[0020] According to some embodiments of the present disclosure, on the other hand, an operating method of a storage array structure is provided, comprising: providing a storage array structure as described in any one of the above items, wherein the storage array structure comprises a plurality of first word lines arranged at intervals along the second direction, a plurality of bit lines arranged at intervals along the first direction, and a plurality of second word lines arranged at intervals along the second direction; and performing a write operation or a read operation on any of the storage cell structures in the storage array structure.

[0021] In some embodiments, performing the write operation on any of the memory cell structures in the memory array structure includes: providing a first voltage to one of the first word lines and providing a second voltage to one of the bit lines to select one of the memory cell structures, and providing a third voltage to the first electrode in the selected memory cell structure to perform the write operation on the selected memory cell structure; wherein the first voltage is the turn-on voltage of the second transistor in the selected memory cell structure; during the write operation on the selected memory cell structure, no voltage signal is provided to all of the second word lines, and no voltage is provided to the remaining first word lines and the remaining bit lines.

[0022] In some embodiments, performing the read operation on any of the memory cell structures in the memory array structure includes: providing a fourth voltage to one of the second word lines, reading the current in a selected one of the memory cell structures through one of the bit lines, so as to perform the read operation on the selected memory cell structure, wherein the selected memory cell structure is jointly determined by the second word line provided with the fourth voltage and the bit line for reading the current; in the process of performing the read operation on the selected memory cell structure, no voltage signal is provided to all of the first word lines, and no voltage is provided to the remaining second word lines.

[0023] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0024] On the one hand, the first transistor is a dual-gate transistor, that is, the threshold voltage of the first transistor is jointly controlled by the first gate and the second gate, which is conducive to flexible control of the conduction or shutdown of the first transistor to improve the electrical performance of the memory cell structure; on the other hand, the first transistor and the second transistor together constitute the memory cell structure, and no capacitor device is required, which is conducive to reducing the size of the memory cell structure itself to improve the integration density of the memory cell structure; on the other hand, the first transistor can be used as a read transistor, the second transistor can be used as a write transistor, and the third electrode is electrically connected to the first gate, then the second transistor can affect the potential at the first gate, and the first transistor is affected by the first gate and the second gate to present different threshold voltages for representing data 1 and data 0, respectively, thereby realizing a 2T0C type memory cell structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 1a is a schematic cross-sectional view of a memory cell structure provided by an embodiment of the present disclosure;

[0027] Figure 1 1b is a schematic diagram of a three-dimensional structure corresponding to the storage unit structure shown in 1a;

[0028] Figure 2 for Figure 1A schematic cross-sectional structure diagram of the first semiconductor layer and the second semiconductor layer in the memory cell structure shown;

[0029] Figure 3 Two other cross-sectional structural schematic diagrams of the first transistor in the memory cell structure provided in one embodiment of the present disclosure;

[0030] Figure 4 4a is another cross-sectional structural diagram of a memory cell structure provided by an embodiment of the present disclosure;

[0031] Figure 4 4b is a schematic diagram of a three-dimensional structure corresponding to the storage unit structure shown in 4a;

[0032] Figure 5 Two further schematic cross-sectional views of the first transistor in the memory cell structure provided in one embodiment of the present disclosure;

[0033] Figure 6 6a is a schematic diagram of another cross-sectional structure of a memory cell structure provided by an embodiment of the present disclosure;

[0034] Figure 6 6b is a schematic diagram of a three-dimensional structure corresponding to the storage unit structure shown in 6a;

[0035] Figure 7 Two schematic diagrams of partial top views of the first transistor in the memory cell structure provided in one embodiment of the present disclosure;

[0036] Figure 8 Schematic diagrams of three cross-sectional structures of the second transistor in the memory cell structure provided in one embodiment of the present disclosure;

[0037] Figure 9 Three schematic diagrams of partial top views of the second transistor in the memory cell structure provided in one embodiment of the present disclosure;

[0038] Figure 10 A simplified circuit diagram of operating a memory cell structure according to another embodiment of the present disclosure;

[0039] Figure 11 A schematic diagram of a three-dimensional structure of a storage array structure provided in yet another embodiment of the present disclosure;

[0040] Figure 12 A simplified circuit diagram of operating a storage array structure according to another embodiment of the present disclosure;

[0041] Figures 13 and 14 This is a schematic cross-sectional structural diagram corresponding to each step in a method for manufacturing a memory cell structure provided in yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] As known from the background art, the electrical performance and integration density of the memory cell structure need to be improved.

[0043] The present disclosure provides a memory cell structure and an operating method thereof, and a memory array structure and an operating method thereof. In the memory cell structure, on the one hand, the first transistor is a dual-gate transistor, that is, the threshold voltage of the first transistor is jointly controlled by the first gate and the second gate, which is conducive to flexible control of the conduction or shutdown of the first transistor to improve the electrical performance of the memory cell structure; on the other hand, the first transistor and the second transistor together constitute the memory cell structure, and no capacitor device is required, which is conducive to reducing the size of the memory cell structure itself to improve the integration density of the memory cell structure; on the other hand, the first transistor can be used as a read transistor, and the second transistor can be used as a write transistor. The third electrode is electrically connected to the first gate, so that the second transistor can affect the potential at the first gate. The first transistor is affected by the first gate and the second gate and exhibits different threshold voltages for representing data 1 and data 0, respectively, thereby realizing a 2T0C type memory cell structure.

[0044] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0045] An embodiment of the present disclosure provides a memory cell structure, which will be described in detail below with reference to the accompanying drawings. Figure 1 1a is a schematic cross-sectional view of a memory cell structure provided by an embodiment of the present disclosure; Figure 1 1b is a schematic diagram of a three-dimensional structure corresponding to the storage unit structure shown in 1a; Figure 2 for Figure 1 A schematic cross-sectional structure diagram of the first semiconductor layer and the second semiconductor layer in the memory cell structure shown; Figure 3 Two other cross-sectional structural schematic diagrams of the first transistor in the memory cell structure provided in one embodiment of the present disclosure; Figure 4 4a is another cross-sectional structural diagram of a memory cell structure provided by an embodiment of the present disclosure; Figure 4 4b is a schematic diagram of a three-dimensional structure corresponding to the storage unit structure shown in 4a; Figure 5 Two further schematic cross-sectional views of the first transistor in the memory cell structure provided in one embodiment of the present disclosure;

[0046] Figure 6 6a is a schematic diagram of another cross-sectional structure of a memory cell structure provided by an embodiment of the present disclosure; Figure 6 6b is a schematic diagram of a three-dimensional structure corresponding to the storage unit structure shown in 6a; Figure 7 Two schematic diagrams of partial top views of the first transistor in the memory cell structure provided in one embodiment of the present disclosure; Figure 8 Schematic diagrams of three cross-sectional structures of the second transistor in the memory cell structure provided in one embodiment of the present disclosure; Figure 9 Three partial top-view structural diagrams of the second transistor in the memory cell structure provided in one embodiment of the present disclosure are shown.

[0047] refer to Figures 1 to 9 The memory cell structure includes: a substrate 100; a first transistor 101 located on a surface of the substrate 100, the first transistor 101 including a first semiconductor layer 111, a first gate 121 and a second gate 131 located on opposite sides of the first semiconductor layer 111, and a first electrode 141 and a second electrode 151 electrically connected to different regions of the first semiconductor layer 111, wherein the first gate 121, the second gate 131, the first electrode 141, and the second electrode 151 are insulated from each other; a second transistor 102 located on a side of the first transistor 101 away from the substrate 100, the second transistor 102 including a second semiconductor layer 112, a third gate 122, and a third electrode 132 and a fourth electrode 142 electrically connected to different regions of the second semiconductor layer 112, wherein the third electrode 132 is also electrically connected to the first gate 121, and wherein the third gate 122, the third electrode 132, and the fourth electrode 142 are insulated from each other.

[0048] It can be understood that the first transistor 101 is a dual-gate transistor, that is, the threshold voltage of the first transistor 101 is jointly controlled by the first gate 121 and the second gate 131. The first transistor 101 exhibits different threshold voltages under the influence of the first gate 121 and the second gate 131. The first transistor 101 at different threshold voltages can be used to represent data 1 and data 0, respectively.

[0049] In this way, the first transistor 101 can be a read transistor and the second transistor 102 can be a write transistor. Since the third electrode 132 of the second transistor 102 is electrically connected to the first gate 121 of the first transistor 101, that is, the second transistor 102 can affect the threshold voltage of the first transistor 101 through the first gate 121. In addition, the second gate 131 also affects the threshold voltage of the first transistor 101. Therefore, during the period of time when the memory cell structure is used, the voltage provided to the second gate 131 remains unchanged. The difference in the voltage provided to the third electrode 132, that is, the voltage provided to the first gate 121 by the second transistor 102 changes the threshold voltage of the first transistor 101, so that the first transistor 101 can store data. Subsequently, the current flowing through the first transistor 101 is read through the first electrode 141 and the second electrode 151 of the first transistor 101 to realize the reading of data. Among them, different voltages on the first gate 121 result in different threshold voltages of the first transistor 101, and thus different currents flowing through the first transistor 101 read from the first electrode 141 and the second electrode 151 are different. The different magnitudes of the current can be used to represent data 1 and data 0, respectively.

[0050] In addition, the threshold voltage of the first transistor 101 will also be affected by the usage time. For example, in the initial stage of using the first transistor 101, when the potential at the first gate 121 is A1 and the potential at the second gate 131 is B1, the first transistor 101 is in a critical state of conduction, that is, the current read through the first transistor 101 at this time is large, and it can be judged that data 1 is read; after using the first transistor 101 for a period of time, when the potential at the first gate 121 is A1 and the potential at the second gate 131 is B1, the first transistor 101 may not be turned on, so that the current read through the first transistor 101 at this time is small or 0, and it will be judged that data 0 is read. At this time, there will be a deviation between writing and reading data. At this time, since the first transistor 101 is a dual-gate transistor, by adjusting the potential at the second gate 131, for example, making the potential at the second gate 131 B2, so that the potential at the first gate 121 is still A1, when the potential at the second gate 131 is B2, the first transistor 101 is in a critical state of conduction to avoid the deviation between writing and reading data, so as to ensure the normal operation of the memory cell structure. It can be understood that by designing the first transistor 101 as a dual-gate transistor, it is beneficial to more flexibly control the memory cell structure through the second gate 131, which is beneficial to improving the service life of the memory cell structure.

[0051] On the other hand, the memory cell structure is a 2T0C type, without a capacitor, which helps reduce the size of the memory cell structure. Furthermore, the first transistor 101 is located near the substrate 100, and the second transistor 102 is located on the side of the first transistor 101 away from the substrate 100. That is, along the third direction Z, the first transistor 101 and the second transistor 102 are stacked one on top of the other. This helps reduce the layout space of the memory cell structure in a direction parallel to the surface of the substrate 100, thereby helping to increase the density of the memory cell structure. The third direction Z is perpendicular to the surface of the substrate 100.

[0052] The memory cell structure provided by an embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0053] In some embodiments, reference Figure 1 、 Figure 2 、 Figure 3 Middle 3a, Figure 4 or Figure 5 The first semiconductor layer 111 forms a first chamber 106 , and the first chamber 106 is a chamber having a first opening 116 .

[0054] In other embodiments, reference Figure 3 3b or Figure 6 The first chamber 106 has two first openings 116 arranged opposite to each other (refer to Figure 2 For example, the two first openings 116 of the first chamber 106 are arranged opposite to each other along the third direction Z.

[0055] It should be noted that Figure 2 The first opening 116 of the first chamber 106 is indicated by a box. Figure 3 In FIG3b, the range of the first chamber 106 is marked with a dotted line.

[0056] In the above two embodiments, reference Figure 2 、 Figure 3 or Figure 6 The first semiconductor layer 111 has a first inner side 111a and a first outer side 111b opposite to each other. Figures 1 to 7 The first semiconductor layer 111 shown has a first inner side 111a and a first outer side 111b opposite to each other. Figure 2 、 Figure 3 and Figure 6 The first inner side 111a and the first outer side 111b of the first semiconductor layer 111 are labeled. It is understood that the first gate 121 is located in the first chamber 106, and a first opening 116 in the first chamber 106 is used to expose the first gate 121 to facilitate electrical connection between the first gate 121 and the third electrode 132.

[0057] refer to Figures 1 to 7 The first gate 121 is directly opposite to at least a portion of the first inner side 111a, and the second gate 131 is directly opposite to at least a portion of the first outer side 111b. The first transistor 101 further includes: a first gate dielectric layer 161 located between the first gate 121 and the first semiconductor layer 111; and a second gate dielectric layer 171 located between the second gate 131 and the first semiconductor layer 111. It should be noted that the first gate dielectric layer 161 is located at least between the first gate 121 and the first semiconductor layer 111, and the second gate dielectric layer 171 is located at least between the second gate 131 and the first semiconductor layer 111. In actual applications, the first gate dielectric layer 161 or the second gate dielectric layer 171 can also be located at other locations to achieve insulation between the other two film layers, depending on the needs.

[0058] It can be understood that in the various embodiments described above, the first semiconductor layer 111 itself forms a first cavity, which is beneficial to increasing the surface area of ​​the first semiconductor layer 111 while ensuring that the first semiconductor layer 111 itself occupies a smaller layout space, and increasing the length of the channel formed in the first semiconductor layer 111, thereby facilitating increasing the facing area between the first gate 121 and the first semiconductor layer 111, and increasing the facing area between the second gate 131 and the first semiconductor layer 111, so as to improve the control ability of the first gate 121 and the second gate 131 over the first semiconductor layer 111, thereby facilitating improving the electrical performance of the first transistor 101.

[0059] Due to the different positional relationships between the first electrode 141, the second electrode 151 and the first semiconductor layer 111, the specific structure of the first transistor 101 includes at least the following various embodiments:

[0060] First, in some embodiments, reference Figures 1 to 3 The second gate dielectric layer 171 covers the area of ​​the first outer side 111b extending in a direction perpendicular to the surface of the substrate 100. Along a direction Z perpendicular to the surface of the substrate 100, the first electrode 141 directly faces a portion of the sidewall of the first gate dielectric layer 161, and the second electrode 151 directly faces other portions of the sidewall of the first gate dielectric layer 161. For example, the first electrode 141 and the second electrode 151 may directly face each other along a first direction X, where the first direction X is parallel to the surface of the substrate 100. In practical applications, to meet other requirements, the first electrode 141 and the second electrode 151 only need to directly face different areas of the sidewall of the first gate dielectric layer 161, and the first electrode 141 and the second electrode 151 may be insulated from each other.

[0061] Continue to refer Figure 1The memory cell structure may further include an isolation layer 103, which is located between the first electrode 141 and the second gate dielectric layer 171, and between the second electrode 151 and the second gate dielectric layer 171. It should be noted that the isolation layer 103 may also be located at other locations to achieve insulation between other two film layers. Moreover, the isolation layer 103 may have a multi-layer structure, and the materials of different film layers in the multi-layer structure may be the same or different.

[0062] Continue to refer Figures 1 to 3 The storage cell structure may further include: a first electrical connection layer 114, one end of the first electrical connection layer 114 is electrically contacted with the first electrode 141, and the other end is electrically contacted with a portion of the first top surface 111c of the first semiconductor layer 111, so as to realize electrical connection between the first electrode 141 and the first semiconductor layer 111 through the first electrical connection layer 114; a second electrical connection layer 124, one end of the second electrical connection layer 124 is electrically contacted with the second electrode 151, and the other end is electrically contacted with the other portion of the first top surface 111c of the first semiconductor layer 111, so as to realize electrical connection between the second electrode 151 and the first semiconductor layer 111 through the second electrical connection layer 124.

[0063] It should be noted that Figure 1 In the example shown in Figure 1b, the orthographic projection of the first cavity enclosed by the first semiconductor layer 111 on the substrate 100 is a circular ring, that is, the first top surface 111c of the first semiconductor layer 111 is a circular ring, the first electrical connection layer 114 is in contact with a portion of the length of the circular ring, and the second electrical connection layer 124 is in contact with the remaining portion of the length of the circular ring. In actual applications, the orthographic projection of the first cavity enclosed by the first semiconductor layer on the substrate 100 can also be a square ring or other ring shape, that is, the first top surface of the first semiconductor layer is a square ring or other ring shape.

[0064] In addition, the first electrical connection layer 114 is electrically insulated from the first gate 121 and the second gate 131 , and the second electrical connection layer 124 is electrically insulated from the first gate 121 and the second gate 131 .

[0065] The first transistor 101 including the first electrical connection layer 114 and the second electrical connection layer 124 will be described in detail below.

[0066] In one example, in conjunction with reference Figure 1 and Figure 2The first semiconductor layer 111 is a first cavity 106 including a first opening 116. The first outer side 111b includes a region extending along the third direction Z and a region extending along the first direction X. The second gate dielectric layer 171 covers not only the region of the first outer side 111b extending along the third direction Z, but also the region of the first outer side 111b extending along the first direction X. That is, the second gate dielectric layer 171 covers the entire first outer side 111b. The second gate 131 covers the side of the second gate dielectric layer 171 away from the first semiconductor layer 111.

[0067] In another example, in conjunction with reference Figure 3 3a and Figure 2 The first semiconductor layer 111 is a first cavity 106 including a first opening 116. The first outer side 111b includes a region extending along the third direction Z and a region extending along the first direction X. The second gate dielectric layer 171 only covers the region of the first outer side 111b extending along the third direction Z. That is, the first outer side 111b extending along the first direction X in the first semiconductor layer 111 is not in contact with the second gate dielectric layer 171. The second gate 131 covers the side of the second gate dielectric layer 171 away from the first semiconductor layer 111.

[0068] In yet another example, reference Figure 3 3b, the first semiconductor layer 111 is a first cavity 106 including two first openings 116. In addition to having a first inner side 111a and a first outer side 111b opposite to each other along the first direction X, the first semiconductor layer 111 further has a first top surface 111c and a first bottom surface 111d opposite to each other along the third direction Z. The second gate dielectric layer 171 covers the region of the first outer side 111b extending along the third direction Z, that is, covers the entire first outer side 111b. The second gate electrode 131 covers the side of the second gate dielectric layer 171 away from the first semiconductor layer 111.

[0069] Second, in other embodiments, reference Figures 4 and 5 The second gate dielectric layer 171 is located on the first outer side 111b (refer to Figure 2 ), the first electrode 141 and the second electrode 151 are respectively in contact with and connected to different areas of other areas of the first outer side 111b.

[0070] In some embodiments, continue to refer to Figures 4 and 5 , the first outer side 111b (reference Figure 2 ) A partial area extending along the third direction Z is not covered by the second gate dielectric layer 171, and this partial area is in contact with the first electrode 141, the second electrode 151 and the isolation layer 103, and the first electrode 141, the second electrode 151 and the second gate 131 are electrically insulated from each other by the isolation layer 103.

[0071] In some embodiments, continue to refer to Figures 4 and 5 , the first electrode 141 and the second electrode 151 are facing each other along the first direction X. It should be noted that, Figure 4 In the example shown in Figure 4b, the orthographic projection of the first cavity surrounded by the first semiconductor layer 111 on the substrate 100 is a circular ring. In actual applications, the orthographic projection of the first cavity surrounded by the first semiconductor layer on the substrate can also be a square ring or a ring of other shapes.

[0072] The first transistor 101 in which the first electrode 141 and the second electrode 151 are both in contact with the first semiconductor layer 111 will be described in detail below.

[0073] In one example, in conjunction with reference Figure 4 and Figure 2 The first semiconductor layer 111 is a first cavity 106 including a first opening 116. The first outer side 111b includes a region extending along the third direction Z and a region extending along the first direction X. The second gate dielectric layer 171 covers the region of the first outer side 111b extending along the first direction X and is located in a partial region of the first outer side 111b extending along the third direction Z. The second gate 131 covers a side of the second gate dielectric layer 171 away from the first semiconductor layer 111.

[0074] In another example, refer to Figure 5 5a and Figure 2 The first semiconductor layer 111 is a first chamber 106 including a first opening 116, the first outer side 111b includes a region extending along the third direction Z and a region extending along the first direction X, the second gate dielectric layer 171 only covers the region of the first outer side 111b extending along the first direction X, and the second gate 131 covers the side of the second gate dielectric layer 171 away from the first semiconductor layer 111.

[0075] In yet another example, reference Figure 5 5b and Figure 2 The first semiconductor layer 111 is a first cavity 106 including a first opening 116. The first outer side 111b includes a region extending along the third direction Z and a region extending along the first direction X. The second gate dielectric layer 171 is only located in a portion of the first outer side 111b extending along the third direction Z. The second gate electrode 131 covers a side of the second gate dielectric layer 171 away from the first semiconductor layer 111. That is, the region of the first outer side 111b extending along the first direction X is not covered by the second gate dielectric layer 171.

[0076] In another example, the first semiconductor layer is a first cavity including two first openings. In addition to having a first inner side and a first outer side opposite to each other along a first direction, the first semiconductor layer further has a first top surface and a first bottom surface opposite to each other along a third direction. The second gate dielectric layer is located only in a portion of the first outer side.

[0077] In the above various embodiments, reference Figures 1 to 5 The first gate dielectric layer 161 covers the first inner side 111 a , and the first gate electrode 121 covers a side of the first gate dielectric layer 161 away from the first semiconductor layer 111 .

[0078] Third, in some other embodiments, reference Figure 6 The first chamber 106 is a chamber having two first openings 116 disposed opposite each other. The first semiconductor layer 111 has a first bottom surface 111d close to the substrate 100 and a first top surface 111c away from the substrate 100. One of the first electrode 141 and the second electrode 151 is in contact with the first bottom surface 111d, and the other of the first electrode 141 and the second electrode 151 is in contact with the first top surface 111c. Furthermore, the first semiconductor layer 111 has a first inner side 111a and a first outer side 111b extending in a third direction Z and facing each other.

[0079] It should be noted that Figure 6 In the example, the first electrode 141 is in contact with the first bottom surface 111d and the second electrode 151 is in contact with the first top surface 111c. In actual applications, the first electrode can be in contact with the first top surface and the second electrode can be in contact with the first bottom surface 111d.

[0080] In addition, the first semiconductor layer 111 further has a first inner side 111a and a first outer side 111b extending along the third direction Z and opposite to each other. The second gate dielectric layer 171 covers the first outer side 111b, and the second gate 131 covers the side of the second gate dielectric layer 171 away from the first semiconductor layer 111.

[0081] In some embodiments, reference Figure 6 The first gate dielectric layer 161 encloses a cavity having two openings facing each other along the third direction Z. In addition to being in contact with the first inner side 111a, the first gate dielectric layer 161 is also in contact with the sidewalls of the first electrode 141 and the second electrode 151 extending along the third direction Z. The first gate electrode 121 covers a side of the first gate dielectric layer 161 away from the first semiconductor layer 111. In other embodiments, the first gate dielectric layer may be in contact with only the first inner side.

[0082] In some embodiments, reference Figure 6The first gate 121 is a solid column. In other embodiments, the first gate may also be a hollow column, and the hollow portion of the column is filled with a dielectric layer.

[0083] In some embodiments, reference Figure 6 The first electrode 141 and the second electrode 151 may respectively surround different regions of the sidewall of the first gate dielectric layer 161 extending along the third direction Z, that is, the first electrode 141 covers the first bottom surface 111d, and the second electrode 151 covers the first top surface 111c.

[0084] In the above various embodiments, reference Figure 7 In FIG7a, the orthographic projection of the first semiconductor layer 111 in the first transistor 101 on the substrate 100 is a ring, that is, the first semiconductor layer 111 is a hollow cylinder, and the first gate dielectric layer 161 surrounds the first inner side 111a (refer to FIG7a). Figure 2 ), the first gate 121 surrounds the sidewall of the first gate dielectric layer 161 extending along the third direction Z, and the second gate dielectric layer 171 surrounds at least the first outer side 111b (reference Figure 2 ) in a partial area extending along the third direction Z, the second gate 131 surrounds the sidewall of the second gate dielectric layer 171 extending along the third direction Z. In practical applications, the orthographic projection of the first semiconductor layer 111 in the first transistor 101 on the substrate 100 may also be a square ring or a ring of other shapes.

[0085] In the above various embodiments, reference Figure 7 In FIG7b, the cross-sectional shape of the first semiconductor layer 111 on a plane perpendicular to the second direction Y is U-shaped. Thus, any one of the first gate dielectric layer 161, the second gate dielectric layer 171 and the second gate electrode 131 can be two long strip structures spaced apart along the first direction X, or have a U-shaped cross-sectional shape on a plane perpendicular to the second direction Y.

[0086] In the various embodiments described above, the first electrode 141 and the second electrode 151 are arranged to surround a portion of the side wall of the first semiconductor layer 111 extending along the third direction Z. This is beneficial for increasing the cross-sectional area of ​​the first electrode 141 and the second electrode 151 in a plane perpendicular to the third direction Z while ensuring that the layout space occupied by the first electrode 141 and the second electrode 151 themselves is small, so as to increase the contact area between the first electrode 141 and the second electrode 151 and other conductive structures (for example, the first electrical connection layer 114 or the second electrical connection layer 124), and is beneficial for improving the capacitive coupling effect between the first electrode 141 and the second electrode 151 and the first gate 121.

[0087] The specific structure of the second transistor 102 includes at least the following embodiments:

[0088] In some embodiments, reference Figure 1 、 Figure 2 、 Figure 4 、 Figure 6 or Figure 8 In FIG8 a , the second semiconductor layer 112 forms a second chamber 126 , and the second chamber 126 is a chamber having a second opening 136 .

[0089] In other embodiments, reference Figure 8 In 8b or 8c, the second chamber 126 has two second openings 136 arranged opposite to each other (refer to Figure 2 ) chamber. For example, the two second openings 136 of the second chamber 126 are arranged opposite each other along the third direction Z. It can be understood that the third gate 122 is located in the second chamber 126, and one of the second openings 136 in the second chamber 126 is used to expose the top surface of the third gate 122 away from the substrate 100.

[0090] It should be noted that Figure 2 The second opening 136 of the second chamber 126 is indicated by a box. Figure 8 In FIG8 c , the second chamber 126 is delineated by a dotted line.

[0091] In the above two embodiments, the second semiconductor layer 112 has a second inner side 112a and a second outer side 112b opposite to each other, and the third gate 122 is opposite to a portion of the second inner side 112a; the second transistor 102 further includes: a third gate dielectric layer 152 located between the third gate 122 and the second semiconductor layer 112.

[0092] Understandably, the reference Figure 8 In FIG8 b or 8 c , when the second chamber 126 is a chamber having two second openings 136 oppositely disposed, the third gate dielectric layer 152 is further located between the third gate 122 and the third electrode 132 .

[0093] In some embodiments, reference Figure 8 , along the direction Z perpendicular to the surface of the substrate 100, the second semiconductor layer 112 includes a first portion 162, a second portion 172 and a third portion 182, and the first portion 162 is not directly opposite the third gate 122; the fourth electrode 142 surrounds the second outer side 112b of the third portion 182, which is beneficial to increasing the contact area between the fourth electrode 142 and the second semiconductor layer 112, thereby reducing the contact resistance between the fourth electrode 142 and the second semiconductor layer 112, thereby facilitating improving the electrical performance of the second transistor 102.

[0094] In some embodiments, reference Figure 1 、 Figure 4 、 Figure 6 and Figure 8In Figure 8c, along the direction Z perpendicular to the surface of the substrate 100, the third electrode 132 surrounds the second outer side 112b of the first portion 162 at least partially in height. This is beneficial to increasing the contact area between the third electrode 132 and the second semiconductor layer 112, thereby reducing the contact resistance between the third electrode 132 and the second semiconductor layer 112, thereby improving the electrical performance of the second transistor 102. Figure 8 8c takes the third electrode 132 surrounding the entire second outer side 112b of the first portion 162 as an example, and, Figure 8 In the embodiment, the third electrode 132 is also in contact with and connected to the second bottom surface 112 c of the second semiconductor layer 112 close to the substrate 100 .

[0095] In other embodiments, reference Figure 8 In Figures 8 a and 8 b , the third electrode 132 is only in contact with and connected to the second bottom surface 112 c of the second semiconductor layer 112 close to the substrate 100 .

[0096] In some embodiments, reference Figure 1 、 Figure 4 and Figure 6 The memory cell structure further includes an isolation layer 103 , which surrounds the second outer side 112 b of the second portion 172 , so that the third electrode 132 and the fourth electrode 142 are electrically insulated by the isolation layer 103 .

[0097] In the above various embodiments, reference Figure 9 In FIG9a, the orthographic projection of the second semiconductor layer 112 in the second transistor 102 on the substrate 100 is a ring, that is, the second semiconductor layer 112 is a hollow cylinder; or, referring to FIG9a, Figure 9 In FIG9c , the orthographic projection of the second semiconductor layer 112 in the second transistor 102 on the substrate 100 is a square ring. In practical applications, the orthographic projection of the second semiconductor layer 112 in the second transistor 102 on the substrate 100 may also be a ring of other shapes.

[0098] In the above various embodiments, in combination with reference Figure 8 and Figure 9 In FIG9b, the cross-sectional shape of the second semiconductor layer 112 in the second transistor 102 on a plane perpendicular to the second direction Y can be U-shaped or two rectangles spaced apart along the first direction X, and the cross-sectional shape of the third gate dielectric layer 152 on a plane perpendicular to the second direction Y is U-shaped.

[0099] It can be understood that in the various embodiments described above, in the second transistor 102, the second semiconductor layer 112 itself forms a second cavity, which is beneficial to increasing the surface area of ​​the second semiconductor layer 112 while ensuring that the second semiconductor layer 112 itself occupies a smaller layout space, thereby facilitating increasing the facing area between the third gate 122 and the second semiconductor layer 112, as well as increasing the facing area between the third gate 122 and the second semiconductor layer 112, so as to improve the control ability of the third gate 122 over the second semiconductor layer 112, thereby helping to improve the electrical performance of the second transistor 102.

[0100] In some embodiments, reference Figure 1 、 Figure 4 and Figure 6 The orthographic projection of the first gate 121 on the substrate 100 is located within the orthographic projection of the third electrode 132 on the substrate 100. This facilitates ensuring that the top surface of the first gate 121 away from the substrate 100 is in contact with the bottom surface of the third electrode 132 close to the substrate 100, thereby maximizing the contact area between the third electrode 132 and the first gate 121. This helps reduce the contact resistance between the third electrode 132 and the first gate 121, thereby improving the electrical performance of the memory cell structure. Furthermore, this facilitates locating the second transistor 102 directly above the first transistor 101, thereby reducing the overall size of the memory cell structure and improving the integration density of the memory cell structure.

[0101] In the above various embodiments, the cross-sectional shape of the third electrode 132 on a plane perpendicular to the second direction Y may be T-shaped or similar to a T-shape. It is understood that, depending on the manufacturing process, the third electrode 132 may be a single-layer structure or a multi-layer structure.

[0102] In the above various embodiments, the material of the first semiconductor layer 111 includes at least one of IGZO (Indium Gallium Zinc Oxide) or ITO (Indium Tin Oxide), and the material of the second semiconductor layer 112 includes at least one of IGZO or ITO.

[0103] It can be understood that when the material of the first semiconductor layer 111 and the material of the second semiconductor layer 112 are composed of the above materials, it is beneficial to improve the carrier mobility of the first semiconductor layer 111 and the second semiconductor layer 112, thereby helping the first semiconductor layer 111 and the second semiconductor layer 112 to transmit electrical signals more efficiently.

[0104] In one example, the material of the first semiconductor layer 111 and the material of the second semiconductor layer 112 are both IGZO. The carrier mobility of IGZO is 20 to 50 times that of polysilicon, which helps to improve the carrier mobility of the channel region formed in the first semiconductor layer 111 and the second semiconductor layer 112, thereby helping to reduce the leakage current of the first transistor 101 and the second transistor 102 during operation, thereby reducing the power consumption of the memory cell structure and improving the operating efficiency of the memory cell structure. In addition, the retention time of the memory cell structure configured by the first transistor 101 and the second transistor 102 including IGZO can exceed 300 seconds, which helps to reduce the refresh rate and power consumption of the memory cell structure.

[0105] It should be noted that for the sake of clarity of the diagram, Figures 1 to 9 The first semiconductor layer 111 and the second semiconductor layer 112 are filled in the same filling manner. It can be understood that the material of the first semiconductor layer 111 and the material of the second semiconductor layer 112 can be the same or different; Figures 1 to 9 The first gate 121 and the second gate 122 are filled in the same filling manner. It can be understood that the material of the first gate 121 and the material of the second gate 122 can be the same or different.

[0106] also, Figures 1 to 9 The electrical connection structure between the first gate 121 and the third electrode 132 is not shown. It can be understood that any structure that can electrically connect the first gate 121 and the third electrode 132 can be applied to the memory cell structure provided in one embodiment of the present disclosure.

[0107] In order to clearly illustrate the positional relationship among the third electrode 132, the second electrode 151 and the first gate dielectric layer 161, Figure 6 In Figure 6b, a partial area of ​​the third electrode 132 and the second electrode 151 are drawn in perspective. In order to clearly illustrate the positional relationship between the fourth electrode 142 and the second semiconductor layer 112, Figure 1 Middle 1b, Figure 4 4b and Figure 6 In Figure 6b, the fourth electrode 142 is drawn in a perspective manner.

[0108] The second direction Y and the first direction X are both parallel to the surface of the substrate 100 , that is, the second direction Y and the first direction X are both perpendicular to the third direction Z, and, Figures 1 to 9 In the examples, the first direction X and the second direction Y are perpendicular to each other. In actual applications, the first direction X and the second direction Y can intersect.

[0109] To sum up, on the one hand, the first transistor 101 is a dual-gate transistor, that is, the threshold voltage of the first transistor 101 is jointly controlled by the first gate 121 and the second gate 131, which is conducive to flexibly controlling the conduction or shutdown of the first transistor 101 to improve the electrical performance of the memory cell structure; on the other hand, the first transistor 101 and the second transistor 102 together constitute a memory cell structure, without the need for a capacitor device, which is conducive to reducing the size of the memory cell structure itself to improve the integration density of the memory cell structure; on the other hand, the first transistor 101 can be used as a read transistor, the second transistor 102 can be used as a write transistor, and the third electrode 132 is electrically connected to the first gate 121, then the second transistor 102 can affect the potential at the first gate 121, and the first transistor 101 is affected by the first gate 121 and the second gate 131 to present different threshold voltages for representing data 1 and data 0, respectively, thereby realizing a 2T0C type memory cell structure.

[0110] Another embodiment of the present disclosure further provides an operating method for a memory cell structure, which is used to operate the memory cell structure provided by an embodiment of the present disclosure. Figure 10 A simplified circuit diagram of operating a memory cell structure according to another embodiment of the present disclosure is provided.

[0111] Combined with reference Figure 1 and Figure 10 The operating method of the memory cell structure includes: providing the aforementioned memory cell structure, wherein the electrically connected third electrode 132 and the first gate 121 constitute a storage node SN; and performing a write operation or a read operation on the storage node SN.

[0112] It can be understood that the first transistor 101 is a read transistor and the second transistor 102 is a write transistor. From a circuit perspective, the first transistor 101 is a dual-gate transistor. The first transistor 101 and the second transistor 102 together form a 2T0C type memory cell structure, which facilitates the use of the two gates of the first transistor 101 to respectively complete data storage and read and write operation control. Based on the advantages of gate-controlled read and write operations, the read and write operations of the constructed 2T0C type memory cell structure are more flexible.

[0113] In addition, it can be seen from the above analysis that the threshold voltage of the first transistor 101 will also be affected by the usage time. By adjusting the potential at the second gate 131, the first transistor 101 can still be in a critical state of conduction when the potential at the first gate 121 remains unchanged, so as to avoid the deviation between data writing and reading, so as to ensure the normal operation of the storage unit structure. It can be understood that by designing the first transistor 101 as a dual-gate transistor, it is beneficial to more flexibly control the storage unit structure through the second gate 131, which is beneficial to improving the service life of the storage unit structure.

[0114] The following describes in detail how to use the two gates of the first transistor 101 to respectively complete data storage and read / write operation control.

[0115] In some embodiments, reference Figure 1 and Figure 10 In Figure 10a, performing a write operation on the storage node SN may include: providing a first voltage V1 to the third gate 122, providing a second voltage V2 to the fourth electrode 142 and the second electrode 151, and providing a third voltage V3 to the first electrode 141, so as to perform a write operation on the storage node SN; wherein the first voltage V1 is the turn-on voltage of the second transistor 102, and the difference in potential at the storage node SN results in a difference in the threshold voltage of the first transistor 101; during the write operation on the storage node SN, no voltage signal is provided to the second gate 131.

[0116] It is understood that the method of providing the second voltage V2 to both the fourth electrode 142 and the second electrode 151 includes electrically connecting the fourth electrode 142 and the second electrode 151 to the same conductive structure, which provides the second voltage V2 to the fourth electrode 142 and the second electrode 151. In this way, by sharing the same potential between the fourth electrode 142 and the second electrode 151, the overall size of the memory cell structure and the complexity of the wiring in the memory cell structure are further reduced.

[0117] In some embodiments, the higher the potential at the storage node SN, the lower the threshold voltage of the first transistor 101. Thus, when writing data 1 to the memory cell structure, the second voltage V2 is at a high level, the third voltage V3 is at a ground voltage, and after the first voltage V1 is supplied to the third gate 122, the second transistor 102 is turned on, causing the potential at the storage node SN to approach the second voltage V2, i.e., the potential at the storage node SN is at a high level. When writing data 0 to the memory cell structure, the second voltage V2 is at a low level, the third voltage V3 is at a ground voltage, and after the first voltage V1 is supplied to the third gate 122, the second transistor 102 is turned on, causing the potential at the storage node SN to approach the second voltage V2, i.e., the potential at the storage node SN is at a low level.

[0118] In some embodiments, reference Figure 1 and Figure 10 In Figure 10b, the reading operation on the storage node SN may include: providing a fourth voltage V4 to the second gate 131, providing a third voltage V3 to the first electrode 141, detecting the current in the first transistor 101 through the second electrode 151 to determine the potential stored at the storage node SN, so as to perform a reading operation on the storage node SN; during the reading operation on the storage node SN, no voltage signal is provided to the third gate 122.

[0119] It can be understood that after the fourth voltage V4 is provided to the second gate 131, when the potential at the storage node SN is at a high level, the threshold voltage of the first transistor 101 is low, so that the conduction degree of the first transistor 101 is relatively high. In this way, the current in the first transistor 101 detected through the second electrode 151 is relatively large, and the data stored at the storage node SN is determined to be 1 based on the larger current value read; when the potential at the storage node SN is at a low level, the threshold voltage of the first transistor 101 is high, so that the conduction degree of the first transistor 101 is relatively small, or the first transistor 101 will not be turned on. In this way, the current in the first transistor 101 detected through the second electrode 151 is relatively small, or there is no current, and the data stored at the storage node SN is determined to be 0 based on the smaller current value read.

[0120] In some embodiments, the level of the fourth voltage V4 can be adjusted according to the usage time of the memory cell structure.

[0121] It can be understood that the threshold voltage of the first transistor 101 will also be affected by the usage time. By adjusting the potential at the second gate 131, that is, adjusting the level value of the fourth voltage V4, the potential at the storage node SN is kept unchanged, so as to ensure that the threshold voltage of the first transistor 101 at this time is consistent with the threshold voltage of the first transistor 101 that is not affected by the usage time, so as to avoid the deviation between the writing and reading of data, so as to ensure the normal operation of the storage cell structure. In this way, by designing the first transistor 101 as a dual-gate transistor, it is beneficial to more flexibly control the storage cell structure through the second gate 131, so as to improve the service life of the storage cell structure.

[0122] It should be noted that in the above description of high level and low level, the high level can be a level value greater than or equal to the power supply voltage, and the low level can be a level value less than or equal to the ground voltage. Moreover, the high level and the low level are relative, and the specific level value ranges included in the high level and the low level can be determined according to the specific device. For example, for an NMOS transistor, the high level refers to the level value range of the gate voltage that can turn on the NMOS transistor, and the low level refers to the level value range of the gate voltage that can turn off the NMOS transistor; for a PMOS transistor, the low level refers to the level value range of the gate voltage that can turn on the PMOS transistor, and the high level refers to the level value range of the gate voltage that can turn off the PMOS transistor. In addition, the high level can be the data 1 in the above description, and the low level can be the data 0 in the above description.

[0123] In summary, the first transistor 101 is a dual-gate transistor, which facilitates utilizing the two gates of the first transistor 101 to separately perform data storage and read / write operation control. Based on the advantages of gate-controlled read / write operations, the read / write operations of the constructed 2TOC type memory cell structure are more flexible. In addition, by adjusting the potential at the second gate 131, the threshold voltage of the first transistor 101 remains unchanged when the potential at the storage node SN remains unchanged, thereby avoiding deviations between data writing and reading, achieving more flexible control of the memory cell structure, and improving the service life of the memory cell structure.

[0124] Another embodiment of the present disclosure further provides a memory array structure, comprising: a plurality of memory cell structures as described in an embodiment of the present disclosure, wherein the plurality of memory cell structures are spaced apart and arranged in an array along a first direction X and a second direction Y. Figure 1 and Figure 11 A storage array structure provided in yet another embodiment of the present disclosure is described in detail. Figure 11 A schematic diagram of a three-dimensional structure of a storage array structure provided in yet another embodiment of the present disclosure.

[0125] It should be noted that the parts that are the same as or corresponding to an embodiment of the present disclosure are not repeated here. Figure 11 The first semiconductor layer 111 and the second semiconductor layer 112 are filled in the same filling manner. It can be understood that the material of the first semiconductor layer 111 and the material of the second semiconductor layer 112 can be the same or different.

[0126] Combined with reference Figure 1 and Figure 11 The memory array structure includes a plurality of memory cell structures spaced apart and arranged in an array along a first direction X and a second direction Y, wherein the first direction X and the second direction Y are both parallel to the surface of the substrate 100 and intersect with each other; a first word line WWL extending along the first direction X, and a plurality of third gates 122 spaced apart and arranged along the first direction X are electrically connected to the same first word line WWL; a bit line BL extending along the second direction Y, and the same bit line BL includes a plurality of fourth electrodes 142 spaced apart and arranged along the second direction Y (refer to Figure 1 ); a third electrical connection layer 134, a third electrical connection layer 134 contacts and connects a bit line BL and a second electrode 151; a second word line RWL extending along the first direction X, and a plurality of second gates 131 spaced apart along the first direction X are electrically connected to the same second word line RWL.

[0127] In some embodiments, the third gate 122 is higher than the second semiconductor layer 112 in terms of the top surface away from the substrate 100 . This facilitates electrical contact between the first word line WWL and the third gate 122 , and creates a gap between the first word line WWL and the second semiconductor layer 112 .

[0128] Moreover, any memory cell structure in the memory array structure is controlled by two word lines (a first word line WWL and a second word line RWL) and one bit line BL, which reduces the number of bit lines required for the memory cell structure, and is conducive to further reducing the overall size of the memory cell structure and reducing the wiring complexity in the memory array structure, thereby helping to further improve the integration density of the memory array structure.

[0129] In addition, the second word line RWL in the storage array structure and the second gate 131 in the first transistor 101 are electrically connected, so the magnitude of the current flowing through the second word line RWL is very small, and the current can be considered to be 0. The current flowing through the second word line RWL will not affect the number of first transistors 101 electrically connected to the same second word line RWL, which is beneficial to improving the storage density of the storage array structure.

[0130] For the sake of simplicity of illustration, Figure 11 Only one storage unit structure is shown in FIG. Figure 1 The first electrode 141 and the second electrode 151, as well as the electrical connection between the second electrode 151 and the bit line BL, can be understood that the memory cell structure in the memory array structure provided in another embodiment of the present disclosure can be any one of the memory cell structures provided in an embodiment of the present disclosure, not limited to Figure 1 The memory cell structure shown, and Figure 11 Only one electrical connection method between the second electrode 151 and the bit line BL is illustrated. In the memory array structure provided in another embodiment of the present disclosure, the specific structure of the third electrical connection layer 134 is not limited.

[0131] It should be noted that Figure 11 In the example, three memory cell structures are arranged at intervals along the first direction X and two memory cell structures are arranged along the second direction Y. In actual applications, there is no limit on the number of memory cell structures arranged at intervals along the first direction X, and there is no limit on the number of memory cell structures arranged along the second direction Y. In addition, in order to clearly illustrate the positional relationship between the first word line WWL, the bit line BL, the second word line RWL, and the memory cell structure, Figure 11 In the figure, the first word line WWL, the bit line BL and the second word line RWL are all drawn in a perspective manner.

[0132] In some embodiments, reference Figure 11, the second word line RWL is in electrical contact with the sidewall of the second gate 131 extending along the third direction Z; in other embodiments, the second word line RWL may be in electrical contact with the bottom surface of the second gate 131 close to the substrate. It is understood that if the memory cell structure is as follows Figure 1 or Figure 4 As shown, the second word line RWL is electrically contacted with the second gate 131 near the bottom surface of the substrate, which is beneficial to increase the contact area between the second word line RWL and the second gate 131 and reduce the contact resistance between the two. If the memory cell structure is as shown Figure 6 As shown, the second word line RWL is in electrical contact with the sidewall of the second gate 131 extending along the third direction Z. Moreover, the second word line RWL may circumferentially surround a portion of the sidewall of the second gate 131 .

[0133] In some embodiments, the first transistors 101 are arranged in a square along the first direction X and the second direction Y, and the second transistors 102 are arranged in a square along the first direction X and the second direction Y. It is understood that the second transistor 102 can be located directly above the first transistor 101. In this case, the first transistor 101 and the second transistor 102 are both arranged in a square, which is beneficial for reducing the spacing between adjacent memory cell structures, thereby further improving the integration density of the memory cell array structure.

[0134] In some embodiments, the first electrode 141 of any memory cell structure is grounded, so that multiple first electrodes 141 can be electrically connected together. A second electrode 151 needs to be electrically connected to the bit line BL electrically connected to the corresponding second transistor 102.

[0135] In summary, the storage array structure provided in another embodiment of the present disclosure is conducive to reducing its wiring complexity and improving its storage density.

[0136] Another embodiment of the present disclosure further provides a method for operating a storage array structure, which is used to operate the storage array structure provided by another embodiment of the present disclosure. Figures 11 to 12 An operating method of a storage array structure provided in yet another embodiment of the present disclosure is described in detail. Figure 12 A simplified circuit diagram of operating a storage array structure according to yet another embodiment of the present disclosure.

[0137] It should be noted that the parts that are the same as or corresponding to another embodiment of the present disclosure are not repeated here.

[0138] refer to Figure 11 and Figure 12The operating method of the memory array structure includes: providing the aforementioned memory array structure, wherein the memory array structure includes a plurality of first word lines WWL arranged at intervals along a second direction Y, a plurality of bit lines BL arranged at intervals along a first direction X, and a plurality of second word lines RWL arranged at intervals along a second direction Y; and performing a write operation or a read operation on any memory cell structure in the memory array structure.

[0139] In some embodiments, reference Figure 11 and Figure 12 In step 12a, performing a write operation on any storage cell structure in the storage array structure may include the following steps:

[0140] A first voltage V1 is provided to a first word line WWL, and a second voltage V2 is provided to a bit line BL to select a memory cell structure. Figure 12 The memory cell structure composed of the marked first transistor 101 and the second transistor 102 is taken as the selected memory cell structure.

[0141] A third voltage V3 is supplied to the first electrode 141 in the selected memory cell structure to perform a write operation on the selected memory cell structure; wherein the first voltage V1 is the on-state voltage of the first transistor 101 in the selected memory cell structure. During the write operation on the selected memory cell structure, no voltage signal is supplied to any second word lines RWL, and no voltage is supplied to the remaining first word lines WWL and the remaining bit lines BL. It will be understood that the write operation on the selected memory cell structure is similar to the write operation on the memory cell structure in another embodiment of the present disclosure and will not be further described here.

[0142] In some embodiments, reference Figure 11 and Figure 12 In step 12b, performing a read operation on any memory cell structure in the memory array structure may include the following steps:

[0143] A fourth voltage V4 is supplied to a second word line RWL, and a current in a selected memory cell structure is read through a bit line BL to perform a read operation on the selected memory cell structure, wherein the selected memory cell structure is determined by the second word line RWL supplied with the fourth voltage V4 and the bit line BL from which the current is read. Figure 12 The memory cell structure composed of the marked first transistor 101 and the second transistor 102 is taken as the selected memory cell structure.

[0144] During a read operation on a selected memory cell structure, no voltage signal is provided to all first word lines WWL, and no voltage is provided to the remaining second word lines RWL. It will be appreciated that the read operation on the selected memory cell structure is similar to the read operation on the memory cell structure in another embodiment of the present disclosure, and will not be further described here.

[0145] In summary, the operating method of a memory array structure provided in yet another embodiment of the present disclosure facilitates utilizing the two gates of the first transistor 101 to separately perform data storage and read / write operation control, thereby making the read / write operations of the memory cell structure more flexible. Furthermore, by adjusting the fourth voltage V4 provided by the second word line RWL, the threshold voltage of the first transistor 101 remains unchanged while the potential at the storage node SN remains unchanged, thereby avoiding deviations between data writing and reading, achieving more flexible control of the memory cell structure, and improving the service life of the memory cell structure.

[0146] Yet another embodiment of the present disclosure further provides a method for manufacturing a memory cell structure, which is used to prepare the memory cell structure provided by an embodiment of the present disclosure. Figures 13 and 14 This is a schematic diagram of the cross-sectional structures corresponding to each step in the manufacturing method of the storage cell structure provided in another embodiment of the present disclosure. The manufacturing method of the semiconductor structure provided in this embodiment will be described in detail in conjunction with the accompanying drawings. The parts that are the same as or corresponding to the above embodiments will not be described in detail below.

[0147] It should be noted that Figure 13 and Figure 14 To form Figure 1 The memory cell structure shown is an example. In actual applications, the method of forming various memory cell structures provided by an embodiment of the present disclosure is as follows: Figure 13 and Figure 14 The manufacturing steps shown are similar and can be flexibly adjusted according to existing manufacturing process technology.

[0148] refer to Figure 13 In step 13a, a substrate 100 is provided, and a first isolation layer 113 is formed on the surface of the substrate 100. The first isolation layer 113 has a first through hole (not shown in the figure). It is understood that the orthographic projection of the first through hole on the substrate 100 can be circular, rectangular or other shapes.

[0149] Continue to refer Figure 13 In FIG13a, a second gate 131 is conformally covered on the sidewalls of the first through hole extending in the third direction Z and the bottom surface parallel to the first direction X. In practical applications, the second gate may also be formed only on the sidewalls of the first through hole extending in the third direction.

[0150] refer to Figure 13In the middle 13b, a second gate dielectric layer 171 is formed, and the second gate dielectric layer 171 conformally covers the inner side of the second gate 131 away from the first isolation layer 113. In practical applications, when the second gate is located only on the sidewall of the first through hole extending in the third direction Z, the second gate dielectric layer may also be located only on the sidewall of the second gate extending in the third direction Z.

[0151] Continue to refer Figure 13 In the middle 13b, a first semiconductor layer 111 is formed, and the first semiconductor layer 111 conformally covers the inner side of the second gate dielectric layer 171 away from the second gate electrode 131. In practical applications, the first semiconductor layer may also be formed only on the sidewall of the second gate dielectric layer extending along the third direction Z.

[0152] refer to Figure 13 In 13c, an initial first gate dielectric layer 181 is formed, and the initial first gate dielectric layer 181 fills the second through hole 105 surrounded by the first semiconductor layer 111 (refer to Figure 13 13b).

[0153] Combined with reference Figure 13 In Figures 13c and 13d, the first isolation layer 113 and the initial first gate dielectric layer 181 are patterned to form a first groove 115 and a second groove 125 spaced apart from each other, as well as a first gate dielectric layer 161 in the remaining first isolation layer 113. It can be understood that the initial first gate dielectric layer 181 remaining after the patterning serves as the first gate dielectric layer 161, and the first gate dielectric layer 161 conformally covers the inner side of the first semiconductor layer 111 away from the second gate dielectric layer 171.

[0154] It is understood that the first recess 115 and the second recess 125 are subsequently used to form the first electrode and the second electrode, respectively, and the third through-hole 135 enclosed by the first gate dielectric layer 161 is subsequently used to form the first gate. In this step, the first isolation layer 113 and the initial first gate dielectric layer 181 are patterned together, which facilitates the subsequent formation of the first electrode, the second electrode, and the first gate in the same step, thereby simplifying the process steps for forming the memory cell structure. Furthermore, during the steps of forming the first recess 115, the second recess 125, and the third through-hole 135, the dimensions of the first recess 115 and the second recess 125 can be controlled to ensure that the subsequently formed first and second electrodes have a large cross-sectional area in a plane perpendicular to the third direction Z.

[0155] It should be noted that Figure 13 The first groove 115 and the second groove 125 shown in FIG13 d are opposite to each other along the first direction X. In practical applications, it is sufficient for the first groove 115 and the second groove 125 to be spaced apart from each other.

[0156] Combined with reference Figure 13In the middle 13d and 13e, the first electrode 141, the second electrode 151 and the first gate 121 are formed. The first electrode 141 fills the first groove 115, the second electrode 151 fills the second groove 125, and the first gate 121 fills the third through hole 135.

[0157] refer to Figure 13 In Figure 13f, a first electrical connection layer 114 and a second electrical connection layer 124 are formed. One end of the first electrical connection layer 114 is in contact with the first electrode 141, and the other end of the first electrical connection layer 114 is in contact with a portion of the first top surface 111c of the first semiconductor layer 111. One end of the second electrical connection layer 124 is in contact with the second electrode 151, and the other end of the second electrical connection layer 124 is in contact with another portion of the first top surface 111c of the first semiconductor layer 111. Furthermore, a gap exists between the first electrical connection layer 114 and the first gate 121, and a gap also exists between the second electrical connection layer 124 and the first gate 121.

[0158] It should be noted that Figure 13 The first electrical connection layer 114 and the second electrical connection layer 124 shown in Figure 13f are only an example. In actual applications, any conductive structure that meets the above requirements can be used as the first electrical connection layer 114 and the second electrical connection layer 124, and the manufacturing method of the storage unit structure provided in another embodiment of the present disclosure does not limit the manufacturing process of the first electrical connection layer 114 and the second electrical connection layer 124.

[0159] refer to Figure 13 In step 13h, a second isolation layer 123 is formed. The second isolation layer 123 fills the gap between the first electrical connection layer 114 and the second electrical connection layer 124, and the second isolation layer 123 has a fourth through hole 145. The fourth through hole 145 exposes the first gate 121 away from the top surface of the substrate 100.

[0160] Combined with reference Figure 13 In 13h and 13g , the third electrode 132 is formed. The third electrode 132 completely fills the fourth through hole 145 , and the third electrode 132 is also located on a portion of the top surface of the second isolation layer 123 away from the substrate 100 .

[0161] It can be understood that the cross-sectional shape of the third electrode 132 on a plane perpendicular to the second direction Y is T-shaped.

[0162] Combined with reference Figure 13 13g and Figure 14 In 14a, an initial third isolation layer (not shown) and an initial fourth electrode (not shown) stacked along a third direction Z are formed, the initial third isolation layer covers the second isolation layer 123 and the third electrode 132 on the side away from the substrate 100, and the initial fourth electrode is located on the side of the initial third isolation layer away from the substrate 100.

[0163] refer to Figure 14 In step 14a, the initial third isolation layer and the initial fourth electrode are patterned to form a fifth through hole 155, which exposes the third electrode 132. The remaining initial third isolation layer serves as the third isolation layer 133, and the remaining initial fourth electrode serves as the fourth electrode 142.

[0164] In some embodiments, during the step of patterning the initial third isolation layer and the initial fourth electrode, a portion of the thickness of the third electrode 132 may also be patterned along the third direction Z, i.e., the fifth through hole 155 penetrates a portion of the thickness of the third electrode 132. In other embodiments, only the initial third isolation layer and the initial fourth electrode may be patterned, i.e., the fifth through hole only exposes the top surface of the third electrode away from the substrate.

[0165] It is understood that the orthographic projection of the fifth through hole 155 on the substrate 100 may be circular, rectangular or other shapes. The first isolation layer 113 , the second isolation layer 123 and the third isolation layer 133 together constitute the isolation layer 103 .

[0166] refer to Figure 14 In Figure 14b, a second semiconductor layer 112 is conformally covered on the sidewalls of the fifth through hole 155 extending along the third direction Z and the bottom surface parallel to the first direction X. In practical applications, the second semiconductor layer may also be formed only on the sidewalls of the first through hole extending along the third direction.

[0167] refer to Figure 14 In middle 14 c , a third gate dielectric layer 152 is formed. The third gate dielectric layer 152 conformally covers the inner side of the second semiconductor layer 112 away from the third isolation layer 133 . The third gate dielectric layer 152 surrounds a sixth through hole 165 .

[0168] Combined with reference Figure 14 In the middle 14 c and 14 d , the third gate 122 is formed, and the third gate 122 fills the sixth through hole 165 .

[0169] For clarity of illustration, Figure 14 The first semiconductor layer 111 and the second semiconductor layer 112 are filled in the same filling manner. It can be understood that the material of the first semiconductor layer 111 and the material of the second semiconductor layer 112 can be the same or different; Figure 14 The first gate 121 and the second gate 122 are filled in the same filling manner. It can be understood that the material of the first gate 121 and the material of the second gate 122 can be the same or different.

[0170] In summary, the manufacturing method of the memory cell structure provided by another embodiment of the present disclosure is conducive to forming the first transistor 101 as a dual-gate transistor (refer to Figure 1 ), that is, the threshold voltage of the first transistor 101 is jointly controlled by the first gate 121 and the second gate 131, which is conducive to flexibly controlling the conduction or cutoff of the first transistor 101 to improve the electrical performance of the memory cell structure; on the other hand, the formed memory cell structure does not require a capacitor device, which is conducive to reducing the size of the memory cell structure itself to improve the integration density of the memory cell structure.

[0171] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A memory cell structure, characterized in that: include: substrate; a first transistor located on the surface of the substrate, the first transistor comprising a first semiconductor layer, a first gate and a second gate located on opposite sides of the first semiconductor layer, a first electrode and a second electrode electrically connected to different regions of the first semiconductor layer, a first gate dielectric layer, and a second gate dielectric layer, wherein the first gate, the second gate, the first electrode, and the second electrode are insulated from each other, and the first semiconductor layer has a first inner side and a first outer side that are opposite; a second transistor located on a side of the first transistor away from the substrate, the second transistor comprising a second semiconductor layer, a third gate, and a third electrode and a fourth electrode electrically connected to different regions of the second semiconductor layer, the third electrode also being electrically connected to the first gate, and the third gate, the third electrode, and the fourth electrode being insulated from each other; The second gate dielectric layer covers an area of ​​the first outer side extending in a direction perpendicular to the substrate surface, the first electrode is directly opposite to a portion of a sidewall of the first gate dielectric layer in the direction perpendicular to the substrate surface, and the second electrode is directly opposite to a portion of another sidewall of the first gate dielectric layer; an isolation layer, the isolation layer being located between the first electrode and the second gate dielectric layer, and between the second electrode and the second gate dielectric layer; a first electrical connection layer, wherein one end of the first electrical connection layer is electrically in contact with the first electrode, and the other end of the first electrical connection layer is electrically in contact with a portion of the first top surface of the first semiconductor layer; A second electrical connection layer, wherein one end of the second electrical connection layer is electrically in contact with the second electrode, and the other end of the second electrical connection layer is electrically in contact with a portion of the other first top surface of the first semiconductor layer.

2. The memory cell structure according to claim 1, wherein: The first semiconductor layer encloses a first chamber, wherein the first chamber is a chamber having a first opening, or the first chamber is a chamber having two first openings arranged opposite to each other; The first gate is opposite to at least a portion of the first inner side, and the second gate is opposite to at least a portion of the first outer side; The first gate dielectric layer is located between the first gate electrode and the first semiconductor layer; the second gate dielectric layer is located between the second gate electrode and the first semiconductor layer.

3. The memory cell structure according to claim 1, wherein: The second semiconductor layer encloses a second chamber, and the second chamber is a chamber having a second opening, or the second chamber is a chamber having two second openings arranged opposite to each other; The second semiconductor layer has a second inner side and a second outer side opposite to each other, and the third gate is directly opposite to a portion of the second inner side; The second transistor further includes a third gate dielectric layer located between the third gate and the second semiconductor layer.

4. The memory cell structure according to claim 3, wherein: Along a direction perpendicular to the surface of the substrate, the second semiconductor layer includes a first portion, a second portion and a third portion, and the first portion does not directly face the third gate; The fourth electrode surrounds the second outer side of the third portion; In a direction perpendicular to the surface of the substrate, the third electrode surrounds at least a portion of the height of the second outer side of the first portion, and / or the third electrode is in contact with and connected to the second bottom surface of the second semiconductor layer near the substrate; The storage unit structure further includes: An isolation layer surrounds the second outer side of the second portion.

5. The memory cell structure according to claim 1, wherein: The orthographic projection of the first gate on the substrate is located in the orthographic projection of the third electrode on the substrate.

6. The memory cell structure according to any one of claims 1 to 5, characterized in that: The material of the first semiconductor layer includes at least one of IGZO and ITO, and the material of the second semiconductor layer includes at least one of IGZO and ITO.

7. A method for operating a memory cell structure, characterized in that: include: There is provided a memory cell structure according to any one of claims 1 to 6, wherein the electrically connected third electrode and the first gate constitute a storage node; Perform a write operation or a read operation on the storage node.

8. The method for operating the memory cell structure according to claim 7, wherein: Performing the write operation on the storage node includes: providing a first voltage to the third gate, providing a second voltage to the fourth electrode and the second electrode, and providing a third voltage to the first electrode, so as to perform the write operation on the storage node; The first voltage is a turn-on voltage of the second transistor, and the difference in potential at the storage node results in a difference in threshold voltage of the first transistor; During the write operation on the storage node, no voltage signal is provided to the second gate.

9. The method for operating the memory cell structure according to claim 8, wherein: Performing the read operation on the storage node includes: providing a fourth voltage to the second gate and a third voltage to the first electrode, detecting a current in the first transistor via the second electrode to determine a potential stored at the storage node, and performing the read operation on the storage node; During the reading operation on the storage node, no voltage signal is provided to the third gate.

10. The method for operating the memory cell structure according to claim 9, wherein: The level of the fourth voltage is adjusted according to the usage time of the memory cell structure.

11. A storage array structure, characterized in that: include: A plurality of memory cell structures according to any one of claims 1 to 6, wherein the plurality of memory cell structures are spaced apart and arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are both parallel to the substrate surface, and the first direction and the second direction intersect; a first word line extending along the first direction, wherein a plurality of the third gates spaced apart and arranged along the first direction are electrically connected to the same first word line; a bit line extending along the second direction, wherein the same bit line includes a plurality of the fourth electrodes arranged at intervals along the second direction; a third electrical connection layer, wherein the third electrical connection layer is in contact with and connected to the bit line and the second electrode; A second word line extends along the first direction, and a plurality of second gates arranged at intervals along the first direction are electrically connected to the same second word line.

12. The storage array structure according to claim 11, wherein: The first transistors are arranged in a quadrilateral along the first direction and the second direction, and the second transistors are arranged in a quadrilateral along the first direction and the second direction.

13. A method for operating a storage array structure, characterized in that: include: A memory array structure according to any one of claims 11 to 12, wherein the memory array structure comprises a plurality of first word lines arranged at intervals along the second direction, a plurality of bit lines arranged at intervals along the first direction, and a plurality of second word lines arranged at intervals along the second direction; A write operation or a read operation is performed on any of the storage cell structures in the storage array structure.

14. The method for operating a storage array structure according to claim 13, wherein: Performing the write operation on any of the storage cell structures in the storage array structure includes: providing a first voltage to one of the first word lines and a second voltage to one of the bit lines to select one of the memory cell structures, and providing a third voltage to the first electrode in the selected memory cell structure to perform the write operation on the selected memory cell structure; Wherein, the first voltage is the turn-on voltage of the second transistor in the selected memory cell structure; During the write operation on the selected memory cell structure, no voltage signal is provided to all the second word lines, and no voltage is provided to the remaining first word lines and the remaining bit lines.

15. The method for operating a storage array structure according to claim 14, wherein: Performing the read operation on any of the storage cell structures in the storage array structure includes: providing a fourth voltage to one of the second word lines, and reading a current in a selected one of the memory cell structures through one of the bit lines, so as to perform the read operation on the selected memory cell structure, wherein the selected memory cell structure is determined by the second word line provided with the fourth voltage and the bit line from which the current is read; During the read operation on the selected memory cell structure, no voltage signal is provided to all the first word lines, and no voltage is provided to the remaining second word lines.

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