Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a substrate, a plurality of active regions arranged in an interval manner; a plurality of bit lines arranged in an interval manner on the substrate; the bit line comprises a bit line conductive layer and a bit line dielectric layer which are stacked; the bit line has a first part and a second part; the first part is located at the overlapping part of the bit line and the active region, and the second part is located between adjacent active regions; the top surface of the bit line conductive layer of the second part is lower than the top surface of the bit line conductive layer of the first part; and a plurality of bit line contact structures are located between the first part and the active region. The semiconductor structure sets the bit line as the first part which overlaps with the active region and the second part which is located between adjacent active regions, and sets the top surface of the bit line conductive layer of the second part as lower than the top surface of the bit line conductive layer of the first part, so that the relative cross-sectional area of adjacent bit lines is reduced, and the coupling capacitance effect between adjacent bit lines is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] With the continuous development of semiconductor integrated circuit device technology, the pursuit of products with high electrical performance has become a long-standing goal.

[0003] However, in existing process technologies, a large coupling capacitance effect is easily formed between adjacent bit lines (BL), which seriously affects electrical performance. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the deficiencies in the prior art.

[0005] In one aspect, the present disclosure provides a semiconductor structure comprising:

[0006] A substrate comprising a plurality of active regions arranged at intervals;

[0007] A plurality of bit lines are arranged in parallel and spaced apart on the substrate; the bit lines include a stacked bit line conductive layer and a bit line dielectric layer; the bit lines have a first portion and a second portion; wherein the first portion is located at an intersection of the bit line and the active region, the second portion is located between adjacent active regions, and a top surface of the bit line conductive layer in the second portion is lower than a top surface of the bit line conductive layer in the first portion;

[0008] A plurality of bit line contact structures are located between the first portion and the active area.

[0009] In some embodiments, the substrate includes a shallow trench isolation structure located between the active regions;

[0010] The top of the shallow trench isolation structure has a plurality of spaced-apart bit line grooves, the projections of the bit line grooves on the substrate at least partially overlap with the projections of the bit lines on the substrate; the bit line conductive layer of the second portion is located in the bit line grooves.

[0011] In some embodiments, the semiconductor structure further comprises:

[0012] An isolation layer is located between the second portion and the sidewall of the bit line groove and between the second portion and the bit line contact structure.

[0013] In some embodiments, the top surfaces of the multiple bit line contact structures corresponding to the same bit line are flush; the top surface of the bit line contact structure is higher than the top surface of the substrate; the top surface of the bit line conductive layer of the second part of the bit line is higher than the bit line contact structure, and higher than the bottom surface of the bit line conductive layer of the first part of the bit line.

[0014] In some embodiments, in the vertical direction, a height difference between a top of the first portion and a top of the second portion is less than a maximum thickness of the first portion.

[0015] In some embodiments, the semiconductor structure further comprises:

[0016] A plurality of word lines are arranged in parallel and spaced apart in the substrate;

[0017] The bit line contact structure covers the top of the word line.

[0018] In another aspect, the present disclosure further provides a method for preparing a semiconductor structure, comprising the following steps:

[0019] Providing a substrate; the substrate includes a plurality of active regions arranged at intervals;

[0020] forming a bit line contact structure in the substrate;

[0021] A plurality of bit lines arranged in parallel and spaced apart are formed on the substrate and electrically connected to the active area via the bit line contact structure; the bit line includes a stacked bit line conductive layer and a bit line dielectric layer; the bit line is formed with a first portion and a second portion; wherein the first portion is located at the intersection of the bit line and the active area, the second portion is located between adjacent active areas, and the top surface of the bit line conductive layer of the second portion is lower than the top surface of the bit line conductive layer of the first portion.

[0022] In some embodiments, a plurality of word lines arranged in parallel and spaced apart are formed in the substrate; and forming a bit line contact structure in the substrate includes:

[0023] forming spaced-apart bit line contact openings on the substrate; the bit line contact openings exposing the active areas between adjacent word lines;

[0024] A bit line contact structure is formed in the bit line contact opening.

[0025] In some embodiments, providing a substrate includes:

[0026] forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active areas arranged at intervals in the substrate;

[0027] The step of forming a plurality of bit lines arranged in parallel and spaced apart on the substrate comprises:

[0028] forming a plurality of spaced-apart bit line grooves on the substrate;

[0029] forming an isolation layer on a sidewall of the bit line groove;

[0030] A plurality of bit lines arranged in parallel and spaced apart are formed on the top of the shallow trench isolation structure; wherein the bit line conductive layer of the second portion is formed in the bit line groove, and the projection of the bit line on the substrate at least partially overlaps with the projection of the bit line groove on the substrate.

[0031] In some embodiments, after forming a shallow trench isolation structure in the substrate and before forming a bit line contact structure in the substrate, the method further includes: forming an etch stop material layer on the substrate;

[0032] Forming spaced-apart bit line contact openings on the substrate, comprising:

[0033] forming a bit line contact opening, wherein the bit line contact opening penetrates the etch stop material layer and extends into the substrate, and the retained etch stop material layer serves as an etch stop layer;

[0034] forming a bit line contact structure in the bit line contact opening, comprising:

[0035] forming a bit line contact material layer, wherein the bit line contact material layer fills the bit line contact opening and covers the etch stop layer;

[0036] removing a portion of the bit line contact material layer, so that the remaining bit line contact material layer and the etch stop layer together constitute the bit line contact structure;

[0037] Among them, the top surfaces of the multiple bit line contact structures corresponding to the same bit line are flush; the top surface of the bit line contact structure is higher than the top surface of the substrate; the top surface of the bit line conductive layer of the second part of the bit line is higher than the bit line contact structure, and higher than the bottom surface of the bit line conductive layer of the first part of the bit line.

[0038] The semiconductor structure and the method for manufacturing the same provided by the present disclosure have at least the following beneficial effects:

[0039] In the semiconductor structure and preparation method provided by the present disclosure, by setting the bit line to a first portion overlapping with the active area and a second portion between adjacent active areas, and setting the bit line conductive layer of the second portion of the bit line to have a top surface lower than the top surface of the bit line conductive layer of the first portion of the bit line, such a setting can reduce the relative cross-sectional area of ​​adjacent bit lines, thereby reducing the coupling capacitance effect between adjacent bit lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0042] Figure 2 A schematic flow chart of step S200 in the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0043] Figure 3 A schematic flow chart of step S300 in the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0044] Figure 4 A schematic flow chart of step S220 in the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0045] Figure 5 A schematic diagram of a process for forming a plurality of bit lines arranged in parallel and spaced apart in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0046] Figure 6 A schematic cross-sectional view of a structure obtained after forming a bit line contact opening in a method for preparing a semiconductor structure provided by some embodiments of the present disclosure;

[0047] Figure 7 A schematic cross-sectional view of a structure obtained after forming a bit line contact material layer in a method for preparing a semiconductor structure provided by some embodiments of the present disclosure;

[0048] Figure 8 A schematic cross-sectional view of a structure obtained after forming a bit line contact structure in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0049] Figure 9 Figure (a) is a schematic cross-sectional view of a structure obtained after forming a patterned photoresist layer in a method for preparing a semiconductor structure provided by some embodiments of the present disclosure; Figure 9 Figure (b) is Figure 9 (a) is a schematic top view of the structure shown in FIG.

[0050] Figure 10A schematic top view of a structure obtained after forming a patterned photoresist layer in a method for preparing a semiconductor structure provided in other embodiments of the present disclosure;

[0051] Figure 11 FIG. (a) is a schematic cross-sectional view of a structure obtained after forming a bit line groove in a method for preparing a semiconductor structure according to some embodiments of the present disclosure; Figure 11 Figure (b) is Figure 11 (a) is a schematic top view of the structure shown in FIG.

[0052] Figure 12 A schematic cross-sectional view of a structure obtained after forming an isolation material layer in a method for preparing a semiconductor structure provided by some embodiments of the present disclosure;

[0053] Figure 13 A schematic cross-sectional view of a structure obtained after forming an isolation layer in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0054] Figure 14 A schematic cross-sectional view of a structure obtained after forming a bit line conductive layer in a method for preparing a semiconductor structure provided by some embodiments of the present disclosure;

[0055] Figure 15 A schematic cross-sectional view of a structure obtained after forming a bit line in a method for preparing a semiconductor structure provided by some embodiments of the present disclosure;

[0056] Figure 16 A schematic cross-sectional view of a structure obtained after planarizing the top surface of a bit line dielectric layer in a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0057] Figure 17 A schematic cross-sectional view of a structure obtained after alternately stacking an oxide layer and a nitride layer on a bit line in a method for fabricating a semiconductor structure provided by some embodiments of the present disclosure;

[0058] Figure 18 FIG. (a) is a schematic cross-sectional view of a structure obtained after two oxide layers and one nitride layer are alternately stacked on a bit line in a method for fabricating a semiconductor structure according to some embodiments of the present disclosure; Figure 18 Figure (b) is Figure 18 (a) is a schematic top view of the structure shown in FIG. Figure 18 Figure (a) is also a schematic diagram of the cross-sectional structure of the semiconductor structure provided in the AA' direction according to some embodiments of the present disclosure;

[0059] Figure 19 FIG. (a) is a schematic cross-sectional view of a structure obtained after forming a bit line in a method for preparing a semiconductor structure according to some embodiments of the present disclosure; Figure 19 Figure (b) is Figure 19 (a) is a schematic top view of the structure shown in FIG. Figure 19 Figure (a) is also a schematic diagram of the cross-sectional structure of the semiconductor structure provided in the BB' direction according to some embodiments of the present disclosure.

[0060] Description of reference numerals:

[0061] 1. Substrate; 11. Active area; 12. Shallow trench isolation structure; 13. Etch stop layer; 14. Bit line groove; 14', second window pattern; 2. Bit line contact structure; 21. Bit line contact opening; 210. Patterned mask layer; 210A. Metal mask layer; 210B. Oxide mask layer; 22. Bit line contact material layer; 23. Patterned photoresist layer; 3. Bit line; 31. Bit line conductive layer; 32. Bit line dielectric layer; 331. Oxide layer; 332. Nitride layer; 34. Bit line isolation sidewall; 3A. First part; 3B. Second part; 4. Isolation layer; 4', Isolation material layer; 5. Word line; 51. Gate dielectric layer; 52. Word line conductive layer; 53. Filling dielectric layer. DETAILED DESCRIPTION

[0062] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0064] It should be understood that when an element or layer is referred to as being "on," "adjacent," or "electrically connected to," it can be directly on, adjacent, or electrically connected to the other element or layer, or there can be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure; for example, a first portion may be referred to as a second portion, and similarly, a second portion may be referred to as a first portion; the first portion and the second portion being different portions of a bit line.

[0065] Spatially relative terms such as "on..." may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "on..." will be oriented "under" the other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0066] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0067] While embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes are not intended to represent the actual shapes of regions of a device and are not intended to limit the scope of the present disclosure.

[0068] In view of the shortcomings of the prior art, the present disclosure provides a semiconductor structure and a method for manufacturing the same, which can reduce the coupling capacitance effect between adjacent bit lines. The details will be described in the subsequent embodiments.

[0069] According to some embodiments, the present disclosure provides a method for preparing a semiconductor structure.

[0070] See also Figure 1 In some embodiments, the method for preparing the semiconductor structure may specifically include the following steps:

[0071] S100: providing a substrate, wherein the substrate includes a plurality of active regions arranged at intervals.

[0072] S200: forming a bit line contact structure in a substrate.

[0073] S300: A plurality of bit lines are formed on a substrate and arranged in parallel and spaced apart arrangements. The bit lines are electrically connected to the active region via a bit line contact structure. The bit lines include a stacked bit line conductive layer and a bit line dielectric layer. The bit lines are formed into a first portion and a second portion. The first portion is located at the intersection of the bit line and the active region, and the second portion is located between adjacent active regions. The top surface of the bit line conductive layer in the second portion is lower than the top surface of the bit line conductive layer in the first portion.

[0074] In the method for preparing the semiconductor structure provided in the above embodiment, the bit line is formed with a first portion overlapping with the active area and a second portion located between adjacent active areas, and the bit line conductive layer of the second portion of the bit line is formed with a top surface lower than the top surface of the bit line conductive layer of the first portion of the bit line. Such a setting can reduce the relative cross-sectional areas of adjacent bit lines, thereby reducing the coupling capacitance effect between adjacent bit lines, which is beneficial to improving the electrical performance of the semiconductor structure.

[0075] See also Figure 2 In some embodiments, step S200 may specifically include the following steps:

[0076] S210: forming spaced-apart bit line contact openings on a substrate; the bit line contact openings expose the active area.

[0077] S220 : forming a bit line contact structure in the bit line contact opening.

[0078] In some embodiments, step S100 may specifically include the following steps: forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate.

[0079] See also Figure 3 In some embodiments, step S300 may specifically include the following steps:

[0080] S310: forming a plurality of spaced-apart bit line grooves on top of the shallow trench isolation structure.

[0081] S320: forming a plurality of bit lines arranged in parallel and spaced apart on the substrate; wherein the second portion of the bit line conductive layer is formed in the bit line groove, and the projection of the bit line on the substrate at least partially overlaps with the projection of the bit line groove on the substrate.

[0082] See also Figure 4 In some embodiments, step S220 may specifically include the following steps:

[0083] S221: forming a bit line contact material layer, wherein the bit line contact material layer fills the bit line contact opening and covers the etch stop layer.

[0084] S222: removing a portion of the bit line contact material layer, and the remaining bit line contact material layer and the etch stop layer together form a bit line contact structure.

[0085] See also Figure 5 In some embodiments, forming a plurality of bit lines spaced apart and arranged in parallel on a substrate may include the following steps:

[0086] S321: forming a stacked bit line conductive material layer and a bit line dielectric material layer on a substrate.

[0087] S322: etching the bit line dielectric material layer and the bit line conductive material layer to obtain a bit line dielectric layer and a bit line conductive layer, wherein the bit line conductive layer and the bit line dielectric layer together constitute a bit line.

[0088] It should be understood that although Figures 1 to 5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figures 1 to 5 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0089] In order to more clearly illustrate the preparation methods in some of the above embodiments, Figures 6 to 19 Understand some embodiments of the present disclosure.

[0090] In step S100, refer to Figure 6 , providing a substrate 1. The substrate 1 includes a plurality of active regions 11 arranged at intervals.

[0091] The embodiments of the present disclosure do not specifically limit the constituent materials of the substrate 1. As an example, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates; or, for example, the substrate 10 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI), or a silicon germanium on insulator.

[0092] As an example, Figure 6 As shown, a shallow trench isolation structure 12 can be formed in the substrate 1, and the shallow trench isolation structure 12 isolates a plurality of active regions 11 arranged at intervals in the substrate 1. Device structures requiring electrical leads, such as transistors, can also be formed in the substrate 1.

[0093] The present disclosure does not specifically limit the constituent material of the shallow trench isolation structure 12. As an example, the constituent material of the shallow trench isolation structure 12 may include silicon oxide (SiO2).

[0094] In some embodiments, please refer to Figure 6 , a plurality of word lines 5 arranged in parallel and spaced apart may also be formed in the substrate 1 .

[0095] In step S200, refer to Figures 6 to 8 , forming a bit line contact structure 2 in the substrate 1.

[0096] In some embodiments, step S200 of forming the bit line contact structure 2 in the substrate 1 may be specifically performed as follows: steps S210 to S220:

[0097] In step S210, please continue to refer to Figure 6 , bit line contact openings 21 are formed on the substrate 1 at intervals, and the bit line contact openings 21 can expose the active area 11 .

[0098] In step S220, refer to Figures 7 and 8 , forming a bit line contact structure 2 in the bit line contact opening 21 .

[0099] In some embodiments, please refer to Figure 6 The bit line contact openings 21 formed in step S210 may expose the active regions 11 between adjacent word lines 5 .

[0100] The present embodiment does not specifically limit the shape of the bit line contact opening 21 formed in step S210. As an example, the bit line contact opening 21 may include, but is not limited to, a circular hole, a rectangular hole, or an elliptical hole; and the longitudinal cross-sectional shape of the bit line contact opening 21 may include, but is not limited to, a rectangle.

[0101] The embodiment of the present disclosure does not specifically limit the method for forming the bit line contact openings 21 in step S210. In some embodiments, the following steps can be used to form the bit line contact openings 21 arranged at intervals on the substrate 1: Figure 6 As shown, a graphic mask layer 210 having a first window pattern is formed on the surface of the substrate 1, wherein the first window pattern can define the shape and position of the bit line contact opening 21 to be formed; the substrate 1 is etched based on the first window pattern to form the bit line contact opening 21.

[0102] The embodiment of the present disclosure does not specifically limit the manner of etching the substrate 1 based on the first window pattern. As an example, the substrate 1 may be etched using at least one of a dry etching process and a wet etching process to form the bit line contact opening 21 .

[0103] The present disclosure does not specifically limit the structure and material of the patterned mask layer 210. For example, Figure 6 As shown, the patterned mask layer 210 may include metal mask layers 210A and oxide mask layers 210B alternately stacked. The metal mask layers 210A may be made of, for example, at least one of titanium nitride (TiN) and tungsten (W). The oxide mask layers 210B may be made of, for example, silicon oxide.

[0104] In some embodiments, after forming the shallow trench isolation structure 12 in the substrate 1 , the following step may be further included: forming an etch stop material layer on the substrate 1 .

[0105] In some embodiments, please refer to Figure 6 In step S210, spaced-apart bitline contact openings 21 are formed on substrate 1. Specifically, bitline contact openings 21 are formed such that they penetrate the etch-stop material layer and extend into substrate 1. The remaining etch-stop material layer can serve as etch-stop layer 13.

[0106] The present embodiment does not specifically limit the material of the etch stop layer 13. As an example, the material of the etch stop layer 13 can be the same as or similar to the material of the bit line contact structure 2. For example, the material of the etch stop layer 13 can also include polysilicon.

[0107] In some embodiments, step S220 of forming the bit line contact structure 2 in the bit line contact opening 21 may be specifically performed as follows: steps S221 - S222 :

[0108] In step S221, refer to Figure 7 , forming a bit line contact material layer 22 , which fills the bit line contact opening 21 and covers the etch stop layer 13 .

[0109] In step S222, refer to Figure 8 , a portion of the bit line contact material layer 22 is removed, and the remaining bit line contact material layer 22 and the etch stop layer 13 together form a bit line contact structure 2.

[0110] The present embodiment does not specifically limit the constituent material of the bit line contact material layer 22 in step S221. As an example, the constituent material of the bit line contact material layer 22 may include, but is not limited to, polysilicon (Poly).

[0111] The embodiment of the present disclosure does not specifically limit the method for forming the bit line contact material layer 22 in step S221. As an example, a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process can be used to deposit the bit line contact material layer 22 in the bit line contact opening 21, and the bit line contact material layer 22 covers the etch stop layer 13. The CVD process can be, for example, an atmospheric pressure CVD (APCVD) process, a low pressure CVD (LPCVD) process, a plasma-enhanced CVD (PECVD) process, a high-density plasma CVD (HDP-CVD) process, and a radical-enhanced CVD (RECVD) process.

[0112] The embodiment of the present disclosure does not specifically limit the method of removing the portion of the bit line contact material layer 22 in step S222. As an example, the portion of the bit line contact material layer 22 can be removed by at least one of chemical mechanical masking, dry etching, and wet etching.

[0113] In step S300, refer to Figures 9 to 19 A plurality of bit lines 3 arranged in parallel and spaced apart are formed on the substrate 1 and electrically connected to the active area 11 via the bit line contact structure 2 .

[0114] like Figures 18 and 19 As shown, the bit line 3 may include a stacked bit line conductive layer 31 and a bit line dielectric layer 32 , and the bit line 3 is formed with a first portion 3A and a second portion 3B.

[0115] The present embodiment does not specifically limit the material constituting the bitline conductive layer 31. For example, the material constituting the bitline conductive layer 31 may be at least one of titanium nitride and tungsten. The present embodiment also does not specifically limit the material constituting the bitline dielectric layer 32. For example, the material constituting the bitline dielectric layer 32 may be a nitride material.

[0116] Please combine Figure 19 As shown in Figure (a), the first part 3A is located at the intersection of the bit line 3 and the active area 11, the second part 3B is located between adjacent active areas 11, and the top surface of the bit line conductive layer 31 of the second part 3B is lower than the top surface of the bit line conductive layer 31 of the first part 3A.

[0117] It should be noted that Figure 18 Figure (a) is Figure 18 The cross-sectional structure diagram of the structure shown in Figure (b) in the BB' direction, Figure 19 Figure (a) is Figure 19 (b) is a schematic diagram of the cross-sectional structure of the structure shown in the AA' direction.

[0118] In some embodiments, step S300 forms a plurality of bit lines 3 arranged in parallel and spaced apart on the substrate 1 , which may be specifically performed as follows: steps S310 to S320 :

[0119] In step S310, Figures 9 to 11 As shown, a plurality of spaced-apart bit line grooves 14 are formed on top of the shallow trench isolation structure 12 .

[0120] In step S320, Figures 12 to 18 As shown, a plurality of bit lines 3 are formed on a substrate 1 and arranged in parallel and spaced apart. A second portion 3B of the bit line conductive layer 31 is formed within the bit line groove 14. Furthermore, the projection of the bit lines 3 on the substrate 1 at least partially overlaps with the projection of the bit line groove 14 on the substrate 1.

[0121] The embodiment of the present disclosure does not specifically limit the method for forming the bit line groove 14 in step S310. In some embodiments, the bit line groove 14 can be formed on the top of the shallow trench isolation structure 12 by the following steps: Figure 9 Figure (a) and Figure 9As shown in FIG. 2 (b), a patterned photoresist layer 23 having a second window pattern 14' is formed on the surface of the bit line contact structure 2, wherein the second window pattern 14' can define the shape and position of the bit line groove 14 to be formed; Figure 11 Figure (a) and Figure 11 As shown in FIG. 5( b ), the substrate 1 and the bit line contact structure 2 are etched based on the second window pattern 14 ′ until the top of the shallow trench isolation structure 12 is exposed, thereby forming a bit line groove 14 .

[0122] The disclosed embodiments do not specifically limit the method for forming the patterned photoresist layer 23 in the above-mentioned steps. As an example, the patterned photoresist layer 23 can be formed using the following methods: forming a photoresist layer covering the upper surface of the resulting structure using a coating-curing method or a deposition method; and patterning the photoresist layer through a patterning process such as exposure, development, and etching to obtain the patterned photoresist layer 23. In other embodiments, an anti-reflective layer and / or a hard mask layer are further formed below the patterned photoresist layer 23.

[0123] The embodiment of the present disclosure does not specifically limit the shape of the second window pattern 14' in the above step. The shape of the second window pattern 14' can be adaptively set according to the requirements of the bit line groove 14, as long as its projection on the substrate 1 falls within the overlapping area of ​​the projection of the bit line 3 and the shallow trench isolation structure 12. As an example, the second window pattern 14' can be as follows Figure 9 The rectangular opening shown in FIG. 2( b ); alternatively, the second window pattern 14 ' may also be, for example Figure 10 The parallelogram opening shown in .

[0124] Regarding bit line 3, the disclosed embodiment does not specifically limit the height difference between the top of first portion 3A and the top of second portion 3B. In some embodiments, the height difference between the top of first portion 3A and the top of second portion 3B is less than the maximum thickness of first portion 3A.

[0125] In some embodiments, please refer to Figures 12 to 13 After forming a plurality of spaced-apart bit line grooves 14 on the substrate 1 , the following step may be further included: forming an isolation layer 4 on the sidewalls of the bit line grooves 14 .

[0126] In the method for fabricating the semiconductor structure provided in the above embodiment, insulating layer 4 is formed on the sidewalls of bitline groove 14 to electrically isolate adjacent bitlines 3 and between bitline 3 and substrate 1, thereby preventing electrical signal interference and leakage. Furthermore, forming insulating layer 4 in bitline groove 14 prevents electrons from drifting on the surface of the resulting structure, thereby improving the reliability and stability of the resulting semiconductor structure.

[0127] The present embodiment does not specifically limit the materials constituting the insulating layer 4. For example, the insulating layer 4 may include, but is not limited to, oxide materials, such as silicon oxide. These materials have high resistivity and excellent electrical insulation properties, effectively preventing current loss and interference.

[0128] It should be noted that, in some embodiments, the constituent material of the isolation layer 4 may be the same as or similar to the constituent material of the shallow trench isolation structure 12 .

[0129] The present disclosure does not specifically limit the method for forming the isolation layer 4. In some embodiments, the isolation layer 4 can be formed on the sidewall of the bit line groove 14 by the following steps: Figure 12 As shown, the sidewalls of the bit line groove 14 and the surface of the bit line contact structure 2 are conformally covered with an isolation material layer 4'; Figure 13 As shown, the isolation material layer 4 ′ located on the surface of the bit line contact structure 2 is removed, and the isolation material layer 4 ′ located on the sidewall of the bit line groove 14 is retained as the isolation layer 4 .

[0130] The presently disclosed embodiments do not specifically limit the method for forming the isolation material layer 4'. For example, a chemical vapor deposition process or an atomic layer deposition process can be used to conformally coat the sidewalls of the bitline recess 14 and the surface of the bitline contact structure 2 with the isolation material layer 4'. Examples of chemical vapor deposition processes include atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, and free radical-enhanced chemical vapor deposition.

[0131] In some embodiments, a plurality of bit lines 3 arranged in parallel and spaced apart are formed on a substrate 1 , which can be specifically performed as follows: Steps S321 to S322 :

[0132] In step S321 , a stacked bit line conductive material layer and a bit line dielectric material layer are formed on the substrate 1 .

[0133] In step S322, please continue to refer to Figures 14 to 16 , the bit line dielectric material layer and the bit line conductive material layer are etched to obtain a bit line conductive layer 31 and a bit line dielectric layer 32 . The bit line conductive layer 31 and the bit line dielectric layer 32 together constitute the bit line 3 .

[0134] The present embodiment does not specifically limit the method for forming the bitline conductive material layer and the bitline dielectric material layer in step S321. As an example, the bitline conductive material layer and the bitline dielectric material layer can be formed on the substrate 1 using a chemical vapor deposition process or an atomic layer deposition process. The chemical vapor deposition process can include, for example, an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, and a radical enhanced chemical vapor deposition process.

[0135] In some embodiments, please refer to Figures 15 and 16 In step S322 , etching the bit line dielectric material layer to obtain the bit line dielectric layer 32 may include the following steps: performing a planarization process on the top surface of the bit line dielectric layer 32 to form the top surface of the bit line dielectric layer 32 into a plane.

[0136] In some embodiments, please refer to Figures 17 and 18 After forming a plurality of bit lines 3 arranged in parallel and spaced apart on the substrate 1, the method for preparing the semiconductor structure may further include the following steps:

[0137] An oxide layer 331 and a nitride layer 332 are alternately stacked and formed on the bit line 3. For example, Figure 17 An oxide layer 331 and a nitride layer 332 are alternately stacked; alternatively, for example Figure 18 Two oxide layers 331 and one nitride layer 332 are alternately stacked.

[0138] In the semiconductor structure fabrication method provided in the above embodiment, by forming alternating oxide layers 331 and nitride layers 332 on bit lines 3, the coupling capacitance effect between adjacent bit lines 3 can be further reduced, thereby further improving the electrical performance of the resulting semiconductor structure. Furthermore, the alternating oxide layers 331 and nitride layers 332 also provide protection and isolation, which helps ensure the performance of bit lines 3, thereby improving the fabrication yield and operational reliability of the resulting semiconductor structure.

[0139] In some embodiments, please refer to Figures 18 and 19 , the top surfaces of the multiple bit line contact structures 2 corresponding to the same bit line 3 are flush with each other.

[0140] In some embodiments, please refer to Figures 18 and 19 , the top surface of the bit line contact structure 2 may be higher than the top surface of the substrate 1 .

[0141] In some embodiments, please refer to Figures 18 and 19 The top surface of the bit line conductive layer 31 of the second portion 3B of the bit line 3 is higher than the bit line contact structure 2 and higher than the bottom surface of the bit line conductive layer 31 of the first portion 3A of the bit line 3 .

[0142] According to some embodiments, the present disclosure also provides a semiconductor structure.

[0143] Please continue reading Figure 19 Figure (a) and Figure 19 In FIG. 5( b ), in some embodiments, the semiconductor structure may specifically include: a substrate 1 , a plurality of bit line contact structures 2 , and a plurality of bit lines 3 .

[0144] The substrate 1 may include a plurality of active regions 11 arranged at intervals.

[0145] Multiple bit lines 3 are arranged in parallel and spaced apart on substrate 1. Specifically, they may include a stacked bit line conductive layer 31 and a bit line dielectric layer 32. Furthermore, each bit line 3 may have a first portion 3A and a second portion 3B. Specifically, first portion 3A is located at the intersection of the bit line 3 and the active area 11, and second portion 3B is located between adjacent active areas 11. The top surface of the bit line conductive layer 31 in the second portion 3B is lower than the top surface of the bit line conductive layer 31 in the first portion 3A.

[0146] The plurality of bit line contact structures 2 are located between the first portion 3A and the active area 11 . Specifically, each bit line contact structure 2 is disposed between the first portion 3A of the corresponding bit line 3 and the active area 11 .

[0147] In the semiconductor structure provided in the above embodiment, the bit line 3 is formed with a first portion 3A overlapping with the active area 11 and a second portion 3B located between adjacent active areas 11. The bit line conductive layer 31 of the second portion 3B of the bit line 3 is formed to have a top surface lower than the top surface of the bit line conductive layer 31 of the first portion 3A of the bit line 3. This arrangement can reduce the relative cross-sectional areas of adjacent bit lines 3, thereby reducing the coupling capacitance effect between adjacent bit lines 3, which is beneficial to improving the electrical performance of the semiconductor structure.

[0148] In some embodiments, please refer to Figure 19 Figure (a) and Figure 19 In FIG. (b), the substrate 1 may include a shallow trench isolation structure 12 located between the active regions 11. The top of the shallow trench isolation structure 12 has a plurality of spaced-apart bit line grooves. The specific positions of the bit line grooves can be referred to. Figures 10 to 13 The bit line groove 14 is shown in FIG.

[0149] It can be understood that the projection of the bit line groove 14 on the substrate 1 at least partially overlaps with the projection of the bit line 3 on the substrate 1 , and the bit line conductive layer 31 of the second portion 3B of the bit line 3 is at least partially located in the bit line groove 14 .

[0150] Please combine Figure 18 As can be understood from Figure (a) in FIG, in some embodiments, the semiconductor structure may further include an isolation layer 4.

[0151] The isolation layer 4 is located between the second portion 3B of the bit line 3 and the sidewall of the bit line groove 14 , and between the second portion 3B and the bit line contact structure 2 .

[0152] Please continue reading Figures 18 and 19 In some embodiments, top surfaces of multiple bit line contact structures 2 corresponding to the same bit line 3 are flush with each other.

[0153] As an example, Figure 18 Figure (a) and Figure 19 As shown in FIG. 8( a ), the top surface of the bit line contact structure 2 may be higher than the top surface of the substrate 1 .

[0154] In some embodiments, please refer to Figure 18 Figure (a) and Figure 19 In FIG. 5 , the top surface of the bit line conductive layer 31 of the second portion 3B of the bit line 3 may be higher than the bit line contact structure 2 and higher than the bottom surface of the bit line conductive layer 31 of the first portion 3A of the bit line 3 .

[0155] Regarding the bit line 3 , in some embodiments, a height difference between a top of the first portion 3A and a top of the second portion 3B in a vertical direction is smaller than a maximum thickness of the first portion 3A.

[0156] In some embodiments, please refer to Figure 19 As shown in FIG. 5 (a), the semiconductor structure may further include a bit line isolation spacer 34. The bit line isolation spacer 34 covers the sidewalls and top surface of the bit line 3; that is, the bit line isolation spacer 34 wraps around the outer peripheral surface of the bit line 3.

[0157] In the semiconductor structure provided in the above embodiment, the bit line isolation sidewall 34 can be provided to provide good protection and isolation for the bit line 3, thereby effectively ensuring the performance of the bit line 3 and improving the manufacturing yield and reliability of the semiconductor structure.

[0158] In some embodiments, please refer to Figures 18 and 19 , the semiconductor structure may further include a plurality of word lines 5 .

[0159] A plurality of word lines 5 are arranged in parallel and spaced apart in the substrate 1 , and the bit line contact structures 2 cover the tops of the word lines 5 .

[0160] It can be understood that each active region 11 runs through two word lines 5 and one bit line 3 , and the bit line contact structure 2 is located between adjacent word lines 5 in the same active region 11 .

[0161] As an example, Figure 19As shown in FIG. 1 (a), the word line 5 can be a buried word line, specifically comprising a gate dielectric layer 51, a word line conductive layer 52, and a filling dielectric layer 53. The gate dielectric layer 51 wraps around the surface of the word line conductive layer 52 to electrically isolate the word line conductive layer 52 from the substrate 1. The filling dielectric layer 53 covers the top surfaces of the word line conductive layer 52 and the gate dielectric layer 51.

[0162] It should be noted that the preparation methods of the semiconductor structures provided in the embodiments of the present disclosure can all be used to prepare corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structural embodiments can be replaced and supplemented with each other without causing conflicts, so that those skilled in the art can understand the technical content of the present disclosure.

[0163] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0164] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate comprising a plurality of active regions arranged at intervals; A plurality of bit lines are arranged in parallel and spaced apart on the substrate; The bit line includes a stacked bit line conductive layer and a bit line dielectric layer; the bit line has a first portion and a second portion; wherein the first portion is located at an overlap between the bit line and the active region, the second portion is located between adjacent active regions, and a top surface of the bit line conductive layer in the second portion is lower than a top surface of the bit line conductive layer in the first portion; A plurality of bit line contact structures are located between the first portion and the active area.

2. The semiconductor structure according to claim 1, wherein: The substrate includes a shallow trench isolation structure located between the active areas; The top of the shallow trench isolation structure has a plurality of spaced-apart bit line grooves, the projections of the bit line grooves on the substrate at least partially overlap with the projections of the bit lines on the substrate; the bit line conductive layer of the second portion is located in the bit line grooves.

3. The semiconductor structure according to claim 2, wherein: The semiconductor structure further comprises: An isolation layer is located between the second portion and the sidewall of the bit line groove and between the second portion and the bit line contact structure.

4. The semiconductor structure according to claim 1, wherein: The top surfaces of the multiple bit line contact structures corresponding to the same bit line are flush with each other; the top surface of the bit line contact structure is higher than the top surface of the substrate; the top surface of the bit line conductive layer of the second part of the bit line is higher than the bit line contact structure, and higher than the bottom surface of the bit line conductive layer of the first part of the bit line.

5. The semiconductor structure according to claim 1, wherein: In a vertical direction, a height difference between a top of the first portion and a top of the second portion is smaller than a maximum thickness of the first portion.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that Also includes: A plurality of word lines are arranged in parallel and spaced apart in the substrate; The bit line contact structure covers the top of the word line.

7. A method for preparing a semiconductor structure, characterized in that: The steps include: Providing a substrate; the substrate includes a plurality of active regions arranged at intervals; forming a bit line contact structure in the substrate; A plurality of bit lines arranged in parallel and spaced apart are formed on the substrate and electrically connected to the active area via the bit line contact structure; the bit line includes a stacked bit line conductive layer and a bit line dielectric layer; the bit line is formed with a first portion and a second portion; wherein the first portion is located at the intersection of the bit line and the active area, the second portion is located between adjacent active areas, and the top surface of the bit line conductive layer of the second portion is lower than the top surface of the bit line conductive layer of the first portion.

8. The method for preparing a semiconductor structure according to claim 7, wherein: A plurality of word lines arranged in parallel and spaced apart are formed in the substrate; The step of forming a bit line contact structure in the substrate includes: forming spaced-apart bit line contact openings on the substrate; the bit line contact openings exposing the active areas between adjacent word lines; A bit line contact structure is formed in the bit line contact opening.

9. The method for preparing a semiconductor structure according to claim 8, wherein: The providing of the substrate comprises: forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active areas arranged at intervals in the substrate; The step of forming a plurality of bit lines arranged in parallel and spaced apart on the substrate comprises: forming a plurality of spaced-apart bit line grooves on top of the shallow trench isolation structure; forming an isolation layer on a sidewall of the bit line groove; A plurality of bit lines arranged in parallel and spaced apart are formed on the substrate; wherein the bit line conductive layer of the second portion is formed in the bit line groove, and the projection of the bit line on the substrate at least partially overlaps with the projection of the bit line groove on the substrate.

10. The method for preparing a semiconductor structure according to claim 9, wherein: After forming a shallow trench isolation structure in the substrate and before forming a bit line contact structure in the substrate, the method further includes: forming an etch stop material layer on the substrate; Forming spaced-apart bit line contact openings on the substrate, comprising: forming a bit line contact opening, wherein the bit line contact opening penetrates the etch stop material layer and extends into the substrate, and the retained etch stop material layer serves as an etch stop layer; forming a bit line contact structure in the bit line contact opening, comprising: forming a bit line contact material layer, wherein the bit line contact material layer fills the bit line contact opening and covers the etch stop layer; removing a portion of the bit line contact material layer, so that the remaining bit line contact material layer and the etch stop layer together constitute the bit line contact structure; Among them, the top surfaces of the multiple bit line contact structures corresponding to the same bit line are flush; the top surface of the bit line contact structure is higher than the top surface of the substrate; the top surface of the bit line conductive layer of the second part of the bit line is higher than the bit line contact structure, and higher than the bottom surface of the bit line conductive layer of the first part of the bit line.

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