A complete RISC-V compressed instruction set customization method

Abstract

The present invention discloses a complete RISC-V compressed instruction set customization method. First, the floating-point operation interval in the compressed instruction set RV32C is removed, and the 5-bit register address in RV32C is reduced to 4 bits. The freed space is used to expand the function code interval or the length of the immediate number, and the shift interval is rearranged; secondly, according to the statistical analysis of the benchmark program set, CSR type instructions, conditional jump instructions, Load instructions and Store instructions are customized; then, instructions with low frequency of use and unsupported in RV32C are customized; finally, long immediate number load instructions are customized. The present invention removes floating-point operation instructions on the basis of retaining the integer instructions in the original compression extension, and supports all operations in RVE through register address reduction, interval rearrangement and other technologies, thereby forming a complete compressed instruction set; it can reduce the instruction storage space in the deep embedded field, and further reduce the power consumption and cost of the deep embedded system.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronics technology, and in particular relates to a complete RISC-V compressed instruction set customization method. Background Art

[0002] RISC-V is an open source instruction set architecture. The RISC-V instruction set provides 16-bit, 32-bit, 64-bit and 128-bit standard formats according to the requirements of instruction length in different application scenarios. 16-bit and 32-bit instruction formats are often used in embedded devices, general computing and other scenarios. 64-bit and 128-bit instructions are mostly used in high-performance computing, high-precision computing and parallel computing because they support the increase of address space. The RISC-V instruction set has the advantages of scalability and modularity. You can choose the supported instruction set extension according to your needs. The existing RISC-V instruction set has nearly 20 standard extended instruction sets, each of which has a unique application field, such as A extension supports atomic operations, V extension supports vector calculations, B extension supports bit-level acceleration operations, and K extension supports acceleration operations of commonly used encryption and decryption algorithms.

[0003] The 32-bit basic integer instruction set RV32I contains Turing-complete instruction types, defines 32 32-bit general register groups, meets the register usage requirements of the Application Binary Interface (ABI), and has an addressing space of 2 to the power of 32. RV32I instructions have six basic instruction formats: R-type instructions, I-type instructions, S-type instructions, B-type instructions, U-type instructions, and J-type instructions; R-type instructions are used for operations between source register 1, source register 2, and destination register, I-type instructions are used for short immediate and memory access load operations, S instructions are used for memory access store operations, B-type instructions are used for conditional jump operations, U-type instructions are used for long immediate operations, and J-type instructions are used for unconditional jump operations. These six basic instruction formats meet the operations that a basic RISC-V processor needs to support, including environment call instructions, environment debug instructions, and externally visible memory access request instructions. The RV32I instruction set has a total of 40 instructions. The streamlined instruction set only occupies a very small encoding space of the 32-bit instruction word. The 32-bit instruction word can be divided into a 7-bit operation code opcode, and the opcode is a mark to distinguish different instruction types.

[0004] RISC-V provides an optional embedded architecture RV32E, which only requires 16 general-purpose integer registers to form a register group, mainly used in embedded scenarios that pursue extremely low area and extremely low power consumption. In addition, the other features of RV32E are exactly the same as RV32I.

[0005] RISC-V's C instruction set RV32C adds support for 16-bit compressed instructions to the processor. Shortening the length of instructions can improve instruction density and reduce storage requirements, making it suitable for scenarios with limited storage resources and storage bandwidth. The RV32C instruction set maps each 16-bit compressed instruction to a standard 32-bit instruction. The RISC-V compressed instruction design method allows the processor design process to only add logic to convert compressed instructions into ordinary instructions during the instruction fetch stage to process compressed instructions. At the same time, this design method allows compiler writers to ignore RV32C instructions.

[0006] In the instruction encoding range of RV32C, the lowest two bits are 00, 01 and 10, and the highest three bits are the function code area. Therefore, the instruction set of RV32C has 24 instruction ranges, which are divided into 8 floating-point operation instruction ranges such as FLD and FLW, 15 integer operation instruction ranges such as ADDISPN and ADDI, and 1 reserved range.

[0007] However, in control-oriented embedded systems, floating-point operations are not required, so the floating-point operation instructions of RV32C are not used in control-oriented embedded systems, which means that these instruction intervals are wasted. In addition, the existing RV32C is incomplete. For example, the slt instruction in RV32E means to perform a signed comparison between source register 1 and source register 2. If it is less than, the destination register is set to 1, otherwise it is set to 0. For this kind of instruction, it cannot be completed using only a single RV32C instruction set. In addition, instructions such as CSR type instructions, environment calls, and environment debugging cannot be implemented through a single RV32C instruction set. Summary of the invention

[0008] In view of the problems existing in the above-mentioned background technology, the purpose of the present invention is to provide a complete RISC-V compressed instruction set customization method, which removes floating-point operation instructions on the basis of retaining the original integer instructions in the compression extension, and supports all operations in RVE through register address reduction, interval rearrangement and other technologies, thereby forming a complete compressed instruction set.

[0009] In order to achieve the above object, the present invention adopts the following technical solution:

[0010] A complete RISC-V compressed instruction set customization method includes the following steps:

[0011] First, the floating-point operation interval in the compressed instruction set RV32C is removed, and the 5-bit register address in RV32C is reduced to 4 bits. The freed space is used to expand the function code interval or the length of the immediate value, and the shift interval is rearranged.

[0012] Secondly, according to the statistical analysis of the benchmark program set, the CSRRW, CSRRC and CSRRS instructions in the CSR type are customized using an interval, and 3 bits of address space are allocated to the CSR register, source register and destination register; the instructions that are frequently used and cannot be implemented in RV32C, including conditional jump instructions, Load instructions and Store instructions, are customized;

[0013] Then, the instructions that are used less frequently and are not supported in RV32C, including shift instructions, less than set instructions, and auipc instructions, are customized to CR type, and the extra space is customized to two register jump instructions;

[0014] Finally, customize the long immediate load instruction. If you only need to support 16-bit instructions, customize the interval with the lowest bit of 11 as a long immediate load instruction, which loads the 12-bit immediate value into the destination register. If you choose to use the complete compressed instruction set as an extension of RV32C, this interval is still a 32-bit instruction interval.

[0015] Eventually, a complete RISC-V customized compressed instruction set is formed.

[0016] Furthermore, the interval rearrangement method is: reducing the immediate length of the shift instruction in RV32C, and reducing the register address of the c.slli instruction interval.

[0017] Furthermore, the method for reducing the register address of the c.slli instruction interval is: merging the two instructions srli and srai in the

[100] -

[01] interval into the

[000] -

[10] interval, and customizing the sltiu instruction to the

[000] -

[10] interval, and then increasing the register address bit width or immediate length of the

[100] -

[01] interval to enhance the instruction.

[0018] Furthermore, the customization of the conditional jump instruction includes customization of a blt instruction, a bltu instruction, a beq instruction and a bne instruction.

[0019] Furthermore, the customization of the Load instruction and the Store instruction should consider supporting 6-bit immediate values, and the default source register is the SP register.

[0020] Compared with the shortcomings and deficiencies of the prior art, the present invention has the following beneficial effects:

[0021] (1) The present invention removes the floating-point operation interval for the existing instructions in RV32C, and improves the original instruction format by register address reduction and interval rearrangement technology, thereby enhancing the function of the original instruction without changing the instruction format; the present invention fully customizes the instructions not supported by RV32C, including CSR type instructions, conditional jump instructions, Load\Store instructions, other instructions, and optional long immediate load instructions;

[0022] (2) The present invention provides a complete RISC-V compressed instruction set, which can reduce instruction storage space in the deep embedded field and further reduce the power consumption and cost of the deep embedded system. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is the result of customizing the CR, CI and CSS type instruction formats provided by the embodiment of the present invention;

[0024] Figure 2 It is the result of re-customizing the instructions in the interval

[100] -

[10] provided in the embodiment of the present invention;

[0025] Figure 3 It is the result of re-customization of CI and CSS type instructions provided by the embodiment of the present invention;

[0026] Figure 4 The shift instruction provided in the embodiment of the present invention performs interval rearrangement customization result;

[0027] Figure 5 is a statistical analysis diagram of a benchmark program set provided by an embodiment of the present invention, wherein (a) is a CSR type instruction distribution diagram, and (b) is a CSR register distribution diagram;

[0028] Figure 6 It is the CSR instruction customization result provided by the embodiment of the present invention;

[0029] Figure 7 is a statistical analysis diagram of non-compressed instructions in a benchmark program set provided by an embodiment of the present invention;

[0030] Figure 8 It is the customized result of the conditional jump instruction provided by the embodiment of the present invention;

[0031] Fig. 9 is the immediate value distribution result of the Load and Store instructions provided by the embodiment of the present invention;

[0032] Fig.10 It is the result of customization of Load and Store instructions provided by the embodiment of the present invention;

[0033] Fig.11 It is other instruction customization results provided by the embodiment of the present invention;

[0034] Fig.12 It is the customization result of the long immediate load instruction provided by the embodiment of the present invention;

[0035] Fig.13 It is a complete RV32C compressed instruction set interval provided by an embodiment of the present invention;

[0036] Fig.14 It is the customization result of CR, CJ, CIW, CB, CL, and CSS type instructions provided in the embodiment of the present invention;

[0037] Fig.15 It is the CI type instruction customization result provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0039] RV32C is actually a shorthand for some high-frequency instructions in the RISC-V instruction set, which are executed as non-compressed instructions after instruction decoding. Therefore, the RV32C instruction set alone cannot complete all program work, that is, it is not complete. In addition, for small systems that do not need to use floating-point operations, the floating-point interval in RV32C is not used. Therefore, the RISC-V instruction set can be customized for compressed instructions for the following three reasons:

[0040] (1) The RV32E instruction set is an integer instruction set that does not include floating-point operations, so the floating-point range in the RV32C instruction set can be re-customized;

[0041] (2) RV32E only needs 16 general registers, so only 4 bits of address space are needed. Therefore, the register address number in RV32C can have extra space to expand the function code;

[0042] (3) The Reserve interval can be used, and the interval with the lowest bit being 11 can be used.

[0043] Based on these three reasons, the present invention proposes a complete RISC-V compressed instruction set customization method, which is as follows:

[0044] (1) Register address reduction

[0045] The floating-point operation range in the compressed instruction set RV32C is removed. At the same time, since RV32E only supports 16 general registers, the register address only needs 4 bits, so the 5-bit register address in RV32C is reduced to 4 bits, and the freed space is used to expand the function code range or the length of the immediate value. It is mainly customized for CR, CI and CSS types. Among them, the CR type instruction has two 5-bit register addresses, so the 2-bit function code range can be increased; while the CI and CSS types have a 5-bit register address, so the 1-bit immediate value length or 1-bit function code range can be increased; the customization results of these three instruction formats are as follows Figure 1 shown.

[0046] The following are some examples:

[0047] Example 1: The interval

[100] -

[10] uses register address reduction. The interval

[100] -

[10] is a CR type instruction with two 5-bit register addresses and needs to rely on the value of the [6:2] segment for decoding. Therefore, the register address is reduced and the extra 2-bit space is used as the extended function code to expand the number of instructions and determine the instruction type without relying on the [6:2] segment data. This interval contains the ebreak instruction, so the ecall and mret instructions are customized to this interval. The result is as follows Figure 2 As shown;

[0048] Example 2: After register address reduction, CI and CSS type instructions increase the length of the immediate value by 1 bit without changing the original instruction format. The result is as follows: Figure 3 shown.

[0049] (2) Interval rearrangement

[0050] The interval rearrangement is mainly aimed at the shift instructions in RV32C. The length of the shift amount shamt of slli, srli and srai in RV32E is 5 bits, while the length of the immediate value of these instructions in RV32C is 6 bits. Therefore, the length of the immediate value can be reduced. For the

[000] -

[10] interval, that is, the c.slli instruction interval, the register address can also be reduced, so this interval can have an extra 2 bits of space to expand the function code. Therefore, the srli and srai instructions in the

[100] -

[01] interval can be merged into the

[000] -

[10] interval, and the sltiu instruction can be customized to the

[000] -

[10] interval. After that, the

[100] -

[01] interval is further planned to increase the register address width or the immediate value length to enhance the instructions. Finally, the results after the two intervals are rearranged are as follows: Figure 4 shown.

[0051] (3) Customization of CSR type instructions

[0052] The original RV32C does not have instructions for CSR operations, so it is necessary to fully customize CSR operation instructions. The results of statistical analysis of the benchmark program set are as follows: Figure 5 As shown, Figure 5 In the figure, (a) is the CSR type instruction distribution diagram, and (b) is the CSR register distribution diagram. As can be seen from the figure, the proportion of CSR type instructions is very small, and no more than 8 CSR registers are used. Therefore, an interval is used to customize the CSRRW, CSRRC and CSRRS instructions in the CSR type, and 3 bits of address space are allocated to the CSR register, source register and destination register. The final CSR type instruction customization is as follows Figure 6 shown.

[0053] (4) Customization of conditional jump instructions

[0054] The statistical analysis of the non-compressed instructions in the benchmark program set is shown in the following figure. Figure 7 As shown in the figure, different colors represent different programs. The figure shows the distribution of the top 20 instructions with the largest number. It can be seen that the proportion of conditional jump instructions such as bge and bgeu is relatively large, but there is no such instruction in RV32C. In addition, since bge and bgeu can be converted to blt and bltu operations, only blt and bltu instructions need to be customized. Similarly, RV32C only has conditional jump instructions such as beqz and bnez that compare with 0, but no beq and bne instructions, so beq and bne instructions also need to be customized. The customized results of conditional jump instructions are shown in the figure below. Figure 8 shown.

[0055] (5) Customization of Load and Store instructions

[0056] RV32C has lw, sw, lwsp, swsp instructions that support word access, but no half-word or byte access. The Load and Store instructions in BenchMarks are analyzed, and the results are as follows: Fig. 9 As shown in the figure, the length of the immediate value is small, and the proportion of those not exceeding 6 bits is extremely high. Therefore, when customizing, consider supporting 6-bit immediate values, and the default source register is the SP register. The customization result is as follows Fig.10 shown.

[0057] (6) Other instruction customization

[0058] Other instructions are mainly customized instructions for operations that are not available in RV32C, such as shift instructions (sll, srl, and sra), less than set instructions (slt and sltu), and auipc instructions. These instructions are mainly R-type instructions, so they are customized to CR type. In addition, the extra space is customized to two register jump instructions. The customized results are as follows Fig.11 shown.

[0059] (7) Customization of long immediate load instructions

[0060] If you only need to support 16-bit instructions, you can choose to customize the interval with the lowest bit of 11 as a long immediate load instruction. This instruction loads the 12-bit immediate value into the destination register. However, if you choose to use the complete compressed instruction set as an extension of RV32C, this interval is still a 32-bit instruction interval. The result of long immediate load instruction customization is as follows: Fig.12 shown.

[0061] After the above customization, the complete RV32C compressed instruction set range is as follows Fig.13 As shown in the figure, the green shaded instructions are improved based on the original instruction format using register address reduction and interval reordering technology, which can enhance the function of the original instructions without changing the instruction format; the blue shaded instructions are fully customized instructions, including CSR type instructions, Load\Store instructions, conditional jump instructions, other instructions, and long immediate load instructions. Finally, the complete RV32C compressed instruction set list is as follows Fig.14 and Fig.15 As shown, Fig.14 Customize results for CR, CJ, CIW, CB, CL, CSS type instructions, Fig.15 The results are customized for CI type instructions, where the green and blue shaded labels have the same meanings as above.

[0062] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A complete RISC-V compressed instruction set customization method, characterized in that: The steps include: First, the floating-point operation interval in the compressed instruction set RV32C is removed, and the 5-bit register address in RV32C is reduced to 4 bits. The freed space is used to expand the function code interval or the length of the immediate value, and the shift interval is rearranged. Secondly, according to the statistical analysis of the benchmark program set, the CSRRW, CSRRC and CSRRS instructions in the CSR type are customized using an interval, and 3 bits of address space are allocated to the CSR register, source register and destination register; the instructions that are frequently used and cannot be implemented in RV32C, including conditional jump instructions, Load instructions and Store instructions, are customized; Then, the instructions that are used less frequently and are not supported in RV32C, including shift instructions, less than set instructions, and auipc instructions, are customized to CR type, and the extra space is customized to two register jump instructions; Finally, customize the long immediate load instruction. If you only need to support 16-bit instructions, customize the interval with the lowest bit of 11 as a long immediate load instruction, which loads the 12-bit immediate value into the destination register. If you choose to use the complete compressed instruction set as an extension of RV32C, this interval is still a 32-bit instruction interval. Eventually, a complete RISC-V customized compressed instruction set is formed.

2. The complete RISC-V compressed instruction set customization method as described in claim 1, characterized in that: The interval rearrangement method is: reducing the immediate length of the shift instruction in RV32C and reducing the register address of the c.slli instruction interval.

3. The complete RISC-V compressed instruction set customization method as described in claim 2, characterized in that: The method for reducing the register address of the c.slli instruction interval is: merge the two instructions srli and srai in the [100]-[01] interval into the [000]-[10] interval, and customize the sltiu instruction to the [000]-[10] interval, and then increase the register address bit width or immediate length of the [100]-[01] interval to enhance the instruction.

4. The complete RISC-V compressed instruction set customization method as described in claim 1, characterized in that: The customization of the conditional jump instruction includes the customization of the blt instruction, the bltu instruction, the beq instruction and the bne instruction.

5. The complete RISC-V compressed instruction set customization method as described in claim 1, characterized in that: The customization of the Load instruction and the Store instruction considers supporting 6-bit immediate values, and the default source register is the SP register.

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