A server integrated firmware system and task processing method

Abstract

This disclosure discloses a server integrated firmware system and task processing method, relating to the field of firmware engineering. The system includes: an integrated control module for receiving and processing task instructions from a target application, calling corresponding BIOS modules and / or BMC modules to execute the target task according to the task instructions, and returning the execution result to the target application; and an embedded system platform integrating multiple BIOS modules and BMC modules. The BIOS modules and BMC modules are obtained by modularizing the BIOS and BMC according to task functions using a RISC-V architecture processor. The integrated firmware design of this disclosure improves the response speed and execution accuracy of instruction processing, enabling the server to adapt more quickly to the needs of cloud computing and big data processing.

Description

Technical Field

[0001] This disclosure relates to the field of firmware engineering, specifically to a server integrated firmware system and task processing method. Background Technology

[0002] With the rapid development of cloud computing and big data technologies, the demand for server hardware is constantly changing. Lightweight servers, due to their portability, rapid deployment, and temporary nature, have shown great application potential in many fields, especially in military and mobile computing.

[0003] Traditional server designs feature separate BIOS and Baseboard Management Controller (BMC). While this separate design offers flexibility to some extent, it also suffers from inefficiency, resource waste, and high maintenance complexity. For example, communication between the BIOS and BMC typically occurs via a low-speed interface, limiting the speed and efficiency of information exchange. Furthermore, each independent module has its own memory and processing resources, potentially leading to resource duplication and waste. Summary of the Invention

[0004] This disclosure provides a server integrated firmware system and task processing method, aiming to solve the problems existing in the background art.

[0005] To solve the above-mentioned technical problems, this disclosure is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide a server integrated firmware system, the system comprising:

[0007] An integrated control module is used to receive and process task instructions from the target application, call the corresponding BIOS module and / or BMC module to execute the target task according to the task instructions, and return the execution result to the target application.

[0008] An embedded system platform integrates multiple BIOS modules and BMC modules. The BIOS modules and BMC modules are obtained by modularizing the BIOS and BMC according to their respective task functions using a RISC-V architecture processor.

[0009] Optionally, the system further includes a hardware resource library and an API interface. The hardware resource library is used to integrate and manage hardware resources on the server. The BIOS module and the BMC module access and operate the hardware resource library through the API interface.

[0010] The hardware resource library integrates a resource manager, which is used to monitor the server's operating load, hardware performance characteristics, and user-defined policies, and to allocate and manage the resources of the hardware resource library.

[0011] Optionally, the embedded system platform is configured with multiple processor modules, which are RISC-V architecture processors modularized according to processor functions;

[0012] Based on the task requirements of the BIOS module and the BMC module, a processor module suitable for the task requirements is selected and combined from multiple processor modules.

[0013] Optionally, the system further includes a management interface and a user interface. The management interface integrates the task functions of the BIOS module and the BMC module. The task functions include, but are not limited to, at least one of the following: hardware configuration management, device driver loading, firmware update, system status monitoring, and fault warning.

[0014] The various tasks and functions of the BIOS module and the BMC module are displayed through the user interface.

[0015] Optionally, the embedded system platform is configured with a message queue to provide a channel for information exchange between the BIOS module and the BMC module;

[0016] When the BIOS starts, the BIOS module obtains the real-time hardware status information in the message queue by querying the message queue, and sends the BIOS running information to the message queue. The real-time hardware status information is obtained and sent to the message queue by the BMC module, and the BIOS running information includes the BIOS startup progress and error log.

[0017] The embedded system platform is configured with an event notification mechanism for real-time communication between the BIOS module and the BMC module;

[0018] The event notification mechanism is configured such that when the BMC module detects a change in the status of a resource in the hardware resource library, or receives a management instruction from the user for a resource, it obtains the real-time hardware status information of the corresponding resource and sends the real-time hardware status information to the BIOS module through the message queue.

[0019] Optionally, the embedded system platform is configured with a message scheduling algorithm;

[0020] The message scheduling algorithm is configured to dynamically sort the information in the message queue based on the priority of each message in the message queue. When executing the target task, it schedules and processes information with higher priority. The priority of information in the message queue is defined according to the nature of the information and the degree of its impact on the system.

[0021] Optionally, the embedded system platform is configured with a machine learning algorithm, which is configured to input the current real-time hardware status information in the message queue into a historical training model, and predict the changing trend of the real-time hardware status information based on the output of the historical training model. The historical training model is pre-trained using the real-time hardware status information collected historically in the message queue.

[0022] Optionally, the system further includes a fast boot module, which integrates a boot function to configure the BIOS boot process as a Linux boot kernel boot process;

[0023] The fast boot module is configured with a fast memory mapping mechanism, which is configured to map large data files required in the BIOS boot process to the memory address space.

[0024] The system also includes a network remote boot module for providing remote wake-up functionality, sending remote wake-up requests over the network, and remotely managing the configuration of the fast boot module over the network.

[0025] Optionally, the system further includes a wake-up control module for listening for wake-up requests from different sources on the server;

[0026] The wake-up control module is configured with a wake-up decision algorithm. The wake-up decision algorithm is configured to determine the current power status of the system based on the current power status and load status of the system. When the current power status of the system is low, the algorithm prioritizes waking up the service indicated by the wake-up request with higher priority. The priority of the wake-up request is defined based on the urgency of the wake-up request and the degree of impact on the system.

[0027] Secondly, embodiments of this disclosure provide a task processing method applied to a server integrated firmware system, the method comprising:

[0028] Receive task instructions from the target application;

[0029] The task instruction calls the corresponding BIOS module and / or BMC module to execute the target task, and allocates the resources required to execute the target task to the BIOS module and / or BMC module. The BIOS module and the BMC module are obtained by modularizing the BIOS and BMC according to the task functions through a RISC-V architecture processor.

[0030] The execution result of the target task is returned to the target application.

[0031] The technical solutions provided by the embodiments of this disclosure have at least the following beneficial effects:

[0032] This disclosure utilizes a RISC-V architecture processor to modularize the BIOS and BMC, enabling functional modules to perform task processing and information exchange more efficiently. This not only improves processing speed but also reduces the limitations of low-speed interface communication, thereby enhancing the overall system performance. By modularly integrating the BIOS and BMC functions onto the same embedded system platform, redundant resource usage and storage requirements are reduced. Furthermore, the introduction of an integrated control module allows direct receipt of task instructions from the target application and coordination of task execution between the BIOS and BMC modules. This integrated firmware design improves instruction processing response speed and execution accuracy, enabling the server to adapt more quickly to the demands of cloud computing and big data processing. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a structural block diagram of a server integrated firmware system provided in one embodiment of the present disclosure;

[0035] Figure 2 This is a schematic diagram of the design architecture of a server integrated firmware system provided in one embodiment of the present disclosure;

[0036] Figure 3 This is a schematic diagram of the steps of a task processing method provided in one embodiment of the present disclosure. Detailed Implementation

[0037] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0038] In the context of the rapid development of modern information technology, the efficient operation of server hardware systems has become crucial for improving computing power and data processing speed. To meet these needs, embodiments of this disclosure provide a server integrated firmware system designed to significantly improve server performance and resource management efficiency through a highly integrated and modular design. Figure 1This is a structural block diagram of a server integrated firmware system provided in one embodiment of the present disclosure, as shown below. Figure 1 As shown, the system includes:

[0039] The integrated control module 101 is used to receive and process task instructions from the target application, call the corresponding BIOS module and / or BMC module to execute the target task according to the task instructions, and return the execution result to the target application.

[0040] The integrated control module (ICM) is primarily used to receive and process task instructions from target applications within the system. It executes these target tasks by calling the corresponding BIOS and / or BMC modules, and ultimately returns the execution results to the target application. The target application refers to various applications or services running on top of the operating system. Target applications can be user interfaces, system management tools, and server monitoring software, etc. The target application sends task instructions to the ICM to execute specific hardware management or system operation tasks. A task instruction is a specific operation request sent by the target application to the ICM, containing the specific task to be performed and its parameters, such as adjusting fan speed, monitoring processor temperature, or updating firmware. Task instructions are explicit operation commands used to instruct the ICM to call which BIOS and / or BMC modules to complete a specific task. The target task refers to the specific operation to be performed according to the task instruction. Target tasks can include, but are not limited to, hardware initialization, system monitoring, hardware configuration adjustments, and firmware updates. After receiving a task instruction, the integrated control module parses its content and, based on the parsing results, determines the necessary BIOS modules (such as boot sequence configuration and hardware initialization) and / or BMC modules (such as system monitoring and fan control) to be invoked. The corresponding BIOS and / or BMC modules then execute the target task and return the execution results, such as success, failure, or specific monitoring data, to the integrated control module. The integrated control module then organizes the results and returns them to the target application for further processing.

[0041] The embedded system platform 102 integrates multiple BIOS modules and BMC modules. The BIOS modules and BMC modules are obtained by modularizing the BIOS and BMC according to their respective task functions using a RISC-V architecture processor.

[0042] RISC-V is an open-source instruction set architecture (ISA) designed to provide a simple, flexible, scalable, and freely usable architecture. This disclosure chooses the RISC-V architecture for server firmware integration primarily based on the following considerations: First, RISC-V's modular design allows for the selection and combination of different processor modules, such as integer arithmetic modules, floating-point arithmetic modules, and memory interface modules, to meet various needs ranging from low-power embedded systems to high-performance computing servers. Second, RISC-V's reduced instruction set design improves system efficiency and provides high-performance computing capabilities. Third, RISC-V's open-source nature avoids licensing fees, reducing costs. Based on different task functions, the BIOS and BMC are modularly designed, resulting in multiple BIOS and BMC modules. Leveraging the flexibility and scalability of the RISC-V processor, these BIOS and BMC modules are integrated into a unified embedded system platform. Optionally, they can also be integrated using advanced microcontrollers or SoCs. In addition, in order to fully leverage the advantages of the RISC-V processor and provide operating system support, this disclosure modifies and optimizes the RISC-V architecture, including kernel scheduling and memory management, to improve the performance stability and response speed of the operating system.

[0043] The BIOS (Basic Input / Output System) is responsible for hardware initialization, hardware detection, and system booting during computer startup. With modularization, each BIOS module handles specific tasks, such as hardware initialization and boot loading. On the RISC-V architecture, BIOS modules can be modularly designed based on different functionalities, such as memory initialization, device detection, and boot loading. The BMC (Baseboard Management Controller) is responsible for server hardware management, monitoring, and remote management. Similarly, with modularization, each BMC module handles specific management tasks, such as hardware monitoring, fan control, and remote management. On the RISC-V architecture, BMC modules can also be modularly designed based on different functionalities, such as hardware monitoring, system alarms, and remote control. By integrating the BIOS and BMC modules into the embedded system platform on the RISC-V architecture, the two modules can share memory space and peripheral resources, improving system resource utilization. This integrated design also makes the system architecture more compact, effectively reducing hardware layout complexity and resource waste, and improving overall system efficiency. It should be noted that since the functions of the BIOS and the OS are highly overlapping, modularizing the BIOS is equivalent to integrating the OS as well. Therefore, the embodiments disclosed herein provide a deep integration design scheme for BIOS, BMC and OS based on RISC-V architecture.

[0044] This disclosure utilizes a RISC-V architecture processor to modularize the BIOS and BMC, enabling functional modules to perform task processing and information exchange more efficiently. This not only improves processing speed but also reduces the limitations of low-speed interface communication, thereby enhancing the overall system performance. By modularly integrating the BIOS and BMC functions onto the same embedded system platform, redundant resource usage and storage requirements are reduced. Furthermore, the introduction of an integrated control module allows direct receipt of task instructions from the target application and coordination of task execution between the BIOS and BMC modules. This integrated firmware design improves instruction processing response speed and execution accuracy, enabling the server to adapt more quickly to the demands of cloud computing and big data processing.

[0045] For example, the system further includes a hardware resource library and an API interface. The hardware resource library is used to integrate and manage hardware resources on the server. The BIOS module and the BMC module access and operate the hardware resource library through the API interface. The hardware resource library integrates a resource manager, which is used to monitor the server's operating load, hardware performance characteristics, and user-defined policies, and to allocate and manage the resources in the hardware resource library.

[0046] To achieve efficient server management and operation, this disclosure presents a unified resource library and API interface, enabling the BIOS module and BMC module to access and manipulate the same hardware resource library. The unified resource library is a global resource pool containing server hardware configuration information, device drivers, firmware updates, and more. It integrates and manages all server hardware resources, such as processors, memory, storage devices, and network interfaces. The API (Application Programming Interface) is a unified interface through which the BIOS module and BMC module can access and manipulate resources in the unified resource library. The API interface provides a standardized access path for the BIOS module and BMC module, simplifying the development and maintenance process.

[0047] Under the unified resource library architecture, BMBIOS (for ease of description and understanding, the functional integration of the BIOS module and BMC module is defined as BMBIOS in this disclosure embodiment) is not only responsible for initializing hardware and booting the operating system, but also acts as a hardware resource manager. During system startup, BMBIOS initializes the processor, memory, and other critical hardware components, loads and boots the operating system. BMBIOS comprehensively manages various hardware resources through a resource manager. The resource manager can monitor hardware resource usage in real time and intelligently adjust resource allocation based on system load, hardware performance characteristics, and user policies. When a target application requires more computing resources, the resource manager temporarily allocates idle processor cores to that application to ensure its smooth operation. When the system load decreases, the resource manager promptly reclaims resources for use by other applications or system services. When system memory usage approaches its limit, the resource manager can optimize memory allocation and release unused memory blocks to ensure stable system operation.

[0048] For example, the embedded system platform is configured with multiple processor modules, which are RISC-V architecture processors modularized according to processor functions; according to the task requirements of the BIOS module and the BMC module, processor modules that are suitable for the task requirements are selected and combined from the multiple processor modules.

[0049] Similar to the modular functionality of BIOS and BMC, this disclosure utilizes the modular design of RISC-V to combine different functional modules of the processor into a multi-processor module system platform. As mentioned earlier, a significant feature of the RISC-V architecture is its modular design. This design allows for the selection and combination of different processor modules according to actual needs, including but not limited to: integer arithmetic modules, responsible for basic arithmetic operations such as addition, subtraction, multiplication, and division; floating-point arithmetic modules, handling floating-point operations, suitable for applications requiring high-precision computing, such as scientific computing and graphics processing; storage interface modules, managing interfaces with memory and storage devices to implement data read and write operations; and accelerator modules, optimized for specific tasks such as image processing and encryption / decryption. For example, in a low-power embedded system, only the integer arithmetic module and the storage interface module can be selected to reduce power consumption and cost, while in a high-performance computing server, a floating-point arithmetic module and multiple accelerator modules can be selected to improve computing power and efficiency.

[0050] For example, the system further includes a management interface and a user interface. The management interface integrates the task functions of the BIOS module and the BMC module. The task functions include, but are not limited to, at least one of the following: hardware configuration management, device driver loading, firmware update, system status monitoring, and fault warning. The various task functions of the BIOS module and the BMC module are displayed through the user interface.

[0051] This disclosure also provides a unified management interface that integrates the functions of the BIOS and BMC, and displays and operates them through a unified user interface, achieving convenience and intuitiveness in system management. Specifically, the unified management interface requires deep integration of the various functional modules of the BIOS and BMC modules at the underlying design level to ensure efficient and accurate information exchange. These tasks include, but are not limited to, hardware configuration management, device driver loading, firmware updates, system status monitoring, and fault warnings. The user interface aims to provide users with an intuitive and easy-to-use system management platform. The main interface displays overview information about the system, such as CPU usage, memory usage, and system temperature. Users can click on the corresponding module to enter a detailed management page to view or operate the various tasks of the BIOS and BMC modules.

[0052] For example, the embedded system platform is configured with a message queue to provide a channel for information interaction between the BIOS module and the BMC module. When the BIOS starts, the BIOS module obtains the real-time hardware status information in the message queue by querying the message queue, and sends the BIOS running information to the message queue. The real-time hardware status information is obtained and sent to the message queue by the BMC module, and the BIOS running information includes the BIOS startup progress and error log.

[0053] The message queue mechanism provides an ordered, cross-module information exchange channel between the BIOS module and the BMC module. During the BIOS boot process, real-time hardware status information sent by the BMC module can be obtained by querying the message queue. Simultaneously, the BIOS module can also send boot progress and error log information to the message queue for analysis and processing by the BMC module. Obtaining real-time hardware status information during BIOS boot is crucial for system initialization and configuration. This information includes, but is not limited to, processor temperature, fan speed, and memory usage. For example, when the BIOS boots, the BIOS module queries the BMC module for processor temperature information via the message queue. If the temperature is too high, the appropriate BIOS module can take measures, such as adjusting fan speed or reducing processor frequency, to prevent system overheating. During the boot process, the BIOS generates BIOS operational information such as boot progress and error logs. This BIOS operational information is sent to the corresponding BMC module via the message queue, helping the BMC understand the BIOS boot status and provide support when necessary.

[0054] The embedded system platform is configured with an event notification mechanism for real-time communication between the BIOS module and the BMC module. The event notification mechanism is configured to obtain the real-time hardware status information of the corresponding resource when the BMC module detects a change in the status of a resource in the hardware resource library or receives a management instruction from the user for the resource, and send the real-time hardware status information to the BIOS module through the message queue.

[0055] In embedded system platforms, the event notification mechanism provides an efficient channel for real-time communication between the BIOS module and the BMC module. This mechanism ensures that when the BMC detects a hardware status change or receives a user's management command, it can quickly notify the relevant BIOS module, allowing the BIOS module to respond promptly, adjust system configuration, or execute specific tasks. For example, when the BMC detects a change in the status of certain resources in the hardware resource library, it sends the real-time hardware status information of the corresponding resource to the BIOS via a message queue through the event notification mechanism. For instance, if the BMC detects a sudden increase in processor temperature to a critical value, it will immediately trigger an event notification, sending this temperature information to the relevant BIOS module. Upon receiving the notification, the BIOS can take appropriate measures, such as increasing fan speed or reducing processor load, to ensure the system operates within a safe temperature range. Similarly, when the BMC receives user management commands for hardware resources, such as system restart, firmware update, or fan speed adjustment, it uses the event notification mechanism to transmit the real-time hardware status information of the corresponding resource to the relevant BIOS module via a message queue, enabling the BIOS to execute the operations indicated by the management commands.

[0056] For example, the embedded system platform is configured with a message scheduling algorithm; the message scheduling algorithm is configured to dynamically sort the information in the message queue based on the priority of each piece of information in the message queue, and schedule and process the information with higher priority when executing the target task. The priority of the information in the message queue is defined according to the nature of the information and the degree of its impact on the system.

[0057] Each message in a message queue has its own priority. Priority is defined based on the nature of the message and its impact on the system. For example, a hardware overheating alarm has high priority; a CPU utilization report has medium priority; and periodic status checks have low priority. Messages in the message queue are dynamically ordered according to their priorities. This ensures that the system always processes high-priority messages first. The dynamic ordering algorithm can be implemented using efficient sorting algorithms such as heap sort and quick sort. When the embedded system platform needs to execute a target task, the message scheduling algorithm schedules and processes messages according to their priorities. Assume there are three messages in the message queue:

[0058] Message A: Hardware overheating alarm (high priority);

[0059] Message B, CPU utilization report (high priority);

[0060] Message C, periodic status check (low priority); Suppose that while the system is processing message A, it receives a new message D captured by the BMC module, a power supply voltage abnormality alarm (highest priority). The message scheduling algorithm will immediately insert message D at the front of the message queue to ensure it is processed first. The queue order becomes: message D > message A > message B > message C. This ensures that, given limited system resources, the most important messages are processed first.

[0061] For example, the embedded system platform is configured with a machine learning algorithm, which is configured to input the current real-time hardware status information in the message queue into a historical training model, and predict the changing trend of the real-time hardware status information based on the output of the historical training model. The historical training model is pre-trained using the real-time hardware status information collected historically in the message queue.

[0062] In embedded system platforms, machine learning algorithms are configured to process real-time hardware status information in message queues. By analyzing current real-time and historical data, these algorithms predict trends in system status changes, thereby optimizing the system's decision-making process and response capabilities. First, a historical training model needs to be pre-built. This model is trained using historically collected real-time hardware status information from the message queue. Optionally, real-time hardware status information is first collected from the message queue, and then the collected data is cleaned to remove noise and invalid data, ensuring data quality. Next, useful features are extracted from the raw data, such as the rate of temperature change and CPU load fluctuation patterns. Finally, using the extracted feature data, a machine learning algorithm is trained to generate the trained historical training model. Assume the system collected the following data over a period of time: at one moment, the hardware temperature was 50°C and the CPU utilization was 70%, subsequently rising to 60°C; at another moment, the hardware temperature was 55°C and the CPU utilization was 75%, subsequently rising to 65°C. Through the historical training model, the relationship between temperature and CPU utilization is identified, and future temperature change trends are predicted. During system operation, machine learning algorithms input the current real-time hardware status information from the message queue into a pre-trained historical model. Suppose that at the current moment, the message queue receives two new real-time hardware status entries: hardware temperature 57℃ and CPU utilization 72%. These two entries are then input into the trained model. The historical training model, based on the input real-time hardware status information and historical data, predicts the changing trends of the real-time hardware status information, thereby predicting the changing trends of the system status. This prediction helps the system respond and adjust in advance. Based on the input real-time data, the model predicts that the hardware temperature may rise to 65℃ within the next 10 minutes. If the temperature exceeds a certain critical value, it may cause the system to overheat, affecting normal operation. Based on the prediction, the system can take preventative measures, such as reducing CPU load, increasing fan speed, and sending warning messages, to avoid potential problems.

[0063] Machine learning algorithms configured in embedded system platforms enable intelligent system management through the analysis and prediction of real-time hardware status information and historical data. They can proactively identify potential risks, optimize the allocation and use of system resources, and improve the overall performance and stability of the system.

[0064] For example, the system further includes a fast boot module, which integrates a boot function to configure the BIOS boot process as a Linux boot kernel boot process; the fast boot module is configured with a fast memory mapping mechanism, which is configured to map large data files required in the BIOS boot process to the memory address space; the system further includes a network remote boot module, which provides a remote wake-up function, sends a remote wake-up request over the network, and remotely manages the configuration of the fast boot module over the network.

[0065] The fast boot module integrates the basic boot functions of traditional BIOS and deeply integrates the boot process into the Linux Boot kernel startup process. Traditional BIOS typically performs a series of self-test steps (such as memory testing and hardware initialization), which can be time-consuming in some cases. To optimize boot time, the fast boot module removes unnecessary self-test steps and directly loads the Linux kernel for system initialization and operating system startup. The fast memory mapping mechanism aims to accelerate the loading of large data files during the boot process. During boot, a large amount of configuration files, drivers, and other data needs to be read and loaded. By directly mapping this data into the memory address space, data access speed can be significantly improved, reducing boot time. For example, if a 100MB operating system image file needs to be loaded during boot, traditionally, this might require multiple disk reads. However, with the fast memory mapping mechanism, the file can be mapped into memory all at once, reducing disk I / O operations and improving loading efficiency.

[0066] The network remote boot module leverages the BMC's management capabilities to provide remote wake-up functionality. Administrators can send wake-up commands via LAN or the internet to trigger the wake-up operation of remote computers. This is significant for managing large-scale servers, allowing administrators to remotely control server power on / off without physically being present on-site. The network remote boot module also provides remote configuration management functions, allowing administrators to update boot configurations and load new system images via the network. This makes system maintenance and updates more flexible and efficient. For example, if an administrator needs to update the operating system image files of multiple servers, traditionally, this would require manual operation on each server individually. However, with the remote configuration management function, the administrator can update the image files of all servers simultaneously over the network, significantly improving work efficiency.

[0067] By combining the fast boot module and the network remote boot module, the system can not only achieve rapid startup but also be flexibly managed remotely over the network. This integration not only improves the system's response speed but also provides administrators with convenient management tools, enhancing the overall system's reliability and security.

[0068] For example, the system further includes a wake-up control module for listening to wake-up requests from different sources on the server; the wake-up control module is configured with a wake-up decision algorithm, which is configured to determine the current power state of the system based on the current power state and load of the system, and, if the current power state of the system is low, prioritize waking up the service indicated by the wake-up request with higher priority, wherein the priority of the wake-up request is defined based on the urgency of the wake-up request and the degree of impact on the system.

[0069] The Agile Wake-up Control Module is responsible for listening to wake-up requests from various sources on the server, including hard drives, PCIe devices, keyboards, mice, and networks. This means that hardware activity, user input, and network commands can all trigger system wake-up. The Wake-up Control Module ensures the priority wake-up of critical services through wake-up request priority management. Different wake-up requests are assigned different priorities based on their urgency and impact on the system. When multiple wake-up requests arrive simultaneously, the Wake-up Control Module determines which request to respond to first based on its priority. For example, if the server receives two wake-up requests: one is a user's mouse movement (lower priority), and the other is an important task on the hard drive (higher priority), the Agile Wake-up Control Module will prioritize the important task on the hard drive, ensuring that critical system functions are restored first. The wake-up decision algorithm intelligently determines whether to execute a wake-up operation based on factors such as the system's current state and power management policies. The algorithm assesses the current power level and system load, deciding under what conditions to execute the wake-up operation. When the system is in a low-power state, the wake-up decision algorithm prioritizes higher-priority wake-up requests. This is to ensure that the system can continue to perform the most important tasks under limited power conditions. Suppose the server has low battery power but receives two wake-up requests simultaneously: a system update notification (low priority) and a remote work instruction from the network (high priority). The wake-up decision algorithm will prioritize the remote work instruction from the network based on the current low battery status to ensure that important tasks can be executed in a timely manner.

[0070] For example, the system further includes a fault recovery module configured to automatically detect faults in the BIOS module and the BMC module, and execute an automatic repair process. The automatic repair process includes, but is not limited to, restoring data from backups, restarting the corresponding modules, and reconfiguring the parameter settings of the faulty module. The fault recovery module interacts with the hardware resource library through the API interface to ensure data integrity and continued system operation in the event of hardware or software failures.

[0071] The fault recovery module monitors the status of the BIOS and BMC modules in real time. Upon detecting an anomaly or fault, it can quickly take measures to repair or restore the system, minimizing system downtime and the risk of data loss. The fault recovery module works closely with the system's API interfaces and hardware resource library, utilizing information from the hardware resource library and the functions provided by the resource manager to perform fault detection and recovery operations. For example, when a BIOS module fault is detected, the fault recovery module can instruct the resource manager to retrieve backup data for restoration or reconfigure hardware settings to suit current operational needs.

[0072] In addition, the fault recovery module is also configured to automatically restart the faulty module or adjust configuration settings to ensure that the system can be restored to its optimal state in the shortest possible time.

[0073] By integrating the fault recovery module into the server integrated firmware system, the system's response speed and processing capability to faults can be greatly improved, thereby ensuring the system's high availability and business continuity. This helps meet the growing reliability and automation requirements of data centers and provides an important guarantee for the stable operation of the server integrated firmware system.

[0074] Figure 2 This is a schematic diagram of the design architecture of a server integrated firmware system according to one embodiment of this disclosure. As mentioned above, this disclosure first provides the lowest-level software design, based on a modular design of the RISC-V architecture. Its design goal is to provide a simple, flexible, scalable, and freely usable architecture. The modular design of the core processor allows for the selection and combination of different processor modules according to specific needs. The modular design of the RISC-V architecture is also reflected in its customizability, allowing for the selection of appropriate processor modules according to different application scenarios to meet various needs ranging from low-power embedded systems to high-performance computing servers. This disclosure uses RISC-V as the core processor of the system, leveraging its reduced instruction set design and high flexibility to provide the system with efficient computing power.

[0075] Next is the integrated design, which involves the underlying hardware design of the BIOS, BMC, and OS. To fully leverage the advantages of the RISC-V processor, this disclosure implements a novel architecture design that deeply integrates the BIOS, BMC, and operating system. By modularizing the BIOS and BMC and integrating these modules on the RISC-V architecture, more efficient task processing and information exchange can be achieved. This disclosure designs a unified resource library and API interface, allowing the BIOS and BMC modules to access and operate the same hardware resource library. The hardware resource library contains server hardware configuration information, device drivers, firmware updates, etc., while the API interface provides standardized access paths, simplifying the development and maintenance process. The integrated control module is responsible for coordinating the task execution of the BIOS and BMC modules and communicating through the unified API interface. This not only reduces the waste of hardware resources but also improves system resource utilization and task execution accuracy. This disclosure deeply integrates the BIOS, BMC, and operating system (OS) into the RISC-V architecture, achieving a more compact and efficient system architecture, forming a highly integrated system solution.

[0076] This disclosure provides a unified internal and external management interface design, a user-oriented integrated design. This unified management interface integrates the functions of the BIOS and BMC, providing users with a convenient management platform through standardized interfaces and protocols. The unified user interface design offers users an intuitive and easy-to-use system management platform. In this disclosure, a unified management interface is crucial for improving the efficiency and convenience of system management. The management interface aims to not only integrate the BIOS and BMC at the underlying level but also integrate management functions into a unified user interface, thereby providing users with a more intuitive and convenient system management and maintenance experience.

[0077] Finally, there's the agile system wake-up function design, an integrated software system design. The fast boot module optimizes the boot process and hardware initialization steps during system startup to achieve rapid booting. This shortens system startup time and improves user experience. The wake-up control module monitors system status and receives external wake-up signals, quickly responding and resuming system operation in hibernation or low-power states. The network remote boot module allows the system to receive boot commands over the network, enabling remote booting and management. This is particularly important for server management in data center and cloud computing environments, significantly improving management efficiency and flexibility. BMBIOS integrates the boot functions of traditional BIOS and OS boot functions, eliminating the distinction between the two boot programs. It directly uses Linux Boot to boot the entire machine, with the Linux kernel directly used to initialize the computer system and load the operating system. Furthermore, BMBIOS also possesses BMC management capabilities, allowing for remote booting of the computer system over the network.

[0078] Figure 3 This is a schematic diagram illustrating the steps of a task processing method provided in one embodiment of the present disclosure. The method is applied to the server firmware integration system described above. Figure 3 As shown, the method includes:

[0079] Step S201: Receive task instructions from the target application.

[0080] Step S202: According to the task instruction, call the corresponding BIOS module and / or BMC module to execute the target task, and allocate the resources required to execute the target task to the BIOS module and / or BMC module. The BIOS module and the BMC module are obtained by modularizing the BIOS and BMC according to the task functions through a RISC-V architecture processor.

[0081] Step S203: Return the execution result of the target task to the target application.

[0082] In step S201, the integrated control module of the server's integrated firmware system receives task instructions from the target application. The target application sends a specific operation request to the integrated control module, which includes the specific task to be executed and its parameters.

[0083] In step S202, the BIOS and BMC are modularly designed according to different task functions, resulting in multiple BIOS modules and BMC modules. Leveraging the flexibility and scalability of the RISC-V processor, these BIOS modules and BMC modules are integrated into a unified embedded system platform. In this step, based on the received task instruction, the integration control module parses the instruction content and determines the specific BIOS module and / or BMC module to be invoked and its functions. The integration control module then invokes the corresponding module to execute the target task and allocates the resources required for task execution to these modules. For example, suppose the target application sends a task instruction requesting the monitoring of the processor temperature of a server. The task instruction includes the identifier of the target server and the specific parameters of the monitoring task. After parsing the task instruction, the integration control module determines that the hardware monitoring function in the BMC module needs to be invoked and allocates the necessary resources (such as memory and computing resources) to the BMC module to execute the temperature monitoring task.

[0084] In step S203, after the BIOS module and / or BMC module complete the target task, they return the task execution result (e.g., operation success, failure, or specific monitoring data) to the integrated control module. The integrated control module processes these results and returns them to the target application that sent the task instruction. Continuing the previous example, after the BMC module completes the temperature monitoring task, it returns the processor's temperature data to the integrated control module. The integrated control module processes this data and returns it to the target application.

[0085] The task processing method provided in this disclosure significantly improves server performance and resource management efficiency through a process of receiving task instructions, calling corresponding modules to execute tasks, and returning execution results. The integration of a control module, a RISC-V architecture processor, and its modular design enables the system to flexibly respond to various task requirements, providing an efficient solution for cloud computing and big data processing.

[0086] Those skilled in the art will understand that embodiments of this disclosure can be provided as systems and methods. Therefore, embodiments of this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of this disclosure can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0087] This disclosure describes embodiments of systems and methods according to embodiments of this disclosure with reference to flowchart illustrations and / or block diagrams. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing terminal equipment to cause a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0088] While preferred embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0089] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element. The above provides a detailed description of a server integrated firmware system and task processing method provided by this disclosure. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the above embodiments are only for the purpose of helping to understand the method and its core ideas; at the same time, for those skilled in the art, based on the ideas of this disclosure, there will be changes in specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A server integrated firmware system, characterized in that, The system includes: An integrated control module is used to receive and process task instructions from the target application, call the corresponding BIOS module and / or BMC module to execute the target task according to the task instructions, and return the execution result to the target application. An embedded system platform integrates multiple BIOS modules and BMC modules. The BIOS modules and BMC modules are obtained by modularizing the BIOS and BMC according to their respective task functions using a RISC-V architecture processor. The system also includes a hardware resource library and an API interface. The hardware resource library is used to integrate and manage hardware resources on the server. The BIOS module and the BMC module access and operate the hardware resource library through the API interface. The hardware resource library integrates a resource manager, which is used to monitor the server's operating load, hardware performance characteristics, and user-defined policies, and to allocate and manage the resources of the hardware resource library. The embedded system platform is configured with a message queue to provide a channel for information exchange between the BIOS module and the BMC module; When the BIOS starts, the BIOS module obtains the real-time hardware status information in the message queue by querying the message queue, and sends the BIOS running information to the message queue. The real-time hardware status information is obtained and sent to the message queue by the BMC module, and the BIOS running information includes the BIOS startup progress and error log. The embedded system platform is configured with an event notification mechanism for real-time communication between the BIOS module and the BMC module; The event notification mechanism is configured such that when the BMC module detects a change in the status of a resource in the hardware resource library, or receives a management instruction from the user for a resource, it obtains the real-time hardware status information of the corresponding resource and sends the real-time hardware status information to the BIOS module through the message queue.

2. The system according to claim 1, characterized in that, The embedded system platform is configured with multiple processor modules, which are obtained by modularizing RISC-V architecture processors according to their functions; Based on the task requirements of the BIOS module and the BMC module, a processor module suitable for the task requirements is selected and combined from multiple processor modules.

3. The system according to claim 1, characterized in that, The system also includes a management interface and a user interface. The management interface integrates the task functions of the BIOS module and the BMC module. The task functions include, but are not limited to, at least one of the following: hardware configuration management, device driver loading, firmware update, system status monitoring, and fault warning. The various tasks and functions of the BIOS module and the BMC module are displayed through the user interface.

4. The system according to claim 1, characterized in that, The embedded system platform is configured with a message scheduling algorithm; The message scheduling algorithm is configured to dynamically sort the information in the message queue based on the priority of each message in the message queue. When executing the target task, it schedules and processes information with higher priority. The priority of information in the message queue is defined according to the nature of the information and the degree of its impact on the system.

5. The system according to claim 1, characterized in that, The embedded system platform is configured with a machine learning algorithm, which is configured to input the current real-time hardware status information in the message queue into a historical training model, and predict the changing trend of the real-time hardware status information based on the output of the historical training model. The historical training model is pre-trained using the real-time hardware status information collected historically in the message queue.

6. The system according to claim 1, characterized in that, The system also includes a fast boot module, which integrates boot functionality to configure the BIOS boot process as a Linux boot kernel boot process. The fast boot module is configured with a fast memory mapping mechanism, which is configured to map large data files required in the BIOS boot process to the memory address space. The system also includes a network remote boot module for providing remote wake-up functionality, sending remote wake-up requests over the network, and remotely managing the configuration of the fast boot module over the network.

7. The system according to claim 1, characterized in that, The system also includes a wake-up control module for listening to wake-up requests from different sources on the server; The wake-up control module is configured with a wake-up decision algorithm. The wake-up decision algorithm is configured to determine the current power status of the system based on the current power status and load status of the system. When the current power status of the system is low, the algorithm prioritizes waking up the service indicated by the wake-up request with higher priority. The priority of the wake-up request is defined based on the urgency of the wake-up request and the degree of impact on the system.

8. A task processing method, characterized in that, Applied to the system as described in any one of claims 1-7, the method comprises: Receive task instructions from the target application; The task instruction calls the corresponding BIOS module and / or BMC module to execute the target task, and allocates the resources required to execute the target task to the BIOS module and / or BMC module. The BIOS module and the BMC module are obtained by modularizing the BIOS and BMC according to the task functions through a RISC-V architecture processor. The execution result of the target task is returned to the target application.

Images