Signal processing circuit and memory

Abstract

The present disclosure provides a signal processing circuit and memory, the signal processing circuit comprising a command processing circuit, a clock processing circuit, and a command sampling circuit. The command processing circuit is configured to generate and output a first command signal based on a command / address signal CA; the clock processing circuit is configured to generate a clock control signal GT based on a first chip select signal CS and a first clock signal CLK, and to process the first clock signal CLK according to the clock control signal to generate and output a sampling clock signal CLKD; the command sampling circuit is coupled to the command processing circuit and the clock processing circuit, respectively, and samples the first command signal based on the sampling clock signal to output a second command signal. The clock control signal is configured to control the output of the sampling clock signal before the first command signal reaches the command sampling circuit, and to control the output of the sampling clock signal when the first command signal reaches the command sampling circuit. Therefore, the power consumption of the signal processing circuit can be reduced.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a signal processing circuit and a memory. Background Art

[0002] A memory is a semiconductor device that stores data and performs corresponding data processing based on received command / address (CA) signals, including but not limited to data reading, data writing, and other control operations. The memory receives not only command / address signals but also a clock signal, CLK, which it uses to sample the command and address signals and then performs data processing based on the sampled command and address signals.

[0003] In the prior art, a memory is provided with a command processing circuit, a clock buffer circuit, a delay circuit, and a command sampling circuit. The command processing circuit is configured to receive and pre-process a command / address signal to output a first command signal. The clock buffer circuit is configured to receive and buffer a clock signal. The delay circuit is configured to retrieve and delay the clock signal from the clock buffer circuit, and output the delayed clock signal as a sampling clock signal, such that the sampling clock signal arrives at the command sampling circuit after the first command signal. The command sampling circuit is configured to sample the first command signal according to the sampling clock signal to generate and output a second command signal.

[0004] However, the above memory has the problem of high circuit power consumption. Summary of the Invention

[0005] An embodiment of the present disclosure provides a signal processing circuit and a memory for reducing circuit power consumption.

[0006] In a first aspect, the present disclosure provides a signal processing circuit, comprising: a command processing circuit, a clock processing circuit, and a command sampling circuit;

[0007] The command processing circuit is configured to receive a command / address signal CA, and generate and output a first command signal based on the command / address signal;

[0008] The clock processing circuit is configured to receive a first chip select signal CS and a first clock signal CLK, generate a clock control signal GT based on the first chip select signal and the first clock signal, and process the first clock signal according to the clock control signal to generate and output a sampling clock signal CLKD;

[0009] The command sampling circuit is coupled to the command processing circuit and the clock processing circuit respectively, and samples the first command signal based on the sampling clock signal to output a second command signal;

[0010] The clock control signal is used to control not outputting the sampling clock signal before the first command signal reaches the command sampling circuit, and to control outputting the sampling clock signal when the first command signal reaches the command sampling circuit.

[0011] In some embodiments, the clock processing circuit includes: a clock control signal generating circuit and a clock control circuit;

[0012] The clock control signal generating circuit is configured to receive the first chip select signal and the first clock signal, and generate and output the clock control signal according to the first chip select signal and the first clock signal; wherein the clock control signal starts to be at an effective level earlier than the time when the first command signal reaches the command sampling circuit;

[0013] The clock control circuit is connected to the clock control signal generating circuit, and is used to control whether to generate and output the sampling clock signal based on the first clock signal according to the clock control signal.

[0014] In some embodiments, the clock control signal generating circuit includes: a decoding window signal generating circuit and a clock control signal generator;

[0015] The decoding window signal generating circuit is configured to adjust the pulse width of the first chip select signal to generate a decoding window signal, and output the decoding window signal from its output terminal;

[0016] The clock control signal generator is used to generate the clock control signal based on the first clock signal and the decoding window signal, wherein the starting time when the clock control signal is at a valid level is determined by the starting time when the decoding window signal is at a valid level, and the pulse width of the clock control signal is equal to a preset number of clock cycles of the first clock signal, and the processing operation corresponding to the second command signal is completed during the period when the clock control signal is at a valid level.

[0017] In some embodiments, the clock control signal generator includes a clock counter, an SR latch, and a first adjustable delay circuit;

[0018] The clock counter is configured to receive a decoding window extension signal and the first clock signal, count the first clock signal to generate a count value after the decoding window extension signal is at an effective level, and generate a reset signal when the count value reaches a preset number, and output the reset signal from an output terminal thereof; wherein the clock counter performs a reset operation based on the reset signal;

[0019] The SR latch is connected to the clock counter and is used to generate the decoding window extension signal according to the decoding window signal and the reset signal;

[0020] The first adjustable delay circuit is connected to the SR latch and is used to delay the decoding window expansion signal to obtain the clock control signal.

[0021] In some embodiments, the first adjustable delay circuit includes a plurality of inverters connected in series;

[0022] The SR latch includes: a first NOR gate, a second NOR gate and a first inverter, wherein the two input ends of the first NOR gate are respectively connected to the output end of the decoding window signal generating circuit and the output end of the second NOR gate, the two input ends of the second NOR gate are respectively connected to the output end of the clock counter and the output end of the first NOR gate, the output end of the first NOR gate is connected to the input end of the first inverter, and the first inverter is used to output the decoding window extension signal.

[0023] In some embodiments, the clock processing circuit further includes: a second adjustable delay circuit, coupled to the output end of the clock control circuit and the input end of the command sampling circuit, respectively, for delaying the sampling clock signal output by the clock control circuit to input the delayed sampling clock signal to the command sampling circuit.

[0024] In some embodiments, when the first adjustable delay circuit includes an odd number of inverters, the clock control circuit includes: a NAND logic circuit, configured to perform a NAND logic operation on the clock control signal and the first clock signal to obtain the sampling clock signal;

[0025] When the first adjustable delay circuit includes an even number of inverters, the clock control circuit includes an AND logic processing circuit configured to perform an AND logic operation on the clock control signal and the first clock signal to obtain the sampling clock signal.

[0026] In some embodiments, the decoding window signal generating circuit includes: a chip select sampling control circuit, a chip select signal sampling circuit and a logic processing circuit;

[0027] The chip select sampling control circuit is configured to receive the first clock signal and generate a plurality of chip select sampling control signals based on the first clock signal;

[0028] The chip select signal sampling circuit is connected to the chip select sampling control circuit and is used to sample the first chip select signal under the control of the multiple chip select sampling control signals to generate and output multiple second chip select signals, wherein the pulse width of each second chip select signal is greater than the pulse width of the first chip select signal;

[0029] The logic processing circuit is connected to the chip select signal sampling circuit, and is used to perform logical operations on multiple second chip select signals and the first chip select signal to generate the decoding window signal. When the first chip select signal and / or at least one second chip select signal is at a valid level, the decoding window signal is at a valid level.

[0030] In some embodiments, the chip select sampling control circuit includes a first chip select sampling control subcircuit and a second chip select sampling control subcircuit;

[0031] The first chip select sampling control subcircuit includes N stages of second inverters connected in series, the first stage of the second inverters is used to receive the first clock signal, and the output signal of each stage of the second inverter serves as a chip select sampling control signal;

[0032] The second chip select sampling control subcircuit includes N stages of third inverters connected in series, wherein the first stage of the third inverter is used to receive a second clock signal, the second clock signal being an inverted signal of the first clock signal, and the output signal of each stage of the third inverter serves as a chip select sampling control signal;

[0033] The second inverter and the third inverter are both identical inverters, and the delay time for inverting and outputting the input signal is a preset delay;

[0034] The chip select sampling control signal includes a first chip select sampling control signal and a second chip select sampling control signal; the first clock signal, the output signal of the third inverter of the odd-numbered stage, and the output signal of the second inverter of the even-numbered stage together constitute N+1 first chip select sampling control signals, and the N+1 first chip select sampling control signals have a preset delay in sequence; the second clock signal, the output signal of the second inverter of the odd-numbered stage, and the output signal of the third inverter of the even-numbered stage together constitute N+1 second chip select sampling control signals, and the N+1 second chip select sampling control signals have a preset delay in sequence.

[0035] In some embodiments, the chip select signal sampling circuit includes: a first chip select sampling subcircuit and a second chip select sampling subcircuit;

[0036] The first chip select sampling subcircuit comprises: N+1 stages of cascaded first flip-flops, wherein the input of the first flip-flop of the first stage receives the first chip select signal, the output of the first flip-flop of each stage is connected to the input of the first flip-flop of the next stage, the clock of the first flip-flop of each stage receives a first chip select sampling control signal, and the output of the first flip-flop of each stage outputs a second chip select signal; wherein the clock of the first flip-flop of the i-th stage receives the (N+2-i)th first chip select sampling control signal, where i is a positive integer less than or equal to N+1;

[0037] The second chip select sampling subcircuit includes: N+1 levels of cascaded second flip-flops, the input end of the first level of the second flip-flop receives the first chip select signal, the output end of each level of the second flip-flop is connected to the input end of the next level of the second flip-flop, the clock end of each level of the second flip-flop receives a second chip select sampling control signal, and the output end of each level of the second flip-flop outputs a second chip select signal; wherein, the clock end of the j-th level of the second flip-flop receives the (N+2-j)th second chip select sampling control signal, and j is a positive integer less than or equal to N+1.

[0038] In some embodiments, the effective levels of the first chip select signal and the second chip select signal are low levels, the effective level of the decoding window signal is high level, and the logic processing circuit includes: a first AND logic circuit, a second AND logic circuit, and a NAND logic circuit;

[0039] The first AND logic circuit is configured to receive the N+1 second chip select signals output by the first chip select sampling sub-circuit, and perform an AND logic operation on the N+1 second chip select signals to generate a first result signal;

[0040] The second AND logic circuit is configured to receive the N+1 second chip select signals output by the second chip select sampling sub-circuit, and perform an AND logic operation on the N+1 second chip select signals to generate a second result signal;

[0041] The NAND logic circuit has an input end connected to the first AND logic circuit and the second AND logic circuit, and is used to perform a NAND logic operation on the first result signal, the second result signal and the first chip select signal to generate the decoding window signal.

[0042] In a second aspect, the present disclosure provides a memory comprising the signal processing circuit according to the first aspect.

[0043] The present disclosure provides a signal processing circuit and memory, including a command processing circuit, a clock processing circuit, and a command sampling circuit. The command processing circuit is configured to receive a command / address signal CA and generate and output a first command signal based on the command / address signal. The clock processing circuit is configured to receive a first chip select signal CS and a first clock signal CLK, generate a clock control signal GT based on the first chip select signal and the first clock signal, and process the first clock signal according to the clock control signal to generate and output a sampling clock signal CLKD. The command sampling circuit is coupled to the command processing circuit and the clock processing circuit, respectively, and samples the first command signal based on the sampling clock signal to output a second command signal. The clock control signal is configured to control the command sampling circuit from outputting the sampling clock signal before the first command signal arrives at the command sampling circuit, and to output the sampling clock signal when the first command signal arrives at the command sampling circuit. Therefore, the power consumption of the signal processing circuit can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0045] Figure 1 It is a structural block diagram of a signal processing circuit provided by the prior art;

[0046] Figure 2 is a structural block diagram of a signal processing circuit provided by an embodiment of the present disclosure;

[0047] Figure 3 1 is a schematic structural diagram of a command receiving circuit and a command processing circuit provided by an embodiment of the present disclosure;

[0048] Figure 4 is a structural diagram of a clock processing circuit provided by an embodiment of the present disclosure;

[0049] Figure 5 is a structural diagram of an SR latch provided by an embodiment of the present disclosure;

[0050] Figure 6 is a schematic diagram of the relationship between a sampling clock signal and related signals provided by an embodiment of the present disclosure;

[0051] Figure 7 1 is a schematic structural diagram of a chip select sampling control circuit provided by an embodiment of the present disclosure;

[0052] Figure 8 1 is a schematic structural diagram of a chip select signal sampling circuit provided by an embodiment of the present disclosure;

[0053] Figure 9is a structural diagram of a logic processing circuit provided by an embodiment of the present disclosure;

[0054] Figure 10 、 Figure 11 Schematic diagrams of two relationships between decoding window signals and correlation signals provided by embodiments of the present disclosure.

[0055] The above drawings illustrate specific embodiments of the present disclosure, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0056] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0057] The embodiments of the present disclosure are applicable to memories, such as DRAM (dynamic random accessing memory), including but not limited to: DDR (double data rate) 1 to DDR5 DRAM. In DRAM, an external circuit sends a command / address signal CA and a clock signal CLK to the DRAM to process the data stored in the DRAM. However, it is necessary to perform a series of processing on the command / address signal CA and the clock signal CLK sent by the external circuit to generate and output a second command signal CMD2 executable by the DRAM, and then realize the data processing in the memory by executing the second command signal CMD2. Therefore, a signal processing circuit is provided in the DRAM to output the second command signal CMD2 according to the above-mentioned command / address signal CA and the clock signal CLK.

[0058] Figure 1 A structural block diagram of a signal processing circuit provided by the prior art. Figure 1 As shown, the signal processing circuit includes a command processing circuit, a clock buffer circuit, a delay circuit and a command sampling circuit.

[0059] The input end of the command processing circuit is connected to the output end of the external circuit, and is used to receive the command / address signal CA sent by the external circuit, so as to pre-process the command / address signal CA and generate and output the first command signal CMD1.

[0060] In addition, the input of the clock buffer circuit is also connected to the output of the external circuit, and is used to receive the clock signal CLK sent by the external circuit and buffer the received clock signal CLK. The input of the delay circuit is connected to the output of the clock buffer circuit, and is used to delay the clock signal CLK to generate and output the sampling clock signal CLKD.

[0061] The delay circuit here is used to make the first command signal CMD1 arrive at the command sampling circuit before the sampling clock signal CLKD, but the time difference between the two arriving at the command sampling circuit is less than or equal to the preset time length. For example, the command / address signal CA is an ODT (On Die Termination) command signal, which is used for impedance matching to reduce reflection when receiving the signal. The ODT command signal needs to pass through Figure 3 The command processing circuit shown in FIG1 processes the output second command signal CMD1 to input the output second command signal CMD1 to the command sampling circuit. As a result, the second command signal CMD1 corresponding to the ODT command signal arrives at the command sampling circuit later than the clock signal CLK. Therefore, a delay circuit is required to delay the clock signal CLK so that the first command signal CMD1 corresponding to the ODT command signal arrives at the command sampling circuit before the sampling clock signal CLKD.

[0062] The two input ends of the command sampling circuit are respectively connected to the output end of the command processing circuit and the output end of the delay circuit, and are used to receive the first command signal CMD1 and the sampling clock signal CLKD, so as to sample the first command signal CMD1 through the sampling clock signal CLKD to obtain the second command signal CMD2.

[0063] In some embodiments, the delay circuit is formed by an even number of inverters connected in series. Therefore, when the clock signal CLK flips in level, the inverters flip in current accordingly, resulting in higher power consumption of the signal processing circuit.

[0064] To address the aforementioned technical issues, the disclosed embodiments utilize a clock control signal GT to prevent the sampling clock signal CLKD from being output before the first command signal CMD1 reaches the command sampling circuit, and to output the sampling clock signal CLKD upon arrival of the first command signal CMD1. Consequently, compared to the first clock signal CLK, the sampling clock signal CLKD undergoes fewer level toggling, thereby reducing power consumption.

[0065] In addition, the clock control signal GT in the embodiment of the present disclosure is generated according to the first chip select signal CS (Chip Select, chip select signal), so that when the first chip select signal CS selects the current chip, the power consumption of the current chip can be reduced.

[0066] Based on this, an embodiment of the present disclosure provides a signal processing circuit, Figure 2 : is a structural block diagram of a signal processing circuit provided by an embodiment of the present disclosure. Figure 2 As shown, the signal processing circuit of the embodiment of the present disclosure includes: a command processing circuit, a clock processing circuit and a command sampling circuit.

[0067] The command processing circuit is configured to receive a command / address signal CA and generate and output a first command signal CMD1 based on the command / address signal CA. The first command signal CMD1 may be obtained by performing at least one of the following processing on the command / address signal CA: drive processing, parameter conversion, or decoding. Drive processing is used to increase the signal's drive capability. Parameter conversion is used to convert external parameters into internal parameters of the memory.

[0068] From the above Figure 2 As can be seen in Figure 1, the command sampling circuit also requires a sampling clock signal CLKD to complete command sampling. The sampling clock signal CLKD is the output signal of the clock processing circuit. Specifically, the clock processing circuit is configured to receive the first chip select signal CS and the first clock signal CLK, generate a clock control signal GT based on the first chip select signal CS and the first clock signal CLK, and process the first clock signal CLK according to the clock control signal GT to generate and output the sampling clock signal CLKD.

[0069] Reference Figure 2 As shown, the command sampling circuit is coupled to the command processing circuit and the clock processing circuit, respectively. Specifically, the two input terminals of the command sampling circuit are coupled to the output terminal of the command processing circuit and the output terminal of the clock processing circuit, respectively. The command sampling circuit is used to sample the first command signal CMD1 based on the sampling clock signal CLKD to output the second command signal CMD2. The clock control signal GT is used to control whether the sampling clock signal CLKD is output before the first command signal CMD1 reaches the command sampling circuit, and to output the sampling clock signal CLKD when the first command signal CMD1 reaches the command sampling circuit. The command sampling circuit can be a D-type flip-flop (DFF, DFlip-Flop). The input terminal of the D-type flip-flop is connected to the output terminal of the command processing circuit for receiving the first command signal CMD1. The clock terminal of the D-type flip-flop is connected to the output terminal of the clock processing circuit for receiving the sampling clock signal CLKD. Therefore, the D-type flip-flop can sample the first command signal CMD1 when the rising edge or falling edge of the sampling clock signal CLKD arrives, generating and outputting the second command signal CMD2 through the output terminal.

[0070] It can be seen from the above description that the aforementioned description is an overview of the signal processing circuit. The detailed internal structures of the command processing circuit and the clock processing circuit in the signal processing circuit are described in detail below.

[0071] Figure 3 Schematic diagram of a command receiving circuit and a command processing circuit provided by an embodiment of the present disclosure. Figure 3 As shown, the command processing circuit may include: a driving circuit, a pre-processing circuit, and a command decoding circuit.

[0072] Among them, the two input ends of the command receiving circuit are respectively connected to the external circuit for receiving and buffering the command / address signal CA1 and the chip select signal CS1. If necessary, the command receiving circuit can also integrate and amplify the command / address signal CA1 and the chip select signal CS1 to obtain a full-swing signal. The command receiving circuit can be a 5G (5-level) gate circuit. Therefore, the command receiving circuit can generate and output the corresponding command / address signal CA and the first chip select signal CS for the command / address signal CA1 and the chip select signal CS1, respectively. Among them, the command / address signal CA can be a cached command / address signal CA1, or a full-swing signal of the command / address signal CA1. The first chip select signal CS can be a cached chip select signal CS1, or a full-swing signal of the chip select signal CS1.

[0073] The input end of the driving circuit is connected to an output end of the command receiving circuit, and is used to receive the command / address signal CA, drive and amplify CA, and generate and output the command / address signal CA2 with better driving capability. Therefore, it can resist the attenuation of the signal during transmission, which helps to ensure the correct transmission of the signal. The driving circuit can be a multi-stage gate circuit, for example, referring to Figure 3 As shown, an 11-level gate circuit is composed of multiple inverters connected in series.

[0074] The input end of the preprocessing circuit is connected to the output end of the driving circuit, and is configured to receive the command / address signal CA2, preprocess the command / address signal CA2, and generate and output the command / address signal CA3. The preprocessing here can be the conversion of external parameters into internal parameters. The preprocessing circuit can be an 8G latch (with 8 gate delays).

[0075] The command decoding circuit has an input connected to the output of the preprocessing circuit, and is configured to receive and decode the command / address signal CA3 to generate and output a first command signal CMD1. Therefore, the output of the command decoding circuit is connected to the input of the command sampling circuit to input the first command signal CMD1 to the command sampling circuit. The command decoding circuit can be a 10G (with 10-stage gate delay) logic gate circuit.

[0076] In summary, the delay of the first command signal CMD1 relative to the command / address signal CA represents the total processing time of the command processing circuit. When the command receiving circuit is a 5G logic gate circuit (with 5 levels of gate delay), the driving circuit is an 11G logic gate circuit (with 11 levels of gate delay), the pre-processing circuit is an 8G logic gate circuit (with 8 levels of gate delay), and the command decoding circuit is a 10G logic circuit (with 10 levels of gate delay), the total processing time of the command processing circuit is (5G + 11G + 8G + 10G) = the processing time of the 34G logic gate circuit.

[0077] It should be noted that the order of the driving circuit, the pre-processing circuit and the command decoding circuit in the above-mentioned command processing circuit can be swapped, and the embodiment of the present disclosure does not limit the order.

[0078] In some embodiments, reference Figure 2 As shown, the clock processing circuit may include a clock control signal generating circuit and a clock control circuit. The clock control signal generating circuit is configured to receive a first chip select signal CS and a first clock signal CLK, and generate and output a clock control signal GT based on the first chip select signal CS and the first clock signal CLK. The clock control circuit has an input terminal connected to an output terminal of the clock control signal generating circuit and is configured to control, based on the clock control signal GT, whether to generate and output a sampling clock signal CLKD based on the first clock signal CLK.

[0079] The clock control signal GT may be a signal obtained by extending the pulse width of the first chip select signal CS, and the duration of the active level of the clock control signal GT is determined by the clock period of the first clock signal CLK, and may be a preset multiple of the clock period of the first clock signal CLK. In addition, the starting time when the clock control signal GT is at the active level is earlier than the time when the first command signal CMD1 reaches the command sampling circuit. In other words, the setup time (ST, 1st F / F setup time) of the command sampling circuit needs to be guaranteed. Figure 6 As shown, the setup time ST is the time it takes for the first command signal CMD1 to remain stable before the sampling clock signal CLKD arrives. This is the time difference between the rising edge of the sampling clock signal CLKD and the rising edge of the first command signal CMD1. If the setup time is insufficient, the sampling clock signal CLKD may not sample the first command signal CMD1 on its rising or falling edge, resulting in command sampling errors. Therefore, embodiments of the present disclosure ensure sufficient setup time through the clock control signal GT, thereby ensuring successful command sampling.

[0080] After the clock control circuit receives the clock control signal GT and the first clock signal CLK, it can output the first clock signal CLK as the sampling clock signal CLKD when the clock control signal GT is at an active level; and not output the sampling clock signal CLKD when the clock control signal GT is at an inactive level. For example, taking the clock control signal GT as a high level, the sampling clock signal CLKD can be the AND signal obtained by performing a logical AND operation on the clock control signal GT and the first clock signal CLK. Therefore, when the clock control signal GT is at a high level, the first clock signal CLK, whose level is constantly changing, is used as the sampling clock signal CLKD. When the clock control signal GT is at a low level, a low-level signal is output, indicating that the sampling clock signal CLKD is not output.

[0081] In some embodiments, reference Figure 4 As shown, the above-mentioned clock control signal generating circuit includes: a decoding window signal generating circuit and a clock control signal generator.

[0082] The input terminal of the decoding window signal generation circuit is connected to the command receiving circuit that outputs the first chip select signal CS. The circuit is configured to adjust the pulse width of the first chip select signal CS to generate a decoding window signal CS_MASK, which is then output from the output terminal. The pulse width of the decoding window signal CS_MASK is greater than the pulse width of the first chip select signal CS. Furthermore, the command processing circuit decodes the command / address signal CA while the decoding window signal CS_MASK is at an active level.

[0083] The input end of the clock control signal generator is connected to the output end of the decoding window generation circuit and the output end of the external circuit that transmits the first clock signal CLK, and is configured to generate the clock control signal GT based on the decoding window signal CS_MASK and the first clock signal CLK. The starting time at which the clock control signal GT reaches an active level is determined by the starting time at which the decoding window signal CS_MASK reaches an active level, and the pulse width of the clock control signal GT is equal to a preset number of clock cycles of the first clock signal CLK. The processing operation corresponding to the second command signal CMD2 is completed while the clock control signal GT is at an active level. When the second command signal CMD2 corresponds to an ODT command, the processing operation corresponding to the ODT command can be executed, namely, setting a corresponding termination resistor to reduce signal reflection.

[0084] It can be understood that the starting time when the clock control signal GT is at the effective level lags behind the starting time when the decoding window signal CS_MASK is at the effective level, and the duration T of the lag is determined by the circuit structure of the clock control signal generator. Figure 6As shown, since the delay of the first command signal CMD1 compared to the decoding window signal CS_MASK is greater than the 12-stage gate delay, and the clock control signal GT controls the sampling clock signal CLKD to be transmitted to the command sampling circuit, it also takes time. Therefore, a clock control signal generator composed of 12-stage gate circuits can be set to make the above-mentioned lag time T equal to the 12G gate circuit delay, thereby avoiding the lag time T being too large, which causes the sampling clock signal CLKD to be unable to sample the first command signal CMD1.

[0085] Furthermore, the preset number may be 128. That is, when the clock control signal GT is at a valid level, the clock control signal generator begins counting the rising edges or falling edges of the first clock signal CLK. When the number of rising edges or falling edges of the first clock signal CLK reaches the preset number, the clock control signal generator outputs the clock control signal GT at an inactive level.

[0086] In some embodiments, reference Figure 4 As shown, the clock control signal generator includes a clock counter, an SR latch and a first adjustable delay circuit.

[0087] The two input terminals of the clock counter are respectively connected to the output terminal of the SR latch and the output terminal of the external circuit that sends the first clock signal CLK. The clock counter is used to receive the decoding window expansion signal ECS_MASK and the first clock signal CLK, and count the first clock signal CLK to generate a count value after the decoding window expansion signal ECS_MASK is at an active level. When the count value reaches a preset number, a reset signal RST is generated and the reset signal RST is output from its output terminal. The clock counter performs a reset operation based on the reset signal RST to reset the count value to 0 and start counting again.

[0088] The two input terminals of the SR latch are respectively connected to the output terminal of the decoding window signal generation circuit and the output terminal of the clock counter, and are used to generate the decoding window extension signal ECS_MASK based on the decoding window signal CS_MASK and the reset signal RST. Because the reset signal RST is used to indicate whether the number of rising edges or falling edges in the first clock signal CLK has reached a preset number, the SR latch can output the valid level of the decoding window extension signal ECS_MASK when the decoding window signal CS_MASK is at a valid level, and output the invalid level of the valid level of the decoding window extension signal ECS_MASK when the reset signal RST is at a valid level. In this way, the pulse width of the decoding window extension signal ECS_MASK can be guaranteed to be a preset number of clock cycles of the first clock signal CLK.

[0089] The input end of the first adjustable delay circuit is connected to the output end of the SR latch, and is used to delay the decoding window expansion signal ECS_MASK to obtain the clock control signal GT. The first adjustable delay circuit may include multiple inverters connected in series, and the first adjustable delay circuit may include an odd number or an even number of inverters.

[0090] The SR latch of the embodiment of the present disclosure can be flexibly configured. In one example, referring to Figure 5 As shown, the SR latch may include a first NOR gate NOR1, a second NOR gate NOR2 and a first inverter IV1. The two input terminals of the first NOR gate NOR1 are connected to Figure 4 The output terminal of the decoding window signal generating circuit shown in FIG. 1 and the output terminal of the second NOR gate NOR2 receive the decoding window signal CS_MASK and the output signal of the second NOR gate NOR2. The two input terminals of the second NOR gate NOR2 are respectively connected to Figure 4 The output of the clock counter and the output of the first NOR gate NOR1 are connected to receive the reset signal RST and the output signal of the first NOR gate NOR1. The output of the first NOR gate NOR1 is connected to the input of the first inverter IV1, which is used to output the decoding window extension signal ECS_MASK.

[0091] The following description is made by taking the reset signal RST, the decoding window signal CS_MASK and the decoding window extension signal ECS_MASK as an example where the valid levels are all high. Figure 6 As shown, the decoding window signal CS_MASK first reaches a high level, and the high level of the reset signal RST lags behind the high level of the decoding window signal CS_MASK. When the decoding window signal CS_MASK reaches a high level, the reset signal RST is at a low level, and the output signal of the first NOR gate NOR1 is at a low level. Therefore, the decoding window extension signal ECS_MASK is at a high level. When the decoding window signal CS_MASK flips to a low level, the reset signal RST remains at a low level. At this time, the SR latch still outputs the high-level decoding window extension signal ECS_MASK. When the reset signal RST flips to a high level, the output signal of the second NOR gate NOR2 is at a low level. At this time, because the decoding window signal CS_MASK is at a low level, the output signal of the first NOR gate NOR1 is at a high level, and the decoding window extension signal ECS_MASK output by the SR latch is at a low level.

[0092] In some embodiments, reference Figure 4As shown, the clock processing circuit further includes a second adjustable delay circuit, whose input is coupled to the output of the clock control circuit and whose output is coupled to the input of the command sampling circuit. The second adjustable delay circuit is configured to delay the sampling clock signal CLKD output by the clock control circuit, thereby inputting the delayed sampling clock signal CLKD to the command sampling circuit. In this way, the first and second adjustable delay circuits can be combined to ensure that the sampling clock signal CLKD arrives just after the first command signal CMD1 reaches the command sampling circuit, thereby ensuring the setup time of the command sampling circuit and effectively reducing the additional power consumption caused by premature clock signal output. It should be noted that the delay durations of the first and second adjustable delay circuits can be flexibly set.

[0093] Similar to the first adjustable delay circuit, the second adjustable delay circuit can also include an even number of inverters connected in series to ensure that the phases of the sampling clock signal CLKD before and after the delay are identical. When the first adjustable delay circuit includes an odd number of inverters, the clock control circuit includes a NAND logic circuit for performing a NAND logic operation on the clock control signal GT and the first clock signal CLK to obtain the sampling clock signal CLKD. When the first adjustable delay circuit includes an even number of inverters, the clock control circuit includes an AND logic processing circuit for performing an AND logic operation on the clock control signal GT and the first clock signal CLK to obtain the sampling clock signal CLKD. This ensures that the phases of the decoding window extension signal ECS_MASK and the sampling clock signal CLKD are identical.

[0094] Further, refer to Figure 4 As shown, the decoding window signal generating circuit includes: a chip selection sampling control circuit, a chip selection signal sampling circuit and a logic processing circuit.

[0095] The input end of the chip select sampling control circuit is connected to the output end of the external circuit that sends the first clock signal CLK, and is used to receive the first clock signal CLK and generate multiple chip select sampling control signals CSSC based on the first clock signal CLK.

[0096] The two input ends of the chip select signal sampling circuit are respectively connected to the output end of the chip select sampling control circuit and the output end of the command receiving circuit that sends the first chip select signal CS, and are used to sample the first chip select signal CS under the control of multiple chip select sampling control signals CSSC, generate and output multiple second chip select signals, the pulse width of each second chip select signal is greater than the pulse width of the first chip select signal CS, and the pulse ends of these multiple second chip select signals overlap in sequence.

[0097] The logic processing circuit has multiple input terminals connected to the output terminal of the chip select signal sampling circuit and the output terminal of the command receiving circuit that transmits the first chip select signal CS, respectively. The circuit is configured to perform a logical operation on multiple second chip select signals and the first chip select signal CS to generate a decoding window signal CS_MASK. When the first chip select signal CS and / or at least one second chip select signal is at an active level, the decoding window signal CS_MASK is at an active level; when the first chip select signal CS and all second chip select signals are at an inactive level, the decoding window signal CS_MASK is at an inactive level. It is understood that when the active levels of the first chip select signal CS, the second chip select signal, and the decoding window signal CS_MASK are all high, the logic processing circuit may be an AND logic circuit. When the active levels of the first chip select signal CS, the second chip select signal, and the decoding window signal CS_MASK are all low, the logic processing circuit may be an OR logic circuit. Of course, the active levels of the first chip select signal CS, the second chip select signal, and the decoding window signal CS_MASK can be flexibly set, thereby flexibly adjusting the structure of the logic processing circuit accordingly.

[0098] Optionally, the chip select sampling control circuit includes a first chip select sampling control sub-circuit and a second chip select sampling control sub-circuit.

[0099] The first chip select sampling control subcircuit includes N stages of second inverters connected in series. The first stage of the second inverter is used to receive the first clock signal CLK. The output signal of each stage of the second inverter is used as a chip select sampling control signal CSSC. For example, when N is 3, refer to Figure 7 As shown, the second inverters IV2, IV3, and IV4 constitute a first chip select sampling control subcircuit. The input of the first-stage second inverter IV2 is connected to the output of the external circuit that transmits the first clock signal CLK. The input of the second-stage second inverter IV3 is connected to the output of the first-stage second inverter IV2. The input of the third-stage second inverter IV4 is connected to the output of the second-stage second inverter IV3. The first clock signal CLK and the output signals CLK_O_1T, CLK_E_2T, and CLK_O_3T of the second inverters IV2, IV3, and IV4 serve as the four chip select sampling control signals CSSC.

[0100] Accordingly, the second chip select sampling control subcircuit includes N stages of third inverters connected in series. The first stage of the third inverter is used to receive the second clock signal, which is the inverted signal CLK_O of the first clock signal CLK. The output signal of each stage of the third inverter serves as a chip select sampling control signal CSSC. For example, when N is 3, refer to Figure 7As shown, third inverters IV5, IV6, and IV7 form a second chip select sampling control subcircuit. The input of the first-stage third inverter IV5 is connected to the output of the external circuit that transmits the second clock signal. The input of the second-stage third inverter IV6 is connected to the output of the first-stage third inverter IV5. The input of the third-stage third inverter IV7 is connected to the output of the second-stage third inverter IV6. The second clock signal CLK_O and the output signals CLK_E_1T, CLK_O_2T, and CLK_E_3T of the third inverters IV5, IV6, and IV7 serve as the four chip select sampling control subcircuits CSSC.

[0101] The chip select sampling control signal CSSC may include a first chip select sampling control signal and a second chip select sampling control signal. The first chip select sampling control signal is used for command sampling in the first chip select sampling subcircuit, and the second chip select sampling control signal is used for command sampling in the second chip select sampling subcircuit. The first clock signal CLK, the output signal of the third inverter of the odd-numbered stage, and the output signal of the second inverter of the even-numbered stage collectively constitute N+1 first chip select sampling control signals. For example, the first clock signals CLK, CLK_E_1T, CLK_E_2T, and CLK_E_3T are sequentially arranged to constitute the first chip select sampling control signals, and any two adjacent first chip select sampling control signals have a preset delay. Accordingly, the second clock signal, the output signal of the second inverter of the odd-numbered stage, and the output signal of the third inverter of the even-numbered stage collectively constitute N+1 second chip select sampling control signals. For example, the aforementioned second clock signals CLK_O, CLK_O_1T, CLK_O_2T, and CLK_O_3T are sequentially arranged to form a second chip selection sampling control signal, and any two adjacent second chip selection sampling control signals have a preset delay.

[0102] It should be noted that the second and third inverters are identical inverters, and the delay time for inverting the input signal to output is the same preset delay. Therefore, the N+1 first chip select sampling control signals: the first clock signal CLK, CLK_E_1T, CLK_E_2T, and CLK_E_3T, have preset delays in sequence, and the N+1 second chip select sampling control signals: the second clock signal CLK_O, CLK_O_1T, CLK_O_2T, and CLK_O_3T, have preset delays in sequence. The preset delay can be the time required for an inverter to perform a level flip.

[0103] In some embodiments, reference Figure 8 As shown, the chip select signal sampling circuit includes: a first chip select sampling sub-circuit and a second chip select sampling sub-circuit.

[0104] The first chip select sampling subcircuit includes: N+1 stages of cascaded first flip-flops, wherein the input end of the first stage first flip-flop receives the first chip select signal CS, the output end of each stage first flip-flop is connected to the input end of the next stage first flip-flop, the clock end of each stage first flip-flop receives a first chip select sampling control signal, and the output end of each stage first flip-flop outputs a second chip select signal; wherein the clock end of the i-th stage first flip-flop receives the (N+2-i)th first chip select sampling control signal, where i is a positive integer less than or equal to N+1.

[0105] For example, when N=3, refer to Figure 8 As shown, the first flip-flops DFF1 to DFF4 constitute a first chip select sampling sub-circuit. The N+1 first chip select sampling control signals are the following four signals in sequence: a first clock signal CLK, CLK_E_1T, CLK_E_2T, and CLK_E_3T.

[0106] The input terminal D of the first-stage first flip-flop DFF1 receives the first chip select signal CS, and the clock terminal of the first-stage first flip-flop DFF1 receives the (3+2-1=4)th first chip select sampling control signal CLK_E_3T.

[0107] The output terminal Q of the first-stage first flip-flop DFF1 is connected to the input terminal D of the second-stage first flip-flop DFF2, the input terminal D of the second-stage first flip-flop DFF2 receives the output signal E_Q1 of the first-stage first flip-flop DFF1, and the clock terminal C of the second-stage first flip-flop DFF2 receives the (3+2-2=3)th first chip select sampling control signal CLK_E_2T.

[0108] The output terminal Q of the second-stage first flip-flop DFF2 is connected to the input terminal D of the third-stage first flip-flop DFF3, the input terminal D of the third-stage first flip-flop DFF3 receives the output signal E_Q2 of the second-stage first flip-flop DFF2, and the clock terminal C of the third-stage first flip-flop DFF3 receives the (3+2-3=2)th first chip select sampling control signal CLK_E_1T.

[0109] The output terminal Q of the third-stage first flip-flop DFF3 is connected to the input terminal D of the fourth-stage first flip-flop DFF4, the input terminal D of the fourth-stage first flip-flop DFF4 receives the output signal E_Q3 of the third-stage first flip-flop DFF3, and the clock terminal C of the fourth-stage first flip-flop DFF4 receives the (3+2-4=1)th first chip select sampling control signal CLK.

[0110] The output terminals Q of the first-stage first flip-flop DFF1 to the fourth-stage first flip-flop DFF4 respectively output a second chip selection sampling control signal E_Q1 , E_Q2 , E_Q3 and E_Q4 .

[0111] Correspondingly, the second chip select sampling subcircuit includes: N+1 levels of cascaded second flip-flops, the input end of the first level second flip-flop receives the first chip select signal CS, the output end of each level second flip-flop is connected to the input end of the next level second flip-flop, the clock end of each level second flip-flop receives a second chip select sampling control signal, and the output end of each level second flip-flop outputs a second chip select signal; wherein, the clock end of the j-th level second flip-flop receives the (N+2-j)th second chip select sampling control signal, and j is a positive integer less than or equal to N+1.

[0112] For example, when N=3, refer to Figure 8 As shown, the second flip-flops DFF5 to DFF8 constitute a second chip select sampling sub-circuit. The N+1 second chip select sampling control signals are the following four signals in sequence: second clock signals CLK_O, CLK_O_1T, CLK_O_2T and CLK_O_3T.

[0113] The input terminal D of the first-stage second flip-flop DFF5 receives the first chip select signal CS, and the clock terminal C of the first-stage second flip-flop DFF5 receives the (3+2-1=4)th second chip select sampling control signal CLK_O_3T.

[0114] The output terminal Q of the first-stage second flip-flop DFF5 is connected to the input terminal D of the second-stage second flip-flop DFF6, the input terminal D of the second-stage second flip-flop DFF6 receives the output signal O_Q1 of the first-stage second flip-flop DFF5, and the clock terminal C of the second-stage second flip-flop DFF6 receives the (3+2-2=3)th second chip select sampling control signal CLK_O_2T.

[0115] The output terminal Q of the second-stage second flip-flop DFF6 is connected to the input terminal D of the third-stage second flip-flop DFF7. The input terminal D of the third-stage second flip-flop DFF7 receives the output signal O_Q2 of the second-stage second flip-flop DFF6. The clock terminal C of the third-stage second flip-flop DFF7 receives the (3+2-3=2)th second chip select sampling control signal CLK_O_1T.

[0116] The output terminal Q of the third-stage second flip-flop DFF7 is connected to the input terminal D of the fourth-stage second flip-flop DFF8, the input terminal D of the fourth-stage second flip-flop DFF8 receives the output signal O_Q3 of the third-stage second flip-flop DFF7, and the clock terminal C of the fourth-stage second flip-flop DFF8 receives the (3+2-4=1)th second chip select sampling control signal CLK_O.

[0117] The output terminals Q of the first-stage second flip-flop DFF5 to the fourth-stage second flip-flop DFF8 respectively output a second chip selection sampling control signal O_Q1 , O_Q2 , O_Q3 and O_Q4 .

[0118] In some embodiments, when the valid levels of the first chip select signal CS and the second chip select signal CS2 are both low and the valid level of the decoding window signal CS_MASK is high, the logic processing circuit includes: a first AND logic circuit, a second AND logic circuit and a NAND logic circuit.

[0119] Multiple input terminals of the first AND logic circuit are connected to the output terminals of each first flip-flop in the first chip select sampling subcircuit, and are used to receive N+1 second chip select signals CS2 output by each first flip-flop, so as to perform an AND logic operation on the N+1 second chip select signals CS2 to generate a first result signal AD1. The first AND logic circuit may include one or more AND gates, such as Figure 9 As shown, when N=3, the first AND logic circuit includes three AND gates for performing an AND logic operation on the four second chip selection signals E_Q1 to E_Q4 to generate a first result signal AD1.

[0120] Multiple input terminals of the second AND logic circuit are connected to the output terminals of each second flip-flop in the second chip select sampling sub-circuit, and are used to receive N+1 second chip select signals CS2 output by each second flip-flop, so as to perform an AND logic operation on the N+1 second chip select signals CS2 to generate a second result signal AD2. Similarly, the second AND logic circuit may include one or more AND gates, such as Figure 9 As shown, when N=3, the second AND logic circuit includes three AND gates for performing an AND logic operation on the four second chip selection signals O_Q1 to O_Q4 to generate a second result signal AD2.

[0121] The multiple input terminals of the NAND logic circuit are connected to the output terminals of the first and second AND logic circuits, and are used to perform a NAND logic operation on the first result signal AD1, the second result signal AD2 and the first chip select signal CS to generate a decoding window signal CS_MASK. Figure 9 As shown, the NAND logic circuit may be a NAND gate, which performs a NAND logic operation on the first result signal AD1 , the second result signal AD2 , and the first chip select signal CS to generate a decoding window signal CS_MASK.

[0122] from Figure 9 As can be seen from the logic processing circuit shown, when at least one of the first chip select signal CS, the second chip select signals E_Q1 to E_Q4, and O_Q1 to O_Q4 is low, the decoding window signal CS_MASK is high. Otherwise, the decoding window signal CS_MASK is low.

[0123] The embodiments of the present disclosure can be Figure 9 The simple logic circuit shown generates the decoding window signal CS_MASK at a low cost.

[0124] Figure 10 、 Figure 11 Schematic diagrams of two relationships between decoding window signals and correlation signals provided by the embodiments of the present disclosure. Figure 10 、 11 In the embodiment, the valid levels of the first chip selection signal CS and the second chip selection signals O_Q1 to O_Q4 and E_Q1 to E_Q4 are all low levels, and the valid level of the decoding window signal CS_MASK is high level.

[0125] The following describes the timing of the second chip select signals E_Q1 to E_Q4. Figure 10 In the embodiment, the rising edges of CLK_E_3T, CLK_E_2T, CLK_E_1T and CLK can sample the input signal of the corresponding first trigger to obtain the second chip select signals E_Q1 to E_Q4, so as to generate the decoding window signal CS_MASK according to the second chip select signals E_Q1 to E_Q4. Figure 8 When the rising edge of the first chip selection sampling control signal CLK_E_3T arrives, the first trigger DFF1 of the first stage samples the first chip selection signal CS and outputs Figure 10 The second chip select signal E_Q1 is shown. Figure 8 When the rising edge of the first chip selection sampling control signal CLK_E_2T arrives, the second-stage first trigger DFF2 samples the output signal E_Q1 of the first-stage first trigger DFF1 and outputs Figure 10 The second chip select signal E_Q2 is shown. Figure 8 When the rising edge of the first chip selection sampling control signal CLK_E_1T arrives, the third-stage first trigger DFF3 samples the output signal E_Q2 of the second-stage first trigger DFF2 and outputs Figure 10 The second chip select signal E_Q3 is shown. Figure 8 When the rising edge of the first chip selection sampling control signal CLK arrives, the fourth-stage first trigger DFF4 samples the output signal E_Q3 of the third-stage first trigger DFF3 and outputs Figure 10 The second chip select signal E_Q4 is shown.

[0126] It should be noted that Figure 10 In the embodiment, the second chip selection sampling control signals CLK_O_3T, CLK_O_2T, CLK_O_1T and CLK_O cannot sample the input signals of the corresponding second triggers through the rising edges, so the output second chip selection signals O_Q1 to O_Q4 are all high levels.

[0127] Next, we will describe the timing of the second chip select signals O_Q1 to O_Q4. Figure 11In the embodiment, the rising edges of CLK_O_3T, CLK_O_2T, CLK_O_1T and CLK_O can sample the input signal of the corresponding second trigger to obtain the second chip select signals O_Q1 to O_Q4, so as to generate the decoding window signal CS_MASK according to the second chip select signals O_Q1 to O_Q4. Figure 8 When the rising edge of the second chip selection sampling control signal CLK_O_3T arrives, the first stage second trigger DFF5 samples the first chip selection signal CS and outputs Figure 11 The second chip select signal O_Q1 is shown. Figure 8 When the rising edge of the second chip selection sampling control signal CLK_O_2T arrives, the second trigger DFF6 of the second stage samples the output signal O_Q1 of the first stage second trigger DFF5 and outputs the signal O_Q1 as shown in FIG. Figure 11 The second chip select signal O_Q2 is shown. Figure 8 When the rising edge of the second chip selection sampling control signal CLK_O_1T arrives, the third-stage second flip-flop DFF7 samples the output signal O_Q2 of the second-stage second flip-flop DFF6, and outputs the following: Figure 11 The second chip select signal O_Q3 is shown. Figure 8 When the rising edge of the second chip selection sampling control signal CLK arrives, the fourth-stage second flip-flop DFF8 samples the output signal O_Q3 of the third-stage second flip-flop DFF7 and outputs the following: Figure 11 The second chip select signal O_Q4 is shown.

[0128] Similarly, Figure 11 In the embodiment, the first chip selection sampling control signals CLK_E_3T, CLK_E_2T, CLK_E_1T and CLK cannot sample the input signal of the corresponding first trigger through the rising edge, so the output second chip selection signals E_Q1 to E_Q4 are all high level.

[0129] It should be noted that the embodiment of the present disclosure can implement signal sampling through a first clock signal and a second clock signal with opposite phases, which can ensure that the signal is sampled as much as possible and improve sampling accuracy.

[0130] Reference Figure 10 、 Figure 11As shown, when at least one of the first chip select signal CS and the second chip select signals E_Q1 to E_Q4 and O_Q1 to O_Q4 is low, the decoding window signal CS_MASK is high. Otherwise, the decoding window signal CS_MASK is low. It can be seen that when the first chip select signal CS begins to go low, the decoding window signal CS_MASK goes high. This ensures that the decoding window signal CS_MASK goes high as early as possible, thereby starting to process the first clock signal CLK as early as possible, thereby reducing power consumption.

[0131] On the one hand, after obtaining the above-mentioned decoding window signal CS_MASK, the first clock signal or the second clock signal can be processed by the decoding window signal CS_MASK to output a decoding clock signal. Specifically, when the decoding window signal is at a valid level, the first clock signal or the second clock signal is used as the decoding clock signal, otherwise, the decoding clock signal is not output. The decoding clock signal can be input to Figure 3 The command decoding circuit shown decodes the command / address signal CA3 under the control of a decoding clock signal and outputs a first command signal CMD1. This can further reduce the power consumption of the command decoding circuit. In this scenario, the pulse width of the decoding window signal CS_MASK determines the decoding time of the command decoding circuit. The larger the pulse width of the decoding window signal CS_MASK, the longer the decoding time of the command decoding circuit and the higher the accuracy of the decoding result. In addition, the earlier the start time of the decoding window signal CS_MASK, the earlier the decoding operation of the command decoding circuit and the faster the decoding.

[0132] On the other hand, after obtaining the above decoding window signal CS_MASK, Figure 5 The SR latch shown can also be Figure 6 The reset signal RST shown in the figure will Figure 6 The decoding window signal CS_MASK is expanded to generate Figure 6 The decoding window expansion signal ECS_MASK is shown. Figure 4 When the preset number used when counting the clock counter shown is 128, refer to Figure 6 As shown, the pulse width of the decoding window extension signal ECS_MASK is 128TCK (128 clock cycles of the first clock signal CLK).

[0133] exist Figure 4 When the first adjustable delay circuit shown is a 12G gate circuit, the first adjustable delay circuit delays the decoding window extension signal ECS_MASK by the processing time of the 12G gate circuit to generate the clock control signal GT.

[0134] from Figure 6It can be seen from the figure that the first clock signal CLK is always in level flipping, while the sampling clock signal CLKD is in level flipping when the clock control signal GT is at a valid level (here a high level), and is not in level flipping when the clock control signal GT is at an invalid level (here a low level). Figure 1 The clock signal CLK shown is input into the delay circuit for delay. The sampling clock signal CLKD of the embodiment of the present disclosure can reduce the current flip of the inverter in the second adjustable delay circuit, thereby reducing power consumption.

[0135] It should be noted that the number of stages of the decoding window signal generating circuit is less than or equal to 22G. Figure 3 When the number of command processing circuits is 34G, refer to Figure 6 As shown, the delay of the first command signal CMD1 compared to the decoding window signal CS_MASK is greater than the processing time corresponding to the 12G gate circuit.

[0136] An embodiment of the present disclosure further provides a memory comprising the aforementioned signal processing circuit.

[0137] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0138] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A signal processing circuit, characterized in that: include: command processing circuit, clock processing circuit and command sampling circuit; The command processing circuit is configured to receive a command / address signal, and generate and output a first command signal based on the command / address signal; The clock processing circuit is configured to receive a first chip select signal and a first clock signal, generate a clock control signal based on the first chip select signal and the first clock signal, and process the first clock signal according to the clock control signal to generate and output a sampling clock signal; The command sampling circuit is coupled to the command processing circuit and the clock processing circuit respectively, and samples the first command signal based on the sampling clock signal to output a second command signal; The clock control signal is used to control not outputting the sampling clock signal before the first command signal reaches the command sampling circuit, and to outputting the sampling clock signal when the first command signal reaches the command sampling circuit; The clock processing circuit includes: a clock control signal generating circuit and a clock control circuit; The clock control signal generating circuit is configured to receive the first chip select signal and the first clock signal, and generate and output the clock control signal according to the first chip select signal and the first clock signal; wherein the clock control signal starts to be at an effective level earlier than the time when the first command signal reaches the command sampling circuit; The clock control circuit is connected to the clock control signal generating circuit, and is used to control whether to generate and output the sampling clock signal based on the first clock signal according to the clock control signal.

2. The signal processing circuit according to claim 1, wherein: The clock control signal generating circuit includes: a decoding window signal generating circuit and a clock control signal generator; The decoding window signal generating circuit is configured to adjust the pulse width of the first chip select signal to generate a decoding window signal, and output the decoding window signal from its output terminal; The clock control signal generator is used to generate the clock control signal based on the first clock signal and the decoding window signal, wherein the starting time when the clock control signal is at a valid level is determined by the starting time when the decoding window signal is at a valid level, and the pulse width of the clock control signal is equal to a preset number of clock cycles of the first clock signal, and the processing operation corresponding to the second command signal is completed during the period when the clock control signal is at a valid level.

3. The signal processing circuit according to claim 2, wherein: The clock control signal generator includes a clock counter, an SR latch and a first adjustable delay circuit; The clock counter is configured to receive a decoding window extension signal and the first clock signal, count the first clock signal to generate a count value after the decoding window extension signal is at an effective level, and generate a reset signal when the count value reaches a preset number, and output the reset signal from an output terminal thereof; wherein the clock counter performs a reset operation based on the reset signal; The SR latch is connected to the clock counter and is used to generate the decoding window extension signal according to the decoding window signal and the reset signal; The first adjustable delay circuit is connected to the SR latch and is used to delay the decoding window expansion signal to obtain the clock control signal.

4. The signal processing circuit according to claim 3, wherein: The first adjustable delay circuit includes a plurality of inverters connected in series; The SR latch includes: a first NOR gate, a second NOR gate and a first inverter, wherein the two input ends of the first NOR gate are respectively connected to the output end of the decoding window signal generating circuit and the output end of the second NOR gate, the two input ends of the second NOR gate are respectively connected to the output end of the clock counter and the output end of the first NOR gate, the output end of the first NOR gate is connected to the input end of the first inverter, and the first inverter is used to output the decoding window extension signal.

5. The signal processing circuit according to claim 4, characterized in that The clock processing circuit also includes: a second adjustable delay circuit, coupled to the output end of the clock control circuit and the input end of the command sampling circuit, respectively, for delaying the sampling clock signal output by the clock control circuit to input the delayed sampling clock signal to the command sampling circuit.

6. The signal processing circuit according to claim 5, wherein: When the first adjustable delay circuit includes an odd number of inverters, the clock control circuit includes: a NAND logic circuit, configured to perform a NAND logic operation on the clock control signal and the first clock signal to obtain the sampling clock signal; When the first adjustable delay circuit includes an even number of inverters, the clock control circuit includes an AND logic processing circuit configured to perform an AND logic operation on the clock control signal and the first clock signal to obtain the sampling clock signal.

7. The signal processing circuit according to claim 6, wherein: The decoding window signal generating circuit includes: a chip selection sampling control circuit, a chip selection signal sampling circuit and a logic processing circuit; The chip select sampling control circuit is configured to receive the first clock signal and generate a plurality of chip select sampling control signals based on the first clock signal; The chip select signal sampling circuit is connected to the chip select sampling control circuit and is used to sample the first chip select signal under the control of the multiple chip select sampling control signals to generate and output multiple second chip select signals, wherein the pulse width of each second chip select signal is greater than the pulse width of the first chip select signal; The logic processing circuit is connected to the chip select signal sampling circuit, and is used to perform logical operations on multiple second chip select signals and the first chip select signal to generate the decoding window signal. When the first chip select signal and / or at least one second chip select signal is at a valid level, the decoding window signal is at a valid level.

8. The signal processing circuit according to claim 7, wherein: The chip select sampling control circuit includes a first chip select sampling control subcircuit and a second chip select sampling control subcircuit; The first chip select sampling control subcircuit includes N stages of second inverters connected in series, the first stage of the second inverters is used to receive the first clock signal, and the output signal of each stage of the second inverter serves as a chip select sampling control signal; The second chip select sampling control subcircuit includes N stages of third inverters connected in series, wherein the first stage of the third inverter is used to receive a second clock signal, the second clock signal being an inverted signal of the first clock signal, and the output signal of each stage of the third inverter serves as a chip select sampling control signal; The second inverter and the third inverter are both identical inverters, and the delay time for inverting and outputting the input signal is a preset delay; The chip select sampling control signal includes a first chip select sampling control signal and a second chip select sampling control signal; the first clock signal, the output signal of the third inverter of the odd-numbered stage, and the output signal of the second inverter of the even-numbered stage together constitute N+1 first chip select sampling control signals, and the N+1 first chip select sampling control signals have a preset delay in sequence; the second clock signal, the output signal of the second inverter of the odd-numbered stage, and the output signal of the third inverter of the even-numbered stage together constitute N+1 second chip select sampling control signals, and the N+1 second chip select sampling control signals have a preset delay in sequence.

9. The signal processing circuit according to claim 8, wherein: The chip select signal sampling circuit includes: a first chip select sampling sub-circuit and a second chip select sampling sub-circuit; The first chip select sampling subcircuit comprises: N+1 stages of cascaded first flip-flops, wherein the input of the first flip-flop of the first stage receives the first chip select signal, the output of the first flip-flop of each stage is connected to the input of the first flip-flop of the next stage, the clock of the first flip-flop of each stage receives a first chip select sampling control signal, and the output of the first flip-flop of each stage outputs a second chip select signal; wherein the clock of the first flip-flop of the i-th stage receives the (N+2-i)th first chip select sampling control signal, where i is a positive integer less than or equal to N+1; The second chip select sampling subcircuit includes: N+1 levels of cascaded second flip-flops, the input end of the first level of the second flip-flop receives the first chip select signal, the output end of each level of the second flip-flop is connected to the input end of the next level of the second flip-flop, the clock end of each level of the second flip-flop receives a second chip select sampling control signal, and the output end of each level of the second flip-flop outputs a second chip select signal; wherein, the clock end of the j-th level of the second flip-flop receives the (N+2-j)th second chip select sampling control signal, where j is a positive integer less than or equal to N+1.

10. The signal processing circuit according to claim 9, wherein: The effective levels of the first chip select signal and the second chip select signal are low levels, the effective level of the decoding window signal is high level, and the logic processing circuit includes: a first AND logic circuit, a second AND logic circuit and a NAND logic circuit; The first AND logic circuit is configured to receive the N+1 second chip select signals output by the first chip select sampling sub-circuit, and perform an AND logic operation on the N+1 second chip select signals to generate a first result signal; The second AND logic circuit is configured to receive the N+1 second chip select signals output by the second chip select sampling sub-circuit, and perform an AND logic operation on the N+1 second chip select signals to generate a second result signal; The NAND logic circuit has an input end connected to the first AND logic circuit and the second AND logic circuit, and is used to perform a NAND logic operation on the first result signal, the second result signal and the first chip select signal to generate the decoding window signal.

11. A memory, characterized in that: The signal processing circuit comprises the signal processing circuit according to any one of claims 1 to 10.

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