Managing page retirements from nonvolatile memory

Abstract

The present application relates to managing page retirement in non-volatile memory. A set of ordered device information pages can be used to store device information. The device information pages can be in non-volatile memory. Each page can include a counter value for the number of accesses to indicate whether the page contains valid data. A flag associated with the page can be set to retire the page when the counter value reaches a threshold. Upon power-up, the device can determine which page to use based on the flag. The flag can be stored in the page or can be separate (e.g., a fuse element). If a fuse element is used, the page can store a programming in progress flag to indicate when programming of the fuse element may not have been completed before power was lost. In this case, the programming can be restarted after power is restored.

Description

[0001] References for divisional applications

[0002] This patent application is a divisional application of the invention patent application No. 202180079408.0, entitled “Managing Page Retirement for Non-Volatile Memory,” filed on November 10, 2021. The parent application is the national phase entry of International Patent Application No. PCT / US21 / 72337, entitled “Managing Page Retirement for Non-Volatile Memory,” filed by Morgan et al. on November 10, 2021. The parent application claims priority to U.S. patent application No. 17 / 105,000 filed by Morgan et al. on November 25, 2020, entitled “MANAGING PAGE RETIREMENT FOR NON-VOLATILE MEMORY,” each of which is assigned to its assignees and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to managing page retirements of non-volatile memory. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to a logical 1 or a logical 0. In some examples, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), three-dimensional cross-point memory (3D cross-point), NOR and NAND memory devices, and the like. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless they are periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods even in the absence of an external power source. Summary of the Invention

[0006] A method is described. The method may include: obtaining a first selector value from a first selector associated with a first page of a plurality of pages of non-volatile memory at power-up; determining that the first page contains valid data based at least in part on the first selector value; determining that the first page should be retired based at least in part on a counter value associated with the first page; updating the first selector value associated with the first page to reflect the retirement of the first page; and writing data to a second page of the plurality of pages in place of the first page.

[0007] Another method is described. The method may include: obtaining a flag value from a flag of a page of a plurality of pages of nonvolatile memory at power-up of a memory device; determining, based at least in part on the flag value, that programming of a fuse element associated with the page has not yet completed; continuing programming of the fuse element based at least in part on determining that the programming of the fuse element has not yet completed, wherein the programming of the fuse element indicates that the page is retired; determining that the programming of the fuse element has completed; and writing a second flag value to the flag of the page based at least in part on determining that the programming of the fuse element has completed.

[0008] A memory device is described. The memory device may include: a plurality of pages of non-volatile memory; and a controller configured to: upon power-up, obtain a first selector value from a first selector associated with a first page of the plurality of pages; determine that the first page contains valid data based at least in part on the first selector value; determine that the first page should be retired based at least in part on a counter value associated with the first page; update the first selector value associated with the first page to reflect the retirement of the first page; and write data to a second page of the plurality of pages in place of the first page. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting a method for retiring pages of a memory device according to examples as disclosed herein is described.

[0010] Figure 2 An example of a system supporting a method for retiring pages of a memory device according to examples as disclosed herein is described.

[0011] Figure 3A and 3B Examples of a layout of pages and a system using the pages according to examples as disclosed herein are described, both of which support a method for retiring pages of a memory device.

[0012] Figures 4 to 6 A flow chart illustrating a method of supporting a method for retiring pages of a memory device according to examples as disclosed herein is shown.

[0013] Figure 7 A block diagram of a memory device supporting a method for retiring pages of the memory device according to aspects of the present disclosure is shown.

[0014] Figure 8 and 9 A flow chart illustrating a method of supporting a method for retiring pages of a memory device according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0015] For memory and other devices, device information (such as configuration, status, or security information) can be stored in non-volatile memory cells so that the information is not lost when power is removed from the device. For example, knowledge of the last power cycle can be used to scramble or otherwise obfuscate data for security purposes. The non-volatile cells can be main memory cells in the case of non-volatile memory devices or can be non-volatile memory included on a different type of device. While non-volatile memory can be advantageous for storing device information, non-volatile memory generally has a limited number of access cycles before its reliability degrades. Therefore, non-volatile memory cells that hold device information should be retired before the integrity of the information is lost.

[0016] According to various aspects described herein, a set of ordered device information pages can be used to store device information. The device information pages can be in non-volatile memory. Each page can include a counter value for the number of accesses to track page usage relative to reliability limits. A flag associated with the page can be set to retire the page when the counter value reaches a threshold. Upon power-up, the device can determine which page to use based on the flag. The flag can be stored in the page or can be separate (e.g., a fuse element). If a fuse element is used, the page can store a programming in progress flag to indicate when programming of the fuse element may not have been completed before power was lost, in which case programming can be restarted after power is restored. As used herein, a fuse element can refer to a fuse (e.g., having a higher resistance after programming) or an antifuse (e.g., having a lower resistance after programming), such as by logical inversion.

[0017] Initially in about Figure 1 Features of the present disclosure are described in the context of the systems, devices, and circuits described in 3. Figures 4 to 9 These and other features of the present disclosure are further illustrated by and described with reference to apparatus diagrams and flow diagrams described in connection with methods for retiring pages of a memory device.

[0018] Figure 1 is an example of a system 100 supporting a method for retiring pages of a memory device according to examples as disclosed herein. The system 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or set of devices that includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual inline memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0020] System 100 may be included in a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked business device), or any other computing device that includes a memory and a processing device.

[0021] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some examples, this coupling may include an interface with a host system controller 106, which may be an example of a control component configured to cause the host system 105 to perform various operations according to examples as described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more cache areas (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 105 may use the memory system 110 to, for example, write data to and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0022] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate using an associated protocol via the physical host interface (e.g., to exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces may include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a UFS interface, an eMMC interface, a Peripheral Component Interconnect Express (PCIe) interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM slot interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0023] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory device 130 may include one or more memory arrays of any type of memory cells, such as non-volatile memory cells, volatile memory cells, or any combination thereof. Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but memory system 110 may include any number of memory devices 130. Furthermore, where memory system 110 includes more than one memory device 130, different memory devices 130 within memory system 110 may include the same or different types of memory cells.

[0024] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory devices 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory devices 130, as well as other such operations, which can be generally referred to as access operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. And in some cases, the memory system controller 115 can exchange data (e.g., in response to or otherwise associated with commands from the host system 105) with the host system 105 and one or more memory devices 130. For example, the memory system controller 115 can convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (e.g., error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operation codes (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or computations related to the functions attributed herein to the memory system controller 115.

[0028] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM). Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include random access memory (RAM) memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0029] In some examples, memory devices 130 may each include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of memory devices 130. Local controller 135 may operate in conjunction with memory system controller 115 or may perform one or more functions attributed herein to memory system controller 115.

[0030] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash memory device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a block of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, where each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0031] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as multi-level cells (MLCs) when configured to store two bits of information each, three-level cells (TLCs) when configured to store three bits of information each, quad-level cells (QLCs) when configured to store four bits of information each, or more generally, multi-level memory cells. Multi-level memory cells may provide greater storage density relative to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0032] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, synchronization operations may occur within different planes 165. For example, synchronization operations may be performed on memory cells within different blocks 170 as long as the different blocks 170 are in different planes 165. In some cases, performing synchronization operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 having the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0033] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0034] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity) but can be erased at a second level of granularity (e.g., at a block granularity). That is, a page 175 can be the smallest memory cell (e.g., a group of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single program or read operation), and a block 170 can be the smallest memory cell (e.g., a group of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be overwritten with new data. Thus, for example, in some cases a used page 175 may not be updated until the entire block 170 including the page 175 has been erased.

[0035] The system 100 may include any number of non-transitory computer-readable media that support methods for retiring pages of a memory device. For example, the host system 105, the memory system controller 115, or the memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, such instructions, when executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), may cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0036] Figure 2 An example of a system 200 supporting a method for retiring pages of a memory device according to an example disclosed herein is illustrated. The system 200 may be as described with respect to Figure 1 or an example of the system 100 described herein. The system 200 may include a memory system 210 configured to store data received from the host system 205 and send data to the host system 205 when requested by the host system 205 using an access command (e.g., a read command or a write command). The system 200 may implement the system 100 described herein. Figure 1 For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0037] The memory system 210 may include a memory device 240 to store data transferred between the memory system 210 and the host system 205, such as in response to receiving an access command from the host system 205, as described below. The memory device 240 may include a memory device 240 as described with respect to FIG. Figure 1For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D XPoint, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0038] The memory system 210 may include a memory controller 230 for controlling the transfer of data directly to and from the memory device 240, such as for storing data, retrieving data, and determining memory locations in which to store data and from which to retrieve data. The memory controller 230 may communicate with the memory device 240 directly or via a bus (not shown) using a protocol specific to each type of memory device. In some cases, a single memory controller 230 may be used to control multiple memory devices of the same or different types. In some cases, the memory system 210 may include multiple memory controllers 230, such as a different memory controller 230 for each type of memory device 240. In some cases, the memory controller 230 may implement the methods described with respect to Figure 1 Aspects of the local controller 135 are described.

[0039] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data transferred between the host system and the memory device 240. The interface 220, buffer 225, and memory controller 230 may be used to translate data between the host system 205 and the memory device 240 (e.g., as shown by the data path 250) and may be collectively referred to as data path components.

[0040] Using buffer 225 to temporarily store data during transfers allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing arbitrary data sizes associated with commands. This can also allow bursts of commands to be handled, and once the burst has ceased, the buffered data can be stored or transferred (or both). Buffer 225 can include relatively fast memory (e.g., some type of volatile memory, such as SRAM or DRAM) or a hardware accelerator, or both, to allow for fast storage and retrieval of data to and from buffer 225. Buffer 225 can include a data path switch component for bidirectional data transfer between buffer 225 and other components.

[0041] Temporarily storing data in buffer 225 may mean storing the data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer remain in buffer 225 (e.g., to be overwritten by data for additional access commands). Furthermore, buffer 225 may be a non-cacheable buffer. That is, data may not be directly read from buffer 225 by host system 205. For example, a read command may be placed on a queue without requiring an address to be matched against an address already in the buffer (e.g., without requiring a cache address match or lookup operation).

[0042] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components in the movement of data. The memory system controller 215 may be a memory system controller 215 such as the one described above. Figure 1 An example of a memory system controller 115 is depicted. Bus 235 may be used for communication between system components.

[0043] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and store queue 270) may be used to control the processing of access commands and the movement of corresponding data. This may be beneficial, for example, when more than one access command from host system 205 is being processed simultaneously by memory system 210. Command queue 260, buffer queue 265, and store queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively, as examples of possible implementations. Queues, if used, may be located anywhere within memory system 210.

[0044] Data transferred between the host system 205 and the memory device 240 may take a different path in the memory system 210 than non-data information (e.g., commands, status information). For example, system components in the memory system 210 may communicate with each other using the bus 235, while data may use the data path 250 that passes through data path components rather than the bus 235. The memory system controller 215 may control how and when data is transferred between the host system 205 and the memory device 240 by communicating with the data path components via the bus 235 (e.g., using a protocol specific to the memory system 210).

[0045] When the host system 205 transmits an access command to the memory system 210, the command may be received by the interface 220, for example, according to a protocol (e.g., the Universal Flash Storage (UFS) protocol or the eMMC protocol). Thus, the interface 220 may be considered the front end of the memory system 210. After receiving each access command, the interface 220 may transmit the command to the memory system controller 215, for example, via the bus 235. In some cases, the interface 220 may add each command to the command queue 260 for transmission to the memory system controller 215.

[0046] The memory system controller 215 may determine that an access command has been received based on communications from the interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving the command from the command queue 260. After the command has been retrieved from the command queue 260, for example, by the memory system controller 215, the command may be removed from the command queue 260. In some cases, the memory system controller 215 may cause the interface 220 to remove the command from the command queue 260, for example, via the bus 235.

[0047] After determining that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0048] In either case, the memory system controller 215 may use the buffer 225 to, among other things, temporarily store data received from or sent to the host system 205. The buffer 225 may be considered an intermediary for the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0049] To process a write command received from the host system 205, the memory system controller 215 may first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, for example, via firmware (e.g., controller firmware), the amount of space within the buffer 225 that is available to store the data associated with the write command.

[0050] In some cases, a buffer queue 265 can be used to control the flow of commands (including write commands) associated with data stored in the buffer 225. The buffer queue 265 can include access commands associated with the data currently stored in the buffer 225. In some cases, commands in the command queue 260 can be moved to the buffer queue 265 by the memory system controller 215 and can remain in the buffer queue 265 while the associated data is stored in the buffer 225. In some cases, each command in the buffer queue 265 can be associated with an address at the buffer 225. That is, an indicator can be maintained indicating where the data associated with each command is stored in the buffer 225. Using the buffer queue 265, multiple access commands can be received sequentially from the host system 205, and at least some of the access commands can be processed simultaneously.

[0051] If buffer 225 has sufficient space to store the write data, memory system controller 215 may cause interface 220 to transmit an availability indication to host system 205 (e.g., a "ready to transfer" indication), for example, according to a protocol (e.g., a UFS protocol or an eMMC protocol). When interface 220 subsequently receives data associated with a write command from host system 205, interface 220 may transfer the data to buffer 225 using data path 250 for temporary storage. In some cases, interface 220 may obtain a location within buffer 225 for storing the data from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235, when the data transfer to buffer 225 has completed.

[0052] Once the write data has been stored in buffer 225 by interface 220, the data can be transferred out of buffer 225 and stored in memory device 240. This can be accomplished using storage controller 230. For example, memory system controller 215 can cause storage controller 230 to retrieve the data from buffer 225 and transfer the data to memory device 240 using data path 250. Storage controller 230 can be considered the back end of memory system 210. Storage controller 230 can indicate to memory system controller 215, for example, via bus 235, when the transfer of memory device data to memory device 240 has completed.

[0053] In some cases, storage queue 270 may be used to assist in the transfer of write data. For example, memory system controller 215 may push a write command from buffer queue 265 (e.g., via bus 235) to storage queue 270 for processing. Storage queue 270 may include an entry for each access command and may include, for example, a buffer pointer (e.g., an address) that may indicate where the data associated with the command is stored in buffer 225 and a storage pointer (e.g., an address) that may indicate the location in memory device 240 associated with the data. In some cases, storage controller 230 may obtain the location within buffer 225 from which the data was obtained from buffer 225, buffer queue 265, or storage queue 270. Storage controller 230 may manage the location within memory device 240 to store data (e.g., perform wear leveling, garbage collection, and the like). Entries may be added to storage queue 270, for example, by memory system controller 215. After the transfer of data is complete, entries may be removed from storage queue 270, for example, by storage controller 230 or memory system controller 215.

[0054] To process a read command received from the host system 205, the memory system controller 215 may again first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, for example, via firmware (e.g., controller firmware), the amount of space within the buffer 225 that is available to store the data associated with the read command.

[0055] In some cases, the buffer queue 265 can be used to assist in buffering data associated with a read command in a manner similar to that discussed above with respect to a write command. For example, if the buffer 225 has sufficient space to store the read data, the memory system controller 215 can cause the memory controller 230 to retrieve the data associated with the read command from the memory device 240 using the data path 250 and store the data in the buffer 225 for temporary storage. The memory controller 230 can indicate to the memory system controller 215, for example, via the bus 235, when the data transfer to the buffer 225 has been completed.

[0056] In some cases, storage queue 270 can be used to assist in the transfer of read data. For example, memory system controller 215 can push read commands to storage queue 270 for processing. In some cases, storage controller 230 can obtain the location within memory device 240 from which to retrieve data from buffer 225 or storage queue 270. In some cases, storage controller 230 can obtain the location within buffer 225 to store data from buffer queue 265. In some cases, storage controller 230 can obtain the location within buffer 225 to store data from storage queue 270. In some cases, memory system controller 215 can move commands processed by storage queue 270 back to command queue 260.

[0057] Once the data has been stored in the buffer 225 by the memory controller 230, the data may be transferred out of the buffer 225 and sent to the host system 205. For example, the memory system controller 215 may cause the interface 220 to retrieve the data from the buffer 225 using the data path 250 and transfer the data to the host system 205, e.g., according to a protocol such as the Universal Flash Storage (UFS) protocol or the eMMC protocol. For example, the interface 220 may process commands from the command queue 260 and may indicate to the memory system controller 215, e.g., via the bus 235, when the data transfer to the host system 205 has been completed.

[0058] The memory system controller 215 may execute received commands according to a certain order (e.g., first-in, first-out order, according to the order of the command queue 260). For each command, the memory system controller 215 may cause data corresponding to the command to be moved into and out of the buffer 225, as discussed above. The command may remain in the buffer queue 265 while the data is moved into and stored within the buffer 225. When processing of a command has been completed (e.g., when data corresponding to an access command has been transferred out of the buffer 225), the command may be removed from the buffer queue 265, for example, by the memory system controller 215. When a command is removed from the buffer queue 265, the address where the data associated with the command was previously stored may be used to store data associated with the new command.

[0059] The memory system controller 215 may additionally be configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (e.g., error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue a command indicating one or more LBAs, and the memory system controller 215 may identify the one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may be non-consecutive physical block addresses. In some cases, the storage controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the storage controller 230, and the storage controller 230 may be omitted.

[0060] Figure 3A An example of the layout of a device information page 300 is illustrated to support a method for retiring pages of a memory device according to examples disclosed herein. A page may include non-volatile memory cells. An ordered set of such pages can be used to store device information for use by the device, such as configuration, status, or security information, so that it is available when the device is powered on. Due to reliability degradation based on the number of page accesses, device information pages can be retired before the integrity of the information is lost.

[0061] The device information page 300 may include a plurality of bits 310 (e.g., bits 310-a through 310-n). In some examples, the device information page 300 may include a flag portion 315 for storing flags corresponding to the page. In some examples, the flags may be used as page selectors to reflect when a page has been retired or has reached a durability limit. For example, when "set," the flag may indicate that the device information page 300 has been retired, and when "unset" (or "cleared" or "reset"), the flag may indicate that the page has not yet been retired and can be used.

[0062] In some examples, a flag can be used to reflect when programming of a fuse element associated with the device information page 300 is in progress. For example, when set, the flag can indicate that programming of the fuse element has been initiated but not yet completed, and when not set, the flag can indicate that no programming of the fuse element is in progress (e.g., programming was initiated and completed, or no programming was initiated).

[0063] In some examples, the flag portion may be a single bit (e.g., bit 310-a), and the flag may be set when it is a logic "1" and unset when it is a logic "0." Alternatively, the flag may be set when it is a logic "0" and unset when it is a logic "1." In some examples, the flag portion may include multiple bits, and the flag may be set when a percentage of the bits of the flag portion (e.g., 75% or more, 80% or more) are set.

[0064] In some examples, the device information page 300 may include a counter portion 320 for storing a counter value corresponding to the page. In some examples, the counter value may be used to determine when the page has reached or exceeded the cell endurance limit. In some examples, the counter value may reflect the number of accesses performed on the device information page; each time the device page 300 is accessed, the counter value may be incremented. Incrementing the counter value may be performed, for example, by reading the counter value into a counter, incrementing the counter, and writing the counter value back to the counter portion of the page. In this manner, the counter portion of the page may reflect the number of times the page has been accessed. The counter value may be monitored to detect when it reaches a predetermined number of times, which may reflect when the page has reached or has nearly reached the endurance limit. When the counter value reflects that the endurance limit has been reached, a flag for the page may be set to indicate this.

[0065] The counter portion 320 of the device information page 300 may incorporate any number of bits (e.g., bits 310-b through 310-f). For example, if the endurance limit of the device information page 300 is 32 accesses, the counter portion 320 may incorporate 6 bits, which would allow the use of additional bits to reach a binary count of 32 to allow counts exceeding 32. Typical endurance limits may be in the thousands, tens of thousands, hundreds of thousands, millions, or possibly higher. In some cases, each use of a page may be considered an access and may involve a read (e.g., at power-up) and a write (e.g., at power-down). Alternatively, the page may be accessed additional times while the device is in operation. For example, new information may be written when it is updated during operation. In some cases, the counter portion 320 may record reads and writes separately, or may weight operations differently. For example, the counter portion 320 may include a counter for read operations and a counter for write operations, or may include a single counter in which write operations are recorded, for example, using a weighting factor. In one example, the counter portion 320 may be incremented by 1 for each read operation and incremented by an integer greater than 1 (eg, 5, 10) for each write operation.

[0066] The device information page 300 may include a data portion 325 for storing, for example, data associated with the device. This may include, for example, knowledge of the last power cycle, security data, status data, and the like. This information may be used after a power cycle, for example, to restore the state of the computer or confirm a user's access privileges. The data portion 325 may incorporate any number of bits (e.g., bits 310-g through 310-n).

[0067] Figure 3B An example of a system 305 supporting a method for retiring pages of a memory device according to examples as disclosed herein is illustrated. The system 305 may include a set of device information pages 300 (e.g., device information pages 300-a through 300-f), each having a counter portion 320 and a data portion 325. In some examples, each device information page 300 may also include a flag portion 315 (e.g., as a page selector). In some examples, the device information pages 300 may belong to the same block, such as with respect to Figure 1 Block 170 of the discussion. In some examples, the system 305 can include a set of fuse elements 335 (e.g., fuse elements 335-a through 335-f), each of which is associated with the device information page 300 (e.g., as a page selector). The fuse elements 335 can be included in place of or in conjunction with the flag portion 315, as discussed in more detail below.

[0068] In some examples, the device information pages 300 may be located in a specific order and may be used one at a time in that specific order. For example, device information may be stored and retrieved from the first device information page 300-a until it is determined (e.g., by using a counter value for the page) that the number of accesses to the page has reached or exceeded a cell endurance limit. When this occurs, the device information page 300-a may be retired (e.g., using a flag for the page or an associated fuse element 335-a) and the next page in the sequence (e.g., device information page 300-b) may be used. That is, system information may be stored and retrieved from the second device information page 300-b rather than the first device information page 300-a. Similar to the first page, the second page may be used until it is determined that the number of accesses to the second page has reached or exceeded a cell endurance limit, at which point the second page may also be retired and the next page in the sequence (e.g., device information page 300-c) may be used. This may continue until all device information pages have been used.

[0069] exist Figure 3BIn the example shown in FIG, the third device information page 300-c is the page in use and the previous pages (device information pages 300-a and 300-b) have been retired. Given this, the page selectors (e.g., flag 315) of pages 300-a and 300-b may be set (e.g., "1") and the page selector of page 300-c may be unset (e.g., "0"). The flags 315 of the remaining pages (e.g., device information pages 300-d to 300-f) may also be unset (e.g., "0") to indicate that the pages have not yet been retired. Alternatively, if fuse elements are used as page selectors, the fuse elements 335-a and 335-b associated with the first two device information pages 300-a and 300-b may already be programmed (e.g., blown) to indicate retirement of those pages.

[0070] During power-up, the flag 315 of the first device information page 300-a may be retrieved and determined to be set. This may indicate that the first page 300-a has been retired and its data may be invalid. The flag 315 of the next page (the second device information page 300-b) may be retrieved and also determined to be set. This may indicate that the second page 300-b has also been retired and its data may be invalid. The flag 315 of the next page (the third device information page 300-c) may be retrieved and determined to be unset. This may indicate that the third page 300-c is the first page in the sequence that has not yet been retired and that the page may contain valid data.

[0071] Alternatively, a data message (e.g., data message 340) may be retrieved that shows the status of each fuse element 335. In some examples, the status of each fuse element may be reflected in different bits in the message. The message may be analyzed to determine that device information pages 300-a and 300-b have been retired and device information page 300-c is the first page in the sequence that has not yet been retired.

[0072] After determining that the device information page 300-c should be used, the data stored in the data portion 325 of the page 300-c can be retrieved and used to restore the device. The counter value stored in the counter portion 320 of the page 300-c can be incremented to reflect the access of the page (e.g., by reading the value into the counter 330, incrementing the counter, and writing the counter value back to the counter portion of the page). The counter value can then be compared to a threshold value (e.g., a page endurance level) to determine whether the page 300-c should be retired. If the counter value of the page 300-c is greater than or equal to the threshold value, the page's flag 315 can be set (e.g., by writing a "1" to the flag portion of the page) or a fuse element 335-c associated with the page can be programmed (e.g., by instructing the system to blow the fuse element) to indicate the retirement of the page 300-c. The device information obtained from the device information page 300-c can be saved to the data field 325 of the original device information page 300-c (if the page is not retired) or the next device information page 300-d (if the original page 300-c is retired) to be used as valid data for forward movement.

[0073] Figures 4 to 6 Flowcharts are shown illustrating examples of methods 400, 500, and 600 for supporting methods for retiring pages of a memory device according to examples as disclosed herein. In methods 400, 500, and 600, selectors (e.g., flags and fuse elements) and counters associated with device information pages are used to determine which page to use and when to switch to the next page. The operations of any of methods 400, 500, or 600 may be implemented by a memory system or components thereof as described herein. For example, the methods may be implemented by a memory system as described herein. Figure 1 The memory device 130 described herein may be used to perform the operations of any of the methods 400, 500, or 600. In some examples, a memory system may execute an instruction set to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0074] Figure 4 A flowchart illustrating an example of a method 400 for supporting a method for retiring pages of a memory device according to an example disclosed herein is shown. Method 400 can be used at power-up to determine which device information page may be in use and when and how to switch to the next page. In method 400, a flag and count embedded in the device information page can be employed in this process.

[0075] At 405, it may be determined whether power-up has completed. In some examples, this may be determined by monitoring the PwrUp signal. If power-up has not yet completed, the method may wait at 405 until power-up has completed. Once power-up is complete, the method may proceed to 410.

[0076] At 410, a flag of the device information page may be used to determine the page to be used. In some examples, the flag of each page may be read until a flag value indicating that the corresponding page may contain valid data is obtained. In some examples, the pages may be located in a certain order, and the flags of the pages may be read starting with the first page and continuing with the other pages in the order. In some examples, the flag may be a single bit and may contain a logic "1" to indicate that the corresponding page may contain valid data and may be used. In other examples, the flag may contain a logic "0" to indicate that the page may contain valid data and may be used. In some examples, the flag may include multiple bits and a percentage of bits (e.g., 66% or higher, 75% or higher, 80% or higher) may be set to indicate that the corresponding page may be used. Once a flag indicating that a page may be used is encountered, the corresponding page may be considered the original "in-use" device information page for the purpose of the method.

[0077] The device information may be restored from the original page and used by the memory system at 415. Also at 415, a counter value corresponding to the original page may be incremented to reflect the accessed page.

[0078] At 420 , the counter value obtained at 415 may be compared to a threshold value (eg, a cell endurance limit). If the counter value for the original page has not exceeded the threshold value, the cells of the original page may be considered to contain valid data, and the method may continue to 435 .

[0079] If the counter value of the original page has exceeded a threshold, the cells of the page may be approaching a point where the data contained in the page may become susceptible to invalidation issues, such as due to corruption of the cells of the page. To alleviate these issues, the original page may be retired so that the cells associated with it can be stopped from being used. If the counter value of the original page has exceeded a threshold, the method may continue to 425 to retire the page.

[0080] At 425, the original page may be retired. In some examples, retirement of the page may be accomplished by changing (e.g., setting or clearing) a flag for the page. In some examples where the flag may be a single bit, the flag may be changed to a logic "0" to set the flag. In some examples, the flag may be changed to a logic "1" to set the flag. Setting the flag may cause the original page to not be used at the next power-up.

[0081] At 430, the next page in the sequence may be set up to replace the most recently retired page with the new device information page to be used. In some examples, a counter value corresponding to the next page may be reset (e.g., to a value of 0 or 1). In some examples, a flag for the next page may be set or cleared. In some examples, the flag may already reflect the correct value, so that it may not change. Also at 430, device information may be written to the next page. In some examples, this may include device information previously stored in the original (now retired) page. The counter value corresponding to the next page may be incremented to reflect the accessed page. The next page may be considered the new "in-use" device information page.

[0082] At 435, it may be determined whether a reset command has been received. In some examples, the reset command may be a system command that may indicate an imminent power loss to the memory device. If a reset command has not been received, the method may wait at 435 until a reset command is received. Once a reset command is received, the method may proceed to 440.

[0083] At 440, device information may be written to the in-use page. Depending on whether steps 425 and 430 are used, the in-use page may be the original page or a new page. In some examples, the in-use page may be determined by a flag of the original page: if the flag is a 1, the original page may be the in-use page; if it is a different value, the original page may have been retired and the new page may be the in-use page. Also at 440, a counter value corresponding to the in-use page may be incremented to reflect the accessed page.

[0084] Figure 5 A flowchart illustrating an example of method 500 supporting a method for retiring pages of a memory device according to examples disclosed herein is shown. Similar to method 400, method 500 can be used at power-up to determine which device information page is in use and when and how to switch to the next page. However, instead of employing flags embedded in the pages, method 500 can utilize fuse elements associated with the pages. Once the original page has been determined based on the fuse elements, method 500 can generally follow the same steps as method 400, with a few exceptions due to the use of fuse elements.

[0085] During power-up, information about the system fuse elements (e.g., which fuses are shorted and which are blown) may become available. At 505, the method may wait until the fuse element information is available. In some examples, this may be accomplished by monitoring the TMBroadcast signal. Once the fuse element information becomes available, the method may proceed to 510.

[0086] At 510, fuse element information associated with the device information pages may be obtained and used to determine which page to use. In some examples, the fuse information associated with each device information page may be checked to identify a first fuse that is not programmed (e.g., not blown). This may indicate that the page associated with that fuse may be used as the in-use page. In some examples, the pages may be located in a certain order and the fuse information associated with the pages may be read in the same order. In some examples, the fuse information may be obtained from power-up information. In some examples, a single bit may be used to indicate the state of the fuse element associated with each page and the bit may be checked to determine the first fuse that is not blown. Once a fuse value indicating that a page may be used is determined, the corresponding page may be considered the original "in-use" device information page for the method.

[0087] At 515, the device information data can be restored from the original page and used by the memory system. Also at 515, the counter value corresponding to the original page can be incremented to reflect the accessed page. This step can be similar to step 415 of method 400.

[0088] At 520, the counter value obtained at 515 may be compared to a threshold. If the counter value for the original page has exceeded the threshold, the method may continue to 525 to retire the page. Otherwise, the method may continue to 535. This step may be similar to step 420 of method 400.

[0089] At 525, the original page can be retired. However, instead of changing a flag value (as in method 400), retiring the page can involve changing the value of a fuse element. In some examples, retiring the original page can be accomplished by programming (e.g., blowing or setting) a fuse element associated with the page. In some examples, a nonvolatile variable can be set so that, at the next power-up, it can trigger the memory system to program the fuse element associated with the original page. Regardless, programming the fuse element can cause the original page to not be used during future power-ups.

[0090] At 530, the next page in the sequence can be set up to replace the most recently retired page with the new device information page. In some examples, the counter value corresponding to the next page can be reset. Also at 530, device information can be written to the next page. The counter value corresponding to the next page can be incremented to reflect the accessed page. The next page can be considered the new "in-use" device information page.

[0091] At 535, it may be determined whether a reset command has been received. If a reset command has not been received, the method may wait at 535 until a reset command has been received. Once a reset command is received, the method may continue to 540. This step may be similar to step 435 of method 400.

[0092] At 540, the device information may be written to the in-use device page. Depending on whether steps 525 and 530 are used, the in-use page may be the original page or a new page. Also at 540, the counter value corresponding to the in-use device page may be incremented to reflect the accessed page. This step may be similar to step 440 of method 400.

[0093] One issue that can arise from using a fuse element as a page selector is the amount of time it can take to program (e.g., blow) the fuse element. Sometimes programming a fuse element can take so long that it is not completed before a power cycle occurs. As a result, when the system powers up, the fuse may still be unprogrammed (e.g., fuse shorted, antifuse open). This can allow the associated page to be used as the device page because the fuse information can still reflect that the fuse has not been blown.

[0094] Figure 6 A flow chart illustrating an example of a method 600 for supporting a method for retiring pages of a memory device according to examples disclosed herein is shown. Similar to method 500, method 600 may employ fuse elements and counts at power-up to determine which device information page may be in use and when and how to switch to the next page. Method 600 also uses flags embedded in the page to identify situations where programming of the fuse element may not be complete before a power cycle.

[0095] At 605, the method may wait until fuse information is available. This step may be similar to step 505 of method 500. Once the fuse information becomes available, the method may continue to 610.

[0096] At 610 , fuse information associated with the pages may be obtained and examined to determine which page to use as the original “in use” device information page for the method. This step may be similar to step 510 of method 500 .

[0097] The flag of the original page may be read and analyzed to determine the status of the fuse elements associated with the page at 615. For example, when set, the flag may indicate that programming of the fuse element has been initiated but not yet completed, and when not set, the flag may indicate that programming of no fuse element is in progress.

[0098] At 620, if the flag is not set, then the fuse element associated with the original page may not be in the process of being programmed. That is, any programming (e.g., blowing) of the fuse element may have been completed. In this case, the device information for the original page may be valid and the method may continue to 625.

[0099] However, if the flag for the original page is set, the fuse element associated with the page may be in the process of being programmed (e.g., blown). That is, programming of the fuse element associated with the original page may have been initiated but may not yet be completed. In this case, the fuse information used to identify the original page at 610 may not have accounted for this. In other words, because programming of the fuse element may not have been completed, the associated page may have been mistakenly identified as the original page to be used. If the flag is set, the method may continue to 645 to correct this error.

[0100] At 625, the device information can be restored from the original page and used by the memory system. Also at 625, the counter value corresponding to the original page can be incremented to reflect the accessed page. This step can be similar to step 615 of method 500.

[0101] At 630, the counter value obtained at 625 may be compared to a threshold. If the counter value for the original page has exceeded the threshold, the method may continue to 635 to retire the page. Otherwise, the method may continue to 655. This step may be similar to step 520 of method 500.

[0102] At 635, a flag in the original page may be set (e.g., by writing a "1" to the flag portion of the page) to indicate that programming of the fuse element associated with the page is about to begin. The flag may remain set until programming of the fuse element is complete (see 670). Also at 635, the counter value corresponding to the next page may be reset.

[0103] Programming (e.g., blowing or setting) of a fuse element associated with the original page may be initiated to retire the page at 640. In some examples, a nonvolatile variable may be set so that upon the next power-up, it may trigger the memory system to program the fuse element associated with the original page.

[0104] At 645, since the flag of the original page may be set, the next page may still be expected to be the in-use device information page, even though programming of the fuse element associated with the original page may not be complete. Therefore, at 645, the device information can be restored from the next page and used by the memory system. Also at 645, the counter value corresponding to the next page may be reset (e.g., to a value of 0 or 1).

[0105] At 650, programming (eg, blowing or setting) of the fuse element associated with the original page may be continued or reinitiated to retire the page.

[0106] At 655, it may be determined whether a reset command has been received. If a reset command has not been received, the method may wait at 655 until a reset command has been received. Once a reset command is received, the method may continue to 660.

[0107] At 660, the flag of the original page can be analyzed again to determine the state of the fuse element associated with the page. If the flag is set, then programming of the associated fuse element may have already been initiated, for example, at 640 or 650. In this case, the method can continue to 665. If the flag is not set, then any programming of the initiated fuse element may have been completed. In this case, the method can continue to 675.

[0108] At 665, it may be determined whether the initiated programming of the fuse element associated with the original page has been completed. In some examples, this may be accomplished by obtaining and analyzing updated information reflecting the state of the fuse. If programming of the fuse element has been completed, the method may continue to 670; otherwise, the method may continue to 675.

[0109] At 670, the flag of the original page may be cleared (eg, by writing a "0" to the flag portion of the page) to indicate completion of programming of the fuse elements associated with the page.

[0110] At 675, device information may be written to the in-use device page. Depending on whether step 640 or 650 is used, the in-use page may be the original page or a new page. If 675 is entered directly from 665, the flag for the original page may be set, indicating that programming of the fuse element associated with the original page may not be complete. The flag (which may now be set) may be read at 615 at the next power-up, and fuse element programming may then be completed. Also at 675, the counter value corresponding to the in-use page may be incremented to reflect the accessed page.

[0111] Figure 7 A block diagram 700 is shown of a memory device 705 supporting a method for retiring pages of a memory device according to examples as disclosed herein. The memory device 705 may be a memory device as described with respect to Figure 1 and 2 Memory device 705 may include a selector read component 710, a page determination component 715, a selector update component 720, a data reader / writer 725, a counter controller 730, a command receiver 735, a flag controller 740, and a fuse programming component 745. Each of these modules can communicate with each other directly or indirectly (e.g., via one or more buses).

[0112] The selector read component 710 can, upon power-up, obtain a first selector value from a first selector associated with a first page of a set of pages of non-volatile memory. In some examples, the selector read component 710 can obtain a third selector value associated with a third page of the set of pages. In some cases, the first selector can include a fuse element associated with the first page. In some cases, the first selector can include a flag stored in the first page. In some cases, the flag can include a set of bits.

[0113] The page determination component 715 can determine that the first page contains valid data based on the first selector value. In some examples, determining that the first page contains valid data can include determining that the first page contains valid data when a threshold percentage of a set of bits of a flag are set. In some examples, the page determination component 715 can determine that the first page should be retired based on a counter value associated with the first page. In some examples, determining that the first page should be retired can include determining that the counter value is above a threshold.

[0114] In some examples, the page determination component 715 may start with the page in the first position in a certain order and perform a page determination process according to the order until a page of the set of pages is found that has not been retired. The page determination process may include obtaining a selector value corresponding to the page and determining whether the page has been retired based on the selector value. In some examples, a page positioned before the first page in the order may have been retired, as reflected in the corresponding selector value. In some examples, a page positioned after the first page in the order may not have been retired, as reflected in the corresponding selector value.

[0115] In some examples, the page determination component 715 can determine that the third page has been retired based on the third selector value.In some examples, obtaining the first selector value associated with the first page can be based on determining that the third page has been retired.

[0116] The selector update component 720 can update a first selector value associated with a first page to reflect retirement of the first page. In some examples, updating the first selector value to reflect retirement of the first page includes setting a first flag stored in the first page. In some examples, updating the first selector value to reflect retirement of the first page includes programming a first fuse element associated with the first page. In some examples, the selector update component 720 can update a second selector value associated with a second page to reflect that the second page contains valid data.

[0117] The data reader / writer 725 may write data to a second page of the set of pages instead of the first page. In some examples, the data reader / writer 725 may obtain status data from the first page based on a determination that the first page contains valid data. In some examples, the data reader / writer 725 may write the status data to the second page. In some examples, writing the data to the second page is based on receiving a reset command. In some examples, the data reader / writer 725 may obtain data from the second page based on a determination that programming of the fuse element is not yet complete.

[0118] The counter controller 730 may obtain a counter value associated with a first page. In some examples, obtaining the counter value associated with the first page may include reading the counter value from the first page. In some examples, the counter controller 730 may determine the counter value associated with the first page. In some examples, determining the counter value associated with the first page may include reading the counter value from the first page. In some examples, the counter controller 730 may obtain a second counter value associated with the first page. In some examples, the counter controller 730 may increment the second counter value to obtain the counter value. In some examples, the counter controller 730 may obtain the counter value for the page before powering up the memory device.

[0119] The command receiver 735 may receive a reset command.

[0120] The flag controller 740 may obtain a first flag value from a flag of a page of a group of pages of the nonvolatile memory upon power-up of the memory device. In some examples, the flag controller 740 may set the flag of the page to the first flag value based on determining that the page should be retired. In some examples, the flag controller 740 may write a second flag value to the flag of the page based on determining that programming of the fuse element has completed. In some examples, the flag controller 740 may initiate a page change operation of the memory device based on setting the flag. The page change operation may include programming the fuse element.

[0121] In some examples, the fuse programming component 745 may determine that programming of the fuse element has been completed. The fuse programming component 745 may determine that programming of the fuse element associated with the page has not been completed based on a flag value. In some examples, determining that programming of the fuse element associated with the page has not been completed may include determining that programming of the fuse element associated with the page has not been completed when a threshold percentage of a set of bits of the flag is set. In some examples, the fuse programming component 745 may continue programming of the fuse element based on determining that programming of the fuse element has not been completed. In some cases, programming of the fuse element may indicate that the page is retired.

[0122] Figure 8A flow chart illustrating a method 800 for supporting a method for retiring pages of a memory device according to aspects of the present disclosure is shown. The operations of the method 800 may be implemented by a memory device or components thereof as described herein. For example, the method 800 may be implemented by a memory device or components thereof as described herein. Figure 7 The memory device described herein may be used to perform the operations of method 800. In some examples, the memory device may execute an instruction set to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0123] At 805, a memory device may, upon power-up, obtain a first selector value from a first selector associated with a first page of a set of pages of non-volatile memory. The operations of 805 may be performed according to the methods described herein. In some examples, the first selector value may be obtained by a method such as that described with respect to Figure 7 Aspects of the operations of the selector reading component to perform 805 are described.

[0124] At 810, the memory device may determine that the first page contains valid data based on the first selector value. The operation of 810 may be performed according to the methods described herein. In some examples, the first page may be determined by the method described in the embodiment of the present invention. Figure 7 The page determines the components to perform aspects of the operation of 810 .

[0125] At 815, the memory device may determine that the first page should be retired based on the counter value associated with the first page. The operation of 815 may be performed according to the methods described herein. In some examples, the first page may be retired based on the counter value associated with the first page. Figure 7 The page determines the aspects of the components used to perform the operations of 815.

[0126] At 820, the memory device may update a first selector value associated with the first page to reflect the retirement of the first page. The operation of 820 may be performed according to the methods described herein. In some examples, the memory device may update a first selector value associated with the first page to reflect the retirement of the first page. Figure 7 Aspects of the operations of the selector update component to perform 820 are described.

[0127] At 825, the memory device may write data to a second page of the set of pages instead of the first page. The operation of 825 may be performed according to the methods described herein. In some examples, the memory device may be configured as described with respect to Figure 7 Aspects of the operations of the data reader / writer to perform 825 are described.

[0128] In some examples, an apparatus as described herein may perform a method or methods, such as method 800. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: obtaining, at power-up, a first selector value from a first selector associated with a first page of a set of pages of non-volatile memory; determining, based on the first selector value, that the first page contains valid data; determining, based on a counter value associated with the first page, that the first page should be retired; updating the first selector value associated with the first page to reflect the retirement of the first page; and writing data to a second page of the set of pages in place of the first page.

[0129] Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for updating a second selector value associated with the second page to reflect that the second page contains valid data.

[0130] Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for starting with the page in the first position in a certain order and performing a page determination process according to the order until a page of the set of pages can be found that may not have been retired. In some examples of the method 800 and apparatus described herein, performing the page determination process may include operations, features, means, or instructions for obtaining a selector value corresponding to the page and determining whether the page may have been retired based on the selector value.

[0131] In some examples of the method 800 and apparatus described herein, determining that the first page should be retired may include operations, features, means, or instructions for determining that a counter value may be above a threshold.

[0132] Some instances of the method 800 and apparatus described herein may further include operations, features, components, or instructions for obtaining a third selector value associated with a third page of the set of pages; and determining, based on the third selector value, that the third page may have been retired, wherein obtaining the first selector value associated with the first page may be based on determining that the third page may have been retired.

[0133] In some examples of the methods 800 and apparatus described herein, the first selector may include a fuse element associated with the first page. In some examples of the methods 800 and apparatus described herein, updating the first selector value to reflect retirement of the first page may include an operation, feature, means, or instruction for programming the first fuse element associated with the first page.

[0134] In some examples of the method 800 and apparatus described herein, the first selector may include a flag stored in the first page. In some examples of the method 800 and apparatus described herein, updating the first selector value to reflect retirement of the first page may include an operation, feature, means, or instruction for setting a first flag stored in the first page. In some examples of the method 800 and apparatus described herein, the flag may include a set of bits. In some examples of the method 800 and apparatus described herein, determining that the first page contains valid data may include determining that the first page contains valid data when a threshold percentage of the set of bits of the flag may be set.

[0135] In some examples of the method 800 and apparatus described herein, determining the counter value may include operations, features, means, or instructions for reading the counter value from the first page. In some examples of the method 800 and apparatus described herein, determining the counter value may include operations, features, means, or instructions for obtaining a second counter value associated with the first page and incrementing the second counter value to obtain the counter value.

[0136] Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for receiving a reset command. In some examples of the method 800 and apparatus described herein, writing data to the second page may be based on receiving a reset command.

[0137] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for obtaining state data from the first page based on determining that the first page contains valid data. In some examples of the method 800 and apparatus described herein, writing data to the second page may include operations, features, components, or instructions for writing state data to the second page.

[0138] Figure 9 A flow chart illustrating a method 900 for supporting a method for retiring pages of a memory device according to aspects of the present disclosure is shown. The operations of the method 900 may be implemented by a memory device or components thereof as described herein. For example, the method 900 may be implemented by a memory device or components thereof as described herein. Figure 7 The memory device described herein may be used to perform the operations of method 900. In some examples, the memory device may execute an instruction set to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0139] At 905, the memory device may obtain a first flag value from flags of a page of a set of pages of a non-volatile memory at power-up of the memory device. The operations of 905 may be performed according to the methods described herein. In some examples, the flag value may be obtained by a memory device such as the one described with respect to FIG. Figure 7Aspects of the operations of the flag controller to perform 905 are described.

[0140] At 910, the memory device may determine that programming of the fuse element associated with the page has not been completed based on the flag value. The operation of 910 may be performed according to the methods described herein. In some examples, the programming may be performed by, for example, Figure 7 Aspects of the operations of the fuse programming component 910 are described.

[0141] At 915, the memory device may continue programming of the fuse element based on determining that programming of the fuse element has not yet completed, wherein programming of the fuse element indicates that the page is retired. The operation of 915 may be performed according to the methods described herein. In some examples, the programming of the fuse element may be performed by, for example, Figure 7 Aspects of the operation of the fuse programming component to perform 915 are described.

[0142] At 920, the memory device may determine that programming of the fuse element is complete. The operation of 920 may be performed according to the methods described herein. In some examples, the programming may be performed by, for example, Figure 7 Aspects of the operations of 920 are described using a fuse programming component to perform.

[0143] At 925, the memory device may write a second flag value to the flag of the page based on determining that programming of the fuse element is complete. The operation of 925 may be performed according to the methods described herein. In some examples, the operation may be performed by, for example, Figure 7 Aspects of the operations of the flag controller to perform 925 are described.

[0144] In some examples, an apparatus as described herein may perform a method or methods, such as method 900. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: obtaining, at power-up of a memory device, a first flag value from a flag of a page of a group of pages of a non-volatile memory; determining, based on the flag value, that programming of a fuse element associated with the page is not yet complete; continuing programming of the fuse element based on determining that programming of the fuse element is not yet complete, wherein programming of the fuse element indicates that the page is retired; determining that programming of the fuse element is complete; and writing a second flag value to the flag of the page based on determining that programming of the fuse element is complete.

[0145] Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for obtaining data from the second page based on determining that programming of the fuse element may not be complete.

[0146] In some examples of the method 900 and apparatus described herein, the flag may include a set of bits. In some examples of the method 900 and apparatus described herein, determining that programming of the fuse element associated with the page may not be complete includes determining that programming of the fuse element associated with the page may not be complete when a threshold percentage of the set of bits of the flag may be set.

[0147] Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for: obtaining a counter value for a page before powering up the memory device; determining that the page should be retired based on the counter value; setting a flag for the page to a first flag value based on determining that the page should be retired; and initiating a page change operation for the memory device based on setting the flag. In some examples of the method 900 and apparatus described herein, the page change operation may include programming a fuse element.

[0148] It should be noted that the methods described above describe possible implementations, and that operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more methods may be combined.

[0149] A memory device is described. The memory device may include multiple pages of nonvolatile memory and a controller. The controller may be configured to: upon power-up, obtain a first selector value from a first selector associated with a first page of the multiple pages; determine that the first page contains valid data based at least in part on the first selector value; determine that the first page should be retired based at least in part on a counter value associated with the first page; update the first selector value associated with the first page to reflect the retirement of the first page; and write data to a second page of the multiple pages in place of the first page.

[0150] In some examples, pages of the plurality of pages may be positioned according to a predetermined order, and the controller may be further configured to perform a page determination process in the order, starting with the page in the first position and according to the order, until a page of the plurality of pages is found that has not been retired. The page determination process may include: obtaining a selector value corresponding to the page; and determining whether the page has been retired based at least in part on the selector value. In some examples, pages of the plurality of pages positioned before the first page in the order may have been retired, as reflected in the corresponding selector value, and pages of the plurality of pages positioned after the first page in the order may not have been retired, as reflected in the corresponding selector value.

[0151] In some examples, the controller may be further configured to update a second counter value associated with the second page.

[0152] In some examples, the controller may be further configured to determine that the first page should be retired based at least in part on determining that the counter value is above a threshold.

[0153] In some instances, the controller may be further configured to: obtain a third selector value associated with a third page of the plurality of pages; and determine, based at least in part on the third selector value, that the third page has been retired, wherein obtaining the first selector value associated with the first page is based at least in part on determining that the third page has been retired.

[0154] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a signal bus, where the bus may have various bit widths.

[0155] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or a subregion of the substrate, can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0156] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor gate, the transistor may be "off" or "deactivated."

[0157] The description set forth herein, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples." The detailed description includes specific details to provide an understanding of the described technology. However, these technologies can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0158] In the accompanying drawings, similar components or features may have the same reference number. Furthermore, components of the same type may be distinguished by following the reference number with a dash and a second label that distinguishes between similar components. If only the first reference number is used in the specification, the description applies to any of the similar components having the same first reference number, regardless of the second reference label.

[0159] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including portions distributed so that the functions are implemented at different physical locations.

[0160] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or executed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0161] As used herein, including in the claims, "or" as used in a list of items (e.g., a list of items followed by a phrase such as "at least one" or "one or more") indicates an inclusive list, such that a list such as at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0162] Computer-readable media include non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage device, or can be used to carry or store desired program code components in the form of instructions or data structures, and any other non-transitory media that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. In addition, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0163] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications of the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: obtaining, at power-up of the memory device, a flag value from a flag of a first page of a plurality of pages of the nonvolatile memory; determining, based at least in part on the flag value, that programming of a fuse element associated with the first page is not yet complete; continuing the programming of the fuse element based at least in part on determining that the programming of the fuse element has not been completed, wherein the programming of the fuse element indicates that the first page is retired; determining that the programming of the fuse element is complete; as well as A second flag value is written to the flag of the first page based at least in part on determining that the programming of the fuse element is complete.

2. The method according to claim 1, further comprising: Data is retrieved from a second page based at least in part on determining that the programming of the fuse element is not complete.

3. The method of claim 1 , wherein the flag comprises a plurality of bits, and wherein determining that the programming of the fuse element associated with the first page is not yet complete comprises: The programming of the fuse element associated with the first page is determined to be not yet complete when a threshold percentage of the plurality of bits of the flag are set.

4. The method according to claim 1, further comprising: Before said powering up of said memory device, obtaining a counter value of said first page; determining that the first page should be retired based at least in part on the counter value; setting the flag of the first page to the flag value based at least in part on determining that the first page should be retired; as well as A page change operation of the memory device is initiated based at least in part on setting the flag, wherein the page change operation includes programming the fuse element.

5. The method according to claim 1, further comprising: obtaining data from a second page based at least in part on determining that the programming of the fuse element is not complete; as well as The memory device is restored based on the data obtained from the second page. 6 . The method of claim 1 , wherein the fuse element comprises a fuse, and the programming of the fuse element comprises blowing the fuse.

7. The method of claim 1, wherein the first page includes a data portion for storing data associated with the memory device.

8. The method of claim 1 , wherein the pages of the plurality of pages are positioned according to a predetermined order, the method further comprising: Starting with the page at the first position in the sequence and performing a page determination process according to the sequence until a page in the plurality of pages is found not to have been retired, the page determination process comprising: obtaining a value of a fuse element corresponding to the page; and determining whether the page has been retired based at least in part on the value of the fuse element, wherein: A page of the plurality of pages positioned before the first page in the sequence has been retired as reflected in a corresponding value of the fuse element, and Pages in the plurality of pages positioned after the first page in the sequence have not been retired, as reflected in corresponding values ​​of the fuse elements.

9. A memory device comprising: multiple pages of non-volatile memory; as well as A processing circuit system configured to: upon power-up of the memory device, obtaining the flag value from a flag of a first page of the plurality of pages of nonvolatile memory; determining, based at least in part on the flag value, that programming of a fuse element associated with the first page is not complete; continuing the programming of the fuse element based at least in part on determining that the programming of the fuse element has not been completed, wherein the programming of the fuse element indicates that the first page is retired; determining that the programming of the fuse element is complete; as well as A second flag value is written to the flag of the first page based at least in part on determining that the programming of the fuse element is complete.

10. The memory device of claim 9, wherein the processing circuitry is further configured to: Data is obtained from a second page based at least in part on determining that the programming of the fuse element is not yet complete.

11. The memory device of claim 10 , wherein the processing circuitry is further configured to: The memory device is restored based on the data obtained from the second page.

12. The memory device of claim 9 , wherein the flag comprises a plurality of bits, and wherein determining that the programming of the fuse element associated with the first page has not been completed comprises determining that the programming of the fuse element associated with the first page has not been completed when a threshold percentage of the plurality of bits of the flag is set.

13. The memory device of claim 9, wherein the processing circuitry is further configured to: Before said powering up of said memory device, obtaining a counter value of said first page; determining, based at least in part on the counter value, that the first page is to be retired; setting the flag of the first page to the flag value based at least in part on determining that the first page is to be retired; and A page change operation of the memory device is initiated based at least in part on setting the flag, wherein the page change operation includes programming the fuse element.

14. The memory device of claim 9, wherein the fuse element comprises a fuse, and programming the fuse element comprises blowing the fuse.

15. The memory device of claim 9, wherein the first page includes a data portion for storing data associated with the memory device.

16. The memory device of claim 9, wherein the pages of the plurality of pages are located according to a predetermined order, and wherein processing circuitry is further configured to: Starting with the page at the first position in the sequence and performing a page determination process according to the sequence until a page in the plurality of pages is found not to have been retired, the page determination process comprising: obtaining a value of a fuse element corresponding to the page; as well as determining whether the page has been retired based at least in part on the value of the fuse element, in: A page of the plurality of pages positioned before the first page in the sequence has been retired as reflected in a corresponding value of the fuse element, and Pages in the plurality of pages positioned after the first page in the sequence have not been retired, as reflected in corresponding values ​​of the fuse elements.

17. A method comprising: Upon power-up of the memory device, obtaining fuse information associated with a plurality of pages of the non-volatile memory; determining a first page of the plurality of pages based on the fuse information; determining a state of a fuse element associated with the first page based on a value of a flag for the first page, the value of the flag indicating that no programming of the fuse element is in progress or that programming of the fuse element has been initiated but not yet completed; In response to the value of the flag indicating that programming of no fuse element is in progress, restoring device information from the first page; and In response to the value of the flag indicating that programming of the fuse element has been initiated but not yet completed: Recovering device information from the second page; and Programming of the fuse element continues to retire the first page.

18. The method of claim 17, further comprising: In response to the value of the flag indicating that programming of no fuse element is in progress, updating a counter corresponding to the first page; as well as In response to the value of the flag indicating that programming of the fuse element has been initiated but not yet completed, resetting a counter corresponding to the second page.

19. The method of claim 17, further comprising: In response to the value of the flag indicating that no programming of the fuse element is in progress: determining, based at least in part on a counter value associated with the first page, that the first page is to be retired; and Programming of the fuse element is initiated to retire the first page.

20. The method of claim 17, further comprising: Before said powering up of said memory device, obtaining a counter value of said first page; determining, based at least in part on the counter value, that the first page is to be retired; setting the flag of the first page to a first value based at least in part on determining that the first page is to be retired; and Based at least in part on setting the flag to the first value, a page change operation of the memory device is initiated, wherein the page change operation includes programming the fuse element.

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