A method for preparing a semiconductor structure and a semiconductor structure

Abstract

The present application discloses a method for preparing a semiconductor structure and a semiconductor structure, the preparation method comprising: providing a substrate, the substrate having a shallow trench isolation structure, a depression formed at the junction of the shallow trench isolation structure and the active area of ​​the substrate; forming a first dielectric layer at least on the side wall of the depression close to the active area; forming a sacrificial layer on the substrate, the sacrificial layer covering the upper surface of the substrate; forming a second dielectric layer, the second dielectric layer covering the shallow trench isolation structure, the first dielectric layer and the sacrificial layer; grinding the second dielectric layer and stopping at the sacrificial layer; and removing the sacrificial layer. Compared with the prior art, the unexpected technical effect of the present application is: without adding a mask, the formation of a depression at the junction of the shallow trench isolation structure and the active area can be avoided, so that the surface of the active area is flat, so as to achieve the effect of reducing INWE.

Description

Technical Field

[0001] The present application generally relates to the field of semiconductor device manufacturing technology. More specifically, the present application relates to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the rapid evolution of semiconductor technology, especially in the context of the gradual reduction in the size of integrated circuits, increasing the density of active devices per unit area on semiconductor substrates has become the focus of current research. With the trend of increasingly compact devices, effective insulation isolation technology between devices is particularly critical. When semiconductor technology enters the deep submicron era, especially when the device size is reduced to below 0.18μm, the active area (AA) isolation layer of the metal oxide semiconductor (MOS) circuit is generally made using the shallow trench isolation (STI) process. The STI process plays an important role in increasing device integration, maintaining surface flatness, and reducing channel width erosion with its advantages such as excellent electrical isolation effect and small occupied area.

[0003] In the prior art, after forming a shallow trench isolation structure, the semiconductor substrate is separated into several active areas (AA) by the shallow trench isolation structure. However, in the subsequent semiconductor structure preparation process based on the active area, a divot will be formed at the junction of the shallow trench isolation structure and the active area due to ion implantation, cleaning, etc., and the surface of the active area cannot be flattened. After polysilicon is deposited in the active area, parasitic MOS tubes will be formed at the divots on both sides of the polysilicon, resulting in an inverse narrow channel effect (INWE). Moreover, as the device develops, the gate width continues to decrease, and the INWE effect will become more and more serious.

[0004] In view of this, there is an urgent need to provide a semiconductor structure preparation scheme so that after the shallow trench isolation structure is formed, in the subsequent semiconductor structure preparation process, a depression is avoided at the junction of the shallow trench isolation structure and the active area, so that the surface of the active area is flat. Summary of the invention

[0005] In order to at least solve one or more of the technical problems mentioned above, the present application proposes a semiconductor structure preparation scheme and a corresponding semiconductor structure in multiple aspects.

[0006] In a first aspect, the present application provides a method for preparing a semiconductor structure, comprising: providing a substrate, wherein the substrate has a shallow trench isolation structure, and a depression is formed at the junction of the shallow trench isolation structure and the active area of ​​the substrate; forming a first dielectric layer at least on the side wall of the depression close to the active area; forming a sacrificial layer on the substrate, wherein the sacrificial layer covers the upper surface of the substrate; forming a second dielectric layer, wherein the second dielectric layer covers the shallow trench isolation structure, the first dielectric layer and the sacrificial layer; grinding the second dielectric layer and stopping at the sacrificial layer; and removing the sacrificial layer.

[0007] In some embodiments, forming a first dielectric layer at least on the side wall of the recess near the active area includes: depositing a dielectric layer material on the substrate, the dielectric layer material covering the upper surface of the substrate and the recess; and etching the dielectric layer material to retain at least the dielectric layer material on the side wall of the recess near the active area.

[0008] In some embodiments, etching the dielectric layer material includes: using the upper surface of the substrate as a stop layer, dry etching the dielectric layer material so that the upper surface of the first dielectric layer on the side wall close to the active area is flush with the upper surface of the substrate.

[0009] In some embodiments, the upper surface of the sacrificial layer is flush with the top surface of the step of the shallow trench isolation structure.

[0010] In some embodiments, the sacrificial layer is a metal silicide layer.

[0011] In some embodiments, forming a sacrificial layer on the substrate includes: sputtering metal on an upper surface of the substrate, and the metal reacts with the upper surface of the substrate to form the sacrificial layer.

[0012] In some embodiments, the material of the metal silicide layer is one or more of NiSi, TiSi2, CoSi2 or PtSi2.

[0013] In some embodiments, the first dielectric layer and the second dielectric layer are made of the same dielectric layer material or different dielectric layer materials; the dielectric layer materials used by the first dielectric layer and the second dielectric layer include one or more of SiO2, Si3N4 and SiON.

[0014] In some embodiments, the preparation method further includes: preparing a well region, a source / drain region and a gate structure in the active region of the substrate to form a transistor.

[0015] In a second aspect, the present application provides a semiconductor structure, which is prepared using the method for preparing a semiconductor structure as described in any embodiment of the first aspect.

[0016] Compared with the prior art, the unexpected technical effect of the present application is that it can avoid the formation of a depression at the junction of the shallow trench isolation structure and the active area without adding a mask, so that the surface of the active area is flat, and parasitic MOS cannot be formed on both sides of the polysilicon, thereby achieving the effect of reducing the INWE effect.

[0017] In the embodiment of the present application, a first dielectric layer is first formed on the sidewall of the depression at the junction of the shallow trench isolation structure and the active area of ​​the substrate close to the active area, and the first dielectric layer is used as a barrier layer, and then a sacrificial layer is formed on the upper surface of the substrate. By adopting the barrier layer plus sacrificial layer method, when grinding with the sacrificial layer as the grinding stop layer and then removing the sacrificial layer, it is possible to avoid the formation of a depression at the junction of the shallow trench isolation structure and the active area, thereby achieving a flat surface of the active area. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present application will become easy to understand. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0019] Figure 1A-1E A schematic diagram of a semiconductor cross-sectional structure using a known method of growing a protective layer on the top of an active region alone is shown;

[0020] Figure 2 An exemplary flowchart of a method for preparing a semiconductor structure according to an embodiment of the present application is shown;

[0021] Figure 3A A schematic cross-sectional structure diagram of a substrate having a shallow trench isolation structure and a recess according to an embodiment of the present application is shown;

[0022] Figure 3B A schematic diagram of a semiconductor cross-sectional structure of a deposited dielectric layer material according to an embodiment of the present application is shown;

[0023] Figure 3C A schematic diagram of a semiconductor cross-sectional structure of an etched dielectric layer material according to an embodiment of the present application is shown;

[0024] Figure 3D A schematic diagram of a semiconductor cross-sectional structure in which a sacrificial layer is formed on the upper surface of a substrate in an embodiment of the present application is shown;

[0025] Figure 3E A schematic diagram of a semiconductor cross-sectional structure for forming a second dielectric layer according to an embodiment of the present application is shown;

[0026] Figure 3FA schematic diagram of a semiconductor cross-sectional structure of a second dielectric layer polished in an embodiment of the present application is shown;

[0027] Figure 3G A schematic diagram of a semiconductor cross-sectional structure with a sacrificial layer removed according to an embodiment of the present application is shown;

[0028] Figure 3H A schematic diagram of a semiconductor cross-sectional structure of a transistor fabricated in an active region according to an embodiment of the present application is shown.

[0029] Figure 1A-1E Explanation of the reference numerals: 110, shallow trench isolation structure; 111, recess; 120, active area; 130, protection layer; 140, oxide layer; 150, polysilicon layer.

[0030] Figure 3A-3H Explanation of the reference numerals: 310, substrate; 311, active area; 320, shallow trench isolation structure; 330, recess; 340, dielectric layer material; 341, first dielectric layer; 350, sacrificial layer; 360, second dielectric layer; 370, well region; 380, gate structure; 381, gate dielectric layer; 382, ​​gate layer; 390, source and drain region; 391, source region; 392, drain region. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0032] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present application indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0033] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in this application specification and claims, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to include plural forms. It should also be further understood that the term "and / or" used in this application specification and claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0034] It should also be understood that, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "on," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. When an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0035] The specific implementation of the present application is described in detail below with reference to the accompanying drawings.

[0036] Most of the known technologies for improving divot require adding a mask layer to process different areas separately during etching, thereby improving divot. However, this method of using a mask increases the complexity of the process. It is also known that there is a technology that does not use a mask, which uses a protective layer grown on the top of the active area alone, and fills a substance at the junction of the active area and the shallow trench isolation structure to improve the concavity at the junction of the shallow trench isolation structure and the active area. However, the implementation effect of this solution is poor.

[0037] Figure 1A-1E A schematic diagram of a semiconductor cross-sectional structure using a known method of growing a protective layer alone on the top of an active region is shown.

[0038] like Figure 1A As shown, a shallow trench isolation structure (STI) 110 separates the silicon substrate into a plurality of active areas (AA) 120, and there is a divot 111 between the shallow trench isolation structure 110 and the active area 120. The known technology adopts a solution of growing a protective layer 130 on silicon alone. As can be seen from the figure, since there is also exposed silicon on the sidewall of the divot 111 close to the active area 120, the above-mentioned protective layer 130 will not only grow on the top of the active area 120, but also grow at the junction of the active area 120 and the shallow trench isolation structure 110, that is, it will fill part of the divot. Among them, the aforementioned protective layer 130 is usually made of known materials such as silicon dioxide (SiO2) and silicon nitride (Si3N4).

[0039] Afterwards, if Figure 1B As shown, the conventional technology uses chemical vapor deposition (CVD) to fill the oxide layer 140 to the junction between the shallow trench isolation structure 110 and the active area 120 .

[0040] Then, if Figure 1CAs shown, chemical mechanical polishing is used to process and stop on the protective layer 130. Figure 1A A filling oxide layer 140 will remain in the recess.

[0041] Then, if Figure 1D As shown, wet etching is used to remove the protective layer 130. It can be seen that with the removal of the protective layer 130, the protective layer 130 previously grown in the recess 111 is also removed, resulting in the recess formed at the junction of the shallow trench isolation structure 110 and the active area 120 to appear again, and the active area cannot be flattened.

[0042] Finally, if Figure 1E As shown, a polysilicon layer 150 is deposited on the active area 120. Since the depression still exists, the deposition of the polysilicon layer 150 will not only form a MOS transistor above the active area 120, but also form a parasitic MOS transistor at the junction of the shallow trench isolation structure 110 and the active area 120. Moreover, as the device develops, the gate width continues to decrease, and the INWE effect will become more and more serious.

[0043] In view of this, the embodiment of the present application provides a method for preparing a semiconductor structure, which first forms a first dielectric layer on the side wall of the depression near the active area at least at the junction of the shallow trench isolation structure and the active area of ​​the substrate, uses the first dielectric layer as a barrier layer, and then forms a sacrificial layer on the upper surface of the substrate. Then, the sacrificial layer is used as a grinding stop layer to grind the second dielectric layer covering the shallow trench isolation structure, the first dielectric layer and the sacrificial layer, so as to avoid the formation of a depression at the junction of the shallow trench isolation structure and the active area, so that the surface of the active area is flat, so as to achieve the effect of reducing the INWE effect.

[0044] Figure 2 An exemplary flowchart of a method 200 for preparing a semiconductor structure according to an embodiment of the present application is shown.

[0045] like Figure 2 As shown, in step S210, a substrate is provided, wherein a shallow trench isolation structure is provided in the substrate, and a depression is formed at the junction of the shallow trench isolation structure and the active area of ​​the substrate. Next, in step S220, a first dielectric layer is formed at least on the side wall of the depression close to the active area. In step S230, a sacrificial layer is formed on the substrate, and the sacrificial layer covers the upper surface of the substrate. Then, in step S240, a second dielectric layer is formed, and the second dielectric layer covers the shallow trench isolation structure, the first dielectric layer and the sacrificial layer. In step S250, the second dielectric layer is ground and stopped at the sacrificial layer. In step S260, the sacrificial layer is removed.

[0046] based on Figure 2 The preparation method of the semiconductor structure is as follows: Figure 3A-3HThe schematic diagram of the semiconductor cross-sectional structure is shown, and an exemplary process flow of a semiconductor structure preparation method using some embodiments of the present application is described in detail.

[0047] Figure 3A A schematic cross-sectional structure diagram of a substrate having a shallow trench isolation structure and a recess according to an embodiment of the present application is shown.

[0048] like Figure 3A As shown, a substrate 310 is provided, and a shallow trench isolation structure 320 is provided in the substrate 310 . A recess 330 is formed at the junction of the shallow trench isolation structure 320 and the active area 311 of the substrate 310 .

[0049] In one embodiment of the present application, the material of the substrate 310 is a material containing Si element, and specifically can be at least one of the following materials: Si, SiGe, SiC, SiGeC or other compound semiconductors containing Si element. The substrate 310 can be a semiconductor single-layer structure or a multi-layer structure composed of these materials. The substrate 310 can also be silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), etc.

[0050] In one embodiment of the present application, the dielectric material filled in the shallow trench isolation structure 320 can be any suitable dielectric material known in the art, for example, it can be a combination of one or more of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), fluorosilicate glass, undoped silicate glass (USG) or tetraethyl orthosilicate, and this embodiment is not limited here.

[0051] Specifically, the shallow trench isolation structure 320 can be made by various known processes, and the embodiments of the present application are not limited in this respect. For example, a buffer oxide layer (oxide) is first formed on the substrate, for example, a silicon dioxide (SiO2) layer, and a nitride layer (nitride) is formed on the buffer oxide layer, for example, a silicon nitride (Si3N4) layer. Then, the buffer oxide layer, the nitride layer and the substrate are etched to form a shallow trench. Next, a dielectric material is filled in the shallow trench, and a top surface chemical mechanical polishing (CMP) is further performed to form a shallow trench isolation structure 320. After the shallow trench isolation structure 320 is formed, the buffer oxide layer and the nitride layer are removed. In the above process of forming the shallow trench isolation structure 320, the chemical mechanical polishing (CMP), the removal of the buffer oxide layer and the nitride layer and other steps will cause uneven material removal or excessive removal, thereby forming a depression at the junction of the shallow trench isolation structure 320 and the active area 311 of the substrate 310.

[0052] In one embodiment of the present application, the substrate 310 may also undergo some other preparation processes or manufacturing processes, and may also have other semiconductor structures thereon, and the embodiment of the present application is not limited in this regard.

[0053] Next, a first dielectric layer needs to be formed at least on the sidewalls of the recess near the active region to prevent a sacrificial layer 350 from being subsequently grown on the sidewalls of the recess.

[0054] Figure 3B A schematic diagram of a semiconductor cross-sectional structure of a deposited dielectric layer material according to an embodiment of the present application is shown.

[0055] like Figure 3B As shown, a dielectric layer material 340 is then deposited on the substrate 310. Specifically, the dielectric layer material 340 at least covers the upper surface of the substrate 310 and covers Figure 3A The depression in the .

[0056] Specifically, the thickness of the dielectric layer material 340 can be selected according to the thickness requirements of different types of devices for the dielectric layer, actual needs, and the thickness requirements or restrictions of the dielectric layer in different production processes.

[0057] Specifically, the dielectric layer material 340 may be formed by processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), chemical assisted deposition (CAD), and atomic layer deposition (ALD).

[0058] Figure 3C A schematic diagram of a semiconductor cross-sectional structure of an etched dielectric layer material according to an embodiment of the present application is shown.

[0059] like Figure 3C As shown, the dielectric layer material 340 is etched to at least retain the dielectric layer material 340 on the sidewalls of the recess 330 close to the active region, thereby forming a first dielectric layer 341 on the sidewalls of the recess 330 close to the active region.

[0060] Specifically, in the process of etching the dielectric layer material 340 and retaining the dielectric layer material 340 on the sidewalls of the recess 330 near the active area, various known processes may be used, and the embodiments of the present application are not limited in this regard. For example, a photoresist layer is formed on the dielectric layer material 340, and then the photoresist layer is exposed and developed to form a patterned photoresist layer, wherein the patterned photoresist layer only covers the sidewalls of the recess 330 near the active area. Then, the dielectric layer material 340 is etched using the patterned photoresist layer as a mask, and after the etching is completed, the dielectric layer material 340 on the sidewalls of the recess 330 near the active area is retained. And after the etching is completed, the patterned photoresist layer is removed.

[0061] In some embodiments of the present application, during the process of etching the dielectric layer material 340, all the dielectric layer material 340 in the recess 330 may be retained, but at least the dielectric layer material 340 on the side wall of the recess 330 close to the active area must be retained, so as to cover the exposed silicon in the recess and prevent the sacrificial layer 350 from growing in the recess in subsequent processes.

[0062] In one embodiment of the present application, the dielectric layer material 340 is etched by dry etching process, and during the etching process, the upper surface of the substrate 310 is used as a stop layer, so that the upper surface of the dielectric layer material 340 on the side wall close to the active area is flush with the upper surface of the substrate 310. In other words, the upper surface of the first dielectric layer 341 is flush with the upper surface of the substrate 310.

[0063] In one embodiment of the present application, the dielectric layer material used for the first dielectric layer 341 may be one or more of SiO 2 , Si 3 N 4 and SiON.

[0064] In the embodiment of the present application, by forming the first dielectric layer 341 at least on the sidewall of the recess 330 close to the active area, the first dielectric layer 341 can be used as a barrier layer for the subsequently deposited sacrificial layer 350, thereby preventing the subsequently deposited sacrificial layer 350 from growing at the interface between the active area 311 of the substrate 310 and the shallow trench isolation structure 320. Thus, after the sacrificial layer 350 is finally removed, the recess filled at the interface between the active area 311 of the substrate 310 and the shallow trench isolation structure 320 is prevented from reappearing.

[0065] Figure 3D A schematic diagram of a semiconductor cross-sectional structure in which a sacrificial layer is formed on the upper surface of a substrate according to an embodiment of the present application is shown.

[0066] like Figure 3D As shown, a sacrificial layer 350 is formed on the substrate 310, so that the sacrificial layer 350 covers the upper surface of the substrate 310. Specifically, the sacrificial layer 350 can be a metal silicide layer. Specifically, the sacrificial layer 350 is formed by sputtering a metal on the upper surface of the substrate 310, and the metal reacts with the upper surface of the substrate.

[0067] In the embodiment of the present application, the material of the metal silicide layer can be one or more of NiSi, TiSi2, CoSi2 or PtSi2. Since the materials of the metal silicide layer listed above can react with the substrate 310 containing Si elements, but will not react with the contacting first dielectric layer 341, they can be well aligned with the active area 311 of the substrate 310.

[0068] In the embodiment of the present application, during the formation of the sacrificial layer 350, the thickness of the sacrificial layer 350 to be formed is obtained based on the height between the top surface of the step of the shallow trench isolation structure 320 and the upper surface of the substrate 310. That is, the thickness of the sacrificial layer 350 to be formed is the height between the top surface of the step of the shallow trench isolation structure 320 and the upper surface of the substrate 310, so that the upper surface of the obtained sacrificial layer 350 is flush with the top surface of the step of the shallow trench isolation structure 320.

[0069] After the thickness of the sacrificial layer 350 to be formed is obtained, the process parameters in the process of metal sputtering on the upper surface of the substrate can be controlled to obtain the sacrificial layer 350 of the desired thickness. For example, by controlling the atomic percentage of the metal element, the gas atmosphere flow rate used during sputtering, the electric field power during sputtering, etc., the process of metal sputtering on the upper surface of the substrate can be accurately controlled to obtain the sacrificial layer 350 of the desired thickness.

[0070] By making the upper surface of the sacrificial layer 350 flush with the top surface of the step of the shallow trench isolation structure 320, in the process of adjusting the recess formed at the junction of the shallow trench isolation structure and the active area, it is possible to avoid changing the step height of the shallow trench isolation structure 320 to affect the isolation effect of the semiconductor structure finally formed. Specifically, the step height of the shallow trench isolation structure 320 is the height between the top surface of the shallow trench isolation structure 320 and the upper surface of the substrate 310.

[0071] Figure 3E A schematic diagram of a semiconductor cross-sectional structure for forming a second dielectric layer according to an embodiment of the present application is shown.

[0072] like Figure 3E As shown, a second dielectric layer 360 is formed to cover the shallow trench isolation structure 320 , the first dielectric layer 341 and the sacrificial layer 350 .

[0073] In one embodiment of the present application, a chemical vapor deposition (“CVD”) process is used to form the second dielectric layer 360. Specifically, the thickness of the second dielectric layer 360 can be selected according to the thickness requirements of the dielectric layer for different types of devices, actual needs, and the thickness requirements or restrictions of the dielectric layer for different production processes. The desired thickness can be obtained by controlling the process parameters of the chemical vapor deposition process. For example, by controlling the deposition time, adjusting the source gas flow rate, adjusting the reaction temperature, the reactant concentration, etc., the chemical vapor deposition process can be accurately controlled to obtain the second dielectric layer 360 of the desired thickness.

[0074] In the embodiment of the present application, the second dielectric layer 360 and the first dielectric layer 341 may be made of the same dielectric layer material or different dielectric layer materials. The dielectric layer material used for the second dielectric layer 360 may be one or more of SiO2, Si3N4 and SiON.

[0075] Figure 3F A schematic diagram of the semiconductor cross-sectional structure of the polished second dielectric layer according to an embodiment of the present application is shown.

[0076] like Figure 3F As shown, the aforementioned second dielectric layer 360 is ground and stopped at the sacrificial layer 350. Specifically, the sacrificial layer 350 is used as a grinding stop layer for the second dielectric layer 360 to perform a chemical mechanical grinding process. During the mechanical grinding process, if it is detected that the upper surface of the sacrificial layer 350 is exposed, it means that the second dielectric layer 360 located on the upper surface of the sacrificial layer 350 and the upper surface of the shallow trench isolation structure 320 has been basically ground and removed. At the same time, it can be understood that after the mechanical grinding process, the step top surface of the shallow trench isolation structure 320 is kept flush with the upper surface of the sacrificial layer 350.

[0077] By keeping the top surface of the step of the shallow trench isolation structure 320 flush with the upper surface of the sacrificial layer 350 , the step height of the shallow trench isolation structure 320 does not change, thereby not affecting the isolation effect of the finally formed semiconductor structure.

[0078] Figure 3G A schematic diagram of a semiconductor cross-sectional structure with a sacrificial layer removed according to an embodiment of the present application is shown.

[0079] like Figure 3G As shown, after the second dielectric layer 360 is polished, the sacrificial layer 350 is removed.

[0080] In the embodiment of the present application, the sacrificial layer 350 can be removed by a wet etching process. The etching rate and other parameters can be selected according to actual needs and the material used for the sacrificial layer 350. Figure 3G It can be seen that after removing the sacrificial layer 350 , the recess between the shallow trench isolation structure and the active area is still filled with the previous dielectric layer, thereby removing the recess and keeping the surface of the active area flat.

[0081] In one embodiment of the present application, after removing the sacrificial layer 350 , a well region, a source / drain region, and a gate structure are prepared in the active region of the substrate 310 to form a transistor.

[0082] Figure 3H A schematic diagram of a semiconductor cross-sectional structure of a transistor fabricated in an active region according to an embodiment of the present application is shown.

[0083] like Figure 3HAs shown, after removing the aforementioned sacrificial layer 350 , a well region 370 , a gate structure 380 and a source / drain region 390 are sequentially prepared in the active region of the substrate 310 to form a transistor.

[0084] In the embodiment of the present application, ion implantation is performed in several active regions separated by the shallow trench isolation structure 320, so as to form a well region in each active region. The conductivity type of the ions implanted in each active region may be the same or different.

[0085] Specifically, when the conductivity type of the ions injected into each active region is the same, the shallow trench isolation structure 320 is shielded by photoresist, and ions of the same conductivity type are injected into each active region through an ion implantation process to form a well region. After the well region is formed, the photoresist covering the shallow trench isolation structure is removed. The conductivity type of the ions may be N-type or P-type.

[0086] Specifically, when the conductivity types of the ions injected into each active area are different, first, the shallow trench isolation structure 320 and the active area that is not currently undergoing ion injection are shielded by photoresist, and ions of the first conductivity type are injected into the active area that is currently undergoing ion injection through the ion injection process. Then, the shallow trench isolation structure 320 and the active area that has been injected with ions of the first conductivity type are shielded by photoresist, and ions of the second conductivity type are injected into the active area that has not yet been injected with ions through the ion injection process. Thus, a well region is formed. In one embodiment, the first conductivity type may be N-type, and the second conductivity type may be P-type. In other embodiments, the first conductivity type may also be P-type, and the second conductivity type may be N-type.

[0087] In the embodiment of the present application, before the aforementioned ion implantation, an oxide layer may be first deposited on the area where the ion implantation is not performed, and then covered with a photoresist. The active area is protected by the oxide layer. After the ion implantation, in order to prevent the ion implantation process from damaging the oxide layer and affecting the electronic isolation effect, the photoresist and oxide layer are removed after the well area is formed.

[0088] After the well region is prepared, a gate structure 380 is formed in the well region. Specifically, the gate structure 380 includes a gate dielectric layer 381 and a gate layer 382. The gate dielectric layer 381 and the gate layer 382 are sequentially formed on the well region, and a photoresist is coated on the gate region on the gate layer 382. After development and etching, the gate dielectric layer 381 and the gate layer 382 outside the target position are removed, thereby obtaining the gate structure 380. Among them, the material used for the gate dielectric layer 381 can be SiO2, and the material used for the gate layer 382 can be polysilicon.

[0089] Specifically, in the process of forming the gate dielectric layer 381 and the gate layer 382, ​​since the first dielectric layer 341 is formed at the junction of the shallow trench isolation structure 320 and the active area, the gate layer 382 will not be deposited at the junction of the shallow trench isolation structure 320 and the active area. Therefore, the formation of a parasitic MOS tube at the junction of the shallow trench isolation structure 320 and the active area is avoided.

[0090] After forming the gate structure 380, ion implantation is performed again in the well regions on both sides of the gate structure 380 to form source and drain regions 390. The source and drain regions 390 include a source region 391 and a drain region 392. Specifically, the conductivity type of the implanted ions during the second ion implantation is different from the conductivity type of the implanted ions in the corresponding well regions.

[0091] In summary, compared with the prior art, the unexpected technical effect of the present application is that it can avoid the formation of a depression at the junction of the shallow trench isolation structure and the active area without adding a mask, so that the surface of the active area is smooth, thereby achieving the effect of reducing INWE.

[0092] In the embodiment of the present application, a first dielectric layer is first formed on the sidewall of the depression at the junction of the shallow trench isolation structure and the active area of ​​the substrate close to the active area, and the first dielectric layer is used as a barrier layer, and then a sacrificial layer is formed on the upper surface of the substrate. By adopting the barrier layer plus sacrificial layer method, when grinding with the sacrificial layer as the grinding stop layer and then removing the sacrificial layer, it is possible to avoid the formation of a depression at the junction of the shallow trench isolation structure and the active area, thereby achieving a flat surface of the active area.

[0093] The embodiment of the present application also provides a semiconductor structure, which can be prepared by the method 200 for preparing the semiconductor structure provided in the embodiment of the present application. After obtaining the corresponding structure, a well region, a gate structure and a source / drain region can be prepared in sequence on the basis of the structure to obtain a further semiconductor structure. The specific structure of the semiconductor structure can refer to the description of the process flow and the cross-sectional view of the corresponding semiconductor structure in combination with the accompanying drawings, which will not be repeated here.

[0094] Although multiple embodiments of the present application have been shown and described herein, it is obvious to those skilled in the art that such embodiments are provided only by way of example. Those skilled in the art can think of many changes, modifications and alternatives without departing from the thought and spirit of the present application. It should be understood that in the process of practicing the present application, various alternatives to the embodiments of the present application described herein can be adopted. The attached claims are intended to limit the scope of protection of the present application, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a shallow trench isolation structure, and a depression is formed at the junction of the shallow trench isolation structure and the active area of ​​the substrate; Depositing a dielectric layer material on the substrate, wherein the dielectric layer material covers the upper surface of the substrate and the recess; as well as Using the upper surface of the substrate as a stop layer, dry-etching the dielectric layer material to form a first dielectric layer on the sidewall of the recess near the active area, and making the upper surface of the first dielectric layer on the sidewall near the active area flush with the upper surface of the substrate; forming a sacrificial layer on the substrate, the sacrificial layer covering the upper surface of the substrate; forming a second dielectric layer, wherein the second dielectric layer covers the shallow trench isolation structure, the first dielectric layer and the sacrificial layer; Grinding the second dielectric layer, stopping at the sacrificial layer; as well as The sacrificial layer is removed.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The upper surface of the sacrificial layer is flush with the top surface of the step of the shallow trench isolation structure.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The sacrificial layer is a metal silicide layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: Forming a sacrificial layer on the substrate comprises: The metal is sputtered on the upper surface of the substrate, and the metal reacts with the upper surface of the substrate to form the sacrificial layer.

5. The method for preparing a semiconductor structure according to claim 3 or 4, characterized in that: The material of the metal silicide layer is one or more of NiSi, TiSi2, CoSi2 or PtSi2.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first dielectric layer and the second dielectric layer are made of the same dielectric layer material or different dielectric layer materials; the dielectric layer materials used by the first dielectric layer and the second dielectric layer include one or more of SiO2, Si3N4 and SiON.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: Also includes: A well region, a source / drain region and a gate structure are prepared in the active region of the substrate to form a transistor.

8. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 7.

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