A double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance

Abstract

The present invention relates to a double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance, comprising: a lower DBC substrate and an upper DBC substrate; the lower DBC substrate comprises a lower AIN substrate and a lower metal plate; the upper DBC substrate comprises an upper AIN substrate and an upper metal plate; the lower metal plate and the upper metal plate both comprise: a DC+ terminal metal layer, a DC-terminal metal layer, a plurality of AC terminal metal layers and a plurality of driving metal layers. The present invention connects the plurality of AC terminal metal layers in the upper metal plate through a copper bridge to reduce the area of ​​the AC terminal metal layer, thereby reducing the parasitic capacitance of the power module. And by arranging the DC+ terminal metal layer and the DC-terminal metal layer relatively, the mutual inductance of the current is canceled to reduce the parasitic inductance inside the module, thereby achieving both low parasitic capacitance and low parasitic inductance.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power modules, and in particular relates to a double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance. Background Art

[0002] As a wide bandgap semiconductor device, silicon carbide devices have smaller parasitic capacitance and faster switching speed. The parasitic inductance problem is a key challenge for silicon carbide modules. Parasitic capacitance will cause a large displacement current, increase the switching loss of the power module, and the parasitic capacitance will also couple noise to the DC+, DC- DC bus and gate drive circuit, increasing electromagnetic interference. In addition, faster switching speeds will also cause larger voltage overshoots due to parasitic inductance, increase the power consumption of the power module, and reduce its reliability.

[0003] In order to reduce the influence of parasitic capacitance of power modules, the existing technology reduces parasitic capacitance by optimizing the packaging structure. Although optimizing the packaging structure can reduce parasitic capacitance, it will also bring the influence of parasitic inductance. Parasitic inductance will cause voltage overshoot and oscillation, further increasing switching loss and electromagnetic interference.

[0004] Therefore, how to reduce the impact of parasitic inductance while reducing parasitic capacitance remains a key challenge that needs to be solved urgently. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance, comprising: a lower DBC substrate and an upper DBC substrate;

[0007] The lower DBC substrate includes a lower AIN substrate and a lower metal plate located on the surface of the lower AIN substrate; the upper DBC substrate includes an upper AIN substrate and an upper metal plate located on the surface of the upper AIN substrate;

[0008] The lower metal plate and the upper metal plate have the same structure; the lower metal plate and the upper metal plate both include: a DC+ terminal metal layer, a DC- terminal metal layer, a plurality of AC terminal metal layers and a plurality of driving metal layers;

[0009] The DC+ terminal metal layer is provided with a DC+ terminal and a silicon carbide chip; the DC- terminal metal layer is provided with a DC- terminal; the multiple AC terminal metal layers are provided with AC terminals and silicon carbide chips, and the multiple AC terminal metal layers in the upper metal plate are connected by copper bridges; the multiple drive metal layers are provided with drive terminals;

[0010] The DC+ terminal metal layer in the lower metal plate and the DC- terminal metal layer in the upper metal plate are arranged opposite to each other, and the DC- terminal metal layer in the lower metal plate and the DC+ terminal metal layer in the upper metal plate are arranged opposite to each other; the silicon carbide chip in the lower metal plate is connected to the AC terminal metal layer in the upper metal plate through molybdenum compound; the silicon carbide chip in the upper metal plate is connected to the AC terminal metal layer in the lower metal plate through molybdenum compound.

[0011] In one achievable manner, the DC+ terminal metal layer in the lower metal plate includes a first DC+ terminal metal layer;

[0012] The DC-terminal metal layer in the lower metal plate includes a first DC-terminal metal layer;

[0013] The plurality of AC terminal metal layers in the lower metal plate include: a first AC terminal metal layer and a second AC terminal metal layer;

[0014] The first DC+ terminal metal layer and the first DC- terminal metal layer are arranged on the first central axis of the lower metal plate;

[0015] The first AC terminal metal layer and the second AC terminal metal layer are respectively located on both sides of the first DC-terminal metal layer, and the first AC terminal metal layer and the second AC terminal metal layer are symmetrical about a first central axis of the lower metal plate.

[0016] In an achievable manner, the first DC+ terminal metal layer includes a first rectangular portion and a second rectangular portion; wherein the first rectangular portion is arranged perpendicular to the first central axis of the lower metal plate, the second rectangular portion is vertically connected to the middle of one side of the first rectangular portion, and the axis of the second rectangular portion coincides with the first central axis of the lower metal plate; the first lower tube silicon carbide chip and the second lower tube silicon carbide chip are respectively arranged at both ends of the first rectangular portion; the first DC+ terminal is arranged at one end of the second rectangular portion away from the first rectangular portion;

[0017] The first DC-terminal metal layer, the first AC terminal metal layer and the second AC terminal metal layer are all rectangular in shape;

[0018] The first DC-terminal metal layer is arranged on a side of the first rectangular portion away from the second rectangular portion, and its axis coincides with the first central axis of the lower metal plate, and a first DC-terminal is arranged on one end of the first DC-terminal metal layer away from the first rectangular portion;

[0019] The first AC terminal metal layer is arranged on one side of the first DC-terminal metal layer, a first AC terminal is arranged at one end of the first AC terminal metal layer away from the first DC-terminal metal layer, and a third lower tube silicon carbide chip is arranged on a surface of the first AC terminal metal layer;

[0020] The second AC terminal metal layer is arranged on the other side of the first DC-terminal metal layer and is symmetrical to the first AC terminal metal layer. A second AC terminal is arranged at one end of the second AC terminal metal layer away from the first DC-terminal metal layer, and a fourth lower tube silicon carbide chip is arranged on the surface of the second AC terminal metal layer.

[0021] In one achievable manner, the DC+ terminal metal layer in the upper metal plate includes a second DC+ terminal metal layer;

[0022] The second DC+ terminal metal layer includes a third rectangular portion and a fourth rectangular portion; wherein the third rectangular portion is arranged perpendicular to the first central axis of the upper metal plate, the fourth rectangular portion is vertically connected to the middle of one side of the third rectangular portion, and the axis of the fourth rectangular portion coincides with the first central axis of the upper metal plate; the first upper tube silicon carbide chip and the second upper tube silicon carbide chip are arranged at two ends of the third rectangular portion respectively; the second DC+ terminal is arranged at one end of the fourth rectangular portion away from the third rectangular portion;

[0023] The DC-terminal metal layer in the upper metal plate includes a second DC-terminal metal layer;

[0024] The second DC-terminal metal layer is arranged on a side of the third rectangular portion away from the fourth rectangular portion, and its axis coincides with the first central axis of the upper metal plate, and a second DC-terminal is arranged on one end of the second DC-terminal metal layer away from the third rectangular portion;

[0025] The plurality of AC terminal metal layers in the upper metal plate include: a third AC terminal metal layer and a fourth AC terminal metal layer;

[0026] The third AC terminal metal layer is arranged on one side of the second DC-terminal metal layer, a third AC terminal is arranged at one end of the third AC terminal metal layer away from the second DC-terminal metal layer, and a third upper tube silicon carbide chip is arranged on the surface of the third AC terminal metal layer;

[0027] The fourth AC terminal metal layer is arranged on the other side of the second DC-terminal metal layer and is symmetrical to the third AC terminal metal layer. A fourth AC terminal is arranged at one end of the fourth AC terminal metal layer away from the second DC-terminal metal layer, and a fourth upper tube silicon carbide chip is arranged on the surface of the fourth AC terminal metal layer.

[0028] In an achievable manner, the source electrode of the first lower tube silicon carbide chip is connected to the third AC terminal metal layer through the first molybdenum compound, and the drain electrode is fixedly connected to the first DC+ terminal metal layer;

[0029] The second lower tube silicon carbide chip has a source electrode connected to the fourth AC terminal metal layer through a second molybdenum compound, and a drain electrode fixedly connected to the first DC+ terminal metal layer;

[0030] The third lower tube silicon carbide chip has a source electrode connected to the first DC-terminal metal layer through a first bonding wire, and a drain electrode fixedly connected to the first AC terminal metal layer;

[0031] The fourth lower tube silicon carbide chip has a source electrode connected to the first DC-terminal metal layer through a second bonding wire, and a drain electrode fixedly connected to the second AC terminal metal layer;

[0032] The first upper tube silicon carbide chip, the source electrode is connected to the first AC terminal metal layer through the third molybdenum compound, and the drain electrode is fixedly connected to the second DC+ terminal metal layer;

[0033] The second upper tube silicon carbide chip, the source electrode is connected to the second AC terminal metal layer through the fourth molybdenum compound, and the drain electrode is fixedly connected to the second DC+ terminal metal layer;

[0034] The third upper tube silicon carbide chip, the source electrode is connected to the second DC-terminal metal layer through a third bonding wire, and the drain electrode is fixedly connected to the third AC terminal metal layer;

[0035] The fourth upper tube silicon carbide chip has a source electrode connected to the second DC-terminal metal layer through a fourth bonding wire, and a drain electrode fixedly connected to the fourth AC terminal metal layer.

[0036] In an implementable manner, one end of the first DC+ terminal metal layer and one end of the second DC+ terminal metal layer are connected via a fifth molybdenum compound, and the other end of the first DC+ terminal metal layer and the other end of the second DC+ terminal metal layer are connected via a sixth molybdenum compound;

[0037] The first AC terminal metal layer and the fourth AC terminal metal layer are connected via a seventh molybdenum compound;

[0038] The second AC terminal metal layer and the third AC terminal metal layer are connected via an eighth molybdenum compound;

[0039] The third AC terminal metal layer and the fourth AC terminal metal layer are connected via a copper bridge;

[0040] The second DC-terminal metal layer and the first DC-terminal metal layer are connected via a ninth molybdenum compound.

[0041] In one feasible manner, the multiple driving metal layers include eight groups of driving metal layers, each group of driving metal layers is arranged corresponding to the silicon carbide chip, wherein four groups of driving metal layers are respectively located at the four corners of the lower metal plate, and the other four groups of driving metal layers are respectively located at the four corners of the upper metal plate; and a group of driving terminals is arranged on each group of driving metal layers.

[0042] In an achievable manner, each group of driving metal layers includes: a source driving metal layer and a gate driving metal layer;

[0043] A source driving terminal is disposed on the surface of the source driving metal layer, and a gate driving terminal is disposed on the surface of the gate driving metal layer.

[0044] In one achievable manner, the one source driving terminal is connected to a source of the silicon carbide chip, and the one gate driving terminal is connected to a gate of the silicon carbide chip.

[0045] In one achievable manner, the lower DBC substrate further includes a lower heat sink;

[0046] The lower heat sink is located on the surface of the lower AIN substrate away from the lower metal plate and is used for mounting a heat sink;

[0047] The upper DBC substrate also includes an upper heat sink;

[0048] The upper heat dissipation plate is located on a surface of the upper AIN substrate away from the upper metal plate and is used for mounting a heat sink.

[0049] Compared with the prior art, the present invention has the following beneficial effects:

[0050] The double-sided heat dissipation power module of the present invention connects multiple AC terminal metal layers in the upper metal plate through copper bridges to reduce the area of ​​the AC terminal metal layer, thereby reducing the parasitic capacitance of the power module. The DC+ terminal metal layer and the DC- terminal metal layer are arranged relative to each other so that the mutual inductance of the current is cancelled to reduce the parasitic inductance inside the module, thereby achieving both low parasitic capacitance and low parasitic inductance. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 1 is a schematic structural diagram of a double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance provided by an embodiment of the present invention;

[0052] Figure 2 is a side view of a double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance provided by an embodiment of the present invention;

[0053] Figure 3 is a top view of a double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance provided by an embodiment of the present invention;

[0054] Figure 4a to Figure 4b is a schematic structural diagram of a lower metal plate provided by an embodiment of the present invention;

[0055] Figure 5a to Figure 5b is a schematic structural diagram of an upper metal plate provided by an embodiment of the present invention;

[0056] Figure 6 is a connection diagram of a DC+ terminal metal layer provided by an embodiment of the present invention;

[0057] Figure 7 is a connection diagram of a DC-terminal metal layer provided by an embodiment of the present invention;

[0058] Figure 8 is a connection diagram of the metal layer of the AC terminal provided by an embodiment of the present invention;

[0059] Fig. 9 is a schematic diagram of a connection method between a lower metal plate and an upper metal plate provided in an embodiment of the present invention;

[0060] Fig.10 It is a schematic diagram of a power circuit of a double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance provided by an embodiment of the present invention.

[0061] Reference numerals:

[0062] 101: lower AIN substrate; 102: lower metal plate; 103: lower heat sink; 201: upper AIN substrate; 202: upper metal plate; 203: upper heat sink; 301: first DC-terminal; 302: second AC terminal; 303: first AC terminal; 304: first DC+terminal; 401-408: lower drive terminal; 501-508: lower bonding wire; 601: second DC+terminal; 602: fourth AC terminal; 603: third AC terminal; 604: second DC-terminal; 701-708: upper drive terminal; 801-808: upper bonding wire; 1A: first molybdenum compound; 2A: second molybdenum compound; 1B: first lower tube silicon carbide chip; 2B: second lower tube silicon carbide chip; 3B: third lower tube silicon carbide chip; 4B: fourth lower tube carbon silicon carbide chip; 1C: first bonding wire; 2C: second bonding wire; 1D: first DC+ terminal metal layer; 2D: first AC terminal metal layer; 3D: second AC terminal metal layer; 4D: first DC-terminal metal layer; 1E: third molybdenum compound; 2E: fourth molybdenum compound; 1F: third upper tube silicon carbide chip; 2F: fourth upper tube silicon carbide chip; 3F: first upper tube silicon carbide chip; 4F: second upper tube silicon carbide chip; 1G: third bonding wire; 2G: fourth bonding wire; 1H: second DC-terminal metal layer; 2H: third AC terminal metal layer; 3H: fourth AC terminal metal layer; 4H: second DC+ terminal metal layer; 1I: fifth molybdenum compound; 2I: sixth molybdenum compound; 3I: seventh molybdenum compound; 4I: eighth molybdenum compound; 5I: copper bridge; 6I: ninth molybdenum compound. DETAILED DESCRIPTION

[0063] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0064] Embodiment 1

[0065] Please combine Figure 1 to Figure 5b , Figure 1 is a schematic structural diagram of a double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance provided by an embodiment of the present invention, Figure 2 is a side view of a double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance provided by an embodiment of the present invention, Figure 3 is a top view of a double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance provided by an embodiment of the present invention, Figure 4a to Figure 4b is a schematic structural diagram of a lower metal plate provided in an embodiment of the present invention, Figure 5a to Figure 5b It is a schematic structural diagram of an upper metal plate provided in an embodiment of the present invention.

[0066] The present embodiment provides a double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance, comprising: a lower DBC substrate and an upper DBC substrate. The lower DBC substrate comprises a lower AIN substrate 101 and a lower metal plate 102 located on the surface of the lower AIN substrate 101, and the upper DBC substrate comprises an upper AIN substrate 201 and an upper metal plate 202 located on the surface of the upper AIN substrate 201. The lower metal plate 102 and the upper metal plate 202 have the same structure. Both the lower metal plate 102 and the upper metal plate 202 include: a DC+ terminal metal layer, a DC-terminal metal layer, a plurality of AC terminal metal layers and a plurality of drive metal layers. Among them, a DC+ terminal and a silicon carbide chip are arranged on the DC+ terminal metal layer, and a DC-terminal is arranged on the DC-terminal metal layer. AC terminals and silicon carbide chips are arranged on the multiple AC terminal metal layers, and the multiple AC terminal metal layers in the upper metal plate 202 are connected by copper bridges 5I. Drive terminals are arranged on the multiple drive metal layers. The DC+ terminal metal layer in the lower metal plate 102 and the DC- terminal metal layer in the upper metal plate 202 are arranged opposite to each other, and the DC- terminal metal layer in the lower metal plate 102 and the DC+ terminal metal layer in the upper metal plate 202 are arranged opposite to each other. The silicon carbide chip in the lower metal plate 102 is connected to the AC terminal metal layer in the upper metal plate 202 through molybdenum, and the silicon carbide chip in the upper metal plate 202 is connected to the AC terminal metal layer in the lower metal plate 102 through molybdenum.

[0067] In this embodiment, the DC+ terminal metal layer in the lower metal plate 102 includes a first DC+ terminal metal layer 1D, and the DC- terminal metal layer in the lower metal plate 102 includes a first DC-terminal metal layer 4D. The multiple AC terminal metal layers in the lower metal plate 102 include: a first AC terminal metal layer 2D and a second AC terminal metal layer 3D. Among them, the first DC+ terminal metal layer 1D and the first DC-terminal metal layer 4D are arranged on the first central axis of the lower metal plate 102. The first AC terminal metal layer 2D and the second AC terminal metal layer 3D are respectively located on both sides of the first DC-terminal metal layer 4D, and the first AC terminal metal layer 2D and the second AC terminal metal layer 3D are symmetrical about the first central axis of the lower metal plate 102.

[0068] In this embodiment, the first DC+ terminal metal layer 1D includes a first rectangular portion and a second rectangular portion; wherein the first rectangular portion is arranged perpendicular to the first central axis of the lower metal plate 102, the second rectangular portion is vertically connected to the middle of one side of the first rectangular portion, and the axis of the second rectangular portion coincides with the first central axis of the lower metal plate 102. The first lower tube silicon carbide chip 1B and the second lower tube silicon carbide chip 2B are arranged at both ends of the first rectangular portion, respectively, and the first DC+ terminal 304 is arranged at one end of the second rectangular portion away from the first rectangular portion. The shapes of the first DC-terminal metal layer 4D, the first AC terminal metal layer 2D, and the second AC terminal metal layer 3D are all rectangular. The first DC-terminal metal layer 4D is arranged on one side of the first rectangular portion away from the second rectangular portion, and the axis of the first DC-terminal metal layer 4D coincides with the first central axis of the lower metal plate 102, and the first DC-terminal 301 is arranged at one end of the first DC-terminal metal layer 4D away from the first rectangular portion. The first AC terminal metal layer 2D is arranged on one side of the first DC-terminal metal layer 4D, the first AC terminal metal layer 2D is provided with a first AC terminal 303 at one end away from the first DC-terminal metal layer 4D, and the third lower tube silicon carbide chip 3B is arranged on the surface of the first AC terminal metal layer 2D. The second AC terminal metal layer 3D is arranged on the other side of the first DC-terminal metal layer 4D and is symmetrical with the first AC terminal metal layer 2D, the second AC terminal metal layer 3D is provided with a second AC terminal 302 at one end away from the first DC-terminal metal layer 4D, and the fourth lower tube silicon carbide chip 4B is arranged on the surface of the second AC terminal metal layer 3D.

[0069] In this embodiment, the DC+ terminal metal layer in the upper metal plate 202 includes a second DC+ terminal metal layer 4H. The second DC+ terminal metal layer 4H includes a third rectangular portion and a fourth rectangular portion, wherein the third rectangular portion is arranged perpendicular to the first central axis of the upper metal plate 202, the fourth rectangular portion is vertically connected to the middle of one side of the third rectangular portion, and the axis of the fourth rectangular portion coincides with the first central axis of the upper metal plate 202. The first upper tube silicon carbide chip 3F and the second upper tube silicon carbide chip 4F are arranged at both ends of the third rectangular portion, respectively, and the second DC+ terminal 601 is arranged at one end of the fourth rectangular portion away from the third rectangular portion. The DC- terminal metal layer in the upper metal plate 202 includes a second DC- terminal metal layer 1H. The second DC- terminal metal layer 1H is arranged on one side of the third rectangular portion away from the fourth rectangular portion, and the axis of the second DC- terminal metal layer 1H coincides with the first central axis of the upper metal plate 202, and the second DC- terminal 604 is arranged at one end of the second DC- terminal metal layer 1H away from the third rectangular portion. The multiple AC terminal metal layers in the upper metal plate 202 include: a third AC terminal metal layer 2H and a fourth AC terminal metal layer 3H. The third AC terminal metal layer 2H is arranged on one side of the second DC-terminal metal layer 1H, and a third AC terminal 603 is arranged at one end of the third AC terminal metal layer 2H away from the second DC-terminal metal layer 1H, and a third upper tube silicon carbide chip 1F is arranged on the surface of the third AC terminal metal layer 2H. The fourth AC terminal metal layer 3H is arranged on the other side of the second DC-terminal metal layer 1H and is symmetrical to the third AC terminal metal layer 2H, and a fourth AC terminal 602 is arranged at one end of the fourth AC terminal metal layer 3H away from the second DC-terminal metal layer 1H, and a fourth upper tube silicon carbide chip 2F is arranged on the surface of the fourth AC terminal metal layer 3H.

[0070] In this embodiment, the source of the first lower tube silicon carbide chip 1B is connected to the third AC terminal metal layer 2H through the first molybdenum compound 1A, and the drain of the first lower tube silicon carbide chip 1B is fixedly connected to the first DC+ terminal metal layer 1D. The source of the second lower tube silicon carbide chip 2B is connected to the fourth AC terminal metal layer 3H through the second molybdenum compound 2A, and the drain of the second lower tube silicon carbide chip 2B is fixedly connected to the first DC+ terminal metal layer 1D. The source of the third lower tube silicon carbide chip 3B is connected to the first DC-terminal metal layer 4D through the first bonding wire 1C, and the drain of the third lower tube silicon carbide chip 3B is fixedly connected to the first AC terminal metal layer 2D. The source of the fourth lower tube silicon carbide chip 4B is connected to the first DC-terminal metal layer 4D through the second bonding wire 2C, and the drain of the fourth lower tube silicon carbide chip 4B is fixedly connected to the second AC terminal metal layer 3D. The source of the first upper tube silicon carbide chip 3F is connected to the first AC terminal metal layer 2D through the third molybdenum compound 1E, and the drain of the first upper tube silicon carbide chip 3F is fixedly connected to the second DC+ terminal metal layer 4H. The source of the second upper tube silicon carbide chip 4F is connected to the second AC terminal metal layer 3D through the fourth molybdenum compound 2E, and the drain of the second upper tube silicon carbide chip 4F is fixedly connected to the second DC+ terminal metal layer 4H. The source of the third upper tube silicon carbide chip 1F is connected to the second DC-terminal metal layer 1H through the third bonding wire 1G, and the drain of the third upper tube silicon carbide chip 1F is fixedly connected to the third AC terminal metal layer 2H. The source of the fourth upper tube silicon carbide chip 2F is connected to the second DC-terminal metal layer 1H through the fourth bonding wire 2G, and the drain of the fourth upper tube silicon carbide chip 2F is fixedly connected to the fourth AC terminal metal layer 3H. The drain of the silicon carbide chip in this embodiment is fixedly connected to the metal layer by welding.

[0071] Please combine Figure 6 to Figure 8 In this embodiment, one end of the first DC+ terminal metal layer 1D and one end of the second DC+ terminal metal layer 4H are connected through the fifth molybdenum compound 1I, and the other end of the first DC+ terminal metal layer 1D and the other end of the second DC+ terminal metal layer 4H are connected through the sixth molybdenum compound 2I. The first AC terminal metal layer 2D and the fourth AC terminal metal layer 3H are connected through the seventh molybdenum compound 3I. The second AC terminal metal layer 3D and the third AC terminal metal layer 2H are connected through the eighth molybdenum compound 4I. The third AC terminal metal layer 2H and the fourth AC terminal metal layer 3H are connected through the copper bridge 5I. The second DC-terminal metal layer 1H and the first DC-terminal metal layer 4D are connected through the ninth molybdenum compound 6I.

[0072] Specifically, the first DC+ terminal 304 is welded on the upper side of one end of the first DC+ terminal metal layer 1D and led out to the lower side, and the second DC+ terminal 601 is welded on the lower side of one end of the second DC+ terminal metal layer 4H and led out to the upper side. The first DC-terminal 301 is welded on the upper side of one end of the first DC-terminal metal layer 4D and led out to the upper side, and the second DC-terminal 604 is welded on the lower side of one end of the second DC-terminal metal layer 1H and led out to the lower side. The first AC terminal 303 and the second AC terminal 302 are welded on the upper side of the first AC terminal metal layer 2D and the second AC terminal metal layer 3D, respectively, and led out from the left and right sides, and the third AC terminal 603 and the fourth AC terminal 602 are welded on the lower side of the third AC terminal metal layer 2H and the fourth AC terminal metal layer 3H, respectively, and led out from the left and right sides.

[0073] Specifically, the first central axis of the lower metal plate 102 is symmetrical and the second central axis of the lower metal plate 102 is perpendicular to each other. The first central axis of the upper metal plate 202 is symmetrical and the second central axis of the upper metal plate 202 is perpendicular to each other. The first rectangular portion and the second rectangular portion form a "T"-shaped first DC+ terminal metal layer 1D, and the third rectangular portion and the fourth rectangular portion form a "T"-shaped second DC+ terminal metal layer 4H. The first DC+ terminal metal layer 1D is located on one side of the second central axis of the lower metal plate 102, and the first DC-terminal metal layer 4D, the first AC terminal metal layer 2D, and the second AC terminal metal layer 3D are all located on the other side of the second central axis of the lower metal plate 102. The first lower tube silicon carbide chip 1B and the second lower tube silicon carbide chip 2B are located at both ends of the first rectangular portion and are arranged close to the second central axis of the lower metal plate 102, and the third lower tube silicon carbide chip 3B and the fourth lower tube silicon carbide chip 4B are respectively arranged on the surfaces of the first AC terminal metal layer 2D and the second AC terminal metal layer 3D away from the second central axis of the lower metal plate 102. The upper metal plate 202 and the lower metal plate 102 have the same structural layout, see Fig. 9, after the upper metal plate 202 is rotated 180°, it is symmetrical with the lower metal plate 102 about the horizontal plane, the first DC+ terminal metal layer 1D and the second DC-terminal metal layer 1H are arranged oppositely, the second DC+ terminal metal layer 4H and the first DC-terminal metal layer 4D are arranged oppositely, and the area of ​​the first AC terminal metal layer 2D and the second AC terminal metal layer 3D is approximately the area of ​​two silicon carbide chips, therefore, the third lower tube silicon carbide chip 3B and the fourth lower tube silicon carbide chip 4B can also accommodate a silicon carbide chip on one side close to the second central axis of the lower metal plate 102, and after the upper metal plate 202 is rotated 180°, the first upper tube silicon carbide chip 3F and the second upper tube silicon carbide chip 4F in the upper metal plate 202 are connected to the first AC terminal metal layer 2D and the second AC terminal metal layer 3D through molybdenum, which can meet the connection requirements and minimize the area of ​​the AC terminal metal layer, effectively reducing the parasitic capacitance, thereby reducing the displacement current, reducing the switching loss of the power module, enhancing the anti-electromagnetic interference capability of the power module, and improving the performance of the power module.

[0074] In this embodiment, the current starts from the DC+ terminal, flows in a "T" shape to the silicon carbide chips on both sides, then flows to another metal plate through the molybdenum compound, and then flows through the silicon carbide chip on the other metal plate and flows back to the DC- terminal in a "T" shape through the bonding wire, and the DC+ terminal and the DC- terminal are arranged crosswise. The power module is centrally symmetrical, wherein the DC+ terminal and the DC- terminal through which the current flows cancel each other out, the adjacent molybdenum compounds cancel each other out, the upper copper metal layer and the lower copper metal layer cancel each other out, and the two copper metal layers on the same layer cancel each other out. For details, please refer to Fig.10 The power module of this embodiment has four symmetrical power loops, wherein the first power loop and the second power loop both start from the first DC+ terminal 304 and end at the second DC-terminal 604. The third power loop and the fourth power loop both start from the second DC+ terminal 601 and end at the first DC-terminal 301.

[0075] Specifically, the first power loop starting from the first DC+ terminal 304 includes: the first DC+ terminal 304, the first DC+ terminal metal layer 1D, the first lower tube silicon carbide chip 1B, the first molybdenum compound 1A, the third AC terminal metal layer 2H, the third upper tube silicon carbide chip 1F, the third bonding wire 1G, the second DC-terminal metal layer 1H, and the second DC-terminal 604.

[0076] The second power loop starting from the first DC+ terminal 304 includes: the first DC+ terminal 304, the first DC+ terminal metal layer 1D, the second lower tube silicon carbide chip 2B, the second molybdenum compound 2A, the fourth AC terminal metal layer 3H, the fourth upper tube silicon carbide chip 2F, the fourth bonding wire 2G, the second DC-terminal metal layer 1H, and the second DC-terminal 604.

[0077] The third power loop starting from the second DC+ terminal 601 includes: the second DC+ terminal 601, the second DC+ terminal metal layer 4H, the first upper tube silicon carbide chip 3F, the third molybdenum compound 1E, the first AC terminal metal layer 2D, the third lower tube silicon carbide chip 3B, the first bonding wire 1C, the first DC-terminal metal layer 4D, and the first DC-terminal 301.

[0078] The fourth power loop starting from the second DC+ terminal 601 includes: a second DC+ terminal 601, a second DC+ terminal metal layer 4H, a second upper tube silicon carbide chip 4F, a fourth molybdenum compound 2E, a second AC terminal metal layer 3D, a fourth lower tube silicon carbide chip 4B, a second bonding wire 2C, a first DC-terminal metal layer 4D, and a first DC-terminal 301.

[0079] Specifically, the first power circuit and the third power circuit are centrally symmetrical, and the second power circuit and the fourth power circuit are centrally symmetrical. On the same metal layer, the current directions of the first power circuit and the third power circuit are opposite, and the current directions of the second power circuit and the fourth power circuit are opposite, thereby realizing the mutual inductance cancellation between the power circuits on the same metal layer. Moreover, the first power circuit and the second power circuit are symmetrical about the horizontal plane, and the third power circuit and the fourth power circuit are symmetrical about the horizontal plane. The current directions of the first power circuit and the second power circuit on the lower metal plate 102 and the upper metal plate 202 are opposite, thereby realizing the mutual inductance cancellation between the two metal plates. The current direction of the first power circuit in the first molybdenum compound 1A is opposite to the current direction of the third power circuit in the third molybdenum compound 1E, and the current direction of the second power circuit in the second molybdenum compound 2A is opposite to the current direction of the fourth power circuit in the fourth molybdenum compound 2E, thereby realizing the inductance cancellation in the vertical direction. The inductance cancellation between the four power circuits effectively reduces the inductance inside the power module, thereby reducing the overshoot voltage and current oscillation of the power module during the opening and closing process.

[0080] In this embodiment, the multiple driving metal layers include eight groups of driving metal layers, each group of driving metal layers is arranged corresponding to the silicon carbide chip, wherein four groups of driving metal layers are respectively located at the four corners of the lower metal plate 102, and the other four groups of driving metal layers are respectively located at the four corners of the upper metal plate 202. A group of driving metal layers is provided with a group of driving terminals. A group of driving metal layers includes: a source driving metal layer and a gate driving metal layer, a source driving terminal is provided on the surface of a source driving metal layer, and a gate driving terminal is provided on the surface of a gate driving metal layer. A source driving terminal is connected to the source of a silicon carbide chip, and a gate driving terminal is connected to the gate of a silicon carbide chip.

[0081] Specifically, please combine Figure 4a to Figure 5b , the four groups of driving terminals in the lower metal plate 102 are lower driving terminals 401 to 408. Exemplarily, the lower driving terminal 401 and the lower driving terminal 402 are a group of driving terminals, one of which is a source driving terminal and the other is a gate driving terminal. The lower driving terminal 401 and the lower driving terminal 402 are connected to the source and gate of the third lower tube silicon carbide chip 3B through the lower bonding wire 501 and the lower bonding wire 502 respectively, the lower driving terminal 403 and the lower driving terminal 404 are connected to the source and gate of the fourth lower tube silicon carbide chip 4B through the lower bonding wire 503 and the lower bonding wire 504 respectively, the lower driving terminal 405 and the lower driving terminal 406 are connected to the source and gate of the second lower tube silicon carbide chip 2B through the lower bonding wire 505 and the lower bonding wire 506 respectively, and the lower driving terminal 407 and the lower driving terminal 408 are connected to the source and gate of the first lower tube silicon carbide chip 1B through the lower bonding wire 507 and the lower bonding wire 508 respectively. The four groups of driving terminals in the upper metal plate 102 are upper driving terminals 701 to 708. For example, the upper driving terminal 701 and the upper driving terminal 702 are a group of driving terminals, one of which is a source driving terminal and the other is a gate driving terminal. The upper driving terminal 701 and the upper driving terminal 702 are connected to the source and gate of the first upper silicon carbide chip 3F through the upper bonding wire 801 and the upper bonding wire 802, respectively. The upper driving terminal 703 and the upper driving terminal 704 are connected to the source and gate of the second upper silicon carbide chip 4F through the upper bonding wire 803 and the upper bonding wire 804, respectively. The upper driving terminal 705 and the upper driving terminal 706 are connected to the source and gate of the fourth upper silicon carbide chip 2F through the upper bonding wire 805 and the upper bonding wire 806, respectively. The upper driving terminal 707 and the upper driving terminal 708 are connected to the source and gate of the third upper silicon carbide chip 1F through the upper bonding wire 807 and the upper bonding wire 808, respectively. In this embodiment, the connection between the silicon carbide chip and the driving terminal is a Kelvin connection. The gate driving terminal, the bonding wire, the silicon carbide chip gate, the silicon carbide chip source, the bonding wire, and the source driving terminal form a driving loop. It should be understood that in this embodiment, there are eight centrosymmetric driving loops.

[0082] Specifically, the power module provided in this embodiment adopts a symmetrical layout with multiple symmetry planes, eight drive circuits are center-symmetrical, and four power circuits are center-symmetrical. Therefore, in this embodiment, the structure of the drive circuit flowing through each silicon carbide chip is the same, the structure of the power circuit flowing through each silicon carbide chip is the same, and each silicon carbide chip has the same parasitic capacitance and parasitic inductance, thereby ensuring the consistency of circuit parameters between internal chips and enhancing the consistency of the switching characteristics of parallel chips.

[0083] In this embodiment, the lower DBC substrate further includes a lower heat sink 103, which is located on the surface of the lower AIN substrate 101 away from the lower metal plate 102 and is used to install a radiator. The upper DBC substrate further includes an upper heat sink 203, which is located on the surface of the upper AIN substrate 201 away from the upper metal plate 202 and is used to install a radiator. Specifically, the radiator is a natural air cooling, forced air cooling or liquid cooling radiator.

[0084] The double-sided heat dissipation power module provided in this embodiment adopts a compact layout design, and connects the third AC terminal metal layer 2H and the fourth AC terminal metal layer 3H through a copper bridge, further reducing the area of ​​the AC terminal metal layer to reduce the parasitic capacitance, thereby reducing the displacement current, reducing the switching loss of the power module, enhancing the anti-electromagnetic interference capability of the power module, and improving the performance of the power module. In addition, through the layout design, this embodiment makes the power loop as short as possible while having multiple power loops that can offset each other, reducing the parasitic inductance of the power module, thereby reducing the overshoot voltage and current oscillation of the power module during the opening and closing process. In addition, the double-sided heat dissipation power module provided in this embodiment adopts a symmetrical structure to ensure that each silicon carbide chip has the same parasitic capacitance and parasitic inductance parameters, thereby ensuring the consistency of circuit parameters between internal chips and enhancing the consistency of the switching characteristics of parallel chips.

[0085] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance, characterized in that: include: a lower DBC substrate and an upper DBC substrate; The lower DBC substrate comprises a lower AIN substrate (101) and a lower metal plate (102) located on the surface of the lower AIN substrate (101); the upper DBC substrate comprises an upper AIN substrate (201) and an upper metal plate (202) located on the surface of the upper AIN substrate (201); The lower metal plate (102) and the upper metal plate (202) have the same structure; the lower metal plate (102) and the upper metal plate (202) both comprise: a DC+ terminal metal layer, a DC- terminal metal layer, a plurality of AC terminal metal layers, and a plurality of driving metal layers; The DC+ terminal metal layer is provided with a DC+ terminal and a silicon carbide chip; the DC- terminal metal layer is provided with a DC- terminal; the multiple AC terminal metal layers are provided with AC terminals and silicon carbide chips, and the multiple AC terminal metal layers in the upper metal plate (202) are connected via copper bridges (5I); the multiple drive metal layers are provided with drive terminals; The DC+ terminal metal layer in the lower metal plate (102) and the DC- terminal metal layer in the upper metal plate (202) are arranged relative to each other, and the DC- terminal metal layer in the lower metal plate (102) and the DC+ terminal metal layer in the upper metal plate (202) are arranged relative to each other; the silicon carbide chip in the lower metal plate (102) is connected to the AC terminal metal layer in the upper metal plate (202) through molybdenum; and the silicon carbide chip in the upper metal plate (202) is connected to the AC terminal metal layer in the lower metal plate (102) through molybdenum; The DC+ terminal metal layer in the lower metal plate (102) includes a first DC+ terminal metal layer (1D); The DC-terminal metal layer in the lower metal plate (102) includes a first DC-terminal metal layer (4D); The multiple AC terminal metal layers in the lower metal plate (102) include: a first AC terminal metal layer (2D) and a second AC terminal metal layer (3D); The first DC+ terminal metal layer (1D) and the first DC- terminal metal layer (4D) are arranged on a first central axis of the lower metal plate (102); The first AC terminal metal layer (2D) and the second AC terminal metal layer (3D) are respectively located on both sides of the first DC-terminal metal layer (4D), and the first AC terminal metal layer (2D) and the second AC terminal metal layer (3D) are symmetrical about a first central axis of the lower metal plate (102).

2. A double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance according to claim 1, characterized in that: The first DC+ terminal metal layer (1D) comprises a first rectangular portion and a second rectangular portion; wherein the first rectangular portion is arranged perpendicular to the first central axis of the lower metal plate (102), the second rectangular portion is vertically connected to the middle of one side of the first rectangular portion, and the axis of the second rectangular portion coincides with the first central axis of the lower metal plate (102); a first lower tube silicon carbide chip (1B) and a second lower tube silicon carbide chip (2B) are arranged at two ends of the first rectangular portion respectively; and a first DC+ terminal (304) is arranged at one end of the second rectangular portion away from the first rectangular portion; The first DC-terminal metal layer (4D), the first AC-terminal metal layer (2D) and the second AC-terminal metal layer (3D) are all rectangular in shape; The first DC-terminal metal layer (4D) is arranged on a side of the first rectangular portion away from the second rectangular portion, and its axis coincides with the first central axis of the lower metal plate (102); a first DC-terminal (301) is arranged on one end of the first DC-terminal metal layer (4D) away from the first rectangular portion; The first AC terminal metal layer (2D) is arranged on one side of the first DC-terminal metal layer (4D), a first AC terminal (303) is arranged at one end of the first AC terminal metal layer (2D) away from the first DC-terminal metal layer (4D), and a third lower tube silicon carbide chip (3B) is arranged on the surface of the first AC terminal metal layer (2D); The second AC terminal metal layer (3D) is arranged on the other side of the first DC-terminal metal layer (4D) and is symmetrical with the first AC terminal metal layer (2D); a second AC terminal (302) is arranged at one end of the second AC terminal metal layer (3D) away from the first DC-terminal metal layer (4D); and a fourth lower tube silicon carbide chip (4B) is arranged on the surface of the second AC terminal metal layer (3D).

3. The double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance according to claim 2, characterized in that: The DC+ terminal metal layer in the upper metal plate (202) includes a second DC+ terminal metal layer (4H); The second DC+ terminal metal layer (4H) comprises a third rectangular portion and a fourth rectangular portion; wherein the third rectangular portion is arranged perpendicular to the first central axis of the upper metal plate (202), the fourth rectangular portion is vertically connected to the middle of one side of the third rectangular portion, and the axis of the fourth rectangular portion coincides with the first central axis of the upper metal plate (202); the first upper tube silicon carbide chip (3F) and the second upper tube silicon carbide chip (4F) are arranged at two ends of the third rectangular portion respectively; the second DC+ terminal (601) is arranged at one end of the fourth rectangular portion away from the third rectangular portion; The DC-terminal metal layer in the upper metal plate (202) includes a second DC-terminal metal layer (1H); The second DC-terminal metal layer (1H) is arranged on a side of the third rectangular portion away from the fourth rectangular portion, and its axis coincides with the first central axis of the upper metal plate (202); a second DC-terminal (604) is arranged on one end of the second DC-terminal metal layer (1H) away from the third rectangular portion; The plurality of AC terminal metal layers in the upper metal plate (202) include: a third AC terminal metal layer (2H) and a fourth AC terminal metal layer (3H); The third AC terminal metal layer (2H) is arranged on one side of the second DC-terminal metal layer (1H), a third AC terminal (603) is arranged at one end of the third AC terminal metal layer (2H) away from the second DC-terminal metal layer (1H), and a third upper tube silicon carbide chip (1F) is arranged on the surface of the third AC terminal metal layer (2H); The fourth AC terminal metal layer (3H) is arranged on the other side of the second DC-terminal metal layer (1H) and is symmetrical to the third AC terminal metal layer (2H); a fourth AC terminal (602) is arranged at one end of the fourth AC terminal metal layer (3H) away from the second DC-terminal metal layer (1H); and a fourth upper tube silicon carbide chip (2F) is arranged on the surface of the fourth AC terminal metal layer (3H).

4. The double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance according to claim 3, characterized in that: The first lower tube silicon carbide chip (1B), the source electrode is connected to the third AC terminal metal layer (2H) through the first molybdenum compound (1A), and the drain electrode is fixedly connected to the first DC+ terminal metal layer (1D); The second lower tube silicon carbide chip (2B), the source electrode is connected to the fourth AC terminal metal layer (3H) through the second molybdenum compound (2A), and the drain electrode is fixedly connected to the first DC+ terminal metal layer (1D); The third lower tube silicon carbide chip (3B) has a source electrode connected to the first DC-terminal metal layer (4D) via a first bonding wire (1C), and a drain electrode fixedly connected to the first AC terminal metal layer (2D); The fourth lower tube silicon carbide chip (4B) has a source electrode connected to the first DC-terminal metal layer (4D) via a second bonding wire (2C), and a drain electrode fixedly connected to the second AC terminal metal layer (3D); The first upper tube silicon carbide chip (3F), the source electrode is connected to the first AC terminal metal layer (2D) through the third molybdenum compound (1E), and the drain electrode is fixedly connected to the second DC+ terminal metal layer (4H); The second upper tube silicon carbide chip (4F), the source electrode is connected to the second AC terminal metal layer (3D) through the fourth molybdenum compound (2E), and the drain electrode is fixedly connected to the second DC+ terminal metal layer (4H); The third upper tube silicon carbide chip (1F), the source electrode is connected to the second DC-terminal metal layer (1H) through a third bonding wire (1G), and the drain electrode is fixedly connected to the third AC terminal metal layer (2H); The fourth upper silicon carbide chip (2F) has a source electrode connected to the second DC-terminal metal layer (1H) via a fourth bonding wire (2G), and a drain electrode fixedly connected to the fourth AC terminal metal layer (3H).

5. The double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance according to claim 3, characterized in that: One end of the first DC+ terminal metal layer (1D) and one end of the second DC+ terminal metal layer (4H) are connected via a fifth molybdenum compound (1I), and the other end of the first DC+ terminal metal layer (1D) and the other end of the second DC+ terminal metal layer (4H) are connected via a sixth molybdenum compound (2I); The first AC terminal metal layer (2D) and the fourth AC terminal metal layer (3H) are connected via a seventh molybdenum compound (3I); The second AC terminal metal layer (3D) and the third AC terminal metal layer (2H) are connected via an eighth molybdenum compound (4I); The third AC terminal metal layer (2H) and the fourth AC terminal metal layer (3H) are connected via a copper bridge (5I); The second DC-terminal metal layer (1H) and the first DC-terminal metal layer (4D) are connected via a ninth molybdenum compound (6I).

6. The double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance according to claim 3, characterized in that: The multiple driving metal layers include eight groups of driving metal layers, each group of driving metal layers is arranged corresponding to the silicon carbide chip, wherein four groups of driving metal layers are respectively located at the four corners of the lower metal plate (102), and the other four groups of driving metal layers are respectively located at the four corners of the upper metal plate (202); and each group of driving metal layers is provided with a group of driving terminals.

7. A double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance according to claim 6, characterized in that: Each group of driving metal layers includes: a source driving metal layer and a gate driving metal layer; A source driving terminal is disposed on the surface of the source driving metal layer, and a gate driving terminal is disposed on the surface of the gate driving metal layer.

8. The double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance according to claim 7, characterized in that: The one source driving terminal is connected to a source of the silicon carbide chip, and the one gate driving terminal is connected to a gate of the silicon carbide chip.

9. The double-sided heat dissipation power module with low parasitic capacitance and low parasitic inductance according to claim 6, characterized in that: The lower DBC substrate also includes a lower heat dissipation plate (103); The lower heat dissipation plate (103) is located on a surface of the lower AIN substrate (101) away from the lower metal plate (102) and is used for installing a heat sink; The upper DBC substrate also includes an upper heat dissipation plate (203); The upper heat dissipation plate (203) is located on a surface of the upper AIN substrate (201) away from the upper metal plate (202) and is used for mounting a heat sink.

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