A high-current, low-inductance power module

Abstract

A high-current, low-inductance power module relates to the field of semiconductor technology. It comprises a base plate, a housing, and a cover plate. The base plate is provided with: an insulating substrate comprising an upper half-bridge insulating substrate, a lower half-bridge insulating substrate, a first metal layer, a second metal layer, and a third metal layer spaced apart from each other; one side of the first metal layer is located at the rear of the upper half-bridge insulating substrate, and the other side extends into the upper half-bridge insulating substrate; one side of the second metal layer is located at the rear of the lower half-bridge insulating substrate, and the other side extends into the lower half-bridge insulating substrate; the third metal layer extends along the bottom region of the upper half-bridge insulating substrate, with one side located at the side of the second metal layer and the other side located at the positive and negative electrodes. The present invention improves the module power density and reduces the module stray inductance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high-current and low-inductance power module. Background Art

[0002] Power semiconductor technology plays a crucial role in today's industrial landscape. Power modules, as a representative example of this technology, are widely used in industries such as electric vehicles, photovoltaic power generation, wind power generation, and industrial frequency conversion. With the rise of my country's industry, power semiconductor modules have a broader market prospect.

[0003] To improve the efficiency of power electronics systems, power modules require higher switching frequencies. However, the high parasitic inductance of traditional packaging structures causes significant voltage overshoots when power semiconductor devices switch on and off, increasing the risk of overvoltage breakdown and limiting further increases in the switching frequency of power modules. Parasitic inductance has always been a major challenge to overcome in power electronics applications, especially in high-frequency applications of 15-20Hz and high-power applications of 900A-1800A.

[0004] The mainstream power modules of existing technologies, such as Figure 11 As shown, the circuit comprises an outer frame A, a base plate B, an insulating substrate C of equal thickness, power chips (D and E in the figure), bonding wires F, and power terminals G. Three insulating substrates C are welded atop base plate B, with several power chips soldered to the top of each insulating substrate C. The copper layer of the insulating substrate C forms an electrical connection with the chip; the front of the chip is electrically connected to the copper layer of the insulating substrate C via bonding wires F. The power circuit relies on the copper layer on the top surface of the insulating substrate, making it difficult to further increase the power density of the power semiconductor. Furthermore, the parasitic inductance of the power circuit is large, making it unable to meet fast switching requirements and unsuitable for high-frequency applications.

[0005] Therefore, developing a product with a parasitic inductance reduced to 15nH and a current specification increased to over 900A in a universal housing (same specifications and volume) is a technical problem that the industry urgently needs to solve. Summary of the Invention

[0006] In response to the above problems, the present invention provides a high-current, low-inductance power module that solves the problem of high parasitic inductance of existing power modules and breaks through the bottleneck of 900A current specification.

[0007] The technical solution of the present invention is:

[0008] A high-current, low-inductance power module comprises a base plate, a housing, and a cover plate, wherein the base plate is provided with:

[0009] An insulating substrate, comprising an upper half-bridge insulating substrate, a lower half-bridge insulating substrate, a first metal layer, a second metal layer and a third metal layer which are spaced apart from each other;

[0010] One side of the first metal layer is located at the tail of the upper half-bridge insulating substrate, and the other side extends into the upper half-bridge insulating substrate;

[0011] One side of the second metal layer is located at the tail of the lower half-bridge insulating substrate, and the other side extends into the lower half-bridge insulating substrate;

[0012] The third metal layer extends along the bottom area of ​​the upper half-bridge insulating substrate, with one side located on the side of the second metal layer and the other side located on the side of the positive and negative electrodes;

[0013] There are several power chips, which are electrically connected to the upper and lower half-bridge insulating substrates;

[0014] There are a number of connecting bridges, which sequentially connect the upper half-bridge insulating substrate, the first metal layer, the lower half-bridge insulating substrate, the second metal layer and the third metal layer to form a loop.

[0015] Specifically, the first metal layer has an L-shaped structure, including a first portion A for electrically connecting to the lower half-bridge insulating substrate and a first portion B for electrically connecting to the power chip on the upper half-bridge insulating substrate.

[0016] Specifically, the second metal layer has an L-shaped structure, including a second A portion for electrically connecting to the power chip on the lower half-bridge insulating substrate and a second B portion for electrically connecting to the third metal layer.

[0017] Specifically, the third metal layer has a U-shaped structure.

[0018] Specifically, the power chip includes several groups of IGBT chip groups and / or several groups of FRD chip groups.

[0019] Specifically, the IGBT chipset includes a plurality of IGBT chips connected in parallel;

[0020] The IGBT chip group is disposed in an upper region of the upper half-bridge insulating substrate and a lower region of the lower half-bridge insulating substrate.

[0021] Specifically, the FRD chipset includes several FRD chips connected in parallel;

[0022] The FRD chip group is disposed in a lower region of the upper half-bridge insulating substrate and an upper region of the lower half-bridge insulating substrate.

[0023] Specifically, the connecting bridge includes a metal bridge 1 and a metal bridge 2;

[0024] The metal bridge 1 is used to electrically connect the power chip to the first metal layer and the second metal layer;

[0025] The second metal bridge is used for electrically connecting the lower half bridge insulating substrate to the first metal layer and for electrically connecting the second metal layer to the third metal layer.

[0026] Specifically, the insulating substrate includes an upper surface layer, an intermediate layer and a lower surface layer arranged in sequence;

[0027] The materials of the upper surface layer and the lower surface layer are both metallic conductive materials;

[0028] The material of the lower surface layer is insulating material.

[0029] Specifically, the thickness of the upper half-bridge insulating substrate is not greater than the thickness of the first metal layer, the second metal layer, and the third metal layer.

[0030] Beneficial effects of the present invention:

[0031] The present invention utilizes a unequal thickness design for the power circuit (the first, second, and third metal layers are thickened), a Clip connection bridge for E-pole chip interconnection, and an optimized module layout design. By utilizing the improved power density of the main circuit chip interconnection and the multi-parallel principle and the magnetic circuit cancellation principle, parasitic inductance and mutual inductance are reduced, and the current path is adjusted, thereby improving the module power density and reducing the module stray inductance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the three-dimensional structure of the present invention;

[0033] Figure 2 It is a schematic diagram of the internal cross-sectional structure;

[0034] Figure 3 It is a schematic diagram of the three-dimensional structure of the power chip layout;

[0035] Figure 4 This is a top view of the power chip layout;

[0036] Figure 5 It is a schematic diagram of the current flow in the power circuit;

[0037] Figure 6 It is a structural diagram of the terminal connection status;

[0038] Figure 7 is a schematic diagram of the insulating substrate layout structure;

[0039] Figure 8 It is a schematic diagram of a three-dimensional structure of a metal bridge;

[0040] Figure 9 It is a schematic diagram of the three-dimensional structure of the metal bridge;

[0041] Figure 10 It is a schematic diagram of the three-dimensional structure of the terminal;

[0042] Figure 11 It is a schematic diagram of the background technology structure;

[0043] In the figure, 100 is the bottom plate.

[0044] 200 is an insulating substrate, 210 is an upper half-bridge insulating substrate, 220 is a lower half-bridge insulating substrate, 230 is a first metal layer, 240 is a second metal layer, 250 is a third metal layer,

[0045] 300 is the power chip, 310 is the IGBT chip, 320 is the FRD chip,

[0046] 400 is a connecting bridge, 410 is a metal bridge 1, 411 is an electrical connection portion, 412 is a cross portion 1, 420 is a metal bridge 2, 421 is a left electrical connection claw portion, 422 is a cross portion 2, and 423 is a right electrical connection claw portion. DETAILED DESCRIPTION

[0047] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0048] In the description of the present invention, it should be understood that terms such as "upper," "lower," "left," "right," "vertical," and "horizontal" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. These terms are used solely to facilitate and simplify the description of the present invention and are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0049] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on the specific circumstances.

[0050] For power modules with multiple chips connected in parallel, the present invention achieves better electrical performance by improving the packaging structure. That is, the parasitic inductance of the power module is low in high-frequency, high-power applications, achieving a larger current specification of more than 900A. In addition, the structure is simple and easy to implement on a universal housing, and mass production can be achieved under the existing universal housing.

[0051] Reference below Figure 1-10 Describe an embodiment according to the present invention;

[0052] A high-current, low-inductance power module includes a base plate 100, a housing, and a cover plate. The base plate 100 is provided with:

[0053] The insulating substrate 200 is disposed on the base plate 100 and includes an upper half-bridge insulating substrate 210, a lower half-bridge insulating substrate 220, a first metal layer 230, a second metal layer 240 and a third metal layer 250 that are spaced apart from each other.

[0054] One side of the first metal layer 230 is located at the tail of the upper half-bridge insulating substrate 210 (close to the middle area of ​​the insulating substrate), and the other side extends into the upper half-bridge insulating substrate 210, that is, extends toward the front of the upper half-bridge insulating substrate 210;

[0055] One side of the second metal layer 240 is located at the rear end of the lower half-bridge insulating substrate 220 (near the middle area of ​​the insulating substrate), and the other side extends into the lower half-bridge insulating substrate 220, that is, extends toward the front of the lower half-bridge insulating substrate 220. The first metal layer 230 and the second metal layer 240 are arranged in an alternating manner.

[0056] The third metal layer 250 extends along the bottom area of ​​the upper half-bridge insulating substrate 210, with one side located on the side of the second metal layer 240 and the other side located on the side of the positive and negative electrodes;

[0057] The insulating substrate 200 in this case includes an upper surface layer, an intermediate layer and a lower surface layer arranged in sequence; the materials of the upper surface layer and the lower surface layer are both metallic conductive materials; the material of the lower surface layer is insulating material.

[0058] In this embodiment, the thickness of the upper half-bridge insulating substrate 210 is not greater than the thickness of the first metal layer 230 , the second metal layer 240 and the third metal layer 250 .

[0059] Preferably, in this case, the thickness values ​​of the upper half-bridge insulating substrate 210 and the lower half-bridge insulating substrate 220 are equal, usually 0.3 mm; the thickness values ​​of the first metal layer 230, the second metal layer 240 and the third metal layer 250 are all greater than the thickness value of the upper half-bridge insulating substrate 210, usually 0.6 mm, that is, the selected values ​​of the thickness of the first, second and third metal layers are usually 2 to 3 times that of the upper and lower half-bridge insulating substrates, taking into account the layout, meeting the high current specification requirements, and taking into account the product's heat dissipation performance.

[0060] The power chip 300 is provided with a plurality of electrically connected to the upper and lower half-bridge insulating substrates;

[0061] There are a number of connecting bridges 400 , or Clips, which sequentially connect the upper half-bridge insulating substrate 210 , the first metal layer 230 , the lower half-bridge insulating substrate 220 , the second metal layer 240 and the third metal layer 250 to form a loop.

[0062] Figure 3 A mid-power semiconductor module consists of two insulating substrates: the upper half-bridge insulating substrate on the right and the lower half-bridge insulating substrate on the left. The insulating substrates are interconnected using ultrasonic welding of power terminals to the upper half-bridge insulating substrate. The upper and lower half-bridge power semiconductor chips (power chip 300 in this case) are soldered to the corresponding copper layers of the left and right insulating substrates. The chips are connected using DTS+ Clips to the corresponding areas of the main circuits of the upper and lower half-bridge insulating substrates. In this case, the thickness of the first metal layer 230, the lower half-bridge insulating substrate 220, and the third metal layer 250 is unequal to that of the second metal layer 240. This means that, given the limited area of ​​the first metal layer 230, the lower half-bridge insulating substrate 220, and the third metal layer 250, their thickness is increased to meet high current flow capacity requirements.

[0063] The principle, advantage and function of the spatial layout of the first, second and third metal layers and the upper and lower half-bridge insulating substrates in this case are to complete multi-chip parallel connection in the existing space, improve the current capacity, increase the current density, reduce parasitic inductance, reduce the current path, and reduce the total parasitic inductance.

[0064] Figure 5 Schematic diagram of the current flow direction of the power circuit of the power semiconductor module; when the power chip on the upper half-bridge insulating substrate 210 is working, the current flowing into the positive electrode ( Figure 5The copper layer of the main circuit is laminated with a thickness of copper (0.3-0.6 mm, which can reproduce the large current flow capacity in a certain space). The copper layers of the upper and lower half-bridge insulating substrates on the left and right sides are connected through the Clip. The power semiconductor chip on the lower half-bridge insulating substrate 220 reaches the output electrode through the DTS (chip surface system) + Clip + insulating substrate copper layer (main circuit copper layer) + Clip.

[0065] Figure 5-6 As shown, the positive electrode terminal is connected to the upper half-bridge insulating substrate 210, the negative electrode terminal is connected to the third metal layer 250, and the output electrode terminal is connected to the lower half-bridge insulating substrate 220; Figure 7 In the figure, 001~007 are module signal connections respectively, which function as module signal data acquisition output or input and are connected to the application driver circuit board.

[0066] When the lower half-bridge power semiconductor chip is working, current flows in through the output electrode, passes through the Clip and reaches the right insulating substrate (of unequal thickness), flows through the lower half-bridge power semiconductor chip and Clip, and flows out through the negative electrode.

[0067] from Figure 5 It can be seen that the current of the DTS+ Clip flows from the positive electrode to the output electrode, and the current of the insulating substrate below the Clip flows from the output electrode to the negative electrode. According to the principle of current carrying density, the designed Clip+ unequal thickness main circuit copper layer and re-layout design increase the module current level, which can significantly reduce the parasitic inductance of the module, high power density, and high reliability.

[0068] Specific description of the first, second and third metal layer structures:

[0069] The first metal layer 230 has an L-shaped structure, including a first portion A for electrically connecting to the lower half-bridge insulating substrate 220 and a first portion B for electrically connecting to the power chip 300 on the upper half-bridge insulating substrate 210 .

[0070] In this embodiment, the first metal layer 230 is made of a conductive metal material (such as copper) on its top and bottom surfaces, and an insulating material zirconium oxide (ZrO2) in its center. The second metal layer 240 and the third metal layer 250 are made of the same material structure as the first metal layer 230.

[0071] The second metal layer 240 has an L-shaped structure, including a second portion A for electrically connecting to the power chip 300 on the lower half-bridge insulating substrate 220 and a second portion B for electrically connecting to the third metal layer 250 .

[0072] The third metal layer 250 has a U-shaped structure.

[0073] Detailed description of power chip 300:

[0074] The power chip 300 includes several groups of IGBT chips and / or several groups of FRD chips.

[0075] That is, it can be in four combinations:

[0076] All IGBT chipsets or all FRD chipsets;

[0077] IGBT chipset and FRD chipset are combined; in this case, 2 sets of IGBT chipsets and 2 sets of FRD chipsets are preferred.

[0078] The IGBT chipset includes a plurality of IGBT chips 310 connected in parallel;

[0079] The IGBT chip set is disposed in the upper region of the upper half-bridge insulating substrate 210 and the lower region of the lower half-bridge insulating substrate 220 .

[0080] The FRD chipset includes several FRD chips 320 connected in parallel;

[0081] The FRD chip set is disposed in the lower region of the upper half-bridge insulating substrate 210 and the upper region of the lower half-bridge insulating substrate 220 .

[0082] In this case, Figure 7 As shown, the first metal layer 230 separates the upper half-bridge insulating substrate 210 into an upper region and a lower region; the second metal layer 240 also separates the lower half-bridge insulating substrate 220 into an upper region and a lower region.

[0083] Figure 6 This is a schematic diagram of the module's internal structure. The upper half-bridge power semiconductor chip consists of six IGBT chips and six FRD chips, while the lower half-bridge power semiconductor chip also consists of six IGBT chips and six FRD chips. The purpose of these chips is to connect multiple chips in parallel to meet high current levels, such as 200A*6=1200A.

[0084] Detailed description of the connecting bridge 400:

[0085] The connecting bridge 400 includes a metal bridge 1 410 and a metal bridge 2 420 ;

[0086] The metal bridge 1 410 is used to electrically connect the power chip 300 to the first metal layer 230 and the second metal layer 240;

[0087] The metal bridge 1 410 includes an electrical connection portion 411 and a cross-over portion 412 that are alternately arranged in sequence;

[0088] like Figure 8As shown, a plurality of concave shapes are provided in the middle of the Clip connection bridge. The provided patterns can connect the current and release the stress, and each current path of the Clip connection bridge corresponds to the current path of the chip below.

[0089] like Figure 9 As shown, the metal bridge 2 420 is used to electrically connect the lower half-bridge insulating substrate 220 to the first metal layer 230 and to electrically connect the second metal layer 240 to the third metal layer 250;

[0090] The second metal bridge 420 includes a left electrical connection claw portion 421 , a second cross portion 422 , and a right electrical connection claw portion 423 that are sequentially connected.

[0091] In the prior art, various drive signal terminals, thermistor terminals, etc. connected to the insulating substrate 200 all adopt a straight L-shaped structure design, which may cause problems such as insufficient stability after being connected to the PCB. Figure 10 As shown, in this case, vertically staggered rectangular notches are provided in the vertical area of ​​the terminal, which not only reduces the effective impact of vibration and stress on the device but also increases the reliability of the device.

[0092] In this case, the parallel chips cause the overall magnetic field distribution to change. Due to the interaction of the magnetic fields of multiple chips, some of the magnetic fields are offset to a certain extent, thereby reducing the equivalent inductance. A new parasitic inductance model of multi-chip power with Clip packaging is established. The mutual inductance between parallel branches is identified and included in the model. Based on the established model, different layout structures of half-bridge multi-chip power module packaging are proposed, which can effectively reduce the total parasitic inductance by 12-15nH.

[0093] This project uses a different layout and structural design to increase the current to 900A-1800A within the same platform and existing space. The chip interconnect adopts a 410 (Clip) design to effectively increase the current capacity. At the same time, the first, second, and third metal layers adopt a design structure with different thicknesses (0.3-0.6MM) than the insulating substrate, effectively increasing the circuit current capacity.

[0094] The power density of automotive-grade power modules is of great significance to the performance of electric vehicles. This paper presents an IGBT power module packaged on the E3 platform. Using a layout design with a partially thickened DBC copper layer and a clip bridge at the chip's E-pole, a 1200 V / 1800 A IGBT power module was developed. Compared with traditional two-dimensional layout methods, the stray inductance was reduced by 80%. Double-pulse experiments were conducted on the power module under conditions of a bus voltage of 800 V and a pulse current of 1800 A. The experimental results demonstrated the improved power density of the module. A water-cooled PinFin heat sink was used at the bottom of the power module, and heat dissipation simulations and junction-to-water thermal resistance tests were conducted. The results showed that the IGBT thermal resistance was 0.05 K / W and the diode thermal resistance was 0.02 K / W, which are not significantly different from commercial 1200 V / 900 A modules in the same package, demonstrating the correctness and effectiveness of the proposed design method.

[0095] Regarding the content disclosed in this case, the following points need to be explained:

[0096] (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design;

[0097] (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to form new embodiments;

[0098] The above are only specific implementation methods disclosed in this case, but the protection scope of this disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A high current low inductance power module, comprising a base plate (100), a housing and a cover plate, characterized in that: The bottom plate (100) is provided with an outer frame, insulating substrates of unequal thickness, a chip and a connecting bridge; An insulating substrate (200) comprising an upper half-bridge insulating substrate (210), a lower half-bridge insulating substrate (220), a first metal layer (230), a second metal layer (240), and a third metal layer (250) that are spaced apart from each other; The thicknesses of the first metal layer (230), the lower half-bridge insulating substrate (220), and the third metal layer (250) are respectively greater than the thickness of the second metal layer (240); The thickness of the upper half-bridge insulating substrate (210) is not greater than the thickness of the first metal layer (230), the second metal layer (240) and the third metal layer (250); One side of the first metal layer (230) is located at the tail of the upper half-bridge insulating substrate (210), and the other side extends into the upper half-bridge insulating substrate (210); One side of the second metal layer (240) is located at the tail of the lower half-bridge insulating substrate (220), and the other side extends into the lower half-bridge insulating substrate (220); The third metal layer (250) extends along the bottom area of ​​the upper half-bridge insulating substrate (210), with one side located on the side of the second metal layer (240) and the other side located on the side of the positive and negative electrodes; A plurality of power chips (300) are provided and are electrically connected to the upper and lower half-bridge insulating substrates; A plurality of connecting bridges (400) are provided, sequentially connecting the upper half-bridge insulating substrate (210), the first metal layer (230), the lower half-bridge insulating substrate (220), the second metal layer (240), and the third metal layer (250) to form a loop; The first metal layer (230) has an L-shaped structure, comprising a first portion A for electrically connecting to the lower half-bridge insulating substrate (220) and a first portion B for electrically connecting to the power chip (300) on the upper half-bridge insulating substrate (210); The second metal layer (240) has an L-shaped structure, comprising a second A portion for electrically connecting to the power chip (300) on the lower half-bridge insulating substrate (220) and a second B portion for electrically connecting to the third metal layer (250); The third metal layer (250) has a U-shaped structure.

2. The high current low inductance power module according to claim 1, characterized in that: The power chip (300) includes several groups of IGBT chip groups and / or several groups of FRD chip groups.

3. The high current low inductance power module according to claim 2, characterized in that: The IGBT chipset comprises a plurality of IGBT chips (310) connected in parallel; The IGBT chip group is arranged in the upper region of the upper half-bridge insulating substrate (210) and the lower region of the lower half-bridge insulating substrate (220).

4. The high current low inductance power module according to claim 2, characterized in that: The FRD chipset includes a plurality of FRD chips (320) connected in parallel; The FRD chip group is arranged in the lower region of the upper half-bridge insulating substrate (210) and the upper region of the lower half-bridge insulating substrate (220).

5. The high current low inductance power module according to claim 1, characterized in that: The connecting bridge (400) includes a first metal bridge (410) and a second metal bridge (420); The metal bridge 1 (410) is used for electrically connecting the power chip (300) with the first metal layer (230) and the second metal layer (240); The second metal bridge (420) is used for electrical connection between the lower half bridge insulating substrate (220) and the first metal layer (230), and for electrical connection between the second metal layer (240) and the third metal layer (250).

6. The high current low inductance power module according to claim 1, characterized in that: The insulating substrate (200) comprises an upper surface layer, an intermediate layer and a lower surface layer which are arranged in sequence; The materials of the upper surface layer and the lower surface layer are both metallic conductive materials; The material of the lower surface layer is insulating material.

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