A metal oxide semiconductor field effect transistor resistant to single event radiation

Abstract

The application provides a kind of metal oxide semiconductor field effect transistor of anti single particle irradiation, when field effect transistor is in the state of cosmic ray or heavy ion incidence, due to the first conductive type polysilicon source region arranged in field effect transistor, when parasitic transistor opens, current gain is reduced, the carrier multiplication effect of device is reduced, to improve the anti single particle performance of device, again through the second conductive type polysilicon source region to form a hole flow channel, to exclude the hole generated in the oxide layer under the device when heavy ion incidence, so that the peak electric field inside the oxide layer is reduced.The application reduces the carrier multiplication effect of device, then improves the anti single particle irradiation performance through hole channel, so that the device has low oxide layer peak electric field and drain current, improves the anti single particle gate wear performance and burn performance of field effect transistor, to improve the anti single particle irradiation ability of device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor power electronic devices, and particularly relates to a metal oxide semiconductor field effect transistor resistant to single particle irradiation. BACKGROUND

[0002] Silicon carbide (SiC) has excellent material properties, and is highly concerned as a next-generation power semiconductor material to replace Si. With the development of power integrated circuits, the application of silicon carbide metal oxide semiconductor field effect transistors (MOSFETs) is becoming more and more mature. Compared with bipolar devices, silicon carbide metal oxide semiconductor field effect transistors (MOSFETs) have the advantage of reverse conduction. However, when silicon carbide metal oxide semiconductor field effect transistors work in a cosmic heavy ion radiation environment, single particle gate punch-through effect and single particle burnout effect are likely to occur, causing permanent damage to the device.

[0003] In related technologies, on the one hand, a buffer layer is added on the drain side to improve the electric field distribution of the field effect transistor, thereby improving the single particle burnout performance; on the other hand, the area of the heavily doped second conductivity type contact region is increased on the source side to better protect the oxide layer, thereby improving the gate punch-through performance and burnout performance. However, the current single particle irradiation hardening structure has limited improvement on the single particle irradiation performance, and this structure is still prone to single particle gate punch-through effect and burnout effect, causing damage to the device.

[0004] Therefore, how to improve the single particle irradiation resistance of the metal oxide semiconductor field effect transistor is a problem to be solved at present. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the present application provides a metal oxide semiconductor field effect transistor resistant to single particle irradiation to solve at least one of the above technical problems.

[0006] To achieve the above-mentioned objects and other related objects, the technical solutions provided by the present application are as follows.

[0007] a drain metal layer and a first conductivity type substrate layer, a first conductivity type buffer layer and a first conductivity type drift region which are sequentially stacked on the drain metal layer;

[0008] a first conductivity type conduction region arranged on a side of the first conductivity type drift region away from the first conductivity type buffer layer;

[0009] two second conductivity type gate body regions arranged on a side of the first conductivity type drift region away from the first conductivity type buffer layer, wherein the first conductivity type conduction region is between the two second conductivity type gate body regions;

[0010] The second conductivity type polysilicon source region is disposed within the first conductivity type conduction region, and the second conductivity type polysilicon source region is located on the side away from the first conductivity type drift region;

[0011] Two second conductivity type contact regions are respectively disposed in two second conductivity type gate body regions, and the second conductivity type contact regions are located on the side away from the first conductivity type drift region;

[0012] Two polysilicon source regions of the first conductivity type are respectively disposed in two contact regions of the second conductivity type, and the polysilicon source regions of the first conductivity type are in contact with the gate body regions of the second conductivity type.

[0013] An oxide layer is disposed on the side of the first conductivity type conduction region away from the first conductivity type drift region, and the oxide layer partially covers the first conductivity type polysilicon source region, the second conductivity type polysilicon source region and the second conductivity type gate body region.

[0014] A first conductivity type gate polysilicon layer is disposed on the side of the oxide layer opposite to the first conductivity type conduction region, and the oxide layer encapsulates the first conductivity type gate polysilicon layer; and,

[0015] A source metal layer is disposed on the side of the second conductivity type contact region away from the second conductivity type gate body region, wherein the source metal layer partially covers the first conductivity type polysilicon source region, the second conductivity type polysilicon source region, and the oxide layer.

[0016] In one embodiment of the present invention, the first conductivity type substrate layer, the second conductivity type contact region, the first conductivity type polysilicon source region, and the first conductivity type gate polysilicon layer are heavily doped.

[0017] In one embodiment of the present invention, the first conductivity type drift region is lightly doped.

[0018] In one embodiment of the present invention, the thickness of the first conductivity type drift region is 5 μm to 10 μm, and its doping concentration is 2 × 10⁻⁶. 16 cm -3 Up to 5×10 16 cm -3 .

[0019] In one embodiment of the present invention, the first conductivity type substrate layer, the first conductivity type buffer layer, the first conductivity type drift region, the first conductivity type conduction region, the second conductivity type gate body region, and the second conductivity type contact region are silicon carbide.

[0020] In one embodiment of the present application, the first conductive type polysilicon source region is N-type doped, and the second conductive type polysilicon source region is P-type doped.

[0021] In one embodiment of the present application, the thickness of the second conductive type polysilicon source region is 0.1 μm to 0.5 μm, and the doping concentration thereof is 1 x 1018 cm-3 to 5 x 1019 cm-3. 17 -3 17 -3 .

[0022] In one embodiment of the present application, the thickness of the first conductive type polysilicon source region is 0.1 μm to 0.5 μm, and the doping concentration thereof is 1 x 1018 cm-3 to 1 x 1019 cm-3. 19 -3 20 -3 .

[0023] In one embodiment of the present application, the thickness of the oxide layer in contact with the first conductive type conduction region, the second conductive type gate body region, the first conductive type polysilicon source region and the second conductive type polysilicon source region is 30 nm to 80 nm.

[0024] The present application provides a metal oxide semiconductor field effect transistor with anti-single particle irradiation. When the field effect transistor is in the state of cosmic ray or heavy ion incidence, the first conductive type polysilicon source region is arranged in the field effect transistor, so that the current gain is reduced when the parasitic transistor is turned on, the carrier multiplication effect of the device is reduced, and the anti-single particle performance of the device is improved. A hole flow channel is formed by the second conductive type polysilicon source region to remove the holes generated under the oxide layer when the heavy ion is incident, so that the peak electric field inside the oxide layer is reduced. After reducing the carrier multiplication effect of the device, the anti-single particle irradiation performance is improved through the hole channel, so that the device has low oxide layer peak electric field and drain current, the anti-single particle gate wear performance and burnout performance of the field effect transistor are improved, and the anti-single particle irradiation performance of the device is improved.

[0025] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0026] ​​​​​​The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0027] Figure 1 A schematic cross-sectional view of a metal-oxide-semiconductor field-effect transistor resistant to single-particle irradiation, as shown in an exemplary embodiment of the present invention.

[0028] Figure 2 A comparison diagram of single-particle gate penetration resistance characteristics shown as an exemplary embodiment of the present invention;

[0029] Figure 3 A comparison diagram illustrating the resistance to single-particle burn-off characteristics, as shown in an exemplary embodiment of the present invention;

[0030] Explanation of reference numerals in the attached figures: 1-Drain metal layer, 2-First conductivity type substrate layer, 3-First conductivity type buffer layer, 4-First conductivity type drift region, 5-First conductivity type conduction region, 6-Second conductivity type gate body region, 7-Second conductivity type contact region, 8-First conductivity type polysilicon source region, 9-Second conductivity type polysilicon source region, 10-Oxide layer, 11-First conductivity type gate polysilicon layer, 12-Source metal layer. Detailed Implementation

[0031] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0032] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0033] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0034] Silicon carbide (SiC) possesses excellent material properties and has attracted much attention as a next-generation power semiconductor material to replace Si. With the development of power integrated circuits, the application of silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) has become increasingly mature. Compared to bipolar devices, MOSFETs have the advantage of reverse conduction. However, when operating in a heavy ion radiation environment, MOSFETs are prone to single-event gate breakdown and single-event burn-out, leading to permanent device damage and insufficient reliability due to single-event irradiation.

[0035] In related technologies, on the one hand, adding a buffer layer on the drain side improves the electric field distribution of the field-effect transistor, thereby improving single-event burn-out performance; on the other hand, increasing the area of ​​the heavily doped second conductivity type contact region on the source side better protects the oxide layer, thus improving gate breakthrough performance and burn-out performance. However, current single-event hardening structures offer limited improvement in single-event irradiation performance, and the structure remains susceptible to single-event gate breakthrough and burn-out effects, leading to device damage.

[0036] like Figure 1 As shown, this application provides a metal-oxide-semiconductor field-effect transistor resistant to single-particle irradiation, comprising:

[0037] Drain metal layer 1 and first conductivity type substrate layer 2, first conductivity type buffer layer 3 and first conductivity type drift region 4 are stacked sequentially on drain metal layer 1;

[0038] The first conductivity type conduction region 5 is disposed on the side of the first conductivity type drift region 4 away from the first conductivity type buffer layer 3;

[0039] Two second conductivity type gate body regions 6 are disposed on the side of the first conductivity type drift region 4 away from the first conductivity type buffer layer 3, wherein the first conductivity type conduction region 5 is located between the two second conductivity type gate body regions 6;

[0040] The second conductivity type polysilicon source region 9 is disposed within the first conductivity type conduction region 5, and the second conductivity type polysilicon source region 9 is located on the side away from the first conductivity type drift region 4.

[0041] Two second conductivity type contact regions 7 are respectively disposed in two second conductivity type gate body regions 6, and the second conductivity type contact regions 7 are located on the side away from the first conductivity type drift region 4;

[0042] Two polysilicon source regions 8 of the first conductivity type are respectively disposed in two contact regions 7 of the second conductivity type, and the polysilicon source regions 8 of the first conductivity type are in contact with the gate body region 6 of the second conductivity type;

[0043] An oxide layer 10 is disposed on the side of the first conductivity type conduction region 5 away from the first conductivity type drift region 4, and a portion of the oxide layer 10 covers the first conductivity type polysilicon source region 8, the second conductivity type polysilicon source region 9, and the second conductivity type gate body region 6.

[0044] A first conductivity type gate polysilicon layer 11 is disposed on the side of the oxide layer 10 opposite to the first conductivity type conductive region 5, and the oxide layer 10 encapsulates the first conductivity type gate polysilicon layer 11; and,

[0045] A source metal layer 12 is disposed on the side of the second conductivity type contact region 7 away from the second conductivity type gate body region 6, wherein a portion of the source metal layer 12 covers the first conductivity type polysilicon source region 8, the second conductivity type polysilicon source region 9, and the oxide layer 10.

[0046] like Figure 1 As shown, the second conductivity type gate body region 6 is L-shaped. A second conductivity type contact region 7 is provided on the horizontal extension of the second conductivity type gate body region 6. An oxide layer 10 is provided on the vertical extension of the second conductivity type gate body region 6. The vertical extension of the second conductivity type gate body region 6 is in contact with the first conductivity type conductive region 5. The horizontal direction is parallel to the drain metal layer 1, and the vertical direction is perpendicular to the drain metal layer 1.

[0047] like Figure 1 As shown, the second conductivity type contact region 7 is L-shaped. A first conductivity type polysilicon source region 8 is disposed on the horizontal extension of the second conductivity type contact region 7, and a source metal layer 12 is disposed on the vertical extension of the second conductivity type contact region 7. The thickness of the first conductivity type polysilicon source region 8 is 0.1 μm to 0.5 μm, and the doping concentration of the first conductivity type polysilicon source region 8 is 1 × 10⁻⁶. 19 cm -3 Up to 1×10 20cm -3 .

[0048] like Figure 1 As shown, a source metal layer 12 is disposed on the polysilicon source region 9 of the second conductivity type, and the two oxide layers 10 are isolated in the horizontal direction by the source metal layer 12.

[0049] Specifically, the first conductivity type substrate layer 2, the second conductivity type contact region 7, the first conductivity type polysilicon source region 8, and the first conductivity type gate polysilicon layer 11 are heavily doped; the first conductivity type drift region 4 is lightly doped. The first conductivity type drift region 4 has a thickness of 5 μm to 10 μm and a doping concentration of 2 × 10⁻⁶. 16 cm -3 Up to 5×10 16 cm -3 .

[0050] Specifically, the first conductivity type substrate layer 2, the first conductivity type buffer layer 3, the first conductivity type drift region 4, the first conductivity type conduction region 5, the second conductivity type gate body region 6, and the second conductivity type contact region 7 are all made of silicon carbide. The doping concentration of the first conductivity type buffer layer 3 ranges from 5 × 10⁻⁶. 17 cm -3 Up to 2×10 18 cm -3 .

[0051] Specifically, the first type of polysilicon source region 8 is N-type doped, and the second type of polysilicon source region 9 is P-type doped. The thickness of the second type of polysilicon source region 9 is 0.1 μm to 0.5 μm, and its doping concentration is 1 × 10⁻⁶. 17 cm -3 Up to 5×10 17 cm -3 The thickness of the first conductivity type polycrystalline silicon source region 8 is 0.1 μm to 0.5 μm, and its doping concentration is 1 × 10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 .

[0052] In detail, such as Figure 1 As shown, the thickness of the oxide layer 10 in contact with the first conductivity type conductive region 5, the second conductivity type gate body region 6, the first conductivity type polysilicon source region 8, and the second conductivity type polysilicon source region 9 is 30 nm to 80 nm; that is, the thickness of the oxide layer 10 located under the heavily doped first conductivity type gate polysilicon layer 11 ranges from 30 nm to 80 nm.

[0053] The principle of the metal-oxide-semiconductor field-effect transistor (MOSFET) provided in this application for resistance to single-particle irradiation is as follows: A second conductivity type polycrystalline silicon source region 9 is formed through P-type doping. This second conductivity type polycrystalline silicon source region 9 and the first conductivity type conduction region 5 constitute a heterojunction diode, providing an additional low-electron conduction path when the MOSFET is reverse-biased, thus forming a low-electron-barrier diode structure. The first conductivity type polycrystalline silicon source region 8 is N-type doped. When the MOSFET is forward-biased, such as… Figure 1 As shown, the two polysilicon source regions 8 of the first conductivity type are in contact with the corresponding gate body regions 6 of the second conductivity type, and form a current flow channel at the contact surface. This does not have any other effect on the device. When a single-event irradiation occurs, the two polysilicon source regions 8 of the first conductivity type act as emitters of parasitic transistors, reducing the current gain of the device and forming a protection structure against single-event burn-out, thereby improving the device's resistance to single-event burn-out.

[0054] When a field-effect transistor is irradiated by a single particle, the polysilicon source region 9 of the second conductivity type forms a hole flow channel, which constitutes a single-particle gate-through effect protection structure. The holes generated below the oxide layer 10 during single-particle irradiation flow out of the device through the hole flow channel, reducing the electric field inside the oxide layer.

[0055] like Figure 2 As shown, the metal oxide semiconductor field-effect transistor (MOSFET) resistant to single-event irradiation provided in this application has a smaller peak electric field in the oxide layer compared to existing field-effect transistors, and the MOSFET provided in this application has better single-event gate penetration resistance.

[0056] like Figure 3 As shown, the drain current of the metal-oxide-semiconductor field-effect transistor (MOSFET) resistant to single-particle irradiation provided in this application is smaller than that of existing field-effect transistors, and the drain current drops to near zero after a period of time. The MOSFET provided in this application has better resistance to single-particle burn-out.

[0057] This application provides a metal-oxide-semiconductor field-effect transistor (MOSFET) resistant to single-event irradiation. When the MOSFET is exposed to cosmic rays or heavy ions, the presence of a polysilicon source region of a first conductivity type reduces the current gain when the parasitic transistor is turned on, thus lowering the carrier multiplication effect and improving the device's single-event irradiation resistance. A hole flow channel is then formed through a polysilicon source region of a second conductivity type to expel holes generated under the oxide layer during heavy ion incidence, thereby reducing the peak electric field within the oxide layer. This application, after reducing the carrier multiplication effect, further enhances single-event irradiation resistance through the hole channel, resulting in a low oxide peak electric field and drain current. This improves the MOSFET's resistance to single-event gate breakdown and burn-out, thereby enhancing the device's overall single-event irradiation resistance.

[0058] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A metal-oxide-semiconductor field-effect transistor resistant to single-particle irradiation, characterized in that, include: Drain metal layer and a first conductivity type substrate layer, a first conductivity type buffer layer and a first conductivity type drift region are sequentially stacked on the drain metal layer; A first conductivity type conductive region is disposed on the side of the first conductivity type drift region away from the first conductivity type buffer layer; Two second conductivity type gate body regions are disposed on the side of the first conductivity type drift region away from the first conductivity type buffer layer, wherein the first conductivity type conduction region is located between the two second conductivity type gate body regions; The second conductivity type polysilicon source region is disposed within the first conductivity type conduction region, and the second conductivity type polysilicon source region is located on the side away from the first conductivity type drift region; Two second conductivity type contact regions are respectively disposed in two second conductivity type gate body regions, and the second conductivity type contact regions are located on the side away from the first conductivity type drift region; Two polysilicon source regions of the first conductivity type are respectively disposed in two contact regions of the second conductivity type, and the polysilicon source regions of the first conductivity type are in contact with the gate body regions of the second conductivity type. An oxide layer is disposed on the side of the first conductivity type conduction region away from the first conductivity type drift region, and the oxide layer partially covers the first conductivity type polysilicon source region, the second conductivity type polysilicon source region and the second conductivity type gate body region. A first conductivity type gate polysilicon layer is disposed on the side of the oxide layer opposite to the first conductivity type conduction region, and the oxide layer encapsulates the first conductivity type gate polysilicon layer; and, A source metal layer is disposed on the side of the second conductivity type contact region away from the second conductivity type gate body region, wherein the source metal layer partially covers the first conductivity type polysilicon source region, the second conductivity type polysilicon source region and the oxide layer; During single-event irradiation, the two polysilicon source regions of the first conductivity type act as emitters of parasitic transistors, reducing the current gain of the device and forming a protective structure against single-event burn-out.

2. The metal-oxide-semiconductor field-effect transistor resistant to single-particle irradiation according to claim 1, characterized in that, The first conductivity type substrate layer, the second conductivity type contact region, the first conductivity type polysilicon source region, and the first conductivity type gate polysilicon layer are heavily doped.

3. The metal-oxide-semiconductor field-effect transistor resistant to single-particle irradiation according to claim 1, characterized in that, The first conductivity type drift region is lightly doped.

4. The metal-oxide-semiconductor field-effect transistor resistant to single-particle irradiation according to claim 3, characterized in that, The thickness of the first conductivity type drift region is 5 μm to 10 μm, and its doping concentration is 2 × 10⁻⁶. 16 cm -3 Up to 5×10 16 cm -3 .

5. The metal-oxide-semiconductor field-effect transistor resistant to single-particle irradiation according to claim 1, characterized in that, The first conductivity type substrate layer, the first conductivity type buffer layer, the first conductivity type drift region, the first conductivity type conduction region, the second conductivity type gate body region, and the second conductivity type contact region are made of silicon carbide.

6. The metal-oxide-semiconductor field-effect transistor resistant to single-particle irradiation according to claim 1, characterized in that, The first type of polycrystalline silicon source region is N-type doped, and the second type of polycrystalline silicon source region is P-type doped.

7. The metal-oxide-semiconductor field-effect transistor resistant to single-particle irradiation according to claim 6, characterized in that, The thickness of the polycrystalline silicon source region of the second conductivity type is 0.1 μm to 0.5 μm, and its doping concentration is 1 × 10⁻⁶. 17 cm -3 Up to 5×10 17 cm -3 .

8. The metal-oxide-semiconductor field-effect transistor resistant to single-particle irradiation according to claim 6, characterized in that, The thickness of the polycrystalline silicon source region of the first conductivity type is 0.1 μm to 0.5 μm, and its doping concentration is 1 × 10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 .

9. The metal-oxide-semiconductor field-effect transistor resistant to single-particle irradiation according to claim 1, characterized in that, The thickness of the oxide layer in contact with the first conductivity type conductive region, the second conductivity type gate body region, the first conductivity type polysilicon source region and the second conductivity type polysilicon source region is 30 nm to 80 nm.

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