A high bandwidth rail-to-rail operational amplifier

Abstract

The present invention belongs to the technical field of integrated circuits, and particularly relates to a high-bandwidth rail-to-rail operational amplifier. The present invention comprises: a three-stage main operational amplifier circuit, which is composed of an input stage module, an intermediate stage module and an output stage module connected in sequence; rail-to-rail input differential signals Vin+ and Vin‑ are input to the input stage module and the intermediate stage module, the input stage module outputs differential signals Vamp+ and Vamp‑ to the intermediate stage module, the intermediate stage module outputs differential signals OUT+ and OUT‑ to the output stage module, and the output stage module outputs a rail-to-rail output signal OUT; a slew rate enhancement circuit, one end of which is connected to the rail-to-rail input differential signals Vin+ and Vin‑, and the other end is connected to the differential signal Vamp+ and a capacitor Cc, and the other end of the capacitor Cc is connected to the rail-to-rail output signal OUT; the present invention improves the output slew rate of the operational amplifier by introducing slew rate enhancement, so as to meet the requirements of high-bandwidth applications.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a high-bandwidth rail-to-rail operational amplifier. Background Art

[0002] Rail-to-rail operational amplifiers are a special type of operational amplifier derived from the low-voltage development trend. The high level of its input and output can reach the power supply voltage, and the low level can be as low as the ground potential; if it is a dual-power application, the low rail can reach or even be lower than the negative power supply. High-performance rail-to-rail operational amplifiers are key building blocks in advanced signal processing systems, supporting the development of high-precision information acquisition, sensor receiving ports, analog filters, and low-noise amplifiers for medical imaging and communication applications. By improving the performance indicators of rail-to-rail operational amplifiers, the overall performance and efficiency of electronic systems can be improved, including improving signal-to-noise ratio, dynamic range, linearity, and power efficiency, thereby achieving better performance and reducing power consumption. Therefore, the study of high-performance rail-to-rail operational amplifiers has become a hot topic in the current field of operational amplifiers.

[0003] In traditional rail-to-rail amplifier circuits, due to the large input voltage range, the output slew rate of the op amp is small when the input swing is large, which cannot meet the needs of high-bandwidth applications. In order to improve the bandwidth, for example, a journal article published by Zhang Yanrong: Design of rail-to-rail operational amplifier with high bandwidth, low noise and low power consumption; by adopting constant current control and four-fold tail current control and other input stage constant transconductance schemes, the flattest possible transconductance curve can be obtained under the condition of fully utilizing the input stage current, but this structure consumes a lot of power, which to a certain extent limits its use in low-power applications. In addition, the trade-off between bandwidth and stability is also a technical problem of high-bandwidth rail-to-rail amplifiers. The traditional structure increases the gain and bandwidth by increasing the number of amplification stages, but the multi-stage structure leads to the introduction of more poles, which causes circuit stability problems. Summary of the invention

[0004] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art. The present invention provides a high-bandwidth rail-to-rail operational amplifier. In order to improve the effective application bandwidth, a slew rate enhancement circuit with a simple structure is designed to improve the output slew rate of the operational amplifier and meet the application requirements of high bandwidth and low power consumption.

[0005] In order to solve the above technical problems, the present invention provides a high-bandwidth rail-to-rail operational amplifier, comprising:

[0006] The three-stage main operational amplifier circuit is composed of an input stage module, an intermediate stage module and an output stage module connected in sequence; rail-to-rail input differential signals Vin+ and Vin- are input to the input stage module and the intermediate stage module, the input stage module outputs differential signals Vamp+ and Vamp- to the intermediate stage module, the intermediate stage module outputs differential signals OUT+ and OUT- to the output stage module, and the output stage module outputs a rail-to-rail output signal OUT;

[0007] A slew rate enhancement circuit, one end of which is connected to the rail-to-rail input differential signals Vin+ and Vin-, and the other end of which is connected to the differential signal Vamp+ and the capacitor Cc, and the other end of which is connected to the rail-to-rail output signal OUT;

[0008] The slew rate enhancement circuit includes: MOS tubes M1 to M16; the source terminals of the MOS tubes M1 and M2 are connected to a grounded current source I2; the gate terminals of the MOS tubes M2 and M1 are connected to rail-to-rail input differential signals Vin+ and Vin-, respectively; the drain terminal of the MOS tube M1 is connected to the drain terminal and gate terminal of the MOS tube M3 and the gate terminal of the MOS tube M4; the drain terminals of the MOS tubes M2 and M4 are connected to the drain terminal and gate terminal of the MOS tube M5 and the gate terminal of the MOS tube M6; the drain terminal of the MOS tube M6 is connected to a grounded current source I3, the drain terminal and gate terminal of the MOS tube M7 and the gate terminal of the MOS tube M8; the source terminal of the MOS tube M7 is grounded; the source terminal of the MOS tube M8 is grounded; the drain terminals of the MOS tube M8 and the MOS tube M16 are connected to a differential signal Vamp+; the gate terminal of the MOS tube M16 is connected to the gate terminal and drain terminal of the MOS tube M15, and a grounded current source I4 and a drain end of the MOS tube M14, the source end of the MOS tube M14 is grounded, the gate end of the MOS tube M14 is connected to the gate end and the drain end of the MOS tube M13, the drain end of the MOS tube M12, and the drain end of the MOS tube M10, the source end of the MOS tube M13 is grounded, the source end of the MOS tube M12 is grounded, the gate end of the MOS tube M12 is connected to the gate end and the drain end of the MOS tube M11, and the drain end of the MOS tube M9, the source end of the MOS tube M11 is grounded, the gate end of the MOS tube M9 is connected to the rail-to-rail input differential signal Vin-, the source end of the MOS tube M9 is connected to the current source I1 and the source end of the MOS tube M10, and the gate end of the MOS tube M10 is connected to the rail-to-rail input differential signal Vin+; the other ends of the current source I1 and the current source I4, the source ends of the MOS tubes M3~M6, and the source ends of the MOS tubes M15~M16 are all connected to the power supply end.

[0009] Preferably, the MOS tubes M1 to M2, M7 to M8 and M11 to M14 are NMOS tubes, and the MOS tubes M5 to M6, M9 to M10 and M15 to M16 constitute PMOS tubes.

[0010] Preferably, the input stage module includes: MOS transistors MC1~MC12 and resistors RC1~RC4; the gate terminals of the MOS transistors MC2 and MOS transistors MC1 are respectively connected to rail-to-rail input differential signals Vin+ and Vin-, the source terminals of the MOS transistors MC1 and MOS transistors MC2 are connected to a 64-fold current source I2, the drain terminal of the MOS transistor MC1 is connected to the source terminal of the MOS transistor MC11 and the grounded resistor RC1; the drain terminal of the MOS transistor MC2 is connected to the source terminal of the MOS transistor MC12 and the grounded resistor RC2; the gate terminal of the MOS transistor MC11 is connected to the gate terminal and the drain terminal of the MOS transistor MC12, and the drain terminal and the differential signal Vamp- of the MOS transistor MC10, the drain terminal of the MOS transistor MC11 is connected to the drain terminal and the differential signal Vamp+ of the MOS transistor MC9, and the gate terminals of the MOS transistors MC9 and MOS transistors MC10 are connected to the bias voltage VC3; the source terminal of the MOS transistor MC9 is connected to the gate terminal of the MOS transistor MC11, and the gate terminal of the MOS transistor MC11 is connected to the gate terminal of the MOS transistor MC12, and the drain terminal and the differential signal Vamp- of the MOS transistor MC10, and the drain terminal of the MOS transistor MC11 is connected to the drain terminal and the differential signal Vamp+ of the MOS transistor MC9, and the gate terminals of the MOS transistor MC10 are connected to the bias voltage VC3; the source terminal of the MOS transistor MC9 is connected to the gate terminal of the MOS transistor MC11. The drain ends of the S transistor MC7 and the MOS transistor MC3, the gate end of the MOS transistor MC3 is connected to the rail-to-rail input differential signal Vin-, the source ends of the MOS transistor MC3 and the MOS transistor MC4 are connected to the grounded 50 times current source I1, the gate end of the MOS transistor MC4 is connected to the rail-to-rail input differential signal Vin+, the drain end of the MOS transistor MC4 is connected to the source end of the MOS transistor MC10 and the drain end of the MOS transistor MC8, and the gate ends of the MOS transistors MC7 and MOS transistors MC8 are connected to the bias voltage VC2; the source end of the MOS transistor MC7 is connected to the drain end of the MOS transistor MC5 and the resistor RC3, and the gate ends of the MOS transistors MC5 and MOS transistors MC6 are connected to the bias voltage VC1; the source end of the MOS transistor MC8 is connected to the drain end of the MOS transistor MC6 and the resistor RC4, and the other ends of the resistors RC3~RC4, the source ends of the MOS transistors MC5~MC6 and the other end of the 64 times current source I2 are all connected to the power supply end.

[0011] Preferably, the MOS transistors MC1 - MC2 constitute a PMOS complementary differential input pair of transistors, and the MOS transistors MC3 - MC4 constitute a NMOS complementary differential input pair of transistors.

[0012] Preferably, the MOS transistors MC5 - MC10 form two groups of PMOS cascode current mirrors, and the MOS transistors MC11 - MC12 form two groups of NMOS cascode current mirrors.

[0013] Preferably, the intermediate module includes: MOS transistors Q13 to Q28; the gate terminals of the MOS transistors Q13 and Q14 are respectively connected to differential signals Vamp+ and Vamp-, the source terminals of the MOS transistors Q13 and Q14 are connected to a current source I3, the drain terminal of the MOS transistor Q13 is connected to the drain terminals of the MOS transistors Q15 and Q27 and the source terminal of the MOS transistor Q25 and is connected to a node P1, the drain terminal of the MOS transistor Q14 is connected to the drain terminals of the MOS transistors Q16 and Q28 The drain end and the source end of the MOS transistor Q26 are connected to the node P2; the gate ends of the MOS transistor Q16 and the MOS transistor Q15 are respectively connected to the rail-to-rail input differential signals Vin+ and Vin-, and the source ends of the MOS transistor Q16 and the MOS transistor Q15 are connected to the current source I4; the source ends of the MOS transistor Q27 and the MOS transistor Q28 are grounded, and the gate ends of the MOS transistor Q27 and the MOS transistor Q28 are connected to the drain ends of the MOS transistor Q25 and the MOS transistor Q23; the gate ends of the MOS transistor Q25 and the MOS transistor Q26 are connected to the drain ends of the MOS transistor Q25 and the MOS transistor Q23; The gate terminals of the MOS transistors Q23 and Q24 are connected to the bias voltage Vb7, the gate terminals of the MOS transistors Q23 and Q24 are connected to the bias voltage Vb6, the source terminals of the MOS transistors Q24 and Q26 are connected to the differential signals OUT+ and OUT- respectively; the source terminal of the MOS transistor Q23 is connected to the drain terminals of the MOS transistors Q21, Q17 and Q19 and is connected to the node N1, the gate terminals of the MOS transistors Q21 and Q22 are connected to the bias voltage Vb5; the source terminal of the MOS transistor Q24 ... gate terminal of the MOS transistor Q24 is connected to The drain ends of the MOS transistors Q22, Q20 and Q18 are connected to the node N2, the gate ends of the MOS transistors Q19 and Q20 are connected to the bias voltage Vb4, the gate ends of the MOS transistors Q18 and Q17 are respectively connected to the rail-to-rail input differential signals Vin+ and Vin-, the source ends of the MOS transistors Q17 and Q18 are connected to the grounded current source I5; the other ends of the current source I3 and the current source I4, and the source ends of the MOS transistors Q19 to Q22 are all connected to the power supply end.

[0014] Preferably, the MOS transistors Q13 - Q14 and the MOS transistors Q15 - Q16 constitute two groups of PMOS differential input pair transistors, and the MOS transistors Q17 - Q18 constitute one group of NMOS differential input pair transistors.

[0015] Preferably, the MOS transistors Q21 to Q24 form two groups of PMOS cascode current mirrors, and the MOS transistors Q25 to Q28 form two groups of NMOS cascode current mirrors.

[0016] Preferably, the output stage module includes: the output stage module includes: MOS tubes T1~T18; the source ends of the MOS tubes T1~T2, MOS tubes T13~T14 and one end of the current source I9 are all connected to the power supply end; the gate ends of the MOS tube T1 and the MOS tube T2 are connected to the bias voltage Vb3, the drain end of the MOS tube T1 is connected to the source end of the MOS tube T3 and the node N1, the drain end of the MOS tube T2 is connected to the source end of the MOS tube T4, the node N2 and one end of the compensation capacitor Cc2, the compensation capacitor The other end of Cc2 is connected to the rail-to-rail output signal OUT; the gate ends of the MOS transistors T3 and T4 are connected to the bias voltage VBN, the drain end of the MOS transistor T4 is connected to the source end of the MOS transistor T6, the drain end of the MOS transistor T8 and the gate end of the MOS transistor T17 and is connected to the differential signal OUT+; the drain end of the MOS transistor T6 is connected to the source end of the MOS transistor T8, the drain end of the MOS transistor T10 and the gate end of the MOS transistor T18 and is connected to the differential signal OUT-; the drain end of the MOS transistor T3 is connected to the source end of the MOS transistor T9, the drain end of the MOS transistor T10 and the gate end of the MOS transistor T18 and is connected to the differential signal OUT-. The gate terminals of the MOS tubes T9 and T10 are connected to the bias voltage VBP; the source terminal of the MOS tube T9 is connected to the node P1 and the drain terminal of the MOS tube T11; the source terminals of the MOS tubes T11, T12, T16 and T18 and one end of the current source I8 are all grounded; the drain terminal of the MOS tube T12 is connected to the node P2, the source terminal of the MOS tube T10 and one end of the compensation capacitor Cc1; the The other end is connected to the rail-to-rail output signal OUT; the other end of the current source I8 is connected to the gate end of the MOS tube T6, the drain end and the gate end of the MOS tube T14, and the source end of the MOS tube T14 is connected to the drain end and the gate end of the MOS tube T13; the other end of the current source I9 is ​​connected to the gate end of the MOS tube T8, the drain end and the gate end of the MOS tube T15, and the source end of the MOS tube T15 is connected to the drain end and the gate end of the MOS tube T16; the drain ends of the MOS tubes T17 and T18 are connected and connected to the rail-to-rail output signal OUT.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] In order to meet the problem of slow circuit operation when inputting a large swing amplitude, the present invention introduces slew rate enhancement to improve the output slew rate of the operational amplifier, thereby meeting the requirements of high-bandwidth applications; a multi-stage structure is adopted to meet the requirements of high gain performance and other performance within a certain reasonable range, and noise is reduced by increasing the area of ​​the operational amplifier input pair tube. Compared with the traditional high-bandwidth structure, the present invention has a simple structure, a significant effect of improving bandwidth, and meets the application requirements of low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1It is a circuit diagram of a high-bandwidth rail-to-rail operational amplifier of the present invention.

[0020] Figure 2 It is a circuit diagram of the slew rate enhancement circuit of the present invention.

[0021] Figure 3 Schematic diagram of the circuit of the input stage module of the present invention.

[0022] Figure 4 Schematic diagram of the circuit of the intermediate module of the present invention.

[0023] Figure 5 Schematic diagram of the circuit of the output stage module of the present invention. DETAILED DESCRIPTION

[0024] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0025] like Figure 1 and Figure 2 As shown, an embodiment of the present invention discloses a high-bandwidth rail-to-rail operational amplifier, comprising:

[0026] The three-stage main operational amplifier circuit is composed of an input stage module, an intermediate stage module and an output stage module connected in sequence; rail-to-rail input differential signals Vin+ and Vin- are input to the input stage module and the intermediate stage module, the input stage module outputs differential signals Vamp+ and Vamp- to the intermediate stage module, the intermediate stage module outputs differential signals OUT+ and OUT- to the output stage module, and the output stage module outputs a rail-to-rail output signal OUT;

[0027] A slew rate enhancement circuit, one end of which is connected to the rail-to-rail input differential signals Vin+ and Vin-, and the other end of which is connected to the differential signal Vamp+ and the capacitor Cc, and the other end of which is connected to the rail-to-rail output signal OUT;

[0028] In order to overcome the large input swing, which causes the operational amplifier to work slowly, a slew rate enhancement circuit is introduced, which includes: MOS tubes M1~M16; the source ends of the MOS tubes M1 and M2 are connected to a grounded current source I2; the gate ends of the MOS tubes M2 and M1 are connected to rail-to-rail input differential signals Vin+ and Vin-, respectively; the drain end of the MOS tube M1 is connected to the drain end and gate end of the MOS tube M3 and the gate end of the MOS tube M4; the drain ends of the MOS tubes M2 and M4 are connected to the drain end and gate end of the MOS tube M5 and the gate end of the MOS tube M6; the drain end of the MOS tube M6 is connected to the grounded current source I3, the drain end and gate end of the MOS tube M7 and the gate end of the MOS tube M8; the source end of the MOS tube M7 is grounded; the source end of the MOS tube M8 is grounded; the drain ends of the MOS tubes M8 and M16 are connected to the differential signal Vamp+; the gate end of the MOS tube M16 is connected to the M The gate and drain of the MOS tube M15, and the grounded current source I4 and the drain of the MOS tube M14, the source of the MOS tube M14 is grounded, the gate of the MOS tube M14 is connected to the gate and drain of the MOS tube M13 and the drain of the MOS tube M12, and the drain of the MOS tube M10, the source of the MOS tube M13 is grounded, the source of the MOS tube M12 is grounded, the gate of the MOS tube M12 is connected to the gate, drain and The drain end of the MOS tube M9 and the source end of the MOS tube M11 are grounded, the gate end of the MOS tube M9 is connected to the rail-to-rail input differential signal Vin-, the source end of the MOS tube M9 is connected to the current source I1 and the source end of the MOS tube M10, and the gate end of the MOS tube M10 is connected to the rail-to-rail input differential signal Vin+; the other ends of the current source I1 and the current source I4, the source ends of the MOS tubes M3~M6 and the MOS tubes M15~M16 are all connected to the power supply end.

[0029] The MOS transistors M1 - M2 , MOS transistors M7 - M8 , and MOS transistors M11 - M14 are NMOS transistors, and the MOS transistors M5 - M6 , MOS transistors M9 - M10 , and MOS transistors M15 - M16 constitute PMOS transistors.

[0030] The tail current source of the above slew rate enhancement circuit is also provided by the bias circuit of the overall circuit. When the circuit is working normally, the voltage difference between Vin+ and Vin- is not very large. GS The left and right currents are equal, and the width-to-length ratio of M12 is much larger than that of M13, so M13 will not be turned on in the circuit, and M15 and M16 are in the cut-off state. Similarly, when the circuit is working normally, M7 and M8 are in the cut-off state, and M16 and M8 are in the high impedance state, which will not affect the working state of the subsequent circuit connected to Vamp+. Design the width-to-length ratio of M5, M6, M13, and M14 to be k times, that is:

[0031] ;

[0032] When the operational amplifier flips due to the large difference in the differential signal at the input, the current in M1 and M3, M9 and M11 is:

[0033] ;

[0034] Then the current in M2 and M4, M10 and M12 is

[0035] ;

[0036] From the above formula, we can get:

[0037] ;

[0038] ;

[0039] Then the flip voltage V is:

[0040] ;

[0041] In the above formula is the MOSFET gate oxide capacitance, μ p , n are the electron mobility of PMOS and NMOS tubes, V TH is the threshold voltage of the MOS tube, V GS2,10 is the gate-source voltage of M2 and M10, V GS1,9 is the gate-source voltage of M1 and M2, (W / L) 1,9 is the width-to-length ratio of M1 and M9.

[0042] According to the above formula, the size of the key MOS tube can be adjusted to change the flip voltage. When the differential signal at the input end of the slew rate enhancement circuit of the operational amplifier has a voltage exceeding the flip threshold, the current mirror M8 or M16 is turned on, and the current is output proportionally through the current mirror. The fast output current charges the Miller capacitor of the first output stage of the main operational amplifier that is connected across the final output stage, and is connected to the Vamp+ end, thereby achieving the purpose of enhancing the slew rate of the operational amplifier.

[0043] like Figure 3As shown, the main function of the input stage module is to amplify the input rail-to-rail differential signal, and this stage adopts a high-gain folding structure to achieve this. The input stage module includes: MOS transistors MC1~MC12 and resistors RC1~RC4; the gate ends of the MOS transistors MC2 and MOS transistors MC1 are respectively connected to rail-to-rail input differential signals Vin+ and Vin-, the source ends of the MOS transistors MC1 and MOS transistors MC2 are connected to a 64-fold current source I2, the drain end of the MOS transistor MC1 is connected to the source end of the MOS transistor MC11 and the grounded resistor RC1; the drain end of the MOS transistor MC2 is connected to the source end of the MOS transistor MC12 and the grounded resistor RC2; the gate end of the MOS transistor MC11 is connected to the gate end and the drain end of the MOS transistor MC12, and the drain end and the differential signal Vamp- of the MOS transistor MC10, the drain end of the MOS transistor MC11 is connected to the drain end and the differential signal Vamp+ of the MOS transistor MC9, and the gate ends of the MOS transistors MC9 and MOS transistors MC10 are connected to the bias voltage VC3; the source end of the MOS transistor MC9 is connected to the gate end of the MOS transistor MC11, and the gate end of the MOS transistor MC10 is connected to the bias voltage VC4; the source end of the MOS transistor MC9 is connected to the gate end of the MOS transistor MC11, and the gate end of the MOS transistor MC11 is connected to the gate end and the drain end of the MOS transistor MC12, and the drain end and the differential signal Vamp- of the MOS transistor MC10, and the drain end of the MOS transistor MC11 is connected to the drain end and the differential signal Vamp+ of the MOS transistor MC9, and the gate ends of the MOS transistor MC10 are connected to the bias voltage VC3; the source end of the MOS transistor MC9 is connected to the gate end of the MOS transistor MC11. The gate end of the MOS transistor MC3 is connected to the rail-to-rail input differential signal Vin-, the source ends of the MOS transistor MC3 and the MOS transistor MC4 are connected to the grounded 50 times current source I1, the gate end of the MOS transistor MC4 is connected to the rail-to-rail input differential signal Vin+, the drain end of the MOS transistor MC4 is connected to the source end of the MOS transistor MC10 and the drain end of the MOS transistor MC8, and the gate ends of the MOS transistor MC7 and the MOS transistor MC8 are connected to the bias voltage VC2; the source end of the MOS transistor MC7 is connected to the drain end of the MOS transistor MC5 and the resistor RC3, and the gate ends of the MOS transistor MC5 and the MOS transistor MC6 are connected to the bias voltage VC1; the source end of the MOS transistor MC8 is connected to the drain end of the MOS transistor MC6 and the resistor RC4, and the other end of the resistors RC3~RC4, the source ends of the MOS transistors MC5~MC6 and the other end of the 64 times current source I2 are all connected to the power supply end.

[0044] The MOS transistors MC1 and MC2 form a PMOS complementary differential input pair of transistors, and the MOS transistors MC3 and MC4 form an NMOS complementary differential input pair of transistors.

[0045] The MOS transistors MC5 - MC10 form two groups of PMOS cascode current mirrors, and the MOS transistors MC11 - MC12 form two groups of NMOS cascode current mirrors.

[0046] Then the input stage gain can be expressed as:

[0047] ;

[0048] In the above formula, is the total equivalent input transconductance, and are the transconductances of the PMOS tube MC10 and the NMOS tube MC12, and The equivalent output impedance of the PMOS tube MC10 and the NMOS tube MC12 is, , , are the equivalent output impedances of PMOS tube MC6, PMOS tube MC8, and PMOS tube MC2 respectively. and is the resistance value of resistor RC2 and resistor RC4, and “ / / ” is the resistor parallel operation symbol.

[0049] like Figure 4As shown, the main function of the intermediate stage module is to provide a high gain stage, and this stage directly drives the output stage. The intermediate stage module includes: MOS transistors Q13~Q28; the gate ends of the MOS transistors Q13 and Q14 are respectively connected to the differential signals Vamp+ and Vamp-, the source ends of the MOS transistors Q13 and Q14 are connected to the current source I3, the drain end of the MOS transistor Q13 is connected to the drain ends of the MOS transistors Q15 and Q27 and the source end of the MOS transistor Q25 and is connected to the node P1, the drain end of the MOS transistor Q14 is connected to the drain ends of the MOS transistors Q16 and Q28 to and the source end of the MOS transistor Q26 and connected to the node P2; the gate ends of the MOS transistor Q16 and the MOS transistor Q15 are respectively connected to the rail-to-rail input differential signals Vin+ and Vin-, and the source ends of the MOS transistor Q16 and the MOS transistor Q15 are connected to the current source I4; the source ends of the MOS transistor Q27 and the MOS transistor Q28 are grounded, and the gate ends of the MOS transistor Q27 and the MOS transistor Q28 are connected to the drain ends of the MOS transistor Q25 and the MOS transistor Q23; the gate ends of the MOS transistor Q25 and the MOS transistor Q26 are connected The bias voltage Vb7 is connected to the gate terminals of the MOS transistors Q23 and Q24, and the source terminals of the MOS transistors Q24 and Q26 are connected to the differential signals OUT+ and OUT-, respectively; the source terminal of the MOS transistor Q23 is connected to the drain terminals of the MOS transistors Q21, Q17 and Q19 and connected to the node N1, and the gate terminals of the MOS transistors Q21 and Q22 are connected to the bias voltage Vb5; the source terminal of the MOS transistor Q24 is connected to the drain terminals of the MOS transistors Q21, Q17 and Q19 and connected to the node N1; the gate terminals of the MOS transistors Q21 and Q22 are connected to the bias voltage Vb5; the source terminal of the MOS transistor Q24 is connected to the drain terminals of the MOS transistors Q21, Q17 and Q19 and connected to the node N1; 22. The drain ends of the MOS transistors Q20 and Q18 are connected to the node N2, the gate ends of the MOS transistors Q19 and Q20 are connected to the bias voltage Vb4, the gate ends of the MOS transistors Q18 and Q17 are respectively connected to the rail-to-rail input differential signals Vin+ and Vin-, and the source ends of the MOS transistors Q17 and Q18 are connected to the grounded current source I5; the other ends of the current source I3 and the current source I4, and the source ends of the MOS transistors Q19 to Q22 are all connected to the power supply end.

[0050] The MOS transistors Q13 - Q14 and the MOS transistors Q15 - Q16 form two groups of PMOS differential input pair transistors, and the MOS transistors Q17 - Q18 form a group of NMOS differential input pair transistors.

[0051] The MOS transistors Q21 to Q24 form two groups of PMOS cascode current mirrors, and the MOS transistors Q25 to Q28 form two groups of NMOS cascode current mirrors.

[0052] The bias tubes PMOS tube Q19 and PMOS tube Q20 provide loads for the NMOS differential input pair NMOS tube Q17 and NMOS tube Q18. This stage has differential output, and the outputs are OUT+ and OUT-. The gain expression of this stage is:

[0053] ;

[0054] In the above formula, is the equivalent input impedance of the complementary differential input pair, are the equivalent transconductances of PMOS tubes Q13 and Q14, , are the equivalent transconductances of Q24 and Q26 respectively, , , , , , and They are the equivalent output impedances of Q26, Q28, Q24, Q16, Q22, Q20 and Q18 respectively, and “ / / ” is the resistor parallel operation symbol.

[0055] like Figure 5As shown, the output OUT+ and OUT- of the intermediate stage drive the output power tubes to be PMOS tube T17 and NMOS tube T18 to realize common source amplification, and finally realize the differential to single-ended output OUT. The output stage module includes: MOS tubes T1~T18; the source ends of the MOS tubes T1~T2, MOS tubes T13~T14 and one end of the current source I9 are all connected to the power supply end; the gate ends of the MOS tubes T1 and MOS tubes T2 are connected to the bias voltage Vb3, the drain end of the MOS tube T1 is connected to the source end of the MOS tube T3 and the node N1, the drain end of the MOS tube T2 is connected to the source end of the MOS tube T4, the node N2 and one end of the compensation capacitor Cc2, and the other end of the compensation capacitor Cc2 is connected to the rail pair The gate terminals of the MOS transistors T3 and T4 are connected to the bias voltage VBN, the drain terminal of the MOS transistor T4 is connected to the source terminal of the MOS transistor T6, the drain terminal of the MOS transistor T8 and the gate terminal of the MOS transistor T17 and is connected to the differential signal OUT+; the drain terminal of the MOS transistor T6 is connected to the source terminal of the MOS transistor T8, the drain terminal of the MOS transistor T10 and the gate terminal of the MOS transistor T18 and is connected to the differential signal OUT-; the drain terminal of the MOS transistor T3 is connected to the drain terminal of the MOS transistor T9, the drain terminal of the MOS transistor T10 and the gate terminal of the MOS transistor T18 and is connected to the differential signal OUT-. The gate ends of the MOS transistor T11 and the MOS transistor T12, and the gate ends of the MOS transistor T9 and the MOS transistor T10 are connected to the bias voltage VBP; the source end of the MOS transistor T9 is connected to the node P1 and the drain end of the MOS transistor T11, the source ends of the MOS transistors T11, T12, T16 and T18 and one end of the current source I8 are all grounded, the drain end of the MOS transistor T12 is connected to the node P2, the source end of the MOS transistor T10 and one end of the compensation capacitor Cc1, and the other end of the compensation capacitor Cc1 is connected to the ground. The rail-to-rail output signal OUT is connected; the other end of the current source I8 is connected to the gate end of the MOS tube T6, the drain end and the gate end of the MOS tube T14, and the source end of the MOS tube T14 is connected to the drain end and the gate end of the MOS tube T13; the other end of the current source I9 is ​​connected to the gate end of the MOS tube T8, the drain end and the gate end of the MOS tube T15, and the source end of the MOS tube T15 is connected to the drain end and the gate end of the MOS tube T16; the drain ends of the MOS tubes T17 and T18 are connected and connected to the rail-to-rail output signal OUT.

[0056] The gate bias voltage of the output power tube T18 is generated by the bias current I9, the diode connected NMOS tubes T15 and T16 and the NMOS tube T8, wherein the bias current I9 and the diode connected NMOS tubes T15 and T16 generate the bias voltage VBN, then VBN is connected to the gate of the NMOS tube T8, and the output drain voltage provides the gate bias voltage for T18; the gate bias voltage of the output power tube T17 is generated by the bias current I8, the diode connected PMOS tubes T13 and T14 and the PMOS tube T6, wherein the bias current I8 and the diode connected PMOS tubes T13 and T14 generate the bias voltage VBP, then VBP is connected to the gate of the PMOS tube T6, and the output drain voltage provides the gate bias voltage for T17. The size of the static current in the output pair tube is determined by the two current loops of T17, T6, T13, T14 and T18, T8, T15, T16, and the bias loop has:

[0057] ;

[0058] ;

[0059] Properly adjust T6, T14, T8, T15 so that their gate-source voltage V GS have , When the relationship is:

[0060] ;

[0061] ;

[0062] If the loop current ,at the same time , then

[0063] ;

[0064] In this way, the bias loop can determine the output quiescent current and will not change due to changes in the common-mode input voltage. 4 、T 10 The drain node of the output stage is short-circuited and in high impedance state, and the gain of the input stage is maintained. The gain expression of the output stage is:

[0065] ;

[0066] In the above formula, , are the equivalent transconductances of the output power tubes PMOS tube T17 and NMOS tube T18, respectively. , are the equivalent output impedances of T18 and T17 respectively.

[0067] In summary, the total voltage gain of the rail-to-rail amplifier of the present invention is:

[0068] .

[0069] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A high bandwidth rail-to-rail operational amplifier, characterized in that: include: The three-stage main operational amplifier circuit is composed of an input stage module, an intermediate stage module and an output stage module connected in sequence; rail-to-rail input differential signals Vin+ and Vin- are input to the input stage module and the intermediate stage module, the input stage module outputs differential signals Vamp+ and Vamp- to the intermediate stage module, the intermediate stage module outputs differential signals OUT+ and OUT- to the output stage module, and the output stage module outputs a rail-to-rail output signal OUT; A slew rate enhancement circuit, one end of which is connected to the rail-to-rail input differential signals Vin+ and Vin-, and the other end of which is connected to the differential signal Vamp+ and the capacitor Cc, and the other end of which is connected to the rail-to-rail output signal OUT; The slew rate enhancement circuit includes: MOS tubes M1 to M16; the source terminals of the MOS tubes M1 and M2 are connected to a grounded current source I2; the gate terminals of the MOS tubes M2 and M1 are connected to rail-to-rail input differential signals Vin+ and Vin-, respectively; the drain terminal of the MOS tube M1 is connected to the drain terminal and gate terminal of the MOS tube M3 and the gate terminal of the MOS tube M4; the drain terminals of the MOS tubes M2 and M4 are connected to the drain terminal and gate terminal of the MOS tube M5 and the gate terminal of the MOS tube M6; the drain terminal of the MOS tube M6 is connected to a grounded current source I3, the drain terminal and gate terminal of the MOS tube M7 and the gate terminal of the MOS tube M8; the source terminal of the MOS tube M7 is grounded; the source terminal of the MOS tube M8 is grounded; the drain terminals of the MOS tube M8 and the MOS tube M16 are connected to a differential signal Vamp+; the gate terminal of the MOS tube M16 is connected to the gate terminal and drain terminal of the MOS tube M15, and a grounded current source I4 and a drain end of a MOS tube M14, the source end of the MOS tube M14 is grounded, the gate end of the MOS tube M14 is connected to the gate end and the drain end of the MOS tube M13, the drain end of the MOS tube M12, and the drain end of the MOS tube M10, the source end of the MOS tube M13 is grounded, the source end of the MOS tube M12 is grounded, the gate end of the MOS tube M12 is connected to the gate end and the drain end of the MOS tube M11, and the drain end of the MOS tube M9, the source end of the MOS tube M11 is grounded, the gate end of the MOS tube M9 is connected to the rail-to-rail input differential signal Vin-, the source end of the MOS tube M9 is connected to the current source I1 and the source end of the MOS tube M10, and the gate end of the MOS tube M10 is connected to the rail-to-rail input differential signal Vin+; the other ends of the current source I1 and the current source I4, the source ends of the MOS tubes M3~M6, and the source ends of the MOS tubes M15~M16 are all connected to the power supply end; The MOS transistors M1 - M2 , MOS transistors M7 - M8 , and MOS transistors M11 - M14 are NMOS transistors, and the MOS transistors M5 - M6 , MOS transistors M9 - M10 , and MOS transistors M15 - M16 constitute PMOS transistors.

2. A high bandwidth rail-to-rail operational amplifier as claimed in claim 1, characterized in that: The input stage module includes: MOS transistors MC1~MC12 and resistors RC1~RC4; the gate ends of the MOS transistors MC2 and MOS transistors MC1 are respectively connected to rail-to-rail input differential signals Vin+ and Vin-, the source ends of the MOS transistors MC1 and MOS transistors MC2 are connected to a 64-fold current source I2, the drain end of the MOS transistor MC1 is connected to the source end of the MOS transistor MC11 and the grounded resistor RC1; the drain end of the MOS transistor MC2 is connected to the source end of the MOS transistor MC12 and the grounded resistor RC2; the gate end of the MOS transistor MC11 is connected to the gate end and the drain end of the MOS transistor MC12, and the drain end and the differential signal Vamp- of the MOS transistor MC10, the drain end of the MOS transistor MC11 is connected to the drain end and the differential signal Vamp+ of the MOS transistor MC9, and the gate ends of the MOS transistors MC9 and MOS transistors MC10 are connected to the bias voltage VC3; the source end of the MOS transistor MC9 is connected to the gate end of the MOS transistor MC11, and the gate end of the MOS transistor MC10 is connected to the bias voltage VC4; the source end of the MOS transistor MC9 is connected to the gate end of the MOS transistor MC11, and the gate end of the MOS transistor MC11 is connected to the gate end and the drain end of the MOS transistor MC12, and the drain end and the differential signal Vamp- of the MOS transistor MC10, and the drain end of the MOS transistor MC11 is connected to the drain end and the differential signal Vamp+ of the MOS transistor MC9, and the gate ends of the MOS transistor MC10 are connected to the bias voltage VC3; the source end of the MOS transistor MC9 is connected to the gate end of the MOS transistor MC11. The gate end of the MOS transistor MC3 is connected to the rail-to-rail input differential signal Vin-, the source ends of the MOS transistor MC3 and the MOS transistor MC4 are connected to the grounded 50 times current source I1, the gate end of the MOS transistor MC4 is connected to the rail-to-rail input differential signal Vin+, the drain end of the MOS transistor MC4 is connected to the source end of the MOS transistor MC10 and the drain end of the MOS transistor MC8, and the gate ends of the MOS transistor MC7 and the MOS transistor MC8 are connected to the bias voltage VC2; the source end of the MOS transistor MC7 is connected to the drain end of the MOS transistor MC5 and the resistor RC3, and the gate ends of the MOS transistor MC5 and the MOS transistor MC6 are connected to the bias voltage VC1; the source end of the MOS transistor MC8 is connected to the drain end of the MOS transistor MC6 and the resistor RC4, and the other end of the resistors RC3~RC4, the source ends of the MOS transistors MC5~MC6 and the other end of the 64 times current source I2 are all connected to the power supply end.

3. A high bandwidth rail-to-rail operational amplifier as claimed in claim 2, characterized in that: The MOS transistors MC1 and MC2 form a PMOS complementary differential input pair of transistors, and the MOS transistors MC3 and MC4 form an NMOS complementary differential input pair of transistors.

4. A high bandwidth rail-to-rail operational amplifier as claimed in claim 2, characterized in that: The MOS transistors MC5 - MC10 form two groups of PMOS cascode current mirrors, and the MOS transistors MC11 - MC12 form two groups of NMOS cascode current mirrors.

5. A high bandwidth rail-to-rail operational amplifier as claimed in claim 1, characterized in that: The intermediate module includes: MOS transistors Q13 to Q28; the gate terminals of the MOS transistors Q13 and Q14 are connected to differential signals Vamp+ and Vamp-, respectively; the source terminals of the MOS transistors Q13 and Q14 are connected to a current source I3; the drain terminal of the MOS transistor Q13 is connected to the drain terminals of the MOS transistors Q15 and Q27 and the source terminal of the MOS transistor Q25 and is connected to a node P1; the drain terminal of the MOS transistor Q14 is connected to the drain terminals of the MOS transistors Q16 and Q28 and is connected to a node P2. and the source end of the MOS transistor Q26 and connected to the node P2; the gate ends of the MOS transistor Q16 and the MOS transistor Q15 are respectively connected to the rail-to-rail input differential signals Vin+ and Vin-, and the source ends of the MOS transistor Q16 and the MOS transistor Q15 are connected to the current source I4; the source ends of the MOS transistor Q27 and the MOS transistor Q28 are grounded, and the gate ends of the MOS transistor Q27 and the MOS transistor Q28 are connected to the drain ends of the MOS transistor Q25 and the MOS transistor Q23; the gate ends of the MOS transistor Q25 and the MOS transistor Q26 are connected The bias voltage Vb7 is connected to the gate terminals of the MOS transistors Q23 and Q24, and the source terminals of the MOS transistors Q24 and Q26 are connected to the differential signals OUT+ and OUT-, respectively; the source terminal of the MOS transistor Q23 is connected to the drain terminals of the MOS transistors Q21, Q17 and Q19 and connected to the node N1, and the gate terminals of the MOS transistors Q21 and Q22 are connected to the bias voltage Vb5; the source terminal of the MOS transistor Q24 is connected to the drain terminals of the MOS transistors Q21, Q17 and Q19 and connected to the node N1; the gate terminals of the MOS transistors Q21 and Q22 are connected to the bias voltage Vb5; the source terminal of the MOS transistor Q24 is connected to the drain terminals of the MOS transistors Q21, Q17 and Q19 and connected to the node N1; 22. The drain ends of the MOS transistors Q20 and Q18 are connected to the node N2, the gate ends of the MOS transistors Q19 and Q20 are connected to the bias voltage Vb4, the gate ends of the MOS transistors Q18 and Q17 are respectively connected to the rail-to-rail input differential signals Vin+ and Vin-, and the source ends of the MOS transistors Q17 and Q18 are connected to the grounded current source I5; the other ends of the current source I3 and the current source I4, and the source ends of the MOS transistors Q19 to Q22 are all connected to the power supply end.

6. A high bandwidth rail-to-rail operational amplifier as claimed in claim 5, characterized in that: The MOS transistors Q13 - Q14 and the MOS transistors Q15 - Q16 form two groups of PMOS differential input pair transistors, and the MOS transistors Q17 - Q18 form a group of NMOS differential input pair transistors.

7. A high bandwidth rail-to-rail operational amplifier as claimed in claim 5, characterized in that: The MOS transistors Q21 to Q24 form two groups of PMOS cascode current mirrors, and the MOS transistors Q25 to Q28 form two groups of NMOS cascode current mirrors.

8. The high bandwidth rail-to-rail operational amplifier according to claim 1, characterized in that: The output stage module includes: MOS transistors T1~T18; the source ends of the MOS transistors T1~T2, MOS transistors T13~T14 and one end of the current source I9 are all connected to the power supply end; the gate ends of the MOS transistors T1 and T2 are connected to the bias voltage Vb3, the drain end of the MOS transistor T1 is connected to the source end of the MOS transistor T3 and the node N1, the drain end of the MOS transistor T2 is connected to the source end of the MOS transistor T4, the node N2 and one end of the compensation capacitor Cc2, and the other end of the compensation capacitor Cc2 is connected to the rail The gate terminals of the MOS transistors T3 and T4 are connected to the bias voltage VBN, the drain terminal of the MOS transistor T4 is connected to the source terminal of the MOS transistor T6, the drain terminal of the MOS transistor T8 and the gate terminal of the MOS transistor T17 and is connected to the differential signal OUT+; the drain terminal of the MOS transistor T6 is connected to the source terminal of the MOS transistor T8, the drain terminal of the MOS transistor T10 and the gate terminal of the MOS transistor T18 and is connected to the differential signal OUT-; the drain terminal of the MOS transistor T3 is connected to the drain terminal of the MOS transistor T9, the drain terminal of the MOS transistor T10 and the gate terminal of the MOS transistor T18 and is connected to the differential signal OUT-. The gate ends of the MOS transistor T11 and the MOS transistor T12, and the gate ends of the MOS transistor T9 and the MOS transistor T10 are connected to the bias voltage VBP; the source end of the MOS transistor T9 is connected to the node P1 and the drain end of the MOS transistor T11, the source ends of the MOS transistors T11, T12, T16 and T18 and one end of the current source I8 are all grounded, the drain end of the MOS transistor T12 is connected to the node P2, the source end of the MOS transistor T10 and one end of the compensation capacitor Cc1, and the other end of the compensation capacitor Cc1 is connected to the ground. The rail-to-rail output signal OUT is connected; the other end of the current source I8 is connected to the gate end of the MOS tube T6, the drain end and the gate end of the MOS tube T14, and the source end of the MOS tube T14 is connected to the drain end and the gate end of the MOS tube T13; the other end of the current source I9 is ​​connected to the gate end of the MOS tube T8, the drain end and the gate end of the MOS tube T15, and the source end of the MOS tube T15 is connected to the drain end and the gate end of the MOS tube T16; the drain ends of the MOS tubes T17 and T18 are connected and connected to the rail-to-rail output signal OUT.

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