Low power nonlinear filter circuit

Abstract

The present application relates to filtering technology, and discloses a low-power nonlinear filtering circuit, including: a nonlinear filter for performing nonlinear filtering on an input digital signal; a feedforward equalization filter for performing feedforward equalization filtering on an input digital signal, and the nonlinear filter and the feedforward equalization filter are fused and set to share a first-order tap; a signal-to-noise ratio detection circuit for detecting the signal-to-noise ratio; and a low-power nonlinear coefficient adaptive updating circuit for adaptively adjusting the filter coefficient of the nonlinear filter according to the signal-to-noise ratio detected by the signal-to-noise ratio detection circuit, and smoothly opening or closing the tap of the nonlinear filter to reduce power consumption. The present application can realize the low-power design of VF while maintaining its ability to process nonlinear signals.

Description

Technical Field

[0001] The present application relates to filtering technology, and in particular to low-power nonlinear filtering technology. Background Art

[0002] As chip speeds continue to increase, the problem of nonlinear interference in communication devices has become more serious, negatively affecting communication performance. As an effective nonlinear filter, the Volterra filter (VF) can effectively filter out nonlinear interference by expanding the input signal into a Volterra series and using FIR filtering. However, the number of taps of the VF increases exponentially with the increase in the number of series, resulting in a significant increase in power consumption, which is a major technical difficulty in VF applications. Directly reducing the number of VF taps can reduce power consumption, but it will weaken its nonlinear processing capability and cannot meet communication quality requirements. Therefore, how to reduce the power consumption of the VF while maintaining its good nonlinear processing capability is a technical challenge to be solved.

[0003] There is not much research on low-power design of VF at present. Existing methods such as simply reducing the number of taps or setting a threshold to directly shut down the filter coefficient may cause system performance fluctuations or even cause the feedback loop to collapse. Therefore, these methods are difficult to maintain good nonlinear processing performance of VF while reducing power consumption and nonlinear filter coefficients.

[0004] In summary, how to achieve low-power design of VF while maintaining its ability to process nonlinear signals is still a technical problem worth exploring. Summary of the invention

[0005] The purpose of the present application is to provide a low-power nonlinear filter circuit to solve the problems raised in the above background technology.

[0006] The present application discloses a low-power nonlinear filter circuit, comprising:

[0007] A nonlinear filter is used to perform nonlinear filtering on the input digital signal;

[0008] A feedforward equalization filter, used for performing feedforward equalization filtering on the input digital signal, and the nonlinear filter is integrated with the feedforward equalization filter to share a first-order tap;

[0009] A signal-to-noise ratio detection circuit, used for detecting the signal-to-noise ratio;

[0010] The low-power nonlinear coefficient adaptive updating circuit is used to adaptively adjust the filter coefficient of the nonlinear filter according to the signal-to-noise ratio detected by the signal-to-noise ratio detection circuit, and smoothly open or close the tap of the nonlinear filter to reduce power consumption.

[0011] In a preferred embodiment, it also includes:

[0012] An analog-to-digital converter, used to receive an analog input signal and convert it into a digital signal;

[0013] A decision circuit, used for making a decision on the filtered signal to generate an error signal;

[0014] The decision feedback equalizer is used to perform feedback equalization filtering on the signal after the decision.

[0015] The coefficient updating circuit is used to update the filter coefficient using the error signal.

[0016] In a preferred embodiment, the nonlinear filter includes a plurality of taps, and the plurality of taps perform nonlinear operations of various orders on the input digital signal and perform weighting to achieve nonlinear filtering; and

[0017] The low-power nonlinear coefficient adaptive updating circuit is used to update the filter coefficients of the multiple taps according to the signal-to-noise ratio, so as to smoothly open or close certain taps to reduce power consumption.

[0018] In a preferred embodiment, the low power consumption nonlinear coefficient adaptive updating circuit is used for:

[0019] When the signal-to-noise ratio is higher than a first threshold, smoothly updating the filter coefficients of the taps in the nonlinear filter whose coefficients are smaller than a coefficient threshold to 0, wherein the first threshold is a maximum threshold;

[0020] When the signal-to-noise ratio is lower than a second threshold and higher than a third threshold, keeping the filter coefficient of the tap whose filter coefficient is equal to 0 in the nonlinear filter unchanged, wherein the second threshold is between the first threshold and the third threshold;

[0021] When the signal-to-noise ratio is lower than the third threshold, the filter coefficients of each tap of the nonlinear filter are updated normally, wherein the third threshold is a minimum threshold.

[0022] In a preferred embodiment, the low power consumption nonlinear coefficient adaptive updating circuit comprises:

[0023] a comparator, configured to compare the signal-to-noise ratio with the first threshold, the second threshold, and the third threshold;

[0024] A control signal generating unit, configured to generate control signals S1 and S2 according to the comparison result of the comparator;

[0025] Wherein, the control signals S1 and S2 are used to control the updating method of the filter coefficients of each tap in the nonlinear filter;

[0026] The control signal generating unit is used for:

[0027] When the comparison result shows that the signal-to-noise ratio is higher than the first threshold, a control signal S1 is generated to control the filter coefficients of the taps whose coefficients are less than the coefficient threshold to update to 0;

[0028] When the comparison result shows that the signal-to-noise ratio is lower than the second threshold and higher than the third threshold, a control signal S2 is generated to control the filter coefficient of the tap with the filter coefficient equal to 0 to remain unchanged;

[0029] When the comparison result indicates that the signal-to-noise ratio is lower than the third threshold, no control signal is generated to control the filter coefficients of each tap to be updated normally.

[0030] In a preferred example, the feedforward equalization filter comprises a plurality of taps, and the plurality of taps perform weighted superposition on the input digital signal to implement feedforward equalization filtering;

[0031] The first tap of the nonlinear filter is shared with the first tap of the feedforward equalization filter as a common first tap of the two.

[0032] In a preferred embodiment, the nonlinear and feedforward equalization filter circuit workflow includes:

[0033] Start the feedforward equalizer and detect whether its convergence time t1 is greater than a preset threshold T1 and whether the coefficient change rate is less than a preset threshold L1. If any of the conditions are met, determine that the feedforward equalizer is stable;

[0034] After the feedforward equalizer is stable, the nonlinear filter is started, and its convergence time t2 is detected to be greater than the preset threshold T2 and the coefficient change rate is less than the preset threshold L2. If any of the conditions are met, it is determined that the nonlinear filter is stable.

[0035] After the nonlinear filter is stabilized, the low-power adaptive coefficient update circuit is started.

[0036] In the implementation mode of the present application, a low-power VF circuit is realized through the fusion design of a feedforward equalizer (FFE) and a Volterra filter (VF). This design reduces the first-order taps and effectively reduces the overall complexity of the system and the data transmission delay.

[0037] Furthermore, the startup process of the VF and nonlinear coefficient adaptive update circuit is reasonably planned to ensure the stability of system performance.

[0038] Furthermore, only a small amount of logic circuits are added to realize a low-power nonlinear coefficient adaptive update circuit, which not only ensures the performance of the system but also significantly reduces the power consumption of the VF.

[0039] A large number of technical features are recorded in the specification of this application, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, and the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a structural schematic diagram of a low-power nonlinear filter circuit according to a first embodiment of the present application;

[0041] Figure 2 is a schematic diagram of a nonlinear and feedforward equalization filter circuit of a low-power nonlinear filter circuit according to a first embodiment of the present application;

[0042] Figure 3 It is a schematic diagram of the working process of the nonlinear and feedforward equalization filter circuit of the low-power nonlinear filter circuit according to the first embodiment of the present application;

[0043] Figure 4 It is a schematic diagram of the structure of a low-power nonlinear coefficient adaptive updating circuit of a low-power nonlinear filter circuit according to the first embodiment of the present application;

[0044] Figure 5 It is a schematic diagram of the logic circuit structure of a low-power nonlinear coefficient adaptive update circuit of a low-power nonlinear filter circuit according to the first embodiment of the present application. DETAILED DESCRIPTION

[0045] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0046] Description of some concepts:

[0047] Nonlinear filter: A filter that can remove nonlinear distortion from the input signal. Nonlinear distortion usually comes from nonlinear devices such as amplifiers and mixers. Nonlinear filters remove nonlinear terms of different orders by expanding the input signal.

[0048] Feedforward equalization filter: A filter that pre-equalizes the input signal to improve the performance of subsequent signal processing. It eliminates interference caused by the channel by adjusting the coefficients of each tap.

[0049] Decision circuit: Decision the filtered digital signal to determine the most likely transmitted binary value for each data bit. Soft decision is often used to calculate the probability of each transmitted bit based on the signal amplitude and noise statistics.

[0050] Signal-to-noise ratio detection circuit: Real-time detection of the signal-to-noise ratio of the signal link, usually obtained by comparing the power of the signal and the noise. The signal-to-noise ratio reflects the signal quality.

[0051] Coefficient update circuit: Use the error signal to iteratively update the tap coefficients in the filter to approach the optimal value. Commonly used algorithms are LMS and RLS.

[0052] Tap: The basic unit of a filter that delays and weights the input signal. The number of taps determines the complexity of the filter.

[0053] In the embodiments of the present application, a new low-power nonlinear filter circuit is proposed. In view of the fact that the Volterra filter (VF) has good performance but extremely high power consumption, a filter circuit that integrates the VF and the feedforward equalizer (FFE) is designed, as well as a coefficient adaptive switching method designed for the VF, thereby realizing a low-power nonlinear filter.

[0054] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0055] A first embodiment of the present application relates to a low-power nonlinear filter circuit.

[0056] Figure 1 The overall block diagram of the low power nonlinear filter circuit of this embodiment is shown.

[0057] Among them, the Volterra filter (VF) is a classic and effective nonlinear filter, which can effectively filter out nonlinear interference in the signal.

[0058] like Figure 1 As shown, the low-power nonlinear filtering circuit system includes: an analog-to-digital converter, a nonlinear and feedforward equalization filtering circuit, a coefficient update circuit, a low-power nonlinear coefficient adaptive update circuit, a decision circuit, a decision feedback equalizer, an adder, and an SNR detection circuit.

[0059] Among them, the analog-to-digital converter is used to convert the analog input signal into a digital signal; the nonlinear and feedforward equalization filter circuit is used to perform nonlinear filtering and feedforward equalization filtering; the coefficient update circuit is used to update the filter coefficient using the error signal; the low-power nonlinear coefficient adaptive update circuit is used to adaptively adjust the filter coefficient according to the signal-to-noise ratio; the decision circuit is used to make a decision on the filtered signal; the decision feedback equalizer is used to perform feedback equalization filtering on the signal after the decision; and the SNR detection circuit is used to detect the signal-to-noise ratio. Among them, the nonlinear filter and the feedforward equalization filter are integrated to reduce the system complexity. The traditional coefficient update method may cause system performance fluctuations. The low-power nonlinear coefficient adaptive update circuit of this solution can smoothly turn on / off the filter tap, reducing power consumption while ensuring system performance.

[0060] It should be noted that the analog-to-digital converter receives the analog data from the previous stage, converts it into a discrete signal and sends it to the subsequent stage circuit. In typical chip applications, the subsequent stage circuit is a feedforward equalizer (FFE). In this solution, VF and FFE are integrated to reduce system complexity, chip area and power consumption. The specific method will be described in more detail below.

[0061] The nonlinear and feedforward equalization filter circuit filters the signal and sends it to the subsequent decision feedback equalizer. The coefficient update circuit uses the error calculated by the decision circuit and the input data, adopts the LMS algorithm or the RLS algorithm to update the coefficient, and feeds back the updated coefficient to the nonlinear and feedforward equalization filter circuit. The application innovatively proposes an adaptive coefficient update circuit, which uses the SNR detection circuit and the current coefficient state to perform adaptive control of the coefficient update, thereby realizing the smooth opening and closing of the nonlinear filter tap, greatly reducing the system power consumption while ensuring the system performance.

[0062] This embodiment is described in further detail below.

[0063] Analog-to-digital converter:

[0064] The function of an analog-to-digital converter is to convert a continuous input signal in analog form into a discrete signal in digital form. Its basic working principle is to sample the analog input signal at a certain sampling frequency, and then quantize the amplitude of each sampling point into a discrete digital quantity.

[0065] Optional, common analog-to-digital converters mainly include the following types: dual-integral ADC, successive approximation ADC, flash ADC, and error-resistant ADC, etc.

[0066] Coefficient update circuit:

[0067] The main function of the coefficient update circuit is to use the error signal to iteratively update the tap coefficients in the nonlinear filter and the feedforward equalization filter. Common update algorithms include the LMS (small mean square) algorithm and the RLS (recursive least squares) algorithm. The LMS algorithm recursively adjusts the coefficients in the direction of the negative gradient of the mean square error. It is simple to implement and has a small amount of calculation. The RLS algorithm uses recursive technology to achieve the minimum mean square error and has a fast convergence speed, but the computational complexity is high. Both algorithms require the use of the error signal calculated by the decision circuit and the input signal of the filter to iterate the new coefficients. The coefficient update circuit is usually implemented using a digital circuit, and data storage and digital operations are performed according to the algorithm requirements.

[0068] Low power nonlinear coefficient adaptive update circuit:

[0069] The main function of the low-power nonlinear coefficient adaptive update circuit is to adaptively adjust the filter coefficients of each tap in the nonlinear filter according to the detection result of the signal-to-noise ratio, so as to smoothly open or close certain taps to achieve the purpose of reducing system power consumption.

[0070] Different from the traditional coefficient update circuit, this circuit can not only update the filter coefficient value of each tap, but also selectively shut down some taps according to the signal-to-noise ratio. When the signal-to-noise ratio is high, some taps with smaller coefficients can be smoothly shut down; when the signal-to-noise ratio is low, all taps can be kept working normally.

[0071] The implementation method can be to compare the signal-to-noise ratio with multiple set thresholds, generate different control signals according to the comparison results, and then adjust the filter coefficient update method of each tap according to the control signal. In this way, the on / off state of the tap can be changed smoothly.

[0072] The specific implementation of the circuit will be described in more detail below. This adaptive update method can effectively reduce the power consumption of the filter while ensuring system performance.

[0073] Decision circuit:

[0074] The function of the decision circuit is to make a decision on the filtered digital signal and determine the most likely transmission binary value of each data bit.

[0075] Optionally, the decision circuit uses a soft decision method to make a decision on the digital signal output after the nonlinear filter and the feedforward equalization filter. Specifically, the decision circuit calculates the posterior probability of each possible transmission bit for the digital signal sample of each clock cycle according to its amplitude and current noise statistics. Then, the transmission bit with the largest posterior probability is selected as the decision result.

[0076] For example, if the amplitude of the digital signal sampled by the current clock is +0.2, according to the current channel noise distribution model, the posterior probability of '1' is calculated to be 0.7, and the posterior probability of '0' is 0.3. Then the decision circuit will decide that the transmission bit corresponding to the sample is '1'.

[0077] Next, the decision circuit compares the determined transmission bit with the original digital signal input and obtains the difference as an error signal, which contains the noise of the clock sample and the residual inter-symbol crosstalk.

[0078] Finally, the error signal will be fed back to the coefficient update circuit to iteratively optimize the filter coefficients of the nonlinear filter and the feedforward equalizer.

[0079] Decision Feedback Equalizer:

[0080] The decision feedback equalizer is used to perform feedback equalization filtering on the signal processed by the nonlinear filter and the feedforward equalization filter.

[0081] Adder

[0082] The adder adds the signal output by the decision feedback equalizer to the error signal calculated by the decision circuit. The error signal contains the noise and inter-symbol crosstalk remaining after the input signal passes through the pre-filter. Adding the error signal to the output of the decision feedback equalizer can help eliminate the residual noise and crosstalk and improve the quality of the final signal. The added digital signal will be passed to the subsequent digital signal processing circuit as the final detection output.

[0083] SNR detection circuit:

[0084] The SNR detection circuit detects the current signal to noise ratio (SNR) of the signal transmission link in real time.

[0085] Optionally, a commonly used detection method is to extract the power of the signal and noise in the signal link and calculate the ratio of the two as the SNR. For example, the power of the input and output signals can be calculated by a mean square operation unit, and then the ratio of the two can be taken as the SNR. The SNR can also be estimated by analyzing the relevant characteristics of the signal through feature extraction.

[0086] The obtained SNR will be fed back to the low-power nonlinear coefficient adaptive update circuit to adjust the filter parameters according to the SNR.

[0087] In order to make the technical solution of the present application easier to understand, a more specific exemplary description of the technical solution of the present application is given below.

[0088] Nonlinear and feedforward equalization filter circuits

[0089] Figure 2 It is the schematic diagram of nonlinear and feedforward equalization filter circuit, such as Figure 2 As shown, the nonlinear and feedforward equalization filter circuit includes: a nonlinear filter and a feedforward equalizer.

[0090] Among them, the feedforward equalization filter circuit is a typical chip application.

[0091] Furthermore, the difference between the nonlinear filter circuit and the traditional typical application is that the traditional application is generally connected in series in the back stage of the FFE or the decision feedback equalizer, and the technical solution of the present application innovatively proposes a fusion design of FFE and VF. This design can save the 1st order tap of VF, saving the corresponding area and power consumption, because FFE can be equivalent to the 1st order tap of VF here. In addition, through the fusion design, VF can be equivalent to the newly added tap of FFE in circuit design and back-end wiring, reducing the delay of the main data path of the system, and greatly reducing the difficulty of digital circuit and back-end layout and wiring. The example given by VF in the figure is 2 3rd order taps and 1 2nd order tap, which are d1*d1*d2, d2*d3, d3*d3*d3 respectively. D represents input data, 1 represents the first beat data (no delay), 2 represents the second beat data (delayed one beat, equivalent to the data entered in the previous beat), and 3 represents the third beat data (delayed two beats, equivalent to the data entered in the previous two beats). It should be noted that the actual application is not limited to 3 taps, nor is it limited to the 3rd order taps in the example. Figure 2 Q1, Q2, and Q3 are switching signals from the low-power nonlinear coefficient adaptive update circuit, which can turn off the corresponding taps to reduce power consumption when the conditions are met. Therefore, in this application, VF is not simply connected in series behind FFE, but is integrated with FFE. Moreover, through integration, the first-order tap of FFE can also serve as the first-order tap of VF, which can save the original first-order tap of VF and reduce the amount of hardware and power consumption. Furthermore, under the integrated design, VF can be designed as an extended tap of FFE, which can simplify the data path of the system, reduce signal delay, and facilitate digital circuit and wiring design.

[0092] However, there is a problem with the direct application of this circuit: FFE and VE are both feedback loops, and their joint convergence will cause resonance in the two filters. When the initial error is large, they are prone to converge to the local optimum, resulting in poor overall system performance. In some cases, the feedback loop is difficult to converge, and the coefficient update gradually runs away. In addition, if the adaptive coefficient update circuit is turned on during the VF convergence stage, it will also affect the convergence of the VF, resulting in poor performance.

[0093] This is because both FFE and VF essentially use error signals for closed-loop feedback to adjust their own parameters in order to eliminate residual inter-code crosstalk. When the two filters are iteratively adjusting parameters at the same time, the two feedback loops will affect each other and produce resonance. This resonance will make the adjustment process more complicated and prone to falling into local optimality, resulting in deviations in the ideal parameter search for the two filters. In extreme cases, the interference between the two feedback loops is too large, causing the entire system to lose stability and even cause parameter divergence. In addition, VF itself also requires a stable convergence process. If adaptive power consumption control is turned on before VF converges, it will interfere with its normal convergence, causing VF to ultimately fail to reach the ideal state, resulting in reduced system performance.

[0094] Therefore, in order to solve the above problems, a corresponding workflow is designed.

[0095] The working process of nonlinear and feedforward equalization filter circuit:

[0096] like Figure 3 As shown, after a typical chip startup process, the feedforward equalizer starts to work, and then starts to detect 1. whether the convergence time t1 is greater than the threshold T1; 2. whether the rate of change of all coefficients in the time period T1 is less than the threshold L1. If both judgment conditions are yes, or one of them is yes, the feedforward equalizer can be considered to have converged stably. After confirming stability, start the nonlinear filter, and then start to detect: 1. whether the convergence time t2 is greater than the threshold T2; 2. whether the rate of change of all coefficients in the time period T1 is less than the threshold L2. If both judgment conditions are yes, or one of them is yes, the nonlinear equalizer can be considered to have converged stably. After confirming stability, start the low-power adaptive coefficient update circuit. At this time, the feedforward equalizer and nonlinear filter have converged stably, and the chip enters the normal working process. At this time, the coefficient update starts, which has a small impact on system performance and is within a controllable range.

[0097] In other words, the workflow of the nonlinear and feedforward equalization filter circuit is divided into the following steps:

[0098] 1) The feedforward equalizer (FFE) starts working and determines whether it has converged stably based on the convergence time and coefficient change rate.

[0099] 2) After the FFE is stable, the nonlinear filter (VF) is started, and then the stability of the VF is determined based on the convergence time and the coefficient change rate.

[0100] 3) After VF stabilizes, the low power adaptive coefficient update circuit is started.

[0101] 4) At this time, FFE and VF have converged stably and the system enters normal working state.

[0102] 5) Start adaptively updating the coefficients. Since FFE and VF are stable, the impact of the update on the system is controllable.

[0103] By starting each module step by step, first allowing FFE and VF to converge stably, and then starting adaptive power consumption control, interference between the two can be avoided and the system can be guaranteed to eventually reach an optimized and stable state.

[0104] The basis for judging stability is the convergence time and the coefficient change rate, which can effectively detect whether each filter has reached stable convergence. This process controls the startup timing of each module and achieves the best balance between performance and power consumption.

[0105] Low power nonlinear coefficient adaptive update circuit:

[0106] Figure 4 The working process of low power nonlinear coefficient adaptive updating circuit is given.

[0107] In this application, different taps of the nonlinear filter correspond to different nonlinear interferences, including 2nd order nonlinearity, 3rd order nonlinearity, etc. In the actual application of the chip, it is often necessary to take into account the nonlinear characteristics in various scenarios, so it is necessary to design multi-order taps, and then in different scenarios, the role played by the taps is not the same, resulting in a great waste of power consumption in the tap configuration. The role of the tap is reflected by the tap coefficient. The larger the coefficient, the greater the contribution of the tap to the final output (the output is the cumulative sum of each tap). Therefore, the basic idea of ​​the adaptive coefficient update circuit is to turn off the tap with a smaller coefficient. However, several issues need to be considered: 1. No matter how small the coefficient is, it still has a certain impact on the performance; 2. Direct shutdown is likely to cause performance mutations and even cause the collapse of the feedback loop; 3. After shutdown, how to start smoothly again. In other words, for multi-order taps in nonlinear filters, taps of different orders correspond to processing different levels of nonlinear interference, such as 2nd order and 3rd order nonlinearity. In a variety of application scenarios, these taps have different roles, resulting in the power consumption of the tap becoming a significant waste in some occasions. In addition, the size of the tap coefficient directly affects its contribution to the final output. Therefore, the goal of the adaptive coefficient update circuit is to turn off those taps with smaller coefficients to reduce power consumption. However, this process needs to be handled carefully to avoid performance abrupt changes and feedback loop collapse.

[0108] To address the above issues, this solution proposes a low-power nonlinear coefficient adaptive update circuit, taking into account that even a small coefficient may affect the performance, and the taps need to be smoothly closed and restarted to ensure system performance and stability.

[0109] The circuit input includes the system snr detected by the snr detection circuit, the coefficient threshold parameter wv_L, the snr upper threshold snr_H and the snr lower threshold snr_L configured by the register. After the circuit starts working, it first determines whether the current snr is greater than snr_L. If not, it means that the system performance does not meet the snr lower threshold requirement at this time, so the coefficient is updated normally and the circuit work of this beat ends. If it is yes (snr is greater than snr_L), proceed to the next step. At this time, it is determined whether the snr is greater than snr_H. If not, it means that the snr is in the range of snr_L and snr_H at this time, and the system performance meets the requirements, but the performance should not continue to decrease. Therefore, the coefficient group C1 of the nonlinear filter equal to 0 is found at this time, and then C1 is kept at 0, and the related circuits are turned off to save power consumption, and other coefficients and circuits are updated normally. If yes, then snr is greater than snr_H, the performance exceeds the requirement and can be reduced, so the coefficient group C2 is found to be less than the coefficient threshold wv_L, and the coefficient of C2 is updated to a fixed direction of 0 (the update speed is consistent with the speed of normal update to ensure smooth coefficient update), and other coefficients are updated normally. In other words, in the input parameters and initial judgment process of the low-power nonlinear coefficient adaptive update circuit, the circuit first determines the coefficient update strategy through the SNR value obtained by the signal-to-noise ratio (SNR) detection circuit and the preset coefficient threshold parameters (such as wv_L, snr_H, snr_L). When the system SNR does not reach the preset lower limit (snr_L), the circuit will update the coefficient normally to improve performance. If the SNR is between the preset upper and lower limits, the tap with a smaller contribution will be turned off to save power. If the SNR exceeds the upper limit (snr_H), the performance is actively reduced to reduce power consumption by reducing the contribution of the smaller coefficient tap. This process is fine-tuned to achieve a balance between performance and power consumption.

[0110] Figure 5 The logic circuit diagram of the low-power nonlinear coefficient adaptive update circuit is given, and two 1-bit control signals S1 and S2 will eventually be output to the coefficient update circuit. The coefficient update circuit adjusts the coefficient update logic according to the status of S1 and S2. The S1 and S2 signals will not be pulled high at the same time. When S1 is high, it means that the system performance is good at this time, snr is greater than snr_H, the update of coefficient group C2 is fixed in the direction of 0, and other coefficients are updated normally; when S2 is high, it means that the system performance is within the acceptable range, which is less than snr_H and greater than snr_L. At this time, coefficient group C1 remains 0, and other coefficients and circuits are updated normally; when S1 and S2 are low at the same time, it means that snr is less than snr_L, and the system is updated normally to improve performance. This circuit only needs a simple comparator, a 1-bit adder and some basic logic gates to achieve a significant reduction in system performance at a very low cost.

[0111] That is to say, Figure 5 The states of S1 and S2 in determine how the nonlinear filter coefficients are updated: when S1 is valid, it means that the system performance is good and the SNR is above the upper limit, and some coefficients are gradually reduced to zero; when S2 is valid, it means that the system performance is within an acceptable range, and some coefficients are kept at zero to save power. This logic ensures that power consumption and performance are balanced by accurately controlling coefficient updates under different performance requirements. Optional, simple circuit components (such as comparators and adders) are sufficient to implement this complex logic, effectively reducing the complexity and cost of the design.

[0112] With the above design, when the system's signal-to-noise ratio (SNR) is high, the circuit can smoothly close taps with smaller coefficients to avoid significant performance degradation. At the same time, when the SNR is within an acceptable range, the circuit will keep some taps closed (the coefficient remains zero and the related circuits are turned off) to reduce power consumption. When the SNR is low, the system will run normally to ensure that performance is not affected. This process saves power consumption and ensures stable operation of the system.

[0113] The technical innovations of the above embodiments mainly include:

[0114] By adopting the FFE and VF fusion design, the 1st-order tap of VF can be omitted, the overall complexity of the system and the delay of the main data path can be reduced, which is beneficial to circuit design and back-end wiring, and reduces the area and power consumption of the chip. Furthermore, the startup process of VF is designed, and VF is turned on after the feedforward equalizer is stable to ensure the convergence stability of VF. Furthermore, by adopting a low-power nonlinear coefficient adaptive update circuit, VF-related taps and circuits can be smoothly turned on or off; adding very little logic circuit can effectively reduce system power consumption while ensuring system performance.

[0115] The technical effects of the above embodiments mainly include:

[0116] Firstly, a low-power Volterra filter (VF) circuit is realized through the fusion design of feedforward equalizer (FFE) and Volterra filter (VF). This design reduces the first-order taps and effectively reduces the overall complexity of the system and data transmission delay.

[0117] Furthermore, the startup process of the VF and nonlinear coefficient adaptive update circuit is reasonably planned to ensure the stability of system performance.

[0118] Furthermore, only a small amount of logic circuits are added to realize a low-power nonlinear coefficient adaptive update circuit, which not only ensures the performance of the system but also significantly reduces the power consumption of the VF.

[0119] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0120] All documents mentioned in this application are considered to be included in the disclosure of this application as a whole, so that they can be used as the basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art can make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A low power nonlinear filter circuit, characterized in that: include: A nonlinear filter for performing nonlinear filtering on an input digital signal, wherein the nonlinear filter is a Volterra filter; a feedforward equalization filter for performing feedforward equalization filtering on an input digital signal, and the nonlinear filter and the feedforward equalization filter are integrated and share a first-order tap; a signal-to-noise ratio detection circuit for detecting a signal-to-noise ratio; a low-power nonlinear coefficient adaptive update circuit for adaptively adjusting the filter coefficient of the nonlinear filter according to the signal-to-noise ratio detected by the signal-to-noise ratio detection circuit, and smoothly opening or closing the tap of the nonlinear filter to reduce power consumption; Among them, the working process of the low-power nonlinear filtering circuit is as follows: 1) The feedforward equalization filter starts working, and judges whether it has converged stably according to the convergence time and the coefficient change rate; 2) After the feedforward equalization filter is stable, start the nonlinear filter, and then judge whether the nonlinear filter is stable according to the convergence time and the coefficient change rate; 3) After the nonlinear filter is stable, start the low-power adaptive coefficient update circuit; 4) At this time, the feedforward equalization filter and the nonlinear filter have both converged stably, and the system enters a normal working state; 5) Start adaptively updating the coefficient. Since the feedforward equalization filter and the nonlinear filter are stable, the impact of the update on the system is controllable.

2. The circuit according to claim 1, characterized in that Also includes: An analog-to-digital converter, used to receive an analog input signal and convert it into a digital signal; A decision circuit, used for making a decision on the filtered signal to generate an error signal; A decision feedback equalizer is used to perform feedback equalization filtering on the signal after the decision; The coefficient updating circuit is used to update the filter coefficient using the error signal.

3. The circuit according to claim 1, characterized in that The nonlinear filter includes a plurality of taps, and the plurality of taps perform nonlinear operations of various orders on the input digital signal and perform weighting to achieve nonlinear filtering; and The low-power nonlinear coefficient adaptive updating circuit is used to update the filter coefficients of the multiple taps according to the signal-to-noise ratio, so as to smoothly open or close certain taps to reduce power consumption.

4. The circuit according to claim 3, characterized in that The low power consumption nonlinear coefficient adaptive updating circuit is used for: When the signal-to-noise ratio is higher than a first threshold, smoothly updating the filter coefficients of the taps in the nonlinear filter whose coefficients are smaller than a coefficient threshold to 0, wherein the first threshold is a maximum threshold; When the signal-to-noise ratio is lower than a second threshold and higher than a third threshold, keeping the filter coefficient of the tap whose filter coefficient is equal to 0 in the nonlinear filter unchanged, wherein the second threshold is between the first threshold and the third threshold; When the signal-to-noise ratio is lower than the third threshold, the filter coefficients of each tap of the nonlinear filter are updated normally, wherein the third threshold is a minimum threshold.

5. The circuit according to claim 4, characterized in that The low power consumption nonlinear coefficient adaptive updating circuit comprises: a comparator, configured to compare the signal-to-noise ratio with the first threshold, the second threshold, and the third threshold; A control signal generating unit, configured to generate control signals S1 and S2 according to the comparison result of the comparator; Wherein, the control signals S1 and S2 are used to control the updating method of the filter coefficients of each tap in the nonlinear filter; The control signal generating unit is used for: When the comparison result shows that the signal-to-noise ratio is higher than the first threshold, a control signal S1 is generated to control the filter coefficients of the taps whose coefficients are less than the coefficient threshold to update to 0; When the comparison result shows that the signal-to-noise ratio is lower than the second threshold and higher than the third threshold, a control signal S2 is generated to control the filter coefficient of the tap with the filter coefficient equal to 0 to remain unchanged; When the comparison result indicates that the signal-to-noise ratio is lower than the third threshold, no control signal is generated to control the filter coefficients of each tap to be updated normally.

6. The circuit according to claim 1, characterized in that The feedforward equalization filter comprises a plurality of taps, and the plurality of taps perform weighted superposition on the input digital signal to implement feedforward equalization filtering; The first tap of the nonlinear filter is shared with the first tap of the feedforward equalization filter as a common first tap of the two.

7. The circuit according to claim 1, characterized in that The nonlinear and feedforward equalization filter circuit workflow includes: Start the feedforward equalizer and detect whether its convergence time t1 is greater than a preset threshold T1 and whether the coefficient change rate is less than a preset threshold L1. If any of the conditions are met, determine that the feedforward equalizer is stable; After the feedforward equalizer is stable, the nonlinear filter is started, and its convergence time t2 is detected to be greater than the preset threshold T2 and the coefficient change rate is less than the preset threshold L2. If any of the conditions are met, it is determined that the nonlinear filter is stable. After the nonlinear filter is stabilized, the low-power adaptive coefficient update circuit is started.

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