An edge delay circuit with anti-shake function
By introducing an inverter and charge and discharge circuit into the edge delay circuit, a positive feedback loop is formed, which solves the jitter problem when the edge of the circuit output signal is flipped, improves the anti-interference ability and ensures the stability of the application.
Patent Information
- Application Number
- CN202411515998.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-04-25
- Estimated Expiration
- 2044-10-29
AI Technical Summary
Existing edge delay circuits are prone to jitter when the output signal edge is flipped, resulting in abnormal reset in application scenarios such as power-on reset circuits and switching power supplies or the upper and lower tubes are turned on at the same time, increasing the risk of failure.
An edge delay circuit with anti-shake function is designed. By introducing an inverter and a charge and discharge circuit, a positive feedback loop is formed, which enhances the anti-interference ability of the circuit and reduces jitter during signal output.
It effectively solves the problem of abnormal jitter during the flip of the delay output signal, improves the anti-interference ability of the circuit, and ensures the application stability in the technical field of high-reliable timing control.
Smart Images
Figure CN119051634B_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an edge delay circuit with an anti-shake function. Background Art
[0002] Edge delay circuit is a very commonly used circuit module in integrated circuit design, with various application scenarios. Here are two examples: Example 1: For example, in a power-on reset circuit, when the voltage rises to a certain threshold voltage, a system reset signal needs to be generated, but the power-on voltage may not be stable at this time, and it is necessary to delay for a short period of time before outputting the system reset signal; Example 2: For example, in a BUCK switching power supply or a motor power drive circuit, in order to prevent the upper and lower tubes from being turned on at the same time, an edge delay circuit is needed for adjustment and control.
[0003] Of course, there are many other application scenarios, so I will not list them one by one. Referring to the above two application examples, in these two application scenarios, there are high requirements for the anti-interference ability of the delay circuit. And many delay circuits are prone to jitter when the output signal edge flips. In Example 1, if the delay circuit is interfered with and falsely triggered, an abnormal reset or wrong reset timing will occur, resulting in an unsuccessful reset; in Example 2, if the delay circuit is interfered with, resulting in an abnormal flip, it is possible that the upper and lower tubes will be turned on at the same time at a certain moment, which will eventually cause the risk of the MOS tube burning through.
[0004] In view of the above situation, the present invention designs an edge delay circuit with an anti-shake function, which can increase the anti-interference ability of the delay circuit to solve the abnormal jitter problem in the process of delay output signal flipping. Summary of the invention
[0005] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art. The present invention provides an edge delay circuit with an anti-shake function, which has a high anti-interference ability, and in particular can well solve the abnormal jitter problem that is easy to occur during the flipping process of the delayed output signal.
[0006] In order to solve the above technical problems, the present invention provides an edge delay circuit with anti-shake function, comprising: PMOS tubes P1-P3, NMOS tubes N1-N3, a charging current generating circuit, a discharging current generating circuit and an inverter INV;
[0007] The signal input terminal IN is connected to the gates of the PMOS tube P1, PMOS tube P3, NMOS tube N1 and NMOS tube N3; the drains of the PMOS tube P1, PMOS tube P3, NMOS tube N1 and NMOS tube N3 are connected to the input terminal of the inverter INV; the output terminal of the inverter INV is connected to the signal output terminal OUT and the gates of the PMOS tube P2 and NMOS tube N2; the source of the PMOS tube P2 is connected to the power supply VCC, and the drain of the PMOS tube P2 is connected to the source of the PMOS tube P1; the source of the NMOS tube N2 is grounded, and the drain of the NMOS tube N2 is connected to the source of the NMOS tube N1; one end of the charging current generating circuit is connected to the power supply VCC, and the other end is connected to the source of the PMOS tube P3; one end of the discharging current generating circuit is connected to the source of the NMOS tube N3, and the other end is grounded.
[0008] Preferably, a capacitor C is further included, one end of the capacitor C is connected to the input end of the inverter INV, and the other end is grounded.
[0009] Preferably, the charging current generating circuit and the discharging current generating circuit constitute a charging and discharging circuit, and the charging and discharging circuit is implemented by a current mirror structure or a resistor structure.
[0010] Preferably, when the charge and discharge circuit adopts a current mirror structure, the charge and discharge circuit includes: PMOS tubes P4~P5, NMOS tubes N4~N6 and a reference current source Iref; one end of the reference current source Iref is connected to the power supply VCC, and the other end is connected to the drain of the NMOS tube N5 and the gates of the NMOS tubes N4~N6; the sources of the NMOS tubes N4~N6 are all grounded, the drain of the NMOS tube N4 is connected to the source of the NMOS tube N3, and the drain of the NMOS tube N6 is connected to the drain and gate of the PMOS tube P5, and the gate of the PMOS tube P4; the sources of the PMOS tubes P4~P5 are connected to the power supply VCC, and the drain of the PMOS tube P4 is connected to the source of the PMOS tube P3.
[0011] Preferably, when the charge and discharge circuit adopts a resistor structure, the charge and discharge circuit includes: resistors R1~R2; one end of the resistor R1 is connected to the power supply VCC, and the other end is connected to the source of the PMOS tube P3, one end of the resistor R2 is connected to the source of the NMOS tube N3, and the other end is grounded.
[0012] Preferably, when the signal input terminal IN changes from a low level to a high level, the PMOS tube P1 and the PMOS tube P3 are turned off, the NMOS tube N1 and the NMOS tube N3 are turned on, and the discharge current generating circuit discharges. At this time, a positive feedback loop is formed from the output to the input of the inverter INV through the NMOS tube N2.
[0013] Preferably, when the signal input terminal IN changes from a high level to a low level, the NMOS tube N1 and the NMOS tube N3 are turned off, the PMOS tube P1 and the PMOS tube P3 are turned on, and the charging current generating circuit starts to work. At this time, a positive feedback loop is formed from the output to the input of the inverter INV through the PMOS tube P2.
[0014] The present invention also provides a rising edge single edge delay circuit, comprising: the edge delay circuit and AND gate as described above; the two input ends of the AND gate are respectively connected to the input end and output end of the edge delay circuit, and the input end of the edge delay circuit is simultaneously connected to the signal input end Vin, and the output end of the AND gate is connected to the signal output end Vout.
[0015] The present invention also provides a falling edge single edge delay circuit, comprising: the edge delay circuit and an OR gate as described above; the two input ends of the OR gate are respectively connected to the input end and the output end of the edge delay circuit, and the input end of the edge delay circuit is simultaneously connected to the signal input end Vin, and the output end of the OR gate is connected to the signal output end Vout.
[0016] Compared with the prior art, the present invention has the following beneficial effects:
[0017] The present invention can delay both the rising edge and the falling edge, and adds a positive feedback signal path on the basis of the traditional delay circuit. Without affecting other performances, the anti-interference ability of the delay circuit can be increased to solve the abnormal jitter problem in the output signal flipping process in the edge delay circuit with anti-shake function; and it has broad application prospects in the technical field requiring high-reliability timing control. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 It is a schematic diagram of the edge delay circuit of the present invention.
[0019] Figure 2 It is a schematic diagram of the working waveform of the edge delay circuit of the present invention.
[0020] Figure 3 It is a schematic diagram of the working waveform of the anti-shake mechanism of the edge delay circuit of the present invention.
[0021] Figure 4 It is a schematic diagram of the charging and discharging circuit implemented by the reference current source and the current mirror.
[0022] Figure 5 This is a schematic diagram of a charging and discharging circuit implemented using resistors.
[0023] Figure 6 It is an application schematic diagram of a rising edge single edge delay circuit derived from the edge delay circuit of the present invention.
[0024] Figure 7 It is a schematic diagram of the working waveform of a rising edge single edge delay circuit derived from the edge delay circuit of the present invention.
[0025] Figure 8 It is an application schematic diagram of a falling edge single edge delay circuit derived from the edge delay circuit of the present invention.
[0026] Fig. 9 It is a schematic diagram of the working waveform of a falling edge single edge delay circuit derived from the edge delay circuit of the present invention. DETAILED DESCRIPTION
[0027] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0028] like Figure 1 As shown, the embodiment of the present invention discloses an edge delay circuit with an anti-shake function, including: PMOS tubes P1-P3, NMOS tubes N1-N3, a charging current generating circuit, a discharging current generating circuit and an inverter INV;
[0029] The signal input terminal IN is connected to the gates of the PMOS tube P1, PMOS tube P3, NMOS tube N1 and NMOS tube N3; the drains of the PMOS tube P1, PMOS tube P3, NMOS tube N1 and NMOS tube N3 are connected to the input terminal of the inverter INV; the output terminal of the inverter INV is connected to the signal output terminal OUT and the gates of the PMOS tube P2 and NMOS tube N2; the source of the PMOS tube P2 is connected to the power supply VCC, and the drain of the PMOS tube P2 is connected to the source of the PMOS tube P1; the source of the NMOS tube N2 is grounded, and the drain of the NMOS tube N2 is connected to the source of the NMOS tube N1; one end of the charging current generating circuit is connected to the power supply VCC, and the other end is connected to the source of the PMOS tube P3; one end of the discharging current generating circuit is connected to the source of the NMOS tube N3, and the other end is grounded.
[0030] like Figure 1 As shown, a capacitor C is also included, one end of the capacitor C is connected to the input end of the inverter INV, and the other end is grounded.
[0031] like Figure 4 and Figure 5 As shown, the charging current generating circuit and the discharging current generating circuit constitute a charging and discharging circuit, and the charging and discharging circuit is implemented by a current mirror structure or a resistor structure.
[0032] like Figure 4 As shown, when the charge and discharge circuit adopts a current mirror structure, the charge and discharge circuit includes: PMOS tubes P4~P5, NMOS tubes N4~N6 and a reference current source Iref; one end of the reference current source Iref is connected to the power supply VCC, and the other end is connected to the drain of the NMOS tube N5 and the gates of the NMOS tubes N4~N6; the sources of the NMOS tubes N4~N6 are all grounded, the drain of the NMOS tube N4 is connected to the source of the NMOS tube N3, and the drain of the NMOS tube N6 is connected to the drain and gate of the PMOS tube P5, and the gate of the PMOS tube P4; the sources of the PMOS tubes P4~P5 are connected to the power supply VCC, and the drain of the PMOS tube P4 is connected to the source of the PMOS tube P3; the above-mentioned NMOS tubes N4~N6 constitute a group of current mirrors.
[0033] like Figure 5 As shown, when the charging and discharging circuit adopts a resistor structure, the charging and discharging circuit includes: resistors R1~R2; one end of the resistor R1 is connected to the power supply VCC, and the other end is connected to the source of the PMOS tube P3, one end of the resistor R2 is connected to the source of the NMOS tube N3, and the other end is grounded.
[0034] The specific working principle of the present invention is as follows:
[0035] See also Figure 1 and Figure 2 As shown, first assume that the initial state of the signal input terminal IN is stable at a low level, the initial state of the inverter input terminal is stable at a high level, the initial state of the signal output terminal OUT is stable at a low level, and at the same time, P1, P2 and P3 tubes are turned on at the same time, while N1, N2 and N3 tubes are turned off at the same time.
[0036] Please continue reading Figure 2As shown, when the input signal IN changes from low level to high level, this is recorded as time t1. At time t1, P1 and P3 are turned off, N1 and N3 are turned on, and the capacitor begins to discharge through the N3 tube and the discharge current generating circuit. The voltage at the input end of the inverter begins to drop. When the inverter flip voltage threshold is reached, the signal output end OUT becomes high level, which is recorded as time t2. At time t2, N2 starts to turn on, which is equivalent to the output of the inverter to the input through N2 to form a positive feedback loop. Under the action of this positive feedback loop, at time t2, the level of the inverter input end will be quickly pulled down to the ground, and the output high level will be more stable. Assuming that there is no positive feedback loop, at time t2, the voltage at the input end of the inverter has just crossed the flip threshold voltage. If the signal input end or the inverter input end is disturbed and generates voltage jitter, the voltage at the input end of the inverter will follow the flip threshold voltage and jitter, and then the signal output end OUT will have a level flipping back and forth. Once the positive feedback loop is added, once the inverter input exceeds the inverter threshold voltage, the inverter input itself will be immediately pulled down to the ground, or a low impedance path to the ground will be immediately formed. If the signal at the inverter input node is interfered with at this time, since the impedance of the node to the ground is very low at this time, it can be considered to be directly grounded, and the interference noise will be directly bypassed to the ground; if the input signal is interfered with at this time and jitter occurs, such as Figure 3 As shown, for example, a negative pulse suddenly comes, N1 and N2 are turned off, P1 and P2 are turned on, and the capacitor starts to charge. However, at this time, the capacitor voltage starts to rise from zero, so it takes a certain amount of time to reach the flip threshold of the inverter. Therefore, as long as the width of this abnormal jitter negative pulse is less than a certain value, it will not affect the output signal OUT, thereby ultimately achieving the anti-shake effect.
[0037] When the input signal IN changes from high level to low level, N1 and N3 are turned off, P1 and P3 are turned on, the charging current generating circuit starts to work, and the positive feedback loop becomes the P2 tube. Figure 3 The time t3 corresponds to the time when the input signal IN changes from high to low, and the time t4 corresponds to the time when the output of the inverter is quickly pulled up to a high level. The entire working principle and working process are the same as above and will not be described in detail.
[0038] For specific applications, a specific application circuit can be selected according to different requirements. For example, the charging current generating circuit of the present invention can be implemented with a reference current source and a current mirror, such as Figure 4 As shown; it can also be implemented directly with a resistor, such as Figure 5As shown. When using a reference current source and a current mirror, the circuit will be a little more complicated, but the current can be accurately controlled to accurately control the delay time; while using resistors directly, although the delay time control is not accurate enough, the advantage is that the circuit structure is simple. Regardless of which solution is used, the delay time of the rising edge or falling edge can be adjusted separately by adjusting the reference current, the ratio of the current mirror, or the size of the resistor.
[0039] In addition, it is important to mention that the edge delay circuit of the present invention delays both the rising edge signal and the falling edge signal. In many applications, in fact, only one of the rising edge or the falling edge needs to be delayed, that is, single edge delay. This single edge delay circuit can also be easily implemented by a simple combination of the edge delay circuit diagram of the present invention and a basic logic gate circuit. Please continue to refer to Figure 6 and Figure 8 , two single-edge delay circuits for rising edge and falling edge are given respectively. Figure 7 and Fig. 9 The schematic diagrams of their working timing waveforms are given respectively. Figure 7 and Fig. 9 Vin in the delay circuit corresponds to Figure 1 IN and OUT in, Figure 7 and Fig. 9 The t1, t2, t3, and t4 in Figure 1 The marked moments correspond one to one.
[0040] for Figure 6 In the circuit diagram, the output Vout will only go high when both inputs of the AND gate are high at the same time, and Vout will go low as long as one of the inputs goes low. Therefore, when Vin changes from low to high at time t1, Vout cannot go high immediately, but waits until the output of the delay circuit goes high at time t2 before it can go high; when Vin changes from high to low at time t3, the output Vout of the AND gate will go low immediately, thus achieving the delay of only the rising edge.
[0041] for Figure 8 In the circuit diagram, the output Vout will only go low when both inputs of the OR gate are low at the same time, and Vout will go high as long as one of the inputs goes high. Therefore, when Vin changes from low to high at time t1, the output Vout of the OR gate will immediately go high; when Vin changes from high to low at time t3, the output Vout of the OR gate will not immediately go low, but will only go low after the output of the delay circuit goes low at time t4, thus achieving the delay of only the falling edge.
[0042] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. An edge delay circuit with anti-shake function, characterized in that: include: PMOS tubes P1-P3, NMOS tubes N1-N3, a charging current generating circuit, a discharging current generating circuit and an inverter INV; The signal input terminal IN is connected to the gates of the PMOS tube P1, PMOS tube P3, NMOS tube N1 and NMOS tube N3; the drains of the PMOS tube P1, PMOS tube P3, NMOS tube N1 and NMOS tube N3 are connected to the input terminal of the inverter INV; the output terminal of the inverter INV is connected to the signal output terminal OUT and the gates of the PMOS tube P2 and NMOS tube N2; the source of the PMOS tube P2 is connected to the power supply VCC, and the drain of the PMOS tube P2 is connected to the source of the PMOS tube P1; the source of the NMOS tube N2 is grounded, and the drain of the NMOS tube N2 is connected to the source of the NMOS tube N1; one end of the charging current generating circuit is connected to the power supply VCC, and the other end is connected to the source of the PMOS tube P3; one end of the discharging current generating circuit is connected to the source of the NMOS tube N3, and the other end is grounded; The charging current generating circuit and the discharging current generating circuit constitute a charging and discharging circuit, and the charging and discharging circuit is implemented by a current mirror structure or a resistor structure; When the charging and discharging circuit adopts a current mirror structure, the charging and discharging circuit includes: PMOS tubes P4-P5, NMOS tubes N4-N6 and a reference current source Iref; One end of the reference current source Iref is connected to the power supply VCC, and the other end is connected to the drain of the NMOS tube N5 and the gates of the NMOS tubes N4~N6; the sources of the NMOS tubes N4~N6 are all grounded, the drain of the NMOS tube N4 is connected to the source of the NMOS tube N3, the drain of the NMOS tube N6 is connected to the drain and gate of the PMOS tube P5, and the gate of the PMOS tube P4; the sources of the PMOS tubes P4~P5 are connected to the power supply VCC, and the drain of the PMOS tube P4 is connected to the source of the PMOS tube P3.
2. An edge delay circuit with anti-shake function as claimed in claim 1, characterized in that: It also includes a capacitor C, one end of which is connected to the input end of the inverter INV, and the other end of which is grounded.
3. The edge delay circuit with anti-shake function as claimed in claim 1, characterized in that: When the charging and discharging circuit adopts a resistor structure, the charging and discharging circuit includes: resistors R1~R2; one end of the resistor R1 is connected to the power supply VCC, and the other end is connected to the source of the PMOS tube P3, one end of the resistor R2 is connected to the source of the NMOS tube N3, and the other end is grounded.
4. The edge delay circuit with anti-shake function according to any one of claims 1 to 3, characterized in that: When the signal input terminal IN changes from a low level to a high level, the PMOS tube P1 and the PMOS tube P3 are turned off, the NMOS tube N1 and the NMOS tube N3 are turned on, and the discharge current generating circuit discharges. At this time, a positive feedback loop is formed from the output to the input of the inverter INV through the NMOS tube N2.
5. The edge delay circuit with anti-shake function according to any one of claims 1 to 3, characterized in that: When the signal input terminal IN changes from a high level to a low level, the NMOS tube N1 and the NMOS tube N3 are turned off, the PMOS tube P1 and the PMOS tube P3 are turned on, and the charging current generating circuit starts to work. At this time, a positive feedback loop is formed from the output to the input of the inverter INV through the PMOS tube P2.
6. A rising edge single edge delay circuit, characterized in that: include: The edge delay circuit and AND gate as described in any one of claims 1 to 3; the two input ends of the AND gate are respectively connected to the input end and the output end of the edge delay circuit, and the input end of the edge delay circuit is simultaneously connected to the signal input end Vin, and the output end of the AND gate is connected to the signal output end Vout.
7. A falling edge single edge delay circuit, characterized in that: include: An edge delay circuit and an OR gate as described in any one of claims 1 to 3; the two input ends of the OR gate are respectively connected to the input end and the output end of the edge delay circuit, and the input end of the edge delay circuit is simultaneously connected to the signal input end Vin, and the output end of the OR gate is connected to the signal output end Vout.
Citation Information
Patent Citations
Low jitter frequency dividing clock circuit
CN109120257A
Input-output receiver
US20170264297A1