10gbase-t physical layer synchronization and equalization method and apparatus

Abstract

The application provides a 10GBase-T physical layer synchronization and equalization method and device, which realizes fast capture of a PN training sequence in PN synchronization by using iteration interaction of a multi-state equalizer and a PN synchronization algorithm; meanwhile, the multi-state equalization method in the equalizer has a high multiplexing degree and an inheritance characteristic of equalization training results on hardware, which can greatly reduce hardware overhead of a synchronization and equalization module in 10GBase-T and significantly improve convergence speed of equalization training; further, with training convergence of filter coefficients in the equalizer, the quality of equalization output signals is continuously improved, and input of the equalization output results to the PN synchronization module will further improve stability of PN synchronization tracking and reduce step-out probability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of 10GBase-T IP chip physical layer algorithm development, in particular to a 10GBase-T physical layer synchronization and equalization method and device. BACKGROUND

[0002] Wireless communication network technology develops rapidly, and a series of new technologies, new standards, new protocols and new equipment development and upgrading make the wireless network rate gradually exceed the current mainstream gigabit rate Ethernet network. Therefore, the upgrade of wired network rate is imminent, and the 10G Ethernet technology emerges in the above background. 10GBase-T is a high-speed Ethernet technology used for transmitting data at a rate of 10 Gbps (Gigabit per second), and "-T" represents the transmission medium as twisted pair, which is one of the most common standards in 10Gbps rate Ethernet technology. In the high-speed system of 10GBase-T, accurate signal transmission is an important performance indicator.

[0003] Equalization technology is a technology of inserting adjustable filters in a communication system to correct and compensate for the transmission characteristics of the system and reduce the influence of inter-symbol interference. In the 10GBase-T system, an equalizer is needed to compensate for the influence of channel transmission on the system. In order to ensure the accuracy of the demodulated signal of the receiver, the performance requirement of the equalizer design in the 10GBase-T system is very high. The equalizer is divided into a training phase and a data equalization phase. In the training phase, the equalizer mainly compares the local reference sequence generated by the receiver with the transmitter sequence received after the influence of channel transmission, and uses the comparison result to continuously train the filter coefficients required in the equalizer. In the data equalization phase, the trained filter coefficients are used to equalize the transmission data. Based on this, the acquisition of the local reference sequence by the receiver becomes a necessary condition for equalization processing. The pseudo-random (PN: pseudo-noise) sequence synchronization technology for realizing this condition plays a crucial role in the 10GBase-T communication system.

[0004] The physical layer training phase in the 10GBase-T system uses a PN sequence as its training sequence. The receiver needs to use the PN synchronization technology to realize the acquisition of the PN training sequence and signal alignment, so as to obtain the local reference sequence for the training and convergence of the equalizer filter coefficients.

[0005] In IEEE 802.3 standard, the generation of PN sequence in 10GBase-T system is implemented by using a 33-bit shift register, and the initial value of the register is usually a random value, and the periodic reset of the register value is not usually performed in the generation of the PN sequence. This feature makes the receiver unable to predict the 33-bit register value in the transmitter PN sequence generator at the initial time and the current time, and further unable to directly obtain the local reference sequence.

[0006] Therefore, when performing PN synchronization, the receiver first needs to capture the data in the PN generation register without any prior information, that is, to capture the PN training sequence. In order to achieve this capture, it is necessary to ensure that the phase information of the input data of the PN synchronization algorithm is basically consistent with the transmitted training sequence, that is, there is no excessive phase error. However, the high baud rate makes the 10GBase-T system extremely sensitive to the transmission characteristics of the twisted pair, which brings a large amount of phase error to the received data of the receiver, so it cannot be directly applied to the register data capture of the PN sequence. In order to improve the quality of the input data of the PN synchronization algorithm and reduce the phase error, a feasible method is to add a pre-equalization operation before the PN synchronization; at the same time, the traditional equalization processing also needs the local reference sequence provided by the PN synchronization algorithm after correct synchronization. Therefore, in order to realize the correct reception of the physical layer of the 10GBase-T system, the PN synchronization and equalization processing need to be jointly designed. However, the IEEE 802.3 standard does not explicitly propose a specific solution. Therefore, it is urgent to develop a set of algorithms and devices for the combination of PN synchronization and equalization for the 10GBase-T system.

[0007] Patent document CN114826843A discloses a high-order quadrature amplitude modulation signal blind equalization method and device and a blind equalizer. The prior probability of a high-order quadrature amplitude modulation signal is obtained based on a plurality of constant modulus values of the high-order quadrature amplitude modulation signal. According to the error sorting of the observation signal and the constant modulus value signal, the sample set of different modulus values is selected in combination with the prior probability, and the plurality of sample sets of different modulus values are aggregated to form the final sample. The cost function under the high-order quadrature amplitude modulation channel is constructed according to the classic constant modulus algorithm and the selected sample set. The high-order quadrature amplitude modulation channel method iterative formula is constructed according to the Newton method, and the channel blind equalizer is optimized.

[0008] In the traditional method, the PN synchronization and the equalization are usually designed separately. The PN synchronization needs to set an independent preprocessing module to achieve the register value capture. After the PN synchronization is successful, the independently designed equalizer starts to train the equalization coefficient. Compared with the joint algorithm scheme of the present application, the traditional method has obvious disadvantages in the equalizer convergence speed and hardware logic overhead. At the same time, since the channel transmission compensation capability of the PN synchronization preprocessing module is far less than that of the equalizer, the input signal quality cannot be further improved after the PN synchronization successfully achieves the first register value capture. Compared with the joint processing method of the present application, there is a high step-out probability in the subsequent PN synchronization tracking. SUMMARY

[0009] In view of the defects in the prior art, the present application aims to provide a 10GBase-T physical layer synchronization and equalization method and device.

[0010] The 10GBase-T physical layer synchronization and equalization method provided by the present application comprises the following steps:

[0011] Step 1: The multi-state equalizer performs a first equalization state operation on the baseband received signal after the first preprocessing, wherein the first equalization state operation adopts a linear equalizer (LE: Linear Equalizer) based on a constant modulus blind equalization (CMA: Constant Modulus Algorithm) algorithm for equalization; the blind equalization algorithm CMA uses the high-order statistics of the signal to train the initial filter coefficient, and the PN synchronization module uses the output result of the multi-state equalizer to capture the PN generation register and generate the local reference signal;

[0012] Step 2: The multi-state equalizer enters a second equalization state and adopts a decision feedback equalizer (DFE: Decision Feedback Equalizer) state based on the blind equalization algorithm CMA, and continues to train and converge based on the first equalization state equalizer coefficient. The second equalization state is not an optional step of the present application, and the multi-state equalizer can skip step 2 and directly proceed to step 3;

[0013] Step 3: As the output signal quality of the multi-state equalizer is continuously improved, the phase error is continuously reduced, and the PN synchronization module eventually realizes the successful capture of the generation register and the successful generation of the local reference signal. At this time, the PN synchronization module outputs the local reference sequence to the multi-state equalizer and notifies the multi-state equalizer to enter the third equalization state, i.e., the decision feedback equalization DFE state using the least mean square LMS algorithm. The multi-state equalizer uses the local reference sequence to train the equalization coefficients based on the LMS algorithm based on the equalization coefficients of the second equalization state equalizer;

[0014] Step 4: When the output signal quality of the multi-state equalizer reaches the preset threshold, the remote transmitter starts THP (Tomlinson-Harashima Precoding) precoding, and at this time the multi-state equalizer enters the fourth equalization state, i.e., LE linear equalization processing based on the LMS algorithm and THP decoding. Among them, the function of the THP precoding of the remote transmitter is to preposition the processing of the feedback filter in the receiver decision feedback equalizer to the remote transmitter. After the THP precoding is started, the multi-state equalizer of the receiver is rolled back from the DFE equalization structure to the LE equalization structure. When the quality of the equalization result meets the decoding requirements of the 802.3 physical coding sublayer (PCS: Physical Coding Sublayer), the system transitions to the data transmission stage, and the receiver realizes the correct decoding of the PCS.

[0015] Preferably, the first preprocessing includes near-end crosstalk cancellation, far-end crosstalk cancellation, echo interference cancellation and the like, and the cancellation process uses the baseband signal generated by the transmitter itself as a reference.

[0016] Preferably, in the transmitter, the training sequence generation and the data signal generation are included; wherein, according to the 802.3 standard, the former generates a PAM2 modulated signal, and the latter generates a PAM16 modulated signal after PCS encoding. The modulated signal is processed by the THP encoder and transmitted to the radio frequency front end as the transmitter baseband signal, and is sent on the transmission medium.

[0017] Preferably, in the receiver, the radio frequency front end obtains the received signal on the transmission medium, and obtains the baseband signal of the receiver through the analog-to-digital conversion operation, the baseband signal is firstly subjected to the interference cancellation operation, the signal after the interference cancellation enters the multi-state equalizer for the multi-state equalization processing, the output result thereof is taken as the input of the PN synchronization module, the PN synchronization module uses the result of the multi-state equalizer to capture the PN generation register value, obtains the local reference sequence, feeds back to the multi-state equalizer, and simultaneously extracts the signaling part in the training sequence; the output result of the multi-state equalizer is simultaneously taken as the input of the receiver PCS decoder and the sampling clock frequency offset (SFO) estimator, and the PCS decoding result is the data bit stream, which is transmitted to the XGMII interface.

[0018] Preferably, the implementation process of the CMA equalization algorithm is shown in formula (1), wherein e(n) is the error signal, z(n) is the equalizer output signal, R is the autocorrelation matrix, s(n) is the independent distribution transmission signal, y(n) is the receiver received signal, J is the cost function, W(n) is the equalizer weight vector, and μ is the step length.

[0019] (1)

[0020] Preferably, the LMS equalization algorithm uses the error between the local reference sequence and the received sequence, realizes the convergence of the equalizer filter coefficient through the least mean square error criterion, and the implementation process is shown in formula (2), wherein X(n) is the input vector, and d(n) is the local reference signal.

[0021] (2)

[0022] Preferably, the linear equalizer LE filters the received signal through the adaptive linear filter to realize the equalization processing, wherein the coefficient training and convergence of the adaptive linear filter are based on the above-mentioned blind equalization algorithms CMA or LMS equalization algorithm.

[0023] Preferably, the decision feedback equalizer DFE is divided into an adaptive feedforward filter and an adaptive feedback filter, and the coefficient convergence thereof is based on the above-mentioned blind equalization algorithms CMA or LMS equalization algorithm.

[0024] The 10GBase-T physical layer synchronization and equalization device provided by the application comprises:

[0025] Module M1: multi-state equalizer, realizing the multi-state equalization processing based on the CMA equalization algorithm, the LMS equalization algorithm, the LE equalization structure and the DFE equalization structure, and realizing the THP decoding processing.

[0026] Module M2: PN synchronizer, using the output result of the multi-state equalizer, realizing the capture of the PN training sequence, generating the local reference sequence, used for the training and processing of the multi-state equalizer;

[0027] There is interaction and iteration between the module M1 and the module M2, and the module M1 realizes the switching of the multiple equalization states according to the processing state of the module M2.

[0028] The first preprocessor comprises an echo interference canceller, and / or a near-end interference canceller, and / or a far-end interference canceller.

[0029] Compared with the prior art, the present application has the beneficial effects as follows:

[0030] The present application proposes a joint algorithm scheme of PN synchronization and equalization, realizes the fast capture of the register data in the PN synchronization by using the iteration and interaction of the multi-state equalizer and the PN synchronization algorithm; meanwhile, the multi-state equalization method in the equalizer has a high multiplexing degree and the inheritance characteristics of the equalization training result in hardware, which can greatly reduce the hardware overhead of the synchronization and equalization module in the 10GBase-T, and significantly improve the convergence speed of the equalization training; further, with the training convergence of the filter coefficients in the equalizer, the quality of the equalization output signal is continuously improved, and using the equalization output result as the input of the PN synchronization module can further improve the stability of the PN synchronization module and reduce the step-out probability. BRIEF DESCRIPTION OF DRAWINGS

[0031] Other characteristics, objects and advantages of the present application will become more apparent from the following detailed description of non-restrictive embodiments, made with reference to the attached drawings:

[0032] Figure 1 The 10GBase-T overall algorithm structure design containing the device and the processing process of the present application is shown in Fig. 1.

[0033] Figure 2 The state switching example 1 of the multi-state equalizer is shown in Fig. 2.

[0034] Figure 3 The state switching example 2 of the multi-state equalizer is shown in Fig. 3.

[0035] Figure 4 The structure diagram of the linear equalizer LE is shown in Fig. 4.

[0036] Figure 5 The structure diagram of the decision feedback equalizer DFE is shown in Fig. 5. DETAILED DESCRIPTION

[0037] The application will be described in detail below with reference to specific embodiments. The following embodiments will help those skilled in the art to further understand the application, but do not limit the application in any form. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the application. These are within the scope of the application.

[0038] Figure 1 The overall algorithm structure of 10GBase-T is designed to include the device and process of the application, wherein the 10GBase-T physical layer processing is a full duplex process, including transmitter processing and receiver processing.

[0039] In the transmitter processing, the training sequence generation and data signal generation are included. According to the 802.3 standard, the former generates a PAM2 modulated signal, and the latter generates a PAM16 modulated signal after PCS encoding. The modulated signal needs to be processed by a THP encoder, and then transmitted to the radio frequency front end as the transmitter baseband signal, and sent on the transmission medium.

[0040] In the receiver processing, the radio frequency front end obtains the received signal on the transmission medium, and obtains the receiver baseband signal through analog-to-digital conversion and other operations. The baseband signal first needs to be subjected to interference cancellation operation, including near-end crosstalk cancellation, far-end crosstalk cancellation, echo interference cancellation and other processing, and the cancellation process needs to use the baseband signal generated by the transmitter itself as a reference. The signal after interference cancellation enters the multi-state equalizer for multi-state equalization processing, and the output result is used as the input of the PN synchronization module. The PN synchronization module uses the result of the multi-state equalizer to capture the PN generation register value, obtains the local reference sequence, feeds back to the multi-state equalizer, and at the same time extracts the signaling part in the training sequence. The output result of the multi-state equalizer is also used as the input of the receiver PCS decoder and the sampling offset SFO estimator. The PCS decoding result is the data bit stream, which is transmitted to the XGMII interface.

[0041] The core of the application is the joint design of the multi-state equalizer and the PN synchronization module. The specific embodiment steps are as follows:

[0042] Embodiment 1:

[0043] Step 1: The multi-state equalizer performs equalization operation in the first equalization state on the baseband received signal which has been pre-processed (including interference cancellation and other processing). The first equalization state adopts a linear equalizer LE based on the constant modulus blind equalization CMA algorithm for equalization. The blind equalization CMA algorithm uses high-order statistics of the signal to train the initial filter coefficients, and does not need a local reference sequence for assistance. The PN synchronization module uses the output result of the multi-state equalizer to capture the PN generation register and generate the local reference signal.

[0044] Step 2: As the training of the equalization filter coefficients in the CMA-LE converges, the quality of the CMA-LE output result is continuously improved, and basically the constellation diagram can be distinguished. At this time, the multi-state equalizer switches to the second equalization state, that is, the decision feedback equalization DFE state based on the blind equalization CMA algorithm, and continues to train and converge based on the equalizer coefficients in the first equalization state, to further improve the quality of the equalizer output signal.

[0045] Step 3: As the quality of the output signal of the multi-state equalizer continuously improves, the phase error continuously decreases, and the PN synchronization module eventually realizes successful capture of the generation register and successful generation of the local reference signal. At this time, the PN synchronization module outputs the local reference sequence to the multi-state equalizer, and notifies the multi-state equalizer to enter the third equalization state, that is, the DFE equalization state based on the least mean square LMS algorithm. At this time, the multi-state equalizer uses the local reference sequence to train the equalization coefficients based on the LMS algorithm based on the equalizer coefficients in the second equalization state, to further improve the quality of the equalizer output signal.

[0046] Step 4: When the quality of the output signal of the multi-state equalizer reaches a preset threshold, the remote transmitter starts THP precoding. At this time, the multi-state equalizer performs the fourth equalization state, that is, LE linear equalization processing and THP decoding based on the LMS algorithm. Among them, the function of the remote transmitter THP precoding is to preposition the processing of the feedback filter in the receiver decision feedback equalizer to the remote transmitter, so after the THP precoding is started, the multi-state equalizer of the receiver needs to back off from the DFE equalization structure to the LE equalization structure.

[0047] Finally, when the quality of the equalization result meets the PCS decoding requirement, the system transits to the data transmission stage, and the receiver can realize correct PCS decoding.

[0048] In the above implementation steps, the state switching process of the multi-state equalizer is as shown in Figure 2 .

[0049] Another preferred embodiment of the present application is based on the above embodiment, and the second equalization state is deleted, as follows:

[0050] Embodiment 2:

[0051] Step 1: The multi-state equalizer performs equalization operation on the baseband received signal which has been pre-processed (including interference cancellation and other processing) in the first equalization state. The first equalization state uses the LE equalizer based on the CMA algorithm for equalization. The CMA algorithm uses high-order statistics of the signal to train the initial filter coefficients, and does not need a local reference sequence for assistance. The PN synchronization module uses the output result of the multi-state equalizer to capture the PN generation register and generate the local reference signal.

[0052] Step 2: As the training of the equalization filter coefficients in the CMA-LE converges, the quality of the CMA-LE output result is continuously improved, and the phase error is continuously reduced. The PN synchronization module eventually achieves successful capture of the generation register and successful generation of the local reference signal. At this time, the PN synchronization module outputs the local reference sequence to the multi-state equalizer and notifies the multi-state equalizer to enter the second equalization state, i.e., the DFE equalization state using the LMS algorithm. At this time, the multi-state equalizer uses the local reference sequence to train the equalization coefficients based on the LMS criterion based on the first equalization state equalizer coefficients, to further improve the quality of the equalizer output signal.

[0053] Step 3: When the output signal quality of the multi-state equalizer reaches a preset threshold, the remote transmitter starts THP precoding. At this time, the multi-state equalizer performs the third equalization state, i.e., LE linear equalization processing and THP decoding based on the LMS criterion.

[0054] Finally, when the quality of the equalization result meets the PCS decoding requirement, the system transitions to the data transmission stage, and the receiver can achieve correct PCS decoding.

[0055] In the above implementation steps, the state switching process of the multi-state equalizer is as shown in Figure 3

[0056] In the above process, the principle of CMA equalization is as follows:

[0057] CMA blind equalization is an algorithm that can realize equalization process only by using the received signal and its high-order statistical characteristics without a local reference sequence.

[0058] The implementation process of the CMA algorithm is shown in formula (1);

[0059] (1)

[0060] ​Wherein, e(n) is error signal, z(n) is equalizer output signal, R is autocorrelation matrix, s(n) is independent distribution transmission signal, y(n) is receiver received signal, J is cost function, W(n) is equalizer weight vector, μ is step length.

[0061] The implementation process of LMS equalization is shown in formula (2);

[0062] (2)

[0063] Wherein, X(n) is input vector, d(n) is local reference signal.

[0064] The structure of LE linear equalizer is shown in Figure 4 The received signal is filtered by adaptive filter to realize equalization processing, wherein the coefficient training and convergence of adaptive filter can be based on the above-mentioned CMA blind equalization algorithm or LMS equalization algorithm.

[0065] The structure of DFE decision feedback equalizer is shown in Figure 5 It is divided into adaptive feedforward filter and adaptive feedback filter, and the coefficient convergence thereof can also be based on the above-mentioned CMA blind equalization algorithm or LMS equalization algorithm.

[0066] The processing principle and process of THP encoding and decoding are as described in standard 802.3an.

[0067] Embodiment 3

[0068] The application also provides a 10GBase-T physical layer synchronization and equalization device, which can be realized by executing the flow steps of the 10GBase-T physical layer synchronization and equalization method, that is, the 10GBase-T physical layer synchronization and equalization method can be understood by those skilled in the art as the preferred embodiment of the 10GBase-T physical layer synchronization and equalization device.

[0069] The 10GBase-T physical layer synchronization and equalization device provided by the application comprises:

[0070] Module M1: multi-state equalizer, realizing multi-state equalization processing based on CMA equalization algorithm, LMS equalization algorithm, LE equalization structure and DFE equalization structure, and THP decoding processing can be realized;

[0071] Module M2: PN synchronizer, realizing PN training sequence capture by using the output result of the multi-state equalizer, generating a local reference sequence for training and processing of the multi-state equalizer;

[0072] There is interaction and iteration between the module M1 and the module M2, and the module M1 switches among multiple balanced states according to the processing state of the module M2;

[0073] The specific processing and state switching process of the module M1 and the module M2 can be realized through the above-mentioned embodiment 1 and embodiment 2.

[0074] Those skilled in the art know that, in addition to implementing the system, device and each module thereof provided by the present application in the form of pure computer readable program code, the same program can also be realized in the form of logic gate, switch, application specific integrated circuit, programmable logic controller and embedded microcontroller, etc. by logically programming the method steps. Therefore, the system, device and each module thereof provided by the present application can be considered as a hardware component, and the modules included therein for realizing various programs can also be considered as structures within the hardware component; the modules for realizing various functions can also be considered as both software programs for realizing methods and structures within the hardware component.

[0075] The specific embodiments of the present application are described above. It needs to be understood that the present application is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essential content of the present application. The embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily without conflict.

Claims

1. A 10GBase-T physical layer synchronization and equalization method, characterized in that, The method comprises the following steps: Step 1: a multi-state equalizer adopts a first equalization state to perform equalization processing on baseband received data after first preprocessing, and the equalization result is used for PN synchronization processing; Step 2: the PN synchronization processing uses the output result of the multi-state equalizer to capture a PN training sequence, and after successfully capturing the PN training sequence, a generated local PN reference sequence is fed back to the multi-state equalizer; Step 3: after obtaining the feedback of the local PN reference sequence, the multi-state equalizer switches to a second equalization state, and uses the local PN reference sequence to assist the equalizer to perform further training and processing; The first equalization state adopts a constant modulus blind equalization (CMA) algorithm to perform training and processing of the equalizer; The first equalization state comprises one sub-state, that is, a linear equalization processing state using the CMA algorithm; Or, the first equalization state comprises two sub-states, the first sub-state is a linear equalization processing state using the CMA algorithm, and the second sub-state is a decision feedback equalization processing state using the CMA algorithm; The second equalization state adopts a local PN reference sequence assisted least mean square (LMS) algorithm to perform training and processing of the equalizer; The second equalization state comprises two sub-states, the first sub-state is a decision feedback equalization processing state using the LMS algorithm, and the second sub-state is a linear equalization processing and THP decoding processing state using the LMS algorithm.

2. The 10GBase-T physical layer synchronization and equalization method of claim 1, wherein, When the multi-state equalizer switches states, the equalization coefficients obtained in the previous state can be inherited, or the equalization coefficients obtained in the previous state can not be inherited.

3. The 10GBase-T physical layer synchronization and equalization method of claim 1, wherein, The first preprocessing comprises echo interference cancellation, near-end interference cancellation and / or far-end interference cancellation processing.

4. A 10GBase-T physical layer synchronization and equalization apparatus, comprising: The method comprises the following steps: A multi-state equalizer and a PN synchronizer; The multi-state equalizer performs equalization processing on baseband received data after first preprocessing, and outputs a first equalization state equalization result to the PN synchronizer, which is used for capturing a PN training sequence; After successfully capturing the PN training sequence, the PN synchronizer feeds back a generated local PN reference sequence to the multi-state equalizer, which is used for equalization training and processing in a second equalization state of the multi-state equalizer; The first equalization state adopts a constant modulus blind equalization (CMA) algorithm to perform training and processing of the equalizer; The first equalization state comprises one sub-state, that is, a linear equalization processing state using the CMA algorithm; Or, the first equalization state comprises two sub-states, the first sub-state is a linear equalization processing state using the CMA algorithm, and the second sub-state is a decision feedback equalization processing state using the CMA algorithm; The second equalization state adopts a local PN reference sequence assisted least mean square (LMS) algorithm to perform training and processing of the equalizer; The second equalization state comprises two sub-states, the first sub-state is a decision feedback equalization processing state using the LMS algorithm, and the second sub-state is a linear equalization processing and THP decoding processing state using the LMS algorithm.

5. The 10GBase-T physical layer synchronization and equalization device of claim 4, wherein, When the multi-state equalizer switches states, the equalization coefficients obtained in the previous state can be inherited, or the equalization coefficients obtained in the previous state can not be inherited.

6. The 10GBase-T physical layer synchronization and equalization device of claim 4, wherein, The first pre-processor comprises an echo interference canceller, and / or a near-end interference canceller, and / or a far-end interference canceller.

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