Side channel attack protection method, device, storage medium and electronic device

Abstract

The present application provides a side channel attack protection method, device, computer storage medium and electronic device, which relates to the field of network security technology. It includes: when executing a branch jump instruction at the current moment, performing branch prediction on the branch jump instruction to obtain a branch prediction result; if the prediction is correct, performing a first flush operation on the first predicted instruction based on a randomly generated target flush number; the first predicted instruction is an instruction that is fetched into the instruction processing pipeline when the prediction of the branch jump instruction at the current moment is correct, and / or, an instruction that is fetched into the instruction processing pipeline when the prediction of the branch jump instruction at the target moment randomly determined based on the target flush number is correct, and the target moment is any moment after the current moment; after executing the first flush operation, the correctly executed instruction is added to the instruction processing pipeline. The present application enables the processor to prevent side channel attacks to ensure network security while improving the efficiency and performance of the processor.

Description

Technical Field

[0001] The present application relates to the field of network security technology, and in particular, to a side channel attack protection method, a side channel attack protection device, a computer storage medium, and an electronic device. Background Art

[0002] With the continuous optimization of embedded processor micro-architecture system, it not only brings about the improvement of processor performance, but also brings about more serious network security issues. Among them, side channel attack (SCA for short) is a way of attacking by using various physical state information such as sound and light information, power consumption, electromagnetic radiation and running time that are closely related to internal operations leaked during the execution of cryptographic algorithms. Side channel attack technology has gradually penetrated from the outside of the device to the central processing unit (CPU), cache, branch prediction unit, etc. inside the device. Frequent memory access and the difference in the speed of program execution create conditions for the occurrence of side channel attacks. For example, attackers attack threads based on the length of reload time through flushing (Flush) + reloading (Reload), or attack based on the execution speed of cl-flush instructions through flush + flush.

[0003] In the related technical solutions, the processor usually makes all branch jump instructions miss when performing branch prediction, so as to flush the instructions in the pipeline and re-fetch instructions, thereby achieving the effect of preventing side channel attacks. However, the above method of making all predicted instructions miss reduces the performance of the processor, thereby reducing the execution efficiency of the processor.

[0004] Therefore, there is an urgent need for a method that can enable the processor to block side channel attacks to ensure network security while ensuring processor performance. Summary of the invention

[0005] The embodiments of the present application provide a side-channel attack protection method, a side-channel attack protection method apparatus, a computer device, and a storage medium, thereby overcoming, at least to a certain extent, the technical problem that the processor cannot prevent side-channel attacks due to the limitations and defects of related technologies, thereby ensuring network security while ensuring high execution efficiency of the processor and ensuring the performance of the processor.

[0006] A first aspect of an embodiment of the present application provides a method for protecting against side channel attacks, the method comprising: when the instruction to be executed at the current moment is a branch jump instruction, performing branch prediction on the branch jump instruction to obtain a branch prediction result corresponding to the branch jump instruction; if the branch prediction result is a correct prediction, randomly generating a target flush number, and performing a first flush operation on the first predicted instruction in the instruction processing pipeline based on the randomly generated target flush number; the first predicted instruction is an instruction that is fetched into the instruction processing pipeline when the prediction for the branch jump instruction at the current moment is correct, and / or an instruction that is fetched into the instruction processing pipeline when the prediction for the branch jump instruction at a target moment randomly determined based on the target flush number is correct, the target moment being any moment after the current moment; after executing the first flush operation, adding the correctly executed instruction corresponding to the branch jump instruction to the instruction processing pipeline.

[0007] In an optional embodiment of the present application, branch prediction is performed on branch jump instructions, including: performing branch prediction on branch jump instructions based on multiple preset branch prediction methods, respectively, to obtain multiple branch prediction results corresponding to the branch jump instructions by each branch prediction method; determining the prediction accuracy of each branch prediction method based on the multiple branch prediction results; determining the branch prediction method with the highest prediction accuracy as the target branch prediction method, and performing branch prediction on the branch jump instruction based on the target branch prediction method.

[0008] In an optional embodiment of the present application, the prediction accuracy of each branch prediction method is determined based on multiple branch prediction results, including: for each branch prediction method in each branch prediction method, branch prediction is performed on the branch jump instruction at the current moment according to the branch prediction method to obtain the branch prediction direction and predicted target address corresponding to the branch prediction method; the branch prediction direction and predicted target address corresponding to the branch prediction method are compared with the actual branch direction and actual target address after the execution stage to obtain the prediction accuracy of each branch prediction method.

[0009] In an optional embodiment of the present application, if the branch prediction result is a correct prediction, a target flush number is randomly generated, and a first flush operation is performed on a first predicted instruction in the instruction processing pipeline based on the randomly generated target flush number, including: if the branch prediction result is a correct prediction, multiple preset flush numbers corresponding to the first flush operation are sent to determine a first target flush number from the multiple preset flush numbers; the first target flush number is any one of the multiple preset flush numbers. A confirmation instruction for the first target flush number is received, and a first flush operation is performed on the first predicted instruction in the instruction processing pipeline based on the first target flush number.

[0010] In an optional embodiment of the present application, if the branch prediction result is a correct prediction, a target flush number is randomly generated, and a first flush operation is performed on a first predicted instruction in the instruction processing pipeline based on the randomly generated target flush number, including: if the branch prediction result is a correct prediction, an adjustment control for the flush number corresponding to the first flush operation is sent; wherein a preset flush number range is represented by the adjustment control, and the maximum flush number in the preset flush number range is less than a preset number threshold; an adjustment instruction based on the adjustment control is received, a second target flush number corresponding to the adjustment instruction is determined from the preset flush number range, and a first flush operation is performed on the first predicted instruction in the instruction processing pipeline based on the second target flush number.

[0011] In an optional embodiment of the present application, based on the target flush number, a target branch jump instruction corresponding to the target flush number is determined; when the corresponding prediction of the target branch jump instruction is correct, the first predicted instruction in the instruction processing pipeline performs a first flush operation.

[0012] In an optional embodiment of the present application, if the branch prediction result is a prediction error, a second flush operation is performed on a second predicted instruction in the instruction processing pipeline, where the second predicted instruction is an instruction that is fetched into the instruction processing pipeline when a branch jump instruction is predicted incorrectly.

[0013] According to a second aspect of an embodiment of the present application, a protection device for side channel attacks is provided, the device comprising: a branch prediction module, for performing branch prediction on a branch jump instruction when the instruction to be executed at the current moment is a branch jump instruction, so as to obtain a branch prediction result corresponding to the branch jump instruction; an instruction flushing module, for randomly generating a target flushing number if the branch prediction result is a correct prediction, and performing a first flushing operation on a first predicted instruction in the instruction processing pipeline based on the randomly generated target flushing number; the first predicted instruction is an instruction that is fetched into the instruction processing pipeline when the prediction of the branch jump instruction at the current moment is correct, and / or an instruction that is fetched into the instruction processing pipeline when the prediction of the branch jump instruction corresponding to a target time randomly determined based on the target flushing number is correct, the target time being any time after the current time; an instruction fetching module, for adding the correctly executed instruction corresponding to the branch jump instruction to the instruction processing pipeline after performing the first flushing operation.

[0014] In an optional embodiment of the present disclosure, a branch prediction module is specifically used to perform branch prediction on branch jump instructions based on multiple preset branch prediction methods, and obtain multiple branch prediction results corresponding to the branch jump instructions by each branch prediction method; determine the prediction accuracy of each branch prediction method based on the multiple branch prediction results; determine the branch prediction method with the highest prediction accuracy as the target branch prediction method, and perform branch prediction on the branch jump instruction based on the target branch prediction method.

[0015] In an optional embodiment of the present disclosure, a branch prediction module is specifically used to perform branch prediction on the branch jump instruction at the current moment according to the branch prediction method for each branch prediction method, and obtain the branch prediction direction and predicted target address corresponding to the branch prediction method; compare the branch prediction direction and predicted target address corresponding to the branch prediction method with the actual branch direction and actual target address after the execution stage, and obtain the prediction accuracy of each branch prediction method.

[0016] In an optional embodiment of the present disclosure, the instruction flushing module is specifically configured to send multiple preset flushing times corresponding to the first flushing operation if the branch prediction result is a correct prediction, so as to determine a first target flushing time from the multiple preset flushing times; the first target flushing time is any one of the multiple preset flushing times. A confirmation instruction for the first target flushing time is received, and a first flushing operation is performed on the first predicted instruction in the instruction processing pipeline based on the first target flushing time.

[0017] In an optional embodiment of the present disclosure, an instruction flushing module is specifically used to send an adjustment control for the number of flushes corresponding to a first flush operation if the branch prediction result is correctly predicted; wherein a preset flush number range is represented by the adjustment control, and the maximum flush number in the preset flush number range is less than a preset number threshold; receive an adjustment instruction based on the adjustment control, determine a second target flush number corresponding to the adjustment instruction from the preset flush number range, and perform a first flush operation on the first predicted instruction in the instruction processing pipeline based on the second target flush number.

[0018] In an optional embodiment of the present disclosure, the instruction flushing module is specifically used to determine the target branch jump instructions corresponding to the target flush number based on the target flush number; when the corresponding prediction of the target branch jump instruction is correct, the first predicted instruction in the instruction processing pipeline executes the first flush operation.

[0019] In an optional embodiment of the present disclosure, the instruction flushing module can also be used to perform a second flushing operation on a second predicted instruction in the instruction processing pipeline if the branch prediction result is a prediction error. The second predicted instruction is an instruction that is fetched into the instruction processing pipeline when the branch jump instruction is predicted incorrectly.

[0020] According to a third aspect of an embodiment of the present application, an electronic device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of any of the above side channel attack protection methods are implemented.

[0021] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, characterized in that when the computer program is executed by a processor, the steps of the side channel attack protection method as described in any one of the above items are implemented.

[0022] A fifth aspect of an embodiment of the present application provides a computer program product, including a computer program, which is executed by a processor to implement the above-mentioned side channel attack protection method.

[0023] Through the side channel attack protection method provided in the embodiment of the present application, on the one hand, the method may perform a flush operation regardless of whether the prediction is correct or failed when executing branch prediction. For the case of failed prediction, the flush operation must be performed. For the case of correct prediction, the processor can randomly generate a flush number, and perform a flush operation on the corresponding number of branch jump instructions according to the randomly generated flush number, instead of performing a flush operation on all correctly predicted branch jump instructions in the related technical solution, thereby ensuring the performance of the processor and the efficiency of processing instructions. On the other hand, after randomly generating the target flush number, whether to perform a flush operation on the branch jump instruction at the current moment or the branch jump instruction at any time after the current moment is also random, that is, the branch jump instruction at the current moment or the branch jump instruction at any time after the current moment can be flushed, or it can not be flushed, which will greatly prevent side channel attacks and ensure network security. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0025] Figure 1 A flowchart of a side channel attack protection method provided by one embodiment of the present application;

[0026] Figure 2 A flow chart of a method for determining branch prediction and performing branch prediction on branch jump instructions provided in one embodiment of the present application;

[0027] Figure 3 A schematic diagram of a process of performing a first flushing operation when a prediction is correct provided by an embodiment of the present application;

[0028] Figure 4 A schematic diagram of an instruction flow of an instruction processing pipeline provided by an embodiment of the present application;

[0029] Figure 5 A schematic diagram of the structure of a protection device for side channel attacks provided by an embodiment of the present application;

[0030] Figure 6 A schematic diagram of the structure of an electronic device provided for one embodiment of the present application. DETAILED DESCRIPTION

[0031] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0032] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0033] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to the actual situation.

[0034] In the relevant technical context, a side channel attack (SCA for short), also known as a side channel attack, is an attack that does not directly target the code, but instead collects information from the system or affects the execution of the code by measuring or exploiting the indirect impact of the system and its hardware on which the code runs. For example, using time information, power consumption, electromagnetic leakage or even sound can provide additional information to crack the system.

[0035] As embedded processors continue to introduce optimization mechanisms, such as data prefetching, speculative execution, and data caching, while bringing processor performance improvements, security issues are becoming increasingly prominent. Although the operating system can isolate illegal access to data to prevent software vulnerabilities, it cannot prevent the leakage of sensitive data through side channels due to design flaws in shared hardware. Side channel attacks are attacks that exploit the leakage of sensitive data through side channels during device operation. They can bypass encryption algorithms, posing a serious threat to user privacy.

[0036] In the above processor microarchitecture storage system, frequent memory access and program execution speed differences also create conditions for side channel attacks. For example, Flush and Reload attacks (also known as Flush+Reload attacks) are representative of side channel attacks based on access-driven caches, and are a cross-core and cross-virtual machine cache detection method. It attacks the target thread by flushing (Flush) and reloading (Reload). The attacker can determine the cache line accessed by the victim based on the length of the reload time. Specifically, in the Flush phase, the attacker evicts the monitored memory block from the cache, and then waits for the target user to access the shared memory in the Trigger phase. In the Reload phase, the attacker reloads the monitored shared memory block. If the memory block accessed by the target virtual machine does not need to be reloaded during the waiting period, the time will be shorter because the data has been cached in the cache. According to the length of the loading time, the data accessed by the target virtual machine can be determined.

[0037] For another example, the Flush and Flush attack (also called the Flush+Flush attack) is based on the execution speed / execution time of the cl-flush instruction. First, flush the original data in the cache, then wait for the target process to run, update the cache, and refresh the shared cache line, and measure the refresh time, so as to determine whether the original data is cached based on the measured time. However, this attack method requires a high-precision timer.

[0038] In one embodiment, in order to improve the processing efficiency of the processor, pipeline technology is usually used to process instructions in parallel to accelerate the instruction processing efficiency. When processing branch jump instructions, in order to overcome the pipeline delay caused by the processor core waiting for the execution result of the branch jump instruction to determine the next instruction fetch, a branch prediction unit (Branch Prediction Unit, referred to as BPU) can be set at the front end of the pipeline to implement branch prediction (Branch Prediction, referred to as BP). When encountering a branch jump instruction, the processor predicts the direction of the jump instruction, or predicts the target address of the jump instruction. The processor executes the program according to the prediction result. Before the result of the jump instruction is finally resolved, these instructions are removed from the memory and then sent to the pipeline for execution. If the branch prediction is correct, the performance of the processor will be improved. However, if the branch prediction is wrong, these speculatively executed instructions will be flushed.

[0039] The inventors have discovered that, in response to the above-mentioned side channel attacks, the traditional technical solution is that the processor makes the results of branch prediction for all branch jump instructions all miss (hit), that is, all branch predictions are flushed regardless of whether the prediction is correct or failed. At this time, since it is impossible to determine whether the predicted instructions are correct, it is impossible to perform side channel attacks based on the information leaked during the program execution, thereby achieving the effect of protecting against side channel attacks.

[0040] However, in the above-mentioned traditional technical solution, the processor makes all branch prediction results for all branch jump instructions miss, so that the processor needs to perform a flush operation and re-fetch instructions when executing branch jump instructions, resulting in low execution efficiency of the processor, which greatly affects the performance of the processor. Therefore, it is urgent to realize a method that can prevent the processor from side channel attacks and ensure network security while ensuring the processing performance of the processor, thereby ensuring the execution efficiency of the processor.

[0041] In response to the above problems, an embodiment of the present application provides a side channel attack protection method, which performs branch prediction on the branch jump instruction when the instruction to be executed at the current moment is a branch jump instruction to obtain a branch prediction result corresponding to the branch jump instruction; if the prediction is correct, a target flush number is randomly generated, and a first flush operation is performed on the first predicted instruction in the instruction processing pipeline based on the randomly generated target flush number; the first predicted instruction is an instruction that is fetched into the instruction processing pipeline when the prediction of the branch jump instruction at the current moment is correct, and / or an instruction that is fetched into the instruction processing pipeline when the prediction of the branch jump instruction at a target moment randomly determined based on the target flush number is correct, and the target moment is any moment after the current moment; after executing the first flush operation, the correctly executed instruction corresponding to the branch jump instruction is added to the instruction processing pipeline.

[0042] Since the processor can randomly generate a flush number for the case where the prediction is correct, and randomly flush the branch jump instruction detected at any time according to the randomly generated flush number, not only the flush operation is performed for the case where the prediction is correct, but also whether the flush operation is performed for the correctly predicted branch jump instruction is random, which greatly prevents side channel attacks. The random flush number is set so that the flush operation can be performed or not for the case where the prediction is correct. Compared with the above-mentioned related technical solutions that perform flush operations for all, the performance consumption of the processor is reduced, thereby improving the efficiency of the processor.

[0043] It should be noted that the solutions in the embodiments of the present application can be implemented in various computer languages, such as object-oriented programming language Java and interpreted scripting language JavaScript, etc. The application scenarios mentioned in the embodiments are merely exemplary and are not intended to limit the methods provided by the present disclosure.

[0044] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0045] The following will be combined Figure 1 The side channel attack protection method provided in the embodiment of the present application is exemplified.

[0046] Figure 1 A flowchart of a method for protecting against side channel attacks provided by an embodiment of the present application. Figure 1 The following embodiments take the processor as the execution subject and apply the method provided in the embodiment of the present application to the above processor as an example for specific description. The side channel attack protection method provided in the embodiment of the present application may include the following steps 101 to 103:

[0047] Step 101: When the instruction to be executed at the current moment is a branch jump instruction, branch prediction is performed on the branch jump instruction to obtain a branch prediction result corresponding to the branch jump instruction.

[0048] Step 102: If the branch prediction result is a correct prediction, a target flush number is randomly generated, and a first flush operation is performed on the first predicted instruction in the instruction processing pipeline based on the randomly generated target flush number; the first predicted instruction is an instruction that is fetched into the instruction processing pipeline when the branch jump instruction prediction at the current moment is correct, and / or an instruction that is fetched into the instruction processing pipeline when the branch jump instruction prediction at the target moment randomly determined based on the target flush number is correct, and the target moment is any moment after the current moment.

[0049] Step 103: After executing the first flush operation, add the correctly executed instructions corresponding to the branch jump instructions to the instruction processing pipeline.

[0050] In the above Figure 3 In the side channel attack protection method shown, on the one hand, the method may perform a flush operation regardless of whether the prediction is correct or failed when executing branch prediction. For the case of failed prediction, the flush operation must be performed. For the case of correct prediction, the processor can randomly generate a flush number, and perform a flush operation on the corresponding number of branch jump instructions according to the randomly generated flush number, instead of performing a flush operation on all correctly predicted branch jump instructions in the related technical solution, thereby ensuring the performance of the processor and the efficiency of processing instructions. On the other hand, after randomly generating the target flush number, whether to perform a flush operation on the branch jump instruction at the current moment or the branch jump instruction at any time after the current moment is also random, that is, the branch jump instruction at the current moment or the branch jump instruction at any time after the current moment can be flushed, or it can not be flushed, which will greatly prevent side channel attacks and ensure network security.

[0051] This process enables the processor to flush the predicted execution instructions regardless of whether they are correctly predicted branch jump instructions or incorrectly predicted branch jump instructions. However, the execution time for correctly predicted instructions is shorter than that for incorrectly predicted instructions. This process takes less time than when the related technology predicts that all instructions do not hit, thereby ensuring that side channel attacks are prevented while achieving the technical effect of reducing the performance consumption of the processor.

[0052] The following will be combined with specific embodiments to Figure 1 The specific implementation methods of each step in the embodiment shown are described in detail:

[0053] In step 101, when the instruction to be executed at the current moment is a branch jump instruction, branch prediction is performed on the branch jump instruction to obtain a branch prediction result corresponding to the branch jump instruction.

[0054] The branch jump instruction may be an instruction triggered by a conditional jump or an instruction triggered by a function call; the branch prediction operation for the branch jump instruction is to improve the efficiency of the processor in executing instructions. When the processor receives the branch jump instruction, it can predict the execution path and obtain the branch prediction result corresponding to the branch jump instruction. The branch prediction result may be a prediction success or a prediction failure.

[0055] In an optional embodiment of the present disclosure, the branch prediction result may also include a branch prediction direction and a predicted target address. The branch prediction direction is the jump direction, and the predicted target address is the branch prediction direction, and the instruction fetch starts from the target address of the branch instruction in the next cycle, so that the pipeline is carried out correctly and the execution efficiency of the processor is improved.

[0056] Exemplarily, before executing step 101, it is necessary to preferentially obtain the instruction stream in the instruction processing pipeline, wherein the instruction stream at least includes branch jump instructions.

[0057] In an optional embodiment of the present disclosure, in the instruction processing pipeline, a branch jump instruction in the instruction stream is obtained by an instruction fetch operation. Exemplarily, in the instruction processing pipeline, the instruction stream is written into the instruction data cache and the branch prediction unit in parallel, the instruction fetch operation is performed to obtain the branch jump instruction in the instruction stream, and the branch jump instruction in the instruction stream and whether there is a branch prediction error for the branch jump instruction are determined in the branch prediction unit, so as to execute Figure 1 The operation shown.

[0058] In this embodiment, performing an instruction fetch operation to obtain a branch jump instruction in an instruction stream facilitates rapid determination of whether branch prediction is required, thereby improving processor performance.

[0059] For example, the processor is usually a pipeline structure. When the processor executes a branch jump instruction, it generally has to wait until the execution stage is completed before the jump direction and jump target address corresponding to the branch jump instruction can be determined. At this time, the subsequent instructions to be executed have been taken out of the memory. When the prediction fails, the above-mentioned instructions need to be flushed, and the instructions are re-obtained from the correct target address of the jump instruction and executed, which greatly affects the performance of the processor. In order to improve the efficiency and performance of the processor, branch prediction can be performed when a branch jump instruction is executed, so as to obtain the branch prediction result corresponding to the branch prediction, that is, the branch prediction direction and target address.

[0060] When performing branch prediction for a branch jump instruction, the prediction method of this embodiment can be any prediction method, and the embodiment of the present disclosure does not impose any special restrictions on this. Figure 2 The method process of performing branch prediction on branch jump instructions is exemplified.

[0061] Figure 2 A flow chart of a method for determining branch prediction and performing branch prediction on branch jump instructions provided by an embodiment of the present application. Figure 2 The method at least comprises steps 201 to 203:

[0062] Step 201 : performing branch prediction on branch jump instructions based on a plurality of preset branch prediction methods respectively, and obtaining a plurality of branch prediction results corresponding to the branch jump instructions by each branch prediction method respectively.

[0063] Exemplarily, multiple branch prediction methods are pre-stored for branch jump instructions, and the multiple branch prediction methods are used to predict the branch jump instructions respectively, thereby obtaining branch prediction results corresponding to each branch prediction method, that is, the branch prediction direction and the target address of the instruction fetch.

[0064] It should be explained that the multiple branch prediction methods may be, for example, static prediction methods, dynamic prediction methods, etc., and the embodiments of the present disclosure do not impose any special restrictions on this.

[0065] Step 202: Determine the prediction accuracy of each branch prediction method based on multiple branch prediction results.

[0066] Exemplarily, the branch prediction results corresponding to each branch prediction method obtained in step 201 respectively determine the prediction accuracy of the prediction method.

[0067] In an optional embodiment of the present disclosure, when executing step 201, the branch prediction direction and predicted target address obtained by performing branch prediction according to each branch prediction method can be compared with the actual branch direction and actual target address after the execution stage to obtain the prediction accuracy of each branch prediction method.

[0068] Exemplarily, the prediction accuracy is obtained by comparing the branch prediction direction and the predicted target address of the instruction fetch in the branch prediction results obtained by performing branch prediction by each branch prediction method with the actual branch direction and the actual target address of the instruction fetch after the instruction execution stage.

[0069] When the branch prediction direction, the predicted target address, the actual branch direction, and the actual target address of the instruction are all the same, the prediction accuracy is the highest; conversely, if the branch prediction direction, the predicted target address, the actual branch direction, and the actual target address of the instruction are all different, the prediction accuracy is the lowest.

[0070] This embodiment can obtain the prediction accuracy corresponding to each branch prediction method through comparison, so as to screen out the branch prediction method with the highest prediction accuracy for prediction processing, thereby reducing the probability of processor prediction errors as much as possible, thereby reducing the performance consumption of the processor caused by prediction errors, so as to ensure the performance of the processor.

[0071] In addition to the above embodiments, the prediction accuracy of each branch prediction method can also be determined by other methods. For example, only judging by the branch prediction direction or the predicted target address of the instruction fetch, or calculating the prediction accuracy by other methods, the embodiments of the present disclosure do not impose any special restrictions on this.

[0072] Step 203: determine the branch prediction method with the highest prediction accuracy as the target branch prediction method, and perform branch prediction on the branch jump instruction based on the target branch prediction method.

[0073] Exemplarily, the branch prediction method with the highest prediction accuracy is determined as the target branch prediction method, so that the branch prediction method with the highest prediction accuracy can be used to perform branch prediction on the branch jump instruction.

[0074] In this embodiment, by using the branch prediction method with the highest prediction accuracy to predict the branch jump instruction, the accuracy of branch prediction can be greatly improved, thereby facilitating high prediction accuracy when defending against side channel attacks, reducing the time consumption of flush operations, and improving the performance of the corresponding processor.

[0075] Before executing the following steps 102 and 103, it is necessary to determine whether the branch prediction is correct or incorrect. In combination with the above embodiment, if the branch prediction direction (jump / no jump), the predicted target address are the same as the actual branch direction and the actual target address, then the branch prediction is determined to be correct; otherwise, the branch prediction is incorrect.

[0076] In step 102, if the branch prediction result is a correct prediction, a target flush number is randomly generated, and a first flush operation is performed on the first predicted instruction in the instruction processing pipeline based on the randomly generated target flush number; the first predicted instruction is an instruction that is fetched into the instruction processing pipeline when the branch jump instruction prediction at the current moment is correct, and / or, an instruction that is fetched into the instruction processing pipeline when the branch jump instruction prediction at the target moment randomly determined based on the target flush number is correct, and the target moment is any moment after the current moment.

[0077] The flush operation is used to clear the instructions fetched during the branch prediction period in the instruction processing pipeline from the instruction processing pipeline so that they can be re-fetched later. The purpose of the flush operation is to correct the wrong branch prediction and ensure that the processor recovers from the wrong path and continues to execute the correct instruction sequence. The branch jump instruction at the target time refers to the branch jump instruction whose branch prediction result is the correct branch jump instruction.

[0078] The target flush number may be any randomly generated number, and only one flush operation can be performed on a branch jump instruction. Therefore, when the randomly generated target flush number is greater than 1, the flush operations are performed on multiple different branch jump instructions respectively.

[0079] Exemplarily, taking the randomly generated target flush number as 1 as an example, the flush operation can be performed on the first predicted instruction that is fetched into the instruction processing pipeline when the corresponding prediction of the branch jump instruction at the current moment is correct, or the flush operation can be performed on the first predicted instruction that is fetched into the instruction processing pipeline when the corresponding prediction of the branch jump instruction at any moment after the current moment is correct. Similarly, when the randomly generated target flush number is greater than 1, the branch jump instruction corresponding to the first flush operation is also random. It can be seen that this method randomly determines whether to perform a flush operation on the first predicted instruction that is taken when the corresponding prediction of the branch jump instruction is correct, so that the technical effect of avoiding side channel attacks can be achieved.

[0080] For ease of understanding, the following will be combined Figure 3 The process of performing the first flushing operation when the above prediction is correct is exemplified.

[0081] Reference Figure 3 As shown, when the instruction processing pipeline is executed from the "i-1" instruction to the "branch jump instruction i", it corresponds to two jump directions. Assuming that the corresponding directions of the "p+1" and "p+2" instructions are the predicted correct adjustment directions, it does not need to wait after executing the "branch jump instruction i", and directly adds the "p+1" and "p+2" instructions to the pipeline for execution. At this time, the first predicted instructions for the "branch jump instruction i" are the "p+1" and "p+2" instructions. When the next step of the "p+2" instruction is the "branch jump instruction p", it also corresponds to two jump directions, among which the "p+3" instruction is the instruction when the prediction is correct.

[0082] If the randomly generated target flush count is 1, when the pipeline executes and detects "branch jump instruction i", it performs branch prediction on it and adds the "p+1" instruction and "p+2" instruction to the pipeline. When it is determined that the branch prediction result for "branch jump instruction i" is correctly predicted, the "p+1" instruction and "p+2" instruction on the pipeline can be flushed. Alternatively, the "p+1" instruction and "p+2" instruction on the pipeline are not flushed, but when the "branch jump instruction p" is executed and the branch prediction result is correctly predicted, the "p+3" instruction on the pipeline is flushed. Whether the flush operation is performed on the instructions corresponding to the "branch jump instruction i" and "branch jump instruction p" when the branch prediction result is correctly predicted is a random decision made by the system and does not follow any rules.

[0083] Further, with respect to the above-mentioned randomly generated target flushing times, in terms of the step of executing the first flushing operation on the first predicted instruction in the instruction processing pipeline based on the randomly generated target flushing times, in addition to the system being able to generate based on a random model, a window can also be provided to the user so that the user can perform flexible control. This can be specifically described based on the following embodiments: Example 1

[0084] In an optional embodiment of the present disclosure, if the branch prediction is correct and the branch prediction result is a correct prediction, multiple preset flush times corresponding to the first flush operation are sent to determine a first target flush number from the multiple preset flush times; a confirmation instruction for the first target flush number is received, and a first flush operation is performed on the first predicted instruction in the instruction processing pipeline based on the first target flush number.

[0085] The first target flushing number is any one of a plurality of preset flushing numbers.

[0086] Exemplarily, a display screen may be provided to display a user interaction interface, and a plurality of preset flushing times may be provided to the user for selection on the user interaction interface, so that the user may select a preset flushing number as the first target flushing number, thereby performing a second flushing operation according to the first target execution time corresponding to the target random degree.

[0087] In this embodiment, the user can flexibly adjust the instruction execution time required for predicting the correct situation according to his own needs, thereby improving the flexibility of processor program execution while ensuring protection against side channel attacks. Example 2

[0088] In another optional embodiment of the present disclosure, if the branch prediction result is correctly predicted, an adjustment control for the number of flushes corresponding to the first flush operation is sent; an adjustment instruction based on the adjustment control is received, and a second target flush number corresponding to the adjustment instruction is determined from a preset flush number range, and a first flush operation is performed on the first predicted instruction in the instruction processing pipeline based on the second target flush number.

[0089] The preset flushing times range is represented by adjusting the control, and the maximum flushing times in the preset flushing times range is less than the preset times threshold. In order to take into account the processor performance, the set maximum flushing times needs to be set within a certain preset times threshold, for example, the maximum flushing times is 10 times.

[0090] For example, an adjustment control, such as a sliding control, may be provided to the user, the sliding control including a sliding track and a sliding mark on the sliding track, and the length of the sliding track may represent a preset flushing number range, such as 1-10. The user may adjust the position of the sliding mark in the control on the sliding track to determine the second target flushing number, so as to perform the first flushing operation on the first predicted instruction in the instruction processing pipeline according to the second target flushing number.

[0091] In summary, when randomly generating the target flushing times, a choice can be provided to the user. The user can choose to make adjustments independently to ensure the flexibility of the user's operation, or the program can automatically make random adjustments to ensure randomness.

[0092] Meanwhile, when the first flush operation is performed on the first predicted instruction in the instruction processing pipeline based on the randomly generated target flush number in step 102, the specific implementation process of the processor performing the first flush operation on the first predicted instruction in the instruction processing pipeline according to the target flush number can be as follows:

[0093] In an optional embodiment of the present disclosure, based on the target flush number, a target branch jump instruction corresponding to the target flush number is determined; when the corresponding prediction of the target branch jump instruction is correct, the first predicted instruction in the instruction processing pipeline performs a first flush operation.

[0094] The target branch jump instruction is a branch jump instruction predicted to be correct after the current moment.

[0095] Exemplarily, after determining the target flush number, a number of target branch jump instructions corresponding to the target flush number may be preselected, so that when the target branch jump instruction is executed, a first flush operation is performed.

[0096] In addition to the above embodiments, when executing a branch jump instruction, the processor may determine whether to perform a first flush operation on the correctly predicted branch jump instruction.

[0097] Furthermore, in another embodiment of the present disclosure, if the processor detects that the branch prediction result is a prediction error, the processor performs a second flush operation on the second predicted instruction in the instruction processing pipeline.

[0098] The second predicted instruction is an instruction that is fetched into the instruction processing pipeline when a branch jump instruction is predicted incorrectly.

[0099] For example, Figure 3Taking the shown embodiment as an example, when it is determined that the branch prediction result for the "branch jump instruction i" is a prediction error, that is, the pipeline execution path is the "i+1", "i+2" instructions, then the second predicted instructions are the "i+1", "i+2" instructions, and the "i+1", "i+2" instructions on the pipeline are executed with the second flush operation.

[0100] In order to facilitate the comparison of the above predictions, the following will combine Figure 4 An exemplary description is given.

[0101] Figure 4 A schematic diagram of an instruction flow of an instruction processing pipeline provided by an embodiment of the present application; Figure 4 As shown in FIG. 1 , the instruction processing pipeline has an IFU module and an EXU module. The instruction processing pipeline includes three steps, namely, IF: instruction acquisition stage, DEC: instruction decoding stage, and EX: instruction execution and effective address generation stage. After two clock cycles, the instruction obtained in the IF stage is executed in the EX stage.

[0102] like Figure 4 As shown, the Arithmetic And Logic Unit (ALU) is a combinational logic circuit that can implement multiple groups of arithmetic operations and logic operations and can perform branch prediction. Figure 4 In the example, two ALUs, ALU1 and ALU2, are used for branch prediction. If the prediction is wrong, the corresponding alu_flush will be initiated, that is, Figure 4 As shown in alu1_flush, alu2_flush. For correctly predicted branch jump instructions, random flush instructions are initiated, that is, the first target prediction instruction needs 6 clock cycles to execute, and for branch instructions that fail to predict, if the ALU parses successfully, the subsequent instructions actually need 9 (6+3=9) clock cycles to execute, of which 3 clock cycles are the number of pipeline stages from the instruction fetch (IF) stage to the ALU, that is, the clock cycles consumed by re-fetching when the prediction fails.

[0103] In step 103, after the first flush operation is performed, the correctly executed instructions corresponding to the branch jump instructions are added to the instruction processing pipeline.

[0104] Exemplarily, when the first flush operation is triggered on the first predicted instruction in the instruction processing pipeline in step 102, the first predicted instruction in the instruction processing pipeline can be cleared, and the corresponding correctly executed instruction can be added to the instruction processing pipeline.

[0105] In this embodiment, since the first predicted instruction in the instruction processing pipeline is a correctly predicted instruction, that is, the correctly executed instruction corresponding to the branch jump instruction is the first predicted instruction, it is flushed and cleared, and then the first predicted instruction is re-fetched and added to the instruction processing pipeline for continued execution.

[0106] In another optional embodiment of the present disclosure, after executing the second flush operation, since the second predicted instruction in the instruction processing pipeline is a mispredicted instruction, after the flush operation is performed on it, another instruction with the correct execution direction is fetched and added to the instruction processing pipeline for continued execution.

[0107] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0108] To implement the above side channel attack protection method, please refer to Figure 5 An embodiment of the present application provides a side channel attack protection device, and the side channel attack protection device 500 includes: a branch prediction module 501, an instruction flushing module 502 and an instruction fetching module 503.

[0109] Among them, the branch prediction module 501 is used to perform branch prediction on the branch jump instruction when the instruction to be executed at the current moment is a branch jump instruction, so as to obtain a branch prediction result corresponding to the branch jump instruction; the instruction flushing module 502 is used to randomly generate a target flushing number if the branch prediction result is correct, and perform a first flushing operation on the first predicted instruction in the instruction processing pipeline based on the randomly generated target flushing number; the first predicted instruction is an instruction that is fetched into the instruction processing pipeline when the prediction of the branch jump instruction at the current moment is correct, and / or an instruction that is fetched into the instruction processing pipeline when the prediction of the branch jump instruction corresponding to the target time randomly determined based on the target flushing number is correct, and the target time is any time after the current time; the instruction fetching module 503 is used to add the correctly executed instruction corresponding to the branch jump instruction to the instruction processing pipeline after executing the first flushing operation.

[0110] In an optional embodiment of the present disclosure, the branch prediction module 501 is specifically used to perform branch prediction on branch jump instructions based on multiple preset branch prediction methods, and obtain multiple branch prediction results corresponding to the branch jump instructions by each branch prediction method; determine the prediction accuracy of each branch prediction method based on the multiple branch prediction results; determine the branch prediction method with the highest prediction accuracy as the target branch prediction method, and perform branch prediction on the branch jump instruction based on the target branch prediction method.

[0111] In an optional embodiment of the present disclosure, the branch prediction module 501 is specifically used to perform branch prediction on the branch jump instruction at the current moment according to the branch prediction method for each branch prediction method, and obtain the branch prediction direction and predicted target address corresponding to the branch prediction method; compare the branch prediction direction and predicted target address corresponding to the branch prediction method with the actual branch direction and actual target address after the execution stage, and obtain the prediction accuracy of each branch prediction method.

[0112] In an optional embodiment of the present disclosure, the instruction flushing module 502 is specifically configured to send multiple preset flushing times corresponding to the first flushing operation if the branch prediction result is a correct prediction, so as to determine a first target flushing time from the multiple preset flushing times; the first target flushing time is any one of the multiple preset flushing times. A confirmation instruction for the first target flushing time is received, and a first flushing operation is performed on the first predicted instruction in the instruction processing pipeline based on the first target flushing time.

[0113] In an optional embodiment of the present disclosure, the instruction flushing module 502 is specifically used to send an adjustment control for the number of flushes corresponding to the first flush operation if the branch prediction result is a correct prediction; wherein a preset flush number range is represented by the adjustment control, and the maximum flush number in the preset flush number range is less than a preset number threshold; receive an adjustment instruction based on the adjustment control, determine a second target flush number corresponding to the adjustment instruction from the preset flush number range, and perform a first flush operation on the first predicted instruction in the instruction processing pipeline based on the second target flush number.

[0114] In an optional embodiment of the present disclosure, the instruction flushing module 502 is specifically used to determine the target branch jump instructions corresponding to the target flush number based on the target flush number; when the corresponding prediction of the target branch jump instruction is correct, the first predicted instruction in the instruction processing pipeline performs the first flush operation.

[0115] In an optional embodiment of the present disclosure, the instruction flush module 502 can also be used to perform a second flush operation on a second predicted instruction in the instruction processing pipeline if the branch prediction result is a prediction error. The second predicted instruction is an instruction that is fetched into the instruction processing pipeline when a branch jump instruction is predicted incorrectly.

[0116] For the specific definition of the side channel attack protection device, please refer to the definition of the side channel attack protection method mentioned above, which will not be repeated here. Each module in the side channel attack protection device can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0117] In one embodiment, an electronic device is provided, the internal structure diagram of the electronic device can be as follows: Figure 6 As shown. The electronic device includes a processor, a memory, a network interface and a database connected via a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the electronic device is used to store data. The network interface of the electronic device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a side channel attack protection method as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the side channel attack protection method as described above is implemented.

[0118] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above side channel attack protection method can be implemented.

[0119] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0120] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0121] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0122] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0123] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0124] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for protecting against side channel attacks, characterized in that: include: When the instruction to be executed at the current moment is a branch jump instruction, branch prediction is performed on the branch jump instruction based on multiple preset branch prediction methods respectively, and multiple branch prediction results corresponding to the branch jump instruction by each branch prediction method are obtained; Determining the prediction accuracy of each branch prediction method based on the multiple branch prediction results; The branch prediction method with the highest prediction accuracy is determined as the target branch prediction method, and branch prediction is performed on the branch jump instruction based on the target branch prediction method to obtain a branch prediction result corresponding to the branch jump instruction; wherein the prediction accuracy of each branch prediction method is determined based on the multiple branch prediction results, including: for each branch prediction method in the branch prediction methods, branch prediction is performed on the branch jump instruction at the current moment according to the branch prediction method to obtain a branch prediction direction and a predicted target address corresponding to the branch prediction method; the branch prediction direction and the predicted target address corresponding to the branch prediction method are compared with the actual branch direction and the actual target address after the execution stage to obtain the prediction accuracy of each branch prediction method; If the branch prediction direction and the predicted target address are all the same as the actual branch direction and the actual target address, the branch prediction is determined to be correct; if the branch prediction result is a correct prediction, a target flush number is randomly generated, and a first flush operation is performed on the first predicted instruction in the instruction processing pipeline based on the randomly generated target flush number; a flush operation is performed for a branch jump instruction, and when the target flush number is greater than 1, flush operations are performed on multiple different branch jump instructions respectively; the first predicted instruction is an instruction that is fetched into the instruction processing pipeline when the branch jump instruction prediction at the current moment is correct, and / or an instruction that is fetched into the instruction processing pipeline when the branch jump instruction prediction at a target moment randomly determined based on the target flush number is correct, and the target moment is any moment after the current moment; After executing the first flush operation, the correctly executed instruction corresponding to the branch jump instruction is added to the instruction processing pipeline.

2. The method according to claim 1, characterized in that If the branch prediction result is a correct prediction, a target flush number is randomly generated, and a first flush operation is performed on a first predicted instruction in the instruction processing pipeline based on the randomly generated target flush number, including: If the branch prediction result is a correct prediction, multiple preset flush times corresponding to the first flush operation are sent to determine a first target flush number from the multiple preset flush times; the first target flush number is any one of the multiple preset flush times; A confirmation instruction for the first target flush number is received, and a first flush operation is performed on a first predicted instruction in the instruction processing pipeline based on the first target flush number.

3. The method according to claim 1, characterized in that If the branch prediction result is a correct prediction, a target flush number is randomly generated, and a first flush operation is performed on a first predicted instruction in the instruction processing pipeline based on the randomly generated target flush number, including: If the branch prediction result is a correct prediction, an adjustment control for the flushing number corresponding to the first flushing operation is sent; wherein a preset flushing number range is represented by the adjustment control, and a maximum flushing number in the preset flushing number range is less than a preset number threshold; An adjustment instruction based on the adjustment control is received, a second target flushing number corresponding to the adjustment instruction is determined from the preset flushing number range, and a first flushing operation is performed on a first predicted instruction in the instruction processing pipeline based on the second target flushing number.

4. The method according to claim 1, characterized in that: Performing a first flush operation on a first predicted instruction in the instruction processing pipeline based on the randomly generated target flush number includes: Based on the target flush number, determining a number of target branch jump instructions corresponding to the target flush number; When the prediction corresponding to the target branch jump instruction is correct, the first predicted instruction in the instruction processing pipeline performs a first flush operation.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: If the branch prediction result is a prediction error, a second flush operation is performed on a second prediction instruction in the instruction processing pipeline, where the second prediction instruction is an instruction fetched into the instruction processing pipeline when the branch jump instruction is predicted incorrectly.

6. A protection device for side channel attacks, characterized in that: include: A branch prediction module, used for, when the instruction to be executed at the current moment is a branch jump instruction, performing branch prediction on the branch jump instruction based on a plurality of preset branch prediction methods, respectively, to obtain a plurality of branch prediction results corresponding to the branch jump instruction by each branch prediction method; Determining the prediction accuracy of each branch prediction method based on the multiple branch prediction results; The branch prediction method with the highest prediction accuracy is determined as the target branch prediction method, and branch prediction is performed on the branch jump instruction based on the target branch prediction method to obtain a branch prediction result corresponding to the branch jump instruction; wherein the prediction accuracy of each branch prediction method is determined based on the multiple branch prediction results, including: for each branch prediction method in the branch prediction methods, branch prediction is performed on the branch jump instruction at the current moment according to the branch prediction method to obtain a branch prediction direction and a predicted target address corresponding to the branch prediction method; the branch prediction direction and the predicted target address corresponding to the branch prediction method are compared with the actual branch direction and the actual target address after the execution stage to obtain the prediction accuracy of each branch prediction method; An instruction flushing module, used for determining that a branch prediction is correct if the branch prediction direction and the predicted target address are the same as the actual branch direction and the actual target address; if the branch prediction result is a correct prediction, randomly generating a target flushing number, and performing a first flushing operation on a first predicted instruction in the instruction processing pipeline based on the randomly generated target flushing number; performing a flushing operation once for a branch jump instruction, and when the target flushing number is greater than 1, performing flushing operations on a plurality of different branch jump instructions respectively; the first predicted instruction is an instruction that is fetched into the instruction processing pipeline when the branch jump instruction prediction at the current moment is correct, and / or an instruction that is fetched into the instruction processing pipeline when the branch jump instruction prediction at a target moment randomly determined based on the target flushing number is correctly predicted, and the target moment is any moment after the current moment; The instruction fetch module is used to add the correctly executed instruction corresponding to the branch jump instruction to the instruction processing pipeline after executing the first flush operation.

7. An electronic device comprising: The invention comprises a memory and a processor, wherein the memory stores a computer program, and is characterized in that when the processor executes the computer program, the steps of the side channel attack protection method described in any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the side channel attack protection method described in any one of claims 1 to 5 are implemented.

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